Reading circuit for differential bits

Abstract

The invention provides a reading circuit of a differential bit, which comprises the differential bit comprising a storage bit and a reference bit which are arranged in pairs; the reference resistor and the third MOS tube are connected in series, and the second end of the reference resistor is grounded through the third MOS tube; the current source circuit is used for generating a first reading current, a second reading current and a reference current which are the same in size; the first input end of the voltage type sensitive amplifier is connected with the first end of the storage bit; the first control switch is connected between the first end of the storage bit and the first end of the reference bit; the second control switch is connected between the second input end of the voltage type sensitive amplifier and the first end of the reference bit; and the third control switch is connected between the second input end of the voltage type sensitive amplifier and the first end of the reference resistor. According to the invention, data and short-circuit information of differential bits can be read.

Description

Technical Field

[0001] This invention relates to the field of magnetic memory technology, and more particularly to a differential bit readout circuit. Background Technology

[0002] The basic storage bits of a magnetic memory include a magnetic tunnel junction and a MOS transistor. To increase the read window when reading data from a storage bit, a differential bit structure is proposed. A differential bit structure includes paired storage bits and reference bits. The storage bits and reference bits have the same structure, but they store opposite data. The storage bits store the actual data needed, while the reference bits provide a reference resistor when reading data from the storage bits.

[0003] In practical applications, it is sometimes necessary to determine whether the storage bit and the reference bit are short-circuited. Therefore, a read circuit structure is needed to read the short-circuit information of the storage bit and the reference bit. Summary of the Invention

[0004] In view of this, the present invention provides a differential bit reading circuit capable of reading differential bit data and short-circuit information.

[0005] In a first aspect, the present invention provides a differential bit readout circuit, comprising:

[0006] The differential bit includes a pair of storage bits and a reference bit, the second end of the storage bit is grounded, and the second end of the reference bit is grounded;

[0007] A reference resistor and a third MOSFET are connected in series, with the second terminal of the reference resistor grounded through the third MOSFET;

[0008] A current source circuit is used to generate a first read current, a second read current, and a reference current of the same magnitude. The first read current is used to generate a first read voltage at the first terminal of the storage bit, the second read current is used to generate a second read voltage at the first terminal of the reference bit, and the reference current is used to generate a reference voltage at the first terminal of the reference resistor.

[0009] A voltage-type sensitive amplifier, wherein the first input terminal of the voltage-type sensitive amplifier is connected to the first terminal of the storage bit;

[0010] A first control switch is connected between the first end of the storage bit and the first end of the reference bit;

[0011] The second control switch is connected between the second input terminal of the voltage-type sensitive amplifier and the first terminal of the reference bit;

[0012] The third control switch is connected between the second input terminal of the voltage-type sensitive amplifier and the first terminal of the reference resistor.

[0013] Optionally, the first control switch, the second control switch, and the third control switch are transmission gates controlled by a voltage enable signal.

[0014] Optionally, when reading data from the storage bit, the first control switch and the third control switch are disconnected, the second control switch is turned on, and the current source circuit only outputs the first read current and the second read current;

[0015] When the short-circuit information of the storage bit and the reference bit is read, the first control switch and the third control switch are turned on, the second control switch is turned off, and the current source circuit outputs only one of the first read current and the second read current and the reference current.

[0016] Secondly, the present invention provides a differential bit reading circuit, comprising:

[0017] The differential bit includes a pair of storage bits and a reference bit, the second end of the storage bit is grounded, and the second end of the reference bit is grounded;

[0018] A first reference resistor and a third MOSFET are connected in series, with the second terminal of the first reference resistor grounded through the third MOSFET;

[0019] A second reference resistor and a fourth MOSFET are connected in series, with the second terminal of the second reference resistor grounded through the fourth MOSFET;

[0020] A current source circuit is used to generate a first read current, a second read current, a first reference current, and a second reference current of the same magnitude. The first read current is used to generate a first read voltage at the first terminal of the storage bit, the second read current is used to generate a second read voltage at the first terminal of the reference bit, the first reference current is used to generate a first reference voltage at the first terminal of the first reference resistor, and the second reference current is used to generate a second reference voltage at the first terminal of the second reference resistor.

[0021] A first voltage-type sensitive amplifier, wherein the first input terminal of the first voltage-type sensitive amplifier is connected to the first terminal of the storage bit, and the second input terminal of the first voltage-type sensitive amplifier is connected to the first terminal of the reference bit;

[0022] A second voltage-type sensitive amplifier, wherein the first input terminal of the second voltage-type sensitive amplifier is connected to the first terminal of the storage bit, and the second input terminal of the second voltage-type sensitive amplifier is connected to the first terminal of the first reference resistor;

[0023] A third voltage-type sensitive amplifier, wherein the first input terminal of the third voltage-type sensitive amplifier is connected to the first terminal of the reference bit, and the second input terminal of the third voltage-type sensitive amplifier is connected to the first terminal of the second reference resistor.

[0024] Optionally, the current source circuit is a current mirror structure.

[0025] Thirdly, the present invention provides a differential bit reading circuit, comprising:

[0026] The differential bit includes a pair of storage bits and a reference bit, wherein the second end of the storage bit is connected to a first voltage terminal and the second end of the reference bit is connected to a second voltage terminal;

[0027] A reference resistor and a third MOSFET are connected in series, with the second terminal of the reference resistor connected to a reference voltage terminal through the third MOSFET;

[0028] Current-mode sensitive amplifier;

[0029] A gating circuit is used to connect the first input terminal of the current-type sensitive amplifier to the first terminal of the storage bit to generate a first read current flowing through the storage bit, or to connect the first input terminal of the current-type sensitive amplifier to the first terminal of the reference resistor to generate a reference current flowing through the reference resistor.

[0030] It is also used to connect the second input terminal of the current-type sensitive amplifier to the first terminal of the reference bit to generate a second reading current flowing through the reference bit, or to connect the second input terminal of the current-type sensitive amplifier to the first terminal of the reference resistor to generate a reference current flowing through the reference resistor.

[0031] Optionally, the gating circuit includes two 2-to-1 gating switches.

[0032] Optionally, when reading data from the storage bit, the gating circuit connects the first input terminal of the current-type sensitive amplifier to the first terminal of the storage bit, and connects the second input terminal of the current-type sensitive amplifier to the first terminal of the reference bit.

[0033] When reading the short-circuit information of the storage bit, the gating circuit connects the first input terminal of the current-type sensitive amplifier to the first terminal of the storage bit, and connects the second input terminal of the current-type sensitive amplifier to the first terminal of the reference resistor.

[0034] When the short-circuit information of the reference bit is read, the gating circuit connects the first input terminal of the current-type sensitive amplifier to the first terminal of the reference resistor, and connects the second input terminal of the current-type sensitive amplifier to the first terminal of the reference bit.

[0035] Fourthly, the present invention provides a differential bit readout circuit, comprising:

[0036] The differential bit includes a pair of storage bits and a reference bit, wherein the second end of the storage bit is connected to a first voltage terminal and the second end of the reference bit is connected to a second voltage terminal;

[0037] A reference resistor and a third MOSFET are connected in series, with the second terminal of the reference resistor connected to a reference voltage terminal through the third MOSFET;

[0038] A first current-type sensitive amplifier, wherein a first input terminal of the first current-type sensitive amplifier is connected to a first terminal of the storage bit to generate a first read current flowing through the storage bit, and a second input terminal of the first current-type sensitive amplifier is connected to a first terminal of the reference bit to generate a second read current flowing through the reference bit;

[0039] A second current-mode sensitive amplifier, wherein the second input terminal of the second current-mode sensitive amplifier is connected to the first terminal of the reference resistor;

[0040] The fourth MOSFET is used to connect the first input terminal of the second current-mode sensitive amplifier to the third voltage terminal.

[0041] The fifth MOSFET is used to connect the first input terminal of the second current-mode sensitive amplifier to the fourth voltage terminal.

[0042] The first current mirror circuit is disposed between the first voltage terminal and the third voltage terminal, and is used to mirror the first reading current 1:1.

[0043] The second current mirror circuit is located between the second voltage terminal and the fourth voltage terminal to mirror the second reading current in a 1:1 manner.

[0044] The differential bit reading circuit provided by this invention can read differential bit data and short circuit information, and comprehensively considers circuit area cost, reading speed and short circuit judgment accuracy to meet the needs of different scenarios. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the differential bit reading circuit structure in Embodiment 1 of the present invention;

[0046] Figure 2This is a schematic diagram of the differential bit reading circuit structure in Embodiment 2 of the present invention;

[0047] Figure 3 This is a schematic diagram of the differential bit reading circuit structure in Embodiment 3 of the present invention;

[0048] Figure 4 This is a schematic diagram of the differential bit reading circuit structure in Embodiment 4 of the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0051] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0052] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0053] Example 1

[0054] One embodiment of the present invention provides a differential bit readout circuit, such as... Figure 1 As shown, the read circuit includes:

[0055] Difference bits, such as Figure 1 As shown in the dashed box, it includes a pair of storage bits and a reference bit. The second end of the storage bit is grounded, and the second end of the reference bit is grounded. In this embodiment, the storage bit includes a first magnetic tunnel junction MTJ1 and a first MOS transistor M1 connected in series, and the reference bit includes a second magnetic tunnel junction MTJ2 and a second MOS transistor M2 connected in series. It should be noted that the structure of the storage bit and the reference bit is not limited to this exemplary structure.

[0056] Series reference resistor R ref And the third MOSFET M3, reference resistor R ref The second terminal is grounded through the third MOSFET M3;

[0057] A current source circuit is used to generate a first reading current I1, a second reading current I2, and a reference current I of the same magnitude. ref The first read current I1 is used to generate a first read voltage at the first terminal of the storage bit, and the second read current I2 is used to generate a second read voltage at the first terminal of the reference bit. The reference current I... ref Used to generate a reference voltage at the first terminal of the reference resistor;

[0058] Voltage-type sensitive amplifier SA1, the first input terminal of voltage-type sensitive amplifier SA1 is connected to the first terminal of the storage bit;

[0059] First control switch S 12 It is connected between the first end of the storage bit and the first end of the reference bit;

[0060] Second control switch S d It is connected between the second input terminal of the voltage-type sensitive amplifier SA1 and the first terminal of the reference bit;

[0061] Third control switch S ref It is connected between the second input terminal of the voltage-type sensitive amplifier SA1 and the first terminal of the reference resistor.

[0062] In one embodiment, the first control switch S 12 Second control switch S d Third control switch S ref This is a transmission gate, controlled by a voltage enable signal. S d The control signal is the enable signal, S 12 S ref The control signal is connected to the enable signal via an inverter.

[0063] In this embodiment, reading the data from the storage bit and reading the short-circuit information between the storage bit and the reference bit require two steps:

[0064] When reading data from storage bits, S12 S ref Disconnect, S d The circuit is turned on. The current source circuit only outputs the first reading current I1 and the second reading current I2, I1 = I2. The current flowing through the two MTJs is the same, but the resistance values ​​of the two MTJs are different, thus generating different voltages. The data information of the storage bits is obtained through the voltage-type sensitive amplifier SA1.

[0065] When reading the short-circuit information of the storage bits and reference bits, S 12 S ref On, S d Disconnect. The current source circuit outputs only one of the first reading current I1 and the second reading current I2, plus the reference current I. ref Generally, a current mirror or other methods can be used to make I1 = I ref Disconnect I2, or equivalently, make I2 = I ref Disconnect I1. Compare the voltage across the parallel resistor of MTJ1 and MTJ2 with the reference resistor R using the voltage-type sensitive amplifier SA1. ref The voltage on the circuit indicates a short circuit.

[0066] The read circuit in this embodiment of the invention performs the reading of data from the storage bit and the reading of short-circuit information in two steps, which increases the reading time compared to a single-ended read circuit. Furthermore, the determination of whether the differential bit is short-circuited compares the resistance of the storage bit and the reference bit connected in parallel with the reference resistance, thus reducing the short-circuit read window. However, it only requires one SA (Self-Alignment), resulting in low area cost.

[0067] Example 2

[0068] On the other hand, one embodiment of the present invention provides a differential bit reading circuit, such as... Figure 2 As shown, the read circuit includes:

[0069] Difference bits, such as Figure 2 As shown in the dashed box, it includes a pair of storage bits and a reference bit. The second end of the storage bit is grounded, and the second end of the reference bit is grounded. In this embodiment, the storage bit includes a first magnetic tunnel junction MTJ1 and a first MOS transistor M1 connected in series, and the reference bit includes a second magnetic tunnel junction MTJ2 and a second MOS transistor M2 connected in series. It should be noted that the structure of the storage bit and the reference bit is not limited to this exemplary structure.

[0070] The first reference resistor R in series ref1 And the third MOSFET M3, the first reference resistor R ref1 The second terminal is grounded through the third MOSFET M3;

[0071] The second reference resistor R connected in series ref2and the fourth MOSFET M4, and the second reference resistor R ref2 The second terminal is grounded through the fourth MOSFET M4;

[0072] A current source circuit is used to generate a first reading current I1, a second reading current I2, and a first reference current I of the same magnitude. ref1 Second reference current I ref2 The first read current I1 is used to generate a first read voltage at the first terminal of the storage bit, and the second read current I2 is used to generate a second read voltage at the first terminal of the reference bit. The first reference current I... ref1 Used in the first reference resistor R ref1 The first terminal generates a first reference voltage, and the second reference current I ref2 Used in the second reference resistor R ref2 The first terminal generates a second reference voltage;

[0073] A first voltage-type sensitive amplifier SA1, the first input terminal of the first voltage-type sensitive amplifier SA1 is connected to the first terminal of the storage bit, and the second input terminal of the first voltage-type sensitive amplifier SA1 is connected to the first terminal of the reference bit;

[0074] The second voltage-type sensitive amplifier SA2 has its first input terminal connected to the first terminal of the storage bit, and its second input terminal connected to the first reference resistor R. ref1 The first end is connected;

[0075] The third voltage-type sensitive amplifier SA3 has its first input terminal connected to the first terminal of the reference bit, and its second input terminal connected to the second reference resistor R. ref2 The first end is connected.

[0076] In one embodiment, the current source circuit may utilize a current mirror structure or other methods to ensure that I1 = I2 = I ref1 =I ref2 .

[0077] In the read circuit of this embodiment, each storage bit and reference bit in the differential bit are configured with a separate SA (Separate SA) to read the short-circuit information of the storage bit and reference bit. The differential bit is further configured with a SA to read the data of the storage bit. Reading the short-circuit information and reading the data of the storage bit are parallel, therefore only one read is needed, without adding delay. The read window when a short circuit is detected is the same as in the single-ended circuit, and the read window is unaffected. However, it requires three SAs, resulting in higher area cost and higher power consumption during reading.

[0078] Example 3

[0079] On the other hand, one embodiment of the present invention provides a differential bit reading circuit, such as... Figure 3 As shown, the read circuit includes:

[0080] Difference bits, such as Figure 3 As shown in the dashed box, it includes a pair of storage bits and reference bits. The second end of the storage bit is connected to the first voltage terminal V1, and the second end of the reference bit is connected to the second voltage terminal V2. In this embodiment, the storage bit includes a first magnetic tunnel junction MTJ1 and a first MOS transistor M1 connected in series, and the reference bit includes a second magnetic tunnel junction MTJ2 and a second MOS transistor M2 connected in series. It should be noted that the structure of the storage bit and the reference bit is not limited to this exemplary structure.

[0081] Series reference resistor R ref And the third MOSFET M3, reference resistor R ref The second terminal is connected to the reference voltage terminal V through the third MOSFET M3. ref ;

[0082] Current-mode sensitive amplifier SA1;

[0083] The gating circuit is used to connect the first input terminal of the current-type sensitive amplifier SA1 to the first terminal of the storage bit to generate the first read current I1 flowing through the storage bit, or to connect the first input terminal of the current-type sensitive amplifier SA1 to the reference resistor R. ref The first end is connected to generate a flow through the reference resistor R. ref Reference current I ref ;

[0084] The gating circuit is also used to connect the second input terminal of the current-type sensitive amplifier SA1 to the first terminal of the reference bit to generate a second reading current I2 flowing through the reference bit, or to connect the second input terminal of the current-type sensitive amplifier SA1 to the reference resistor R. ref The first end is connected to generate a flow through the reference resistor R. ref Reference current I ref .

[0085] In one embodiment, reference Figure 3 The gating circuit includes two 2-to-1 gating switches.

[0086] In this embodiment, reading the data of the storage bit and reading the short-circuit information of the storage bit and the reference bit need to be read serially, requiring three steps:

[0087] When reading data from the stored bits in the differential bit array, the gating circuit connects the first input terminal of the current-type sensitive amplifier to the first terminal of the stored bit array, and connects the second input terminal of the current-type sensitive amplifier to the first terminal of the reference bit array. That is, L1 and L2 are turned on, and L3 and L4 are turned on. Generally, V1 = V2. Because the two MTJs have different resistance values, the current flowing through them is different. The data information of the stored bit array is obtained through the current-type sensitive amplifier SA1.

[0088] When reading the short-circuit information of the stored bits in the differential bits, the gating circuit connects the first input terminal of the current-type sensitive amplifier to the first terminal of the stored bit, and connects the second input terminal of the current-type sensitive amplifier to the reference resistor R. ref The first end is connected. That is, L1 and L2 are conducting, and L3 and L5 are conducting. Generally, V1 = V ref Comparison of current-mode sensitive amplifier SA1 with MTJ1 and reference resistor R ref The current.

[0089] When reading the short-circuit information of the reference bit, the gating circuit connects the first input terminal of the current-mode sensitive amplifier to the reference resistor R. ref The first terminal is connected, and the second input terminal of the current-mode sensitive amplifier is connected to the first terminal of the reference bit. That is, L1 and L5 are turned on, L3 and L4 are turned on, and generally V2 = V ref Comparison of current-mode sensitive amplifier SA1 with MTJ2 and reference resistor R ref The current.

[0090] Understandably, the gating circuit will not connect both the first and second input terminals of the current-mode sensitive amplifier to the reference resistor R simultaneously. ref The first end.

[0091] The read circuit of this invention requires three steps—reading the data in the storage bit and reading the short-circuit information—which increases the read time considerably. Its advantage lies in that the read window for determining a short circuit is the same as that of a single-ended circuit, and only one SA is needed, resulting in low area cost.

[0092] Example 4

[0093] On the other hand, one embodiment of the present invention provides a differential bit reading circuit, such as... Figure 4 As shown, the read circuit includes:

[0094] Difference bits, such as Figure 4As shown in the dashed box, it includes a pair of storage bits and reference bits. The second end of the storage bit is connected to the first voltage terminal V1, and the second end of the reference bit is connected to the second voltage terminal V2. In this embodiment, the storage bit includes a first magnetic tunnel junction MTJ1 and a first MOS transistor M1 connected in series, and the reference bit includes a second magnetic tunnel junction MTJ2 and a second MOS transistor M2 connected in series. It should be noted that the structure of the storage bit and the reference bit is not limited to this exemplary structure.

[0095] Series reference resistor R ref And the third MOSFET M3, reference resistor R ref The second terminal is connected to the reference voltage terminal V through the third MOSFET M3. ref ;

[0096] A first current-type sensitive amplifier SA1 has its first input terminal connected to the first terminal of a storage bit to generate a first read current I1 flowing through the storage bit, and its second input terminal connected to the first terminal of a reference bit to generate a second read current I2 flowing through the reference bit.

[0097] The second current-mode sensitive amplifier SA2 has its second input terminal connected to the reference resistor R. ref The first terminal, to generate a flow through the reference resistor R ref Reference current I ref ;

[0098] The first input terminal of the second current-mode sensitive amplifier SA2 is connected to the third voltage terminal V3 through the fourth MOSFET M4;

[0099] The first input terminal of the second current-mode sensitive amplifier SA2 is connected to the fourth voltage terminal V4 through the fifth MOSFET M5;

[0100] The first current mirror circuit is set between the first voltage terminal V1 and the third voltage terminal V3 to mirror the first reading current I1 in a 1:1 ratio.

[0101] The second current mirror circuit is located between the second voltage terminal V2 and the fourth voltage terminal V4, and is used to mirror the second reading current I2 in a 1:1 ratio.

[0102] In this embodiment, when reading the data of the stored bits in the differential bits, the current flowing through the two MTJs is different. The data information of the stored bits is obtained through the current-type sensitive amplifier. At this time, V1 = V2 is generally set.

[0103] When reading short-circuit information from the storage bit and the reference bit, the magnitudes of the currents flowing through the two MTJs are copied using two current mirrors. The two currents are then added together and compared with the current flowing through the reference resistor R. ref Reference current I ref Comparison. Generally, V is used. ref =V1=V2=V3=V4.

[0104] The reading circuit of this invention requires only one reading step to complete the reading of data information and short-circuit information, but the circuit requires two sensitive amplifiers, occupying a large area. Since the comparison current is the current of the equivalent parallel resistance of MTJ1 and MTJ2 and the reference current, the reading window is also reduced.

[0105] The differential bit readout circuits in the above embodiments can read the data of the stored bits in the differential bits, as well as the short-circuit information between the stored bits and the reference bits. The table below compares the above embodiments in terms of circuit area cost, readout speed, and accuracy of short-circuit detection to meet the needs of different application scenarios.

[0106] Example Circuit area cost Read speed Accuracy of short circuit detection 1 good middle middle 2 Difference good good 3 good Difference good 4 middle good middle

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A differential bit readout circuit, characterized in that, The reading circuit includes: The differential bit includes a pair of storage bits and a reference bit, the second end of the storage bit is grounded, and the second end of the reference bit is grounded; A reference resistor and a third MOSFET are connected in series, with the second terminal of the reference resistor grounded through the third MOSFET; A current source circuit is used to generate a first read current, a second read current, and a reference current of the same magnitude. The first read current is used to generate a first read voltage at the first terminal of the storage bit, the second read current is used to generate a second read voltage at the first terminal of the reference bit, and the reference current is used to generate a reference voltage at the first terminal of the reference resistor. A voltage-type sensitive amplifier, wherein the first input terminal of the voltage-type sensitive amplifier is connected to the first terminal of the storage bit; A first control switch is connected between the first end of the storage bit and the first end of the reference bit; The second control switch is connected between the second input terminal of the voltage-type sensitive amplifier and the first terminal of the reference bit; The third control switch is connected between the second input terminal of the voltage-type sensitive amplifier and the first terminal of the reference resistor.

2. The differential bit reading circuit according to claim 1, characterized in that, The first control switch, the second control switch, and the third control switch are transmission gates controlled by a voltage enable signal.

3. The differential bit reading circuit according to claim 1, characterized in that, When reading data from the storage bit, the first control switch and the third control switch are disconnected, the second control switch is turned on, and the current source circuit only outputs the first read current and the second read current; When the short-circuit information of the storage bit and the reference bit is read, the first control switch and the third control switch are turned on, the second control switch is turned off, and the current source circuit outputs only one of the first read current and the second read current and the reference current.

4. A differential bit reading circuit, characterized in that, The reading circuit includes: The differential bit includes a pair of storage bits and a reference bit, the second end of the storage bit is grounded, and the second end of the reference bit is grounded; A first reference resistor and a third MOSFET are connected in series, with the second terminal of the first reference resistor grounded through the third MOSFET; A second reference resistor and a fourth MOSFET are connected in series, with the second terminal of the second reference resistor grounded through the fourth MOSFET; A current source circuit is used to generate a first read current, a second read current, a first reference current, and a second reference current of the same magnitude. The first read current is used to generate a first read voltage at the first terminal of the storage bit, the second read current is used to generate a second read voltage at the first terminal of the reference bit, the first reference current is used to generate a first reference voltage at the first terminal of the first reference resistor, and the second reference current is used to generate a second reference voltage at the first terminal of the second reference resistor. A first voltage-type sensitive amplifier, wherein the first input terminal of the first voltage-type sensitive amplifier is connected to the first terminal of the storage bit, and the second input terminal of the first voltage-type sensitive amplifier is connected to the first terminal of the reference bit; A second voltage-type sensitive amplifier, wherein the first input terminal of the second voltage-type sensitive amplifier is connected to the first terminal of the storage bit, and the second input terminal of the second voltage-type sensitive amplifier is connected to the first terminal of the first reference resistor; A third voltage-type sensitive amplifier, wherein the first input terminal of the third voltage-type sensitive amplifier is connected to the first terminal of the reference bit, and the second input terminal of the third voltage-type sensitive amplifier is connected to the first terminal of the second reference resistor.

5. The differential bit reading circuit according to claim 4, characterized in that, The current source circuit is a current mirror structure.

6. A differential bit reading circuit, characterized in that, The reading circuit includes: The differential bit includes a pair of storage bits and a reference bit, wherein the second end of the storage bit is connected to a first voltage terminal and the second end of the reference bit is connected to a second voltage terminal; A reference resistor and a third MOSFET are connected in series, with the second terminal of the reference resistor connected to a reference voltage terminal through the third MOSFET; Current-mode sensitive amplifier; A gating circuit is used to connect the first input terminal of the current-type sensitive amplifier to the first terminal of the storage bit to generate a first read current flowing through the storage bit, or to connect the first input terminal of the current-type sensitive amplifier to the first terminal of the reference resistor to generate a reference current flowing through the reference resistor. It is also used to connect the second input terminal of the current-type sensitive amplifier to the first terminal of the reference bit to generate a second reading current flowing through the reference bit, or to connect the second input terminal of the current-type sensitive amplifier to the first terminal of the reference resistor to generate a reference current flowing through the reference resistor.

7. The differential bit reading circuit according to claim 6, characterized in that, The gating circuit includes two 2-to-1 gating switches.

8. The differential bit reading circuit according to claim 6, characterized in that, When reading data from the storage bit, the gating circuit connects the first input terminal of the current-type sensitive amplifier to the first terminal of the storage bit, and connects the second input terminal of the current-type sensitive amplifier to the first terminal of the reference bit. When reading the short-circuit information of the storage bit, the gating circuit connects the first input terminal of the current-type sensitive amplifier to the first terminal of the storage bit, and connects the second input terminal of the current-type sensitive amplifier to the first terminal of the reference resistor. When the short-circuit information of the reference bit is read, the gating circuit connects the first input terminal of the current-type sensitive amplifier to the first terminal of the reference resistor, and connects the second input terminal of the current-type sensitive amplifier to the first terminal of the reference bit.

9. A differential bit reading circuit, characterized in that, The reading circuit includes: The differential bit includes a pair of storage bits and a reference bit, wherein the second end of the storage bit is connected to a first voltage terminal and the second end of the reference bit is connected to a second voltage terminal; A reference resistor and a third MOSFET are connected in series, with the second terminal of the reference resistor connected to a reference voltage terminal through the third MOSFET; A first current-type sensitive amplifier, wherein a first input terminal of the first current-type sensitive amplifier is connected to a first terminal of the storage bit to generate a first read current flowing through the storage bit, and a second input terminal of the first current-type sensitive amplifier is connected to a first terminal of the reference bit to generate a second read current flowing through the reference bit; A second current-mode sensitive amplifier, wherein the second input terminal of the second current-mode sensitive amplifier is connected to the first terminal of the reference resistor; The fourth MOSFET is used to connect the first input terminal of the second current-mode sensitive amplifier to the third voltage terminal. The fifth MOSFET is used to connect the first input terminal of the second current-mode sensitive amplifier to the fourth voltage terminal. The first current mirror circuit is disposed between the first voltage terminal and the third voltage terminal, and is used to mirror the first reading current 1:

1. The second current mirror circuit is located between the second voltage terminal and the fourth voltage terminal to mirror the second reading current in a 1:1 manner.

Images