A single-tube flash memory array of a group pair structure

Abstract

In the single-tube flash memory array of the group pair structure, the virtual storage array is located outside the effective storage array, the virtual storage array comprises a plurality of virtual group pair structures arranged in rows and columns, each virtual group pair structure comprises two virtual storage tubes with connected source electrodes, one column of virtual group pair structures corresponds to one column of group pair storage units, one column of virtual group pair structures is connected to one of a group of bit lines corresponding to the group pair storage units in the same column, the drain electrode of at most one virtual storage tube in one virtual group pair structure is connected to the bit line, in one column of virtual group pair structures, the drain electrodes of at least two virtual storage tubes located at both ends of the column are connected to the corresponding bit line, and the drain electrodes of the remaining virtual storage tubes are connected to the drain electrodes of adjacent virtual storage tubes. By arranging the virtual storage array in this way, the process debugging margin in the flash memory array manufacturing process can be increased, the process precision can be improved, the product yield can be improved, and the virtual storage tube leakage can also be avoided.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a single-tube flash memory array with a pair structure. Background Technology

[0002] Flash memory is a non-volatile semiconductor storage chip that retains its stored data even when power is off. Flash memory is also widely used because it is small in size, consumes little power, and is not easily damaged by physical forces.

[0003] As the capacity of flash memory arrays increases, their area continues to expand. Furthermore, with the advancement of advanced manufacturing processes, the process adjustment margins for photolithography and etching during flash memory array fabrication are becoming increasingly smaller, affecting process accuracy and product yield. Summary of the Invention

[0004] This invention provides a single-tube flash memory array with a paired structure, which can increase the process adjustment margin for photolithography and etching during the fabrication of the single-tube flash memory array with a paired structure, facilitate the adjustment of the manufacturing process, and help improve process accuracy and product yield.

[0005] To achieve the above objectives, the present invention provides a single-tube flash memory array with a pair structure, comprising: an effective memory array including multiple pair memory cells arranged in rows and columns, each pair memory cell including two adjacent effective memory cells connected at their sources; a virtual memory array located outside the effective memory array, including multiple virtual pair structures arranged in rows and columns, each virtual pair structure including two adjacent virtual memory cells connected at their sources; multiple bit lines, two bit lines forming a group; wherein, one column of virtual pair structures corresponds to one column of pair memory cells and is disposed at the end of the corresponding column of pair memory cells; one column of pair memory cells... Each storage cell is connected to a set of bit lines. The drain of one valid storage transistor in the set of storage cells is connected to one of the corresponding bit lines, and the drain of the other valid storage transistor is connected to the other bit line in the corresponding set of bit lines. A column of virtual set-pair structures is connected to one of the bit lines corresponding to the set of storage cells in the same column. At most one virtual storage transistor in a virtual set-pair structure is connected to the bit line. In a column of virtual set-pair structures, the drains of at least two virtual storage transistors located at both ends of the column are connected to a corresponding bit line, and the drains of the remaining virtual storage transistors are connected to the drains of adjacent virtual storage transistors.

[0006] The single-transistor flash memory array with a pair structure includes multiple valid word lines and multiple virtual word lines. The valid memory transistors in a row of the pair memory cells are arranged in two rows, and one valid word line is connected to the gate of the valid memory transistors in a row. The virtual memory transistors in a row of the virtual pair structure are arranged in two rows, and one virtual word line is connected to the gate of the virtual memory transistors in a row.

[0007] Optionally, in a column of the virtual group structure, the drains of the two virtual memory transistors located at both ends of the column are connected to a corresponding bit line, and the drains of the remaining virtual memory transistors are connected to the drains of the adjacent virtual memory transistors.

[0008] Optionally, in a column of virtual pair structures, each pair of adjacent virtual pair structures forms a group; for the four virtual memory tubes of two virtual pair structures in the same group, the drains of the virtual memory tubes on both sides are connected to a corresponding bit line, and the drains of the two virtual memory tubes in the middle are connected to each other.

[0009] Optionally, at least a portion of the virtual word lines are electrically connected together via an upper metal layer.

[0010] Optionally, the initial state of all the virtual memory tubes is programmed to be zero.

[0011] Optionally, the single-tube flash array of the pair structure includes a substrate having multiple active regions, wherein the effective storage tubes and the virtual storage tubes in the same column are formed on the same active region.

[0012] Optionally, the drain of the effective storage tube is provided with a contact hole connected to the corresponding bit line, and the drain of the virtual storage tube connected to the bit line is provided with a contact hole connected to the corresponding bit line.

[0013] Optionally, the active region extends linearly along the column direction.

[0014] Optionally, an active region includes a plurality of first segments extending along a first direction and a plurality of second segments extending along a second direction. The first segments and the second segments are alternately arranged and extend continuously in the extension direction of the active region. Both the first direction and the second direction are inclined relative to the extension direction of the active region. The angle between the first direction and the second direction is greater than 0 degrees and less than 180 degrees. The plurality of active regions are arranged in parallel in the substrate. A pair storage unit or a virtual pair structure is disposed on a first segment, and a pair storage unit or a virtual pair structure is disposed on a second segment.

[0015] The single-tube flash memory array with a pair structure provided by this invention includes an effective memory array and a virtual memory array located outside the effective memory array. Each pair of memory cells in the effective memory array includes two adjacent effective memory cells connected at their sources. Each virtual pair structure in the virtual memory array includes two adjacent virtual memory cells connected at their sources. A column of virtual pair structures corresponds to a column of pair memory cells and is disposed at the end of the corresponding column of pair memory cells. A column of pair memory cells is connected to a set of bit lines. The drain of one effective memory cell in a pair of memory cells is connected to one bit line in the corresponding set, and the drain of the other effective memory cell is connected to another bit line in the corresponding set. A column of virtual pair structures is connected to one bit line in the set corresponding to the pair of memory cells in the same column. In a column of virtual pair structures, the drains of at least two virtual memory cells located at both ends of the column are connected to a corresponding bit line, and at most one virtual memory cell in a virtual pair structure is connected to a corresponding bit line, while the drains of the remaining virtual memory cells are connected to the drains of adjacent virtual memory cells. Adding a virtual memory array outside the effective memory array increases the process adjustment margin for photolithography and etching during the fabrication of single-transistor flash memory arrays with paired structures. This facilitates process adjustment, improves process accuracy, and increases product yield. Furthermore, in a virtual paired structure, at most one virtual memory transistor's drain is connected to a bit line. In a column of virtual paired structures, at least two virtual memory transistors at the ends of the column have their drains connected to a corresponding bit line, while the drains of the remaining virtual memory transistors are connected to the drains of adjacent virtual memory transistors. This ensures that the drain and source of the virtual memory transistors are connected to the same bit line, meaning that the drain and source of the virtual memory transistors are at the same potential, preventing leakage. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the layout of a single-tube flash memory array with a paired structure provided in an embodiment of the present invention.

[0017] Figure 2 This is an architectural diagram of a pair of storage units provided in an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of the layout of a single-tube flash memory array with a pair structure provided in another embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of the active region provided in an embodiment of the present invention.

[0020] Explanation of reference numerals in the attached figures: 101-Active area; 101a-First segment; 101b-Second segment; 102-Isolation structure; 103-Paired memory cell; 103a-Valid memory cell; 104-Bit line; 105-Valid word line; 106-Contact hole; 107-Virtual paired structure; 107a-Virtual memory cell; 108-Virtual word line. Detailed Implementation

[0021] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the single-transistor flash memory array with a paired structure proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0022] Figure 1 This is a schematic diagram of the layout of a single-tube flash memory array with a paired structure provided in an embodiment of the present invention. Figure 2 This is an architectural diagram of a pair of storage units provided in an embodiment of the present invention.

[0023] refer to Figure 1 and Figure 2 As shown, this application provides a single-transistor flash memory array with a pair structure, including an active memory array, a virtual memory array located outside the active memory array, and multiple bit lines 104. The active memory array includes multiple pair memory cells 103 arranged in rows and columns, each pair memory cell 103 including two adjacent active memory cells 103a connected at their sources. The virtual memory array includes multiple virtual pair structures 107 arranged in rows and columns, each virtual pair structure 107 including two adjacent virtual memory cells 107a connected at their sources. Each pair of bit lines 104 forms a group.

[0024] In this configuration, a virtual pair structure 107 corresponds to a pair of memory cells 103 and is located at the end of the corresponding pair of memory cells 103; a pair of memory cells 103 is connected to a set of bit lines 104; the drain of one active memory cell 103a of the pair of memory cells 103 is connected to one of the corresponding bit lines 104, and the drain of the other active memory cell 103a is connected to the other of the corresponding bit lines 104; a virtual pair structure 107 is connected to one of the bit lines 104 corresponding to the pair of memory cells 103 in the same column; at most one virtual memory cell 107a in a virtual pair structure 107 has its drain connected to a bit line 104; in a virtual pair structure 107, at least two virtual memory cells 107a located at both ends of the column have their drains connected to a corresponding bit line 104, and the drains of the remaining virtual memory cells 107a are connected to the drains of adjacent virtual memory cells 107a. In this way, the drain and source of the virtual memory transistor 107a are connected to the same bit line, meaning that the drain and source of the virtual memory transistor 107a are at the same potential, and no leakage current will occur.

[0025] In this embodiment, the two effective storage tubes 103a in the paired storage unit 103 are each independent minimum storage units, that is, each minimum storage unit contains one effective storage tube, and each effective storage tube 103a can independently store data (binary data), thereby achieving a storage density of 1T.

[0026] In this application, the two active memory transistors 103a of the paired memory cell 103 are identical memory transistors, and the two virtual memory transistors 107a of the virtual paired structure 107 are identical memory transistors. The active memory transistors 103a and the virtual memory transistors 107a are identical memory transistors; "identical" means identical in both size and structure. Thus, the single-transistor flash memory array with this paired structure contains only a single device, has a symmetrical structure, a simple layout, and all memory transistors are identical in size and process, facilitating the acquisition (fabrication) of the single-transistor flash memory array with the paired structure and helping to reduce manufacturing costs.

[0027] In one embodiment of this application, both the effective storage tube 103a and the virtual storage tube 107a can be charge-trap type storage tubes. This results in a lower vertical height of the storage tubes, which facilitates continuous miniaturization with the iteration of process technology and can be applied to 3D storage technology. In another embodiment of this application, both the effective storage tube 103a and the virtual storage tube 107a can be floating-gate type storage tubes, but are not limited thereto.

[0028] A single-tube flash memory array with a paired structure includes a substrate, such as Figure 1As shown, the substrate has multiple active regions 101 and isolation structures 102 separating the multiple active regions 101. The source and drain of the active memory transistor 103a and the virtual memory transistor 107a are formed in the active region 101, and the gate can be formed on the active region 101. The active memory transistor 103a and the virtual memory transistor 107a in the same column are formed on the same active region 101, that is, the active memory transistor 103a and the virtual memory transistor 107a located on one active region 101 are in a column.

[0029] In one embodiment of this application, as Figure 1 As shown, the active region 101 extends in a straight line along the column direction.

[0030] refer to Figure 1 As shown, the drain of the effective storage tube 103a is provided with a contact hole 106 connected to the corresponding bit line 104, and the drain of the virtual storage tube 107a connected to the bit line 104 is provided with a contact hole 106.

[0031] To achieve the connection between the two active memory transistors 103a of the paired memory cell 103 and the corresponding set of bit lines 104, as follows: Figure 1 As shown, the sum of the spacing between the two contact holes 106 on the drain of the two effective storage tubes 103a of a pair of storage structures 103 in the width direction of the active region 101 and the width of the two contact holes 106 is the first width W1, and the width of the active region 101 is the second width W2. The second width W2 needs to be greater than or equal to the first width W1.

[0032] Figure 3 This is a schematic diagram of the layout of a single-tube flash memory array with a pair structure provided in another embodiment of the present invention. Figure 4 This is a schematic diagram of the active region provided in an embodiment of the present invention. (See reference...) Figure 3 and Figure 4As shown, in another embodiment of this application, the active region 101 in the substrate extends curvedly in its extension direction X3. Specifically, an active region 101 may include a plurality of first segments 101a extending along a first direction X1 and a plurality of second segments 101b extending along a second direction X2. The first segments 101a and the second segments 101b are alternately arranged and extend continuously to each other in the extension direction X3 of the active region 101. Both the first direction X1 and the second direction X2 are inclined relative to the extension direction X3 of the active region 101, and the included angle between the first direction X1 and the second direction X2 is greater than 0 degrees and less than 180 degrees. The plurality of active regions 101 extend in parallel in the substrate. A pair memory unit 103 or a virtual pair structure 107 is provided on a first segment 101a, and a pair memory unit 103 or a virtual pair structure 107 is provided on a second segment 101b. This approach, while ensuring the connection between the paired memory cells 103 and the corresponding set of bit lines 104, avoids limiting the width of the active region 101 by the width of the contact holes on the paired memory cells 103 and the spacing between the two bit lines 104 in the same group. Consequently, the width of the active region 101 can be reduced, and the space of the isolation structure 102 between the active regions 101 can be expanded. This facilitates further miniaturization of the paired single-tube flash memory array, which is beneficial for reducing the area of ​​the flash memory array or improving the integration density of the flash memory array.

[0033] refer to Figure 4 As shown, in this embodiment, the sum of the distance between the two contact holes 106 on the drains of the two active storage transistors 103a of a pair of storage cells 103 in the active region width direction and the width of the two contact holes 106 is the first width W1, and the width of the active region 101 is the second width W2, which is smaller than the first width W1. The distance between the two contact holes 106 on the drains of the two active storage transistors 103a of a pair of storage cells 103 in the active region width direction is related to the distance between the two bit lines in the same group.

[0034] In one embodiment, reference Figure 3 and Figure 4 As shown, the first segment 101a of the active region 101 can extend linearly in the first direction X1, and the second segment 101b of the active region 101 can extend linearly in the second direction X2. The active region 101 generally extends in the X3 direction. In another embodiment, both the first and second segments of the active region 101 can extend in an arc in a set direction. In other embodiments, one of the first and second segments of the active region 101 can extend linearly while the other can extend in an arc.

[0035] In one embodiment, reference Figure 4As shown, the length of the first segment 101a in the extension direction X3 of the active region 101 is L1, and the length of the second segment 101b in the extension direction X3 of the active region 101 is L2. L1 and L2 can be equal, which facilitates the arrangement of bit lines 104, but is not limited to this.

[0036] For example, the first direction X1 and the second direction X2 point to both sides of the extension direction X3 of the active region 101; the angle between the first direction X1 and X3 and the angle between the second direction X2 and X3 can be equal, but are not limited thereto. It should be noted that the first segment 101a can be understood as extending along the positive or negative direction of the first direction X1, the second segment 101b can be understood as extending along the positive or negative direction of the second direction X2, and the active region 101 can be understood as extending along the positive or negative direction of the third direction X3.

[0037] For example, multiple active memory tubes 103a of the active memory array and multiple virtual memory tubes 107a of the virtual memory array are all formed on the same well region of the substrate. (Refer to...) Figure 2 As shown, each effective memory cell 103a has a substrate end, and the substrate end is connected to the well connection line VPwell. However, as... Figure 1 As shown, in the actual layout of a single-tube flash memory array with a pair structure, the well region of the substrate is the well region connection line VPwell, and applying voltage to the well region connection line VPwell is equivalent to applying voltage to the well region in the substrate.

[0038] In this embodiment, the well region can be P-type, and both the effective memory transistor 103a and the virtual memory transistor 107a can be N-type memory transistors. In another embodiment, the well region can be N-type, and both the effective memory transistor 103a and the virtual memory transistor 107a can be P-type memory transistors.

[0039] In this embodiment, two active storage tubes 103a in the same pair of storage cells 103 can share the same source region, and no contact hole 106 is required between the two active storage tubes 103a in the same pair of storage cells 103. One active storage tube 103a in one pair of storage cells 103 and another active storage tube 103a in the same column and adjacent to it in another pair of storage cells 103 share a drain region, and a contact hole 106 is provided on the shared drain region. In this way, the active region area can be effectively utilized, which helps to improve the storage density.

[0040] In this embodiment, two virtual memory transistors 107a in the same virtual pair structure 107 can share the same source region, and no contact hole 106 is required between the two virtual memory transistors 107a in the same virtual pair structure 107; one virtual memory transistor 107a in one virtual pair structure 107 and one virtual memory transistor 107a in another virtual pair structure 107 in the same column and adjacent to each other share the drain region. In this way, the active area can be effectively utilized, which helps to improve the storage density.

[0041] like Figure 1 and Figure 3 As shown, multiple bit lines 104 (BL) are located on the substrate and extend along the extension direction X3 of the active region 101. Two bit lines 104 form a group, and a pair of memory cells 103 are connected to a corresponding pair of bit lines 104. The drain of one active memory cell 103a of the pair of memory cells 103 is connected to one of the corresponding bit lines 104, and the drain of the other active memory cell 103a is connected to the other of the corresponding bit lines 104. A virtual pair structure 107 is connected to one of the bit lines 104 corresponding to the pair memory cells 103 in the same column, but not to the other bit line in the same group; the drain of at most one virtual memory tube 107a in a virtual pair structure 107 is connected to the bit line 104; in a virtual pair structure 107, the drains of at least two virtual memory tubes 107a located at both ends of the column are connected to the corresponding bit line 104, and the drains of the remaining virtual memory tubes 107a are connected to the drains of the adjacent virtual memory tubes 107a.

[0042] In one embodiment of this application, as Figure 1 As shown, in a column of virtual group pairs 107, each pair of virtual group pairs 107 forms a group; for the four virtual memory transistors 107a of two virtual group pairs 107 in the same group, the drains of the two virtual memory transistors 107a on both sides are connected to a corresponding bit line 104, and the drains of the two virtual memory transistors 107a in the middle are connected to each other. More detailed... Figure 1 This diagram shows four virtual memory tubes 107a in a column virtual grouping structure 107, with the column direction being... Figure 1 In the vertical direction, the first column group on the left corresponds to a set of bit lines BL for memory cell 103. m-2 and BL m-1 In the first column of virtual group structure 107, in the top-to-bottom direction, the drains of the first virtual memory tube 107a and the fourth virtual memory tube 107a are connected to the bit line BL through contact holes 106. m-2 The second and third virtual memory transistors 107a share a common source, and none of the four virtual memory transistors 107a are connected to the bit line BL. m-1 connect.

[0043] In another embodiment of this application, in a column of virtual group structure 107, the drains of two virtual memory tubes 107a located at both ends of the column are connected to a corresponding bit line 104, and the drains of the remaining virtual memory tubes 107a are all connected to the drains of adjacent virtual memory tubes 107a.

[0044] In other embodiments, four or eight adjacent virtual group pairs 107 can be grouped together, and in a group of virtual group pairs 107, only the drains of the virtual memory tubes 107a located at both ends of the column are connected to a corresponding bit line 104. The number of virtual group pairs 107 in a column of virtual group pairs 107 can be set according to actual needs.

[0045] For example, virtual storage arrays can be set up on both sides of the effective storage array, but this is not a limitation.

[0046] refer to Figure 1 and Figure 3 As shown, the single-transistor flash memory array with a paired structure includes multiple active word lines 105 and multiple virtual word lines 108. For example, the multiple active word lines 105 include WL0, WL1, WL2, WL3, and WL4, and the multiple virtual word lines 108 include WL1, WL2, WL3, and WL4. d1 WL d2 WL d3 and WL d4 Both the effective word line 105 and the virtual word line 108 extend along the row direction. In a row of paired storage cells 103, the effective storage transistors 103a are arranged in two rows, with one effective word line 105 connecting to the gate of each row of effective storage transistors 103a. Similarly, in a row of paired virtual storage cells 107a, the virtual storage transistors 107a are arranged in two rows, with one virtual word line 108 connecting to the gate of each row of virtual storage transistors 107a. The effective word line 105 and the virtual word line 108 can be made of the same material, such as polysilicon, but are not limited to this.

[0047] For example, at least a portion of the virtual word lines 108 are electrically connected together via an upper metal layer. For instance, all virtual word lines 108 on the same side of the effective memory array can be connected together, which facilitates simultaneous operation of multiple virtual word lines and saves wiring space, but is not limited thereto.

[0048] For example, during the initial testing phase of a chip including a single-tube flash memory array with a pair structure, the initial state of all virtual memory tubes 107a can be programmed to zero, that is, the threshold voltage Vt of the virtual memory tubes 107a is in a high state, which can prevent leakage.

[0049] For the single-tube flash memory array with a pair structure of this application, when data is written and read from one of the two effective storage tubes 103a in the same pair storage cell 103, the other acts as a selection tube. That is, the two effective storage tubes 103a in the same pair storage cell 103 can act as selection tubes for each other, and the two bit lines 104 corresponding to the pair storage cell 103 can act as source lines for each other. Compared with the 2T storage array which requires special selection tubes and the structure of setting one bit line and one fixed source line at the same time in the conventional technology, this helps to reduce the power consumption of the flash memory array when performing data writing and data reading operations, simplifies the peripheral high-voltage auxiliary circuit of the flash memory array, saves physical space of the pair storage cell 103, and increases the storage density of the storage cell array. Moreover, this can reduce the length of the bit line metal line, which helps to improve the voltage drop (IR Drop) of the line resistance of the storage array.

[0050] During data writing operations, the voltages of the two bit lines 104 in the same group can be applied independently. When the two bit lines 104 in the same group are applied with the same voltage, the effective storage transistors 103a connected to the two bit lines 104 have no channel current, which helps to further reduce the power consumption during data writing operations.

[0051] The single-tube flash memory array with a pair structure provided by this invention includes an effective memory array and a virtual memory array located outside the effective memory array. Each pair of memory cells 103 in the effective memory array includes two adjacent effective memory cells 103a connected at their sources. Each virtual pair structure 107 in the virtual memory array includes two adjacent virtual memory cells 107a connected at their sources. A row of virtual pair structures 107 corresponds to a row of pair memory cells 103 and is disposed at the end of the corresponding row of pair memory cells 103. This addition of a virtual memory array outside the effective memory array increases the process adjustment margin for photolithography and etching during the fabrication of the single-tube flash memory array with a pair structure, facilitating process adjustment and improving process accuracy and product yield. Furthermore, a row of pair memory cells 103 is connected to a set of bit lines 104. The drain of one effective memory cell 103a is connected to one of the corresponding bit lines 104, and the drain of another effective memory cell 103a is connected to the other of the corresponding bit lines. A column of virtual pairing structures 107 connects only one of the bit lines 104 corresponding to the pair of memory cells 103 in the same column. At most one virtual memory cell 107a in a virtual pairing structure 107 has its drain connected to the bit line 104. In a column of virtual pairing structures 107, at least two virtual memory cells 107a located at both ends of the column have their drains connected to one of the corresponding bit lines 104, and the drains of the remaining virtual memory cells 107a are connected to the drains of adjacent virtual memory cells 107a. In this way, the drain and source of the virtual memory cell 107a are connected to the same bit line 104, that is, the drain and source of the virtual memory cell 107a are at the same potential, and no leakage current will be generated.

[0052] In the embodiments of this application, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more. In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "exemplarily," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0053] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A single-transistor flash memory array with a paired structure, characterized in that, include: An effective storage array comprising multiple pairs of storage cells arranged in rows and columns, each pair of storage cells comprising two adjacent and source-connected effective storage tubes; A virtual storage array, located outside the effective storage array, includes multiple virtual pair structures arranged in rows and columns, each of the virtual pair structures including two adjacent virtual storage tubes connected at their sources; Multiple bit lines, with two bit lines forming a group; In this configuration, when writing and reading data from one of the two active storage transistors in the paired storage unit, the other acts as a selection transistor. A column of virtual paired structures corresponds to a column of paired storage units and is located at the end of the corresponding column. A column of paired storage units is connected to a set of bit lines; the drain of one active storage transistor in the paired storage unit is connected to one of the corresponding bit lines, and the drain of the other active storage transistor is connected to the other bit line. A column of virtual paired structures is connected to one of the bit lines corresponding to the paired storage units in the same column, but not connected to the other bit line. In a column of virtual paired structures, the drains of at least two virtual storage transistors located at both ends of the column are connected to a corresponding bit line, and the drains of the remaining virtual storage transistors are connected to the drains of adjacent virtual storage transistors. The single-transistor flash memory array with a pair structure includes multiple valid word lines and multiple virtual word lines. The valid memory transistors in a row of the pair memory cells are arranged in two rows, and one valid word line is connected to the gate of the valid memory transistors in a row. The virtual memory transistors in a row of the virtual pair structure are arranged in two rows, and one virtual word line is connected to the gate of the virtual memory transistors in a row.

2. The single-transistor flash memory array with a paired structure as described in claim 1, characterized in that, In a column of the virtual group structure, the drains of the two virtual memory transistors located at both ends of the column are connected to a corresponding bit line, and the drains of the remaining virtual memory transistors are connected to the drains of the adjacent virtual memory transistors.

3. The single-transistor flash memory array with a paired structure as described in claim 1, characterized in that, In a column of virtual pair structures, each pair of virtual pair structures is a group; for the four virtual memory tubes of two virtual pair structures in the same group, the drains of the virtual memory tubes on both sides are connected to a corresponding bit line, and the drains of the two virtual memory tubes in the middle are connected to each other.

4. The single-transistor flash memory array with a paired structure as described in claim 1, characterized in that, At least a portion of the virtual word lines are electrically connected together via an upper metal layer.

5. The single-transistor flash memory array with a paired structure as described in claim 1, characterized in that, The initial state of all the virtual memory tubes is programmed to be zero.

6. The single-transistor flash memory array with a paired structure as described in claim 1, characterized in that, The single-tube flash array with a paired structure includes a substrate having multiple active regions, and the active memory tubes and the virtual memory tubes in the same column are formed on the same active region.

7. The single-transistor flash memory array with a pair structure as described in claim 6, characterized in that, The drain of the effective storage tube is provided with a contact hole that is connected to the corresponding bit line, and the drain of the virtual storage tube connected to the bit line is provided with a contact hole that is connected to the corresponding bit line.

8. The single-transistor flash memory array with a pair structure as described in claim 6, characterized in that, The active region extends in a straight line along the column direction.

9. The single-transistor flash memory array with a pair structure as described in claim 6, characterized in that, An active region includes a plurality of first segments extending along a first direction and a plurality of second segments extending along a second direction, the first segments and the second segments being alternately arranged and extending continuously to each other in the extension direction of the active region, both the first direction and the second direction being inclined relative to the extension direction of the active region, and the included angle between the first direction and the second direction being greater than 0 degrees and less than 180 degrees. The plurality of said active regions are arranged in parallel and extend in the substrate; A first segment is provided with a pair storage unit or a virtual pair structure, and a second segment is provided with a pair storage unit or a virtual pair structure.

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