A method of fault testing

Abstract

The application discloses a fault test method, relates to the technical field of fault test, and comprises the following steps: in response to receiving a fault test instruction, analyzing the fault test instruction, and determining a fault test mode; in response to the fault test mode being an impedance mutation test, acquiring storage parameters of a storage unit and determining an impedance baseline; generating an impedance calibration signal based on the impedance baseline and delivering the impedance calibration signal to a fault simulation unit, so that the fault simulation unit performs impedance calibration; acquiring an impedance calibration residual returned by the fault simulation unit, determining impedance mutation simulation parameters based on the impedance calibration residual; and generating an impedance mutation simulation control signal based on the impedance mutation simulation parameters and delivering the impedance mutation simulation control signal to the fault simulation unit, so that the fault simulation unit applies an impedance mutation in a data storage link. The application can apply an impedance mutation to the storage unit in the data storage link, thereby solving the problem that there is a lack of controllable simulation of link transient impedance mutation in the prior art, and improving the comprehensiveness of fault test.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of fault testing, in particular to a fault testing method. BACKGROUND

[0002] In a data storage system, fault testing is an important link to ensure the reliability and stability of the equipment. It mainly verifies the performance of the storage link in the abnormal state by artificially introducing abnormalities, so as to evaluate the fault tolerance capability and recovery mechanism of the controller, the storage unit and the related circuit.

[0003] However, the related art does not consider the scenario of link transient impedance mutation, that is, the sudden deviation of the link impedance in a short time caused by factors such as poor connector contact, board-level interconnection defects or transient electromagnetic interference in the storage link. The impedance mutation will cause signal reflection enhancement, waveform distortion or link transient interruption, and has randomness and concealment in the actual running environment, which has a significant impact on the stability and data reliability of the high-speed storage link. The existing testing means cannot effectively reproduce this type of abnormal process, so it is difficult to verify the robustness and data reliability of the storage link under dynamic failure. SUMMARY

[0004] The present application provides a fault testing method capable of applying impedance mutation to the storage unit in the data storage link, to at least solve the problem of lack of controllable simulation of link transient impedance mutation in the related art, and difficulty in verifying the robustness and data reliability of the storage link under dynamic failure.

[0005] The present application provides a fault testing method applied to a controller in a data storage link, the data storage link further comprising a controller, a storage unit, and a fault simulation unit connected with the controller and the storage unit respectively, the method comprising:

[0006] In response to receiving a fault testing instruction, parsing the fault testing instruction, and determining a fault testing mode;

[0007] In response to the fault testing mode being impedance mutation testing, obtaining the storage parameters of the storage unit and determining an impedance baseline;

[0008] Generating an impedance calibration signal based on the impedance baseline and delivering it to the fault simulation unit to make the fault simulation unit perform impedance calibration;

[0009] Obtaining the impedance calibration residual returned by the fault simulation unit, and determining the impedance mutation simulation parameters based on the impedance calibration residual;

[0010] Based on the impedance mutation simulation parameters, generating an impedance mutation simulation control signal and delivering it to the fault simulation unit, so that the fault simulation unit applies impedance mutation in the data storage link according to the impedance mutation simulation control signal;

[0011] In response to the data storage link being applied with the impedance mutation, the performance of the storage unit is recorded to obtain a fault test result.

[0012] According to the application, since the link impedance baseline is determined in the controller based on the storage parameters of the storage unit, and the controlled impedance mutation is applied to the data storage link by the fault simulation unit, the link experiences transient impedance change under controlled conditions, causing performance fluctuations or potential abnormalities of the storage unit, so that the fault phenomenon can be observed and recorded during the test process, thereby effectively verifying the fault tolerance and data reliability of the storage unit under sudden impedance interference, improving the coverage and accuracy of the fault test, and solving the problem of lack of impedance mutation simulation capability in the existing fault test technology. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings described in the following are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0014] Figure 1 An application environment schematic diagram provided for the embodiments of the present application;

[0015] Figure 2 A fault test method schematic diagram provided for the embodiments of the present application;

[0016] Figure 3 A fault test step schematic diagram provided for the embodiments of the present application;

[0017] Figure 4 A fault test flowchart provided for the embodiments of the present application;

[0018] Figure 5 A data storage link architecture schematic diagram provided for the embodiments of the present application;

[0019] Figure 6 A fault test method timing diagram provided for the embodiments of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0021] It should be noted that in the description of the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0022] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.

[0023] The fault test method provided by the present application can be applied to an application environment as shown in Figure 1 The terminal 102 communicates with the server 104 through the network. The user sends a fault test instruction to the server 104 through the terminal 102. The controller deployed in the server 104 receives the test instruction, analyzes and determines the fault test mode, such as the impedance mutation test mode. The controller obtains the storage parameters of the storage unit, determines the link impedance baseline, generates the impedance calibration signal based on the impedance baseline, and sends it to the fault simulation unit, so that the fault simulation unit performs impedance calibration. The controller further obtains the impedance calibration residual returned by the fault simulation unit, determines the impedance mutation simulation parameters based on the residual, and generates the impedance mutation simulation control signal and sends it to the fault simulation unit. The fault simulation unit applies a controlled impedance mutation in the data storage link according to the control signal, thereby simulating the performance change of the storage unit under the link impedance abnormal condition, and realizing the fault test of the storage unit. The terminal 102 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices. The server 104 can be implemented by an independent server or a server cluster composed of multiple servers. The server 104 includes at least one controller and one or more storage units connected thereto, and a fault simulation unit connected to the controller and the storage unit respectively. In a specific embodiment, the storage unit is preferably a SATA or NVMe interface hard disk, and its capacity ranges from 256GB to 20TB. The link impedance mutation refers to the phenomenon that the link impedance deviates from the baseline impedance by ±10-50Ω within a time scale of 10ns to 1μs.

[0024] In one embodiment, as shown in Figure 2 The present application provides a fault test method, which comprises:

[0025] Step 201, in response to receiving a fault test instruction, analyzing the fault test instruction and determining a fault test mode;

[0026] In step 202, in response to the fault test mode being an impedance mutation test, a storage parameter of the storage unit is acquired and an impedance baseline is determined;

[0027] In step 203, an impedance calibration signal is generated based on the impedance baseline and is sent to the fault simulation unit, so that the fault simulation unit performs impedance calibration;

[0028] In step 204, an impedance calibration residual returned by the fault simulation unit is acquired, and an impedance mutation simulation parameter is determined based on the impedance calibration residual;

[0029] In step 205, an impedance mutation simulation control signal is generated based on the impedance mutation simulation parameter and is sent to the fault simulation unit, so that the fault simulation unit applies an impedance mutation in the data storage link according to the impedance mutation simulation control signal;

[0030] In step 206, in response to the data storage link being applied with the impedance mutation, a performance of the storage unit is recorded to obtain a fault test result.

[0031] The fault test method provided in the application determines a link impedance baseline in the controller based on a storage parameter of the storage unit, and applies a controlled impedance mutation to the data storage link by using the fault simulation unit, so that the link experiences transient impedance change under controlled conditions, causing performance fluctuation or potential abnormality of the storage unit, making the fault phenomenon observable and recordable in the test process, thereby being able to effectively verify the fault tolerance capability and data reliability of the storage unit under sudden impedance interference, and improving the coverage and accuracy of the fault test.

[0032] In one embodiment, acquiring the storage parameter of the storage unit and determining the impedance baseline comprises:

[0033] The storage parameter is analyzed to obtain an interface type of the storage unit, a maximum transmission rate of the storage unit, and a link wire length;

[0034] According to the interface type of the storage unit and the maximum transmission rate of the storage unit, a target impedance value of the link and a tolerance range are determined;

[0035] According to the link wire length, a signal propagation delay is obtained, and an impedance sampling window is determined;

[0036] According to pre-stored board-level design data, a link trace width and a dielectric constant of a link medium are obtained, for a plurality of preset termination configurations, a plurality of predicted impedance values of the link within the impedance sampling window are respectively calculated, and the termination configuration includes an adjustable resistance gear and an operation scheme of a terminal element combination executable by the fault simulation unit;

[0037] The predicted impedance value of the link and the target impedance value of the link are compared to obtain an impedance deviation value, and if the impedance deviation value is within the tolerance range, the corresponding termination configuration is taken as a candidate termination configuration.

[0038] One or more of the selected candidate termination configurations are sequentially sent to the fault simulation unit, and the baseline termination configuration and the corresponding impedance baseline are determined based on the component resistance adjustment results fed back by the fault simulation unit.

[0039] In one embodiment, the step of sequentially sending one or more of the selected candidate termination configurations to the fault simulation unit, and determining the baseline termination configuration and the corresponding impedance baseline based on the component resistance adjustment results fed back by the fault simulation unit, includes:

[0040] Based on one or more candidate termination configurations selected, configuration control signals are generated sequentially and sent to the fault simulation unit so that the fault simulation unit can adjust physical components to achieve the corresponding link predicted impedance value.

[0041] Within the impedance sampling window, the actual impedance value of the link is measured, and the actual impedance value of the link is compared with the target impedance value of the link. The candidate termination configuration with the smallest difference between the actual impedance value of the link and the target impedance value of the link is determined as the baseline termination configuration, and the actual impedance value of the link corresponding to the baseline termination configuration is taken as the impedance baseline.

[0042] If the impedance deviation between the predicted impedance value and the target impedance value of the link in the preset multiple termination configurations exceeds the tolerance range, then the multiple termination configurations are adjusted or a compensation strategy is generated, and the configuration control signal is regenerated and sent out until the impedance baseline is obtained.

[0043] In one specific embodiment, the storage parameters of the storage unit include interface type (such as SATA III), maximum transfer rate (such as 6Gb / s), and link connection length (20–200mm). The link impedance baseline is determined based on the storage parameters, wherein the target link impedance value is preferably 50Ω and the tolerance range is ±5%.

[0044] Specifically, in this embodiment, by analyzing the interface type, maximum transmission rate, and link connection length of the storage unit, and combining the board-level design data to calculate the predicted impedance value of the link, and screening candidate termination configurations, the target impedance value and impedance baseline of the link can be accurately determined. This allows the controller to fully understand the physical characteristics of the link before generating the impedance calibration signal, thereby achieving precise impedance adjustment and calibration, providing a reliable benchmark for subsequent impedance change simulation, and ensuring the authenticity and effectiveness of the simulation test.

[0045] In one embodiment, if the impedance deviation between the predicted link impedance value and the target link impedance value of multiple preset termination configurations exceeds the tolerance range, then the multiple termination configurations are adjusted or a compensation strategy is generated, and the configuration control signal is regenerated and sent out until an impedance baseline is obtained, including:

[0046] The controller adjusts the preset termination configuration step by step based on the pre-stored electrical parameter range to reduce the impedance deviation, specifically including:

[0047] Adjusting the resistance value, such as the controller driving the digital potentiometer to switch the resistance value position, so that the overall impedance converges to the target value;

[0048] Adjusting the capacitance configuration, such as the controller selecting whether to enable the parallel capacitance unit, to correct the high-frequency end impedance;

[0049] Adjusting the inductance configuration, such as the controller selecting whether to enable the series inductance unit, to improve the low-frequency end impedance stability;

[0050] When the controller attempts to adjust the preset termination configuration multiple times and still cannot make the impedance deviation value meet the tolerance range, it is determined that the predicted impedance cannot be converged to the target range through conventional resistance, capacitance, and inductance adjustment, and a compensation strategy is generated, including but not limited to:

[0051] Physical layer compensation, such as the controller issuing a signal to enable additional controllable impedance units (such as a fine-tunable resistance array) to achieve fine-tuning in smaller steps;

[0052] Protocol layer compensation, such as the controller issuing a configuration to make the link insert a specific calibration sequence during data transmission, thereby facilitating the use of equalization circuits at the receiving end to offset the effects of impedance mismatch;

[0053] Algorithm compensation, such as the controller performing fitting calculation based on historical adjustment data to calculate the possible best impedance correction combination and generate new configuration control signals;

[0054] The controller generates configuration control signals based on the adjusted or compensated scheme and issues them to the fault simulation unit, measures the actual impedance value of the link within the impedance sampling window, and judges the difference between it and the target impedance value. If it still does not meet the target range, the previous steps are re-executed until the impedance baseline with the smallest difference from the target impedance value is determined.

[0055] In a preferred embodiment, the digital potentiometer position is preferably 0-100Ω with a step of 1Ω; the parallel capacitance unit range is 0-50pF; and the series inductance unit range is 0-20nH.

[0056] Specifically, in the embodiment, the link impedance is converged to the target range by adjusting the termination configuration and necessary compensation step by step, ensuring the accuracy of the baseline measurement; at the same time, combined with the compensation strategies of the physical layer, the protocol layer and the algorithm layer, the accurate baseline is obtained as the reference point, which is beneficial to the implementation of the mutation simulation in the fault test, and ensures the controllability and reliability of the mutation process; in addition, the controller automatically generates the control signal, measures and evaluates the impedance, reduces the manual intervention, and improves the efficiency and repeatability of the impedance baseline acquisition.

[0057] In one embodiment, the fault simulation unit performs impedance calibration, including:

[0058] In response to receiving the impedance calibration signal issued by the controller, the impedance baseline is obtained by analysis, and the calibration target value is determined;

[0059] According to the calibration target value, the resistance position of the fault simulation unit is adjusted, and the current impedance value of the link is measured;

[0060] The difference between the current impedance value of the link and the calibration target value is taken as the impedance calibration intermediate difference value, and is sent to the controller for the controller to judge whether the impedance calibration intermediate difference value is within the tolerance range and generate a corresponding verification signal;

[0061] In response to receiving the verification signal representing yes, the impedance calibration intermediate difference value is taken as the impedance calibration residual error, and is fed back to the controller combined with the current timestamp;

[0062] In response to receiving the verification signal representing no, the resistance position of the fault simulation unit is readjusted, the impedance calibration intermediate difference value is updated and re-sent to the controller.

[0063] Specifically, in the embodiment, the fault simulation unit performs impedance calibration and feeds back the calibration intermediate difference value to the controller, and judges whether it is within the tolerance range combined with the verification signal, which can realize the closed-loop calibration mechanism, and when the calibration does not meet the requirements, the resistance position can be readjusted for iterative correction, thereby ensuring that the link impedance is highly consistent with the target value, improving the precision of the impedance baseline, providing a stable foundation for subsequent impedance mutation simulation, and avoiding test errors or test failures due to calibration deviation.

[0064] In one embodiment, the fault simulation unit includes a digital potentiometer array, obtains the impedance calibration residual error returned by the fault simulation unit, and determines the impedance mutation simulation parameters based on the impedance calibration residual error, including:

[0065] According to the returned impedance calibration residual error, a link impedance deviation vector is determined, and the link impedance deviation vector includes a link impedance deviation direction and a link impedance deviation amplitude;

[0066] The gear adjustment amount of the digital potentiometer array is set to be proportional to the magnitude of the link impedance deviation, and the direction of the gear adjustment amount is set to be consistent with the direction of the link impedance deviation. The link impedance deviation vector is converted into the gear adjustment amount according to the gear parameter of the digital potentiometer array.

[0067] An impedance mutation simulation parameter is generated based on the gear adjustment amount, and a mutation simulation threshold is set for the impedance mutation simulation parameter.

[0068] An impedance mutation simulation control signal is generated based on the impedance mutation simulation parameter and the mutation simulation threshold, and is sent to the digital potentiometer array.

[0069] Specifically, in the present embodiment, the impedance calibration residual is converted into a link impedance deviation vector, and an impedance mutation simulation parameter is generated based on the digital potentiometer gear, so that the controller can accurately control the impedance adjustment amount and direction of each channel. At the same time, the mutation simulation threshold is set to ensure that the applied impedance mutation is controlled and quantifiable, thereby realizing fine control of the impedance mutation simulation, making the simulated link exception fully reflect the actual fault scenario, and improving the repeatability and accuracy of the fault test.

[0070] In one embodiment, the digital potentiometer array includes a plurality of potentiometer channels, and the fault simulation unit applies an impedance mutation in the data storage link according to the impedance mutation simulation control signal, including:

[0071] In response to receiving the impedance mutation simulation control signal, the impedance mutation simulation parameter, the mutation simulation threshold, the mutation trigger time specified by the controller, and the mutation duration are parsed;

[0072] Based on the impedance mutation simulation parameter, the target resistance value of the plurality of potentiometer channels is determined, and the target resistance value is linearly constrained and planned based on the mutation simulation threshold, so that the theoretical resistance value mutation amplitude applied by the plurality of potentiometer channels is less than or equal to the mutation simulation threshold;

[0073] In response to the system clock reaching the mutation trigger time, the resistance value of the plurality of potentiometer channels is adjusted from the initial value to the target resistance value, and is maintained to the mutation end time determined by the mutation trigger time and the mutation duration;

[0074] In response to the system clock reaching the mutation end time, the resistance value of the plurality of potentiometer channels is restored to the initial value.

[0075] In a preferred embodiment, the impedance mutation simulation amplitude is preferably ±5-20Ω, the mutation duration is 10ns-1μs, and the mutation trigger time is triggered based on the system clock and has an error of not more than ±1ns.

[0076] Specifically, in the embodiment, by linearly constraining the target resistance value of the digital potentiometer channel, and combining the trigger time and the mutation duration to achieve dynamic adjustment, it can ensure that the impedance mutation applied by each channel meets the preset threshold, and the adjustment and recovery are completed within the specified time window, which is conducive to realizing controlled and predictable impedance mutation process, and at the same time realizing controlled fault excitation of the storage unit, which is conducive to verifying the performance of the storage link under transient impedance anomaly.

[0077] As shown in Figure 3 In one embodiment, before generating the impedance mutation simulation control signal and issuing it to the fault simulation unit, the following steps are further included:

[0078] Step 301, obtaining historical data of the storage unit, combining storage parameters of the storage unit, predicting a probability of subsequent impedance mutation failure of the storage unit, and generating a fault risk factor;

[0079] Step 302, mapping and scaling the impedance mutation simulation parameters according to the fault risk factor to obtain risk-associated impedance mutation simulation parameters;

[0080] Step 303, generating an impedance mutation simulation control signal based on the risk-associated impedance mutation simulation parameters.

[0081] Specifically, in the embodiment, by obtaining the historical data of the storage unit and combining the storage parameters to predict the probability of subsequent impedance mutation failure, generating the fault risk factor, and mapping and scaling the impedance mutation simulation parameters, the risk can be adjusted before the impedance mutation is applied, so that the impedance mutation simulation can be closer to the actual potential fault condition, improving the pertinence and reliability of the fault test, and helping to evaluate the stability and fault tolerance capability of the storage unit in high-risk scenarios.

[0082] In one specific embodiment, obtaining historical data of the storage unit, combining storage parameters of the storage unit, predicting a probability of subsequent impedance mutation failure of the storage unit, and generating a fault risk factor, includes:

[0083] According to the historical impedance mutation times of the storage unit, the impedance mutation-associated risk parameters of the storage unit are extracted, combined with a preset weight coefficient for weighted summation and normalization to obtain the fault risk factor, which can be expressed as:

[0084] ;

[0085] Wherein, P i represents the probability of impedance mutation failure of the storage unit at the i-th time, i.e. the fault probability factor, N i represents the historical impedance mutation times of the storage unit, N maxrepresents the maximum reference number for normalizing the historical impedance mutation number, h i,j represents the actual value of the jth impedance mutation associated risk parameter of the storage unit at the ith time point, represents the preset reference value of the jth impedance mutation associated risk parameter of the storage unit, γ j represents the sensitivity weight of the jth impedance mutation associated risk parameter of the storage unit, t i represents the cumulative use time of the storage unit, f(t i ) is a time accumulation function, and α, β, and δ respectively represent the weights of historical data, hardware parameters, and time factors. σ(·) is a normalization function, and is preferably a sigmoid function;

[0086] According to the fault risk factor, the impedance mutation simulation parameter is saturatedly scaled to obtain a risk-associated impedance mutation simulation parameter, which can be represented as:

[0087] ;

[0088] wherein, represents the ith risk-associated impedance mutation simulation parameter applicable to the storage unit, Ri represents the ith impedance mutation simulation parameter applicable to the storage unit, k represents a probability sensitivity coefficient, preferably 1-10, and P0 is a probability midpoint reference value, preferably 0.1-0.5.

[0089] Specifically, in the embodiment, the historical impedance mutation number, the hardware parameters of the storage unit, and the time evolution characteristics are comprehensively considered to reflect the fault risk of each storage unit at different time points, so that the impedance mutation simulation is more close to the actual fault evolution law, and a risk-driven dynamic simulation is realized. At the same time, the mapping function is used to scale the simulation parameter, so that the impedance change amplitude smoothly transitions with the increase of risk, avoiding too large or too small mutation, and improving the stability and controllability of the test. In addition, by adjusting the coefficient and the threshold value, the impedance amplification rate and the sensitivity can be controlled, and the targeted test of low-probability and high-risk scenarios can be realized. Furthermore, the fault probability of each storage unit can be calculated in advance, which can guide the test to preferentially cover high-risk units, improve the efficiency and reliability of the test, and reduce the consumption of blind test resources.

[0090] In one embodiment, after the fault simulation unit applies the impedance mutation in the data storage link, it further comprises:

[0091] According to the impedance mutation simulation parameter, the expected mutation amplitude of the link is determined;

[0092] monitoring the actual mutation amplitude of the link applied by the fault simulation unit, judging whether the direction of the actual mutation amplitude of the link is consistent with the expected mutation amplitude of the link, and whether the difference between the absolute value of the actual mutation amplitude of the link and the absolute value of the expected mutation amplitude of the link is less than or equal to a preset mutation effective threshold, wherein the mutation effective threshold is preferably ±2Ω;

[0093] obtaining performance information of the storage unit, analyzing the performance abnormal record, and judging whether the occurrence time of the performance abnormal record is consistent with the time of the impedance mutation applied by the fault simulation unit, wherein the performance abnormal record includes but is not limited to the number of I / O errors, the number of CRC failures, and the number of delay overruns, and the record period is 1ms-1s;

[0094] In response to the judgment results being all yes, it is determined that the impedance mutation applied by the fault simulation unit meets the expectation, and in response to one or more judgment results being no, it is determined that the impedance mutation applied by the fault simulation unit does not meet the expectation, and the impedance mutation simulation parameters are regenerated and the impedance mutation simulation control signal is updated.

[0095] Specifically, in this embodiment, the deviation between the actual mutation amplitude and the expected mutation amplitude applied by the fault simulation unit is monitored, and whether it meets the expectation is judged in combination with the performance abnormal record of the storage unit, a closed-loop verification mechanism can be formed, and when the deviation or the abnormality is found to be inconsistent, the impedance mutation simulation parameters can be regenerated and the control signal can be updated, so that the applied impedance mutation can truly reflect the expected fault scenario, the accuracy and effectiveness of the fault test result are guaranteed, and the fault response verification level of the storage unit is improved.

[0096] In one embodiment, the method further comprises:

[0097] In response to the fault test mode being a protocol layer logic abnormality test, one or more soft error instructions are selected from a pre-stored soft error instruction set, and the soft error instruction set at least includes command disorder and cyclic redundancy check abnormality;

[0098] Based on the soft error instruction, a soft error data frame is generated and sent to the fault simulation unit, so that the fault simulation unit applies logic abnormality to the storage unit at the protocol layer according to the soft error data frame, wherein the length of the soft error data frame is preferably 64-512 bytes, and is generated according to the SATA / PCIe protocol format.

[0099] Specifically, in this embodiment, by selecting the pre-stored soft error instruction and generating the soft error data frame, logic abnormality is applied at the protocol layer, the verification of the protocol processing capability of the storage unit can be realized, the fault test means is expanded, not only covering the physical link impedance abnormality, but also being able to simulate the protocol layer logic abnormality, providing more comprehensive storage unit reliability verification means, and providing multi-dimensional reference for system design and maintenance.

[0100] In one embodiment, the data storage link includes a plurality of storage units, and each of the plurality of storage units is connected with a plurality of fault simulation units, and the fault simulation units are configured to simulate one or more preset fault types, and the method is applied to a controller and includes:

[0101] Analyzing the fault test instruction to determine a target storage unit and a corresponding target fault test mode;

[0102] Based on the target fault test mode, determining a target fault simulation unit corresponding to the associated preset fault type;

[0103] Generating a fault simulation control signal and delivering it to the target fault simulation unit to make the target fault simulation unit apply a corresponding fault simulation operation to the target storage unit.

[0104] Specifically, in this embodiment, by analyzing the test instruction to determine the target storage unit and the fault mode in the multi-storage unit and multi-fault simulation unit environment, and delivering the control signal for the corresponding fault simulation operation, the directional and controllable fault test of the complex storage system can be realized, the parallel test of the multi-storage unit and the combination simulation of the multiple fault types can be realized, the fault tolerance capability and the overall stability of the system in the complex scenario can be evaluated, and the technical support for the reliability verification of the large-scale storage system can be provided.

[0105] In one embodiment, generating a fault simulation control signal and delivering it to the target fault simulation unit to make the target fault simulation unit apply a corresponding fault simulation operation to the target storage unit includes:

[0106] Obtaining a fault probability factor of a plurality of target storage units to obtain an impedance mutation fault probability of the plurality of target storage units at the current time;

[0107] Based on the impedance mutation fault probability of the plurality of storage units at the current time, determining a priority of the plurality of target storage units, and generating a dynamic scheduling plan, wherein since the fault probability factor may increase slowly over time, the high-risk storage unit will obtain a higher test priority, and the low-risk storage unit can be appropriately delayed for testing, so as to reasonably allocate the test resources;

[0108] According to the target fault test mode and the priority of the plurality of target storage units, determining a target fault simulation unit corresponding to the associated preset fault type, dynamically adjusting the simulation strength or frequency based on the size of the fault probability factor to generate a corresponding fault simulation control signal, so as to ensure that the high-risk storage unit is fully covered, and the low-risk storage unit maintains the preset simulation parameters, thereby avoiding resource waste;

[0109] During the execution of the fault simulation operation by the target fault unit, the states of the plurality of target storage units are continuously monitored, and the subsequent scheduling is adjusted in combination with the time variation and the real-time fault probability factor, for example, for a storage unit that abnormally appears in a high-probability period, the priority thereof can be immediately increased for retesting or the simulation operation density thereof can be increased, and for a low-probability unit that abnormally appears, the scheduling priority thereof can be temporarily adjusted, so that the fault test strategy is kept in synchronization with the risk variation, and the collaborative fault test and optimized scheduling of the plurality of storage units are realized.

[0110] Specifically, in the embodiment, the fault probability factor is introduced and dynamically associated with time, so that the collaborative scheduling of the fault test of the plurality of storage units is realized; through risk assessment and dynamic adjustment of the priority, the high-risk storage unit can be fully covered in the fault test, so as to ensure the reliability and stability of the key storage unit, the test of the low-risk storage unit can be delayed or the simulation strength thereof can be lower, so that the test resources are effectively saved and invalid or repeated operations are avoided; meanwhile, the simulation strength and the scheduling sequence are dynamically adjusted according to the real-time state and the variation of the fault probability factor, so that the fault test strategy can be optimized according to the running state of the storage unit and the time variation, the comprehensive improvement of the test coverage, the efficiency and the resource utilization is realized, the accuracy and the scientificity of the fault test of the plurality of storage units are improved, and the overall reliability and stability of the storage system are enhanced.

[0111] In one embodiment, the above-mentioned fault test method further comprises:

[0112] In response to the data storage link being applied with an impedance mutation, a physical damage of the hard disk is artificially manufactured, and a monitoring tool is combined to realize the fault test of the hard disk, wherein the physical damage of the hard disk includes, but is not limited to, a short circuit of the hard disk, a defect of the hard disk and the like.

[0113] As shown in Figure 4 A fault test method provided by the embodiment is applied to a data storage link, and includes:

[0114] Firstly, storage parameters are acquired to determine the basic information such as the number, type and link state of the storage unit;

[0115] Then, it is judged whether the storage unit is multiple, if the storage unit is multiple, a multiple-storage-unit collaborative control mode is adopted, if the storage unit is single, a single-storage-unit independent control mode is adopted, wherein the multiple-storage-unit collaborative control mode includes that the controller parallelly issues a test task, so that the plurality of storage units enter a fault test state according to a unified time sequence, so as to realize the fault tolerance capability verification of the multiple-channel link under the consistent abnormal condition, and the single-storage-unit independent control mode includes that the controller only issues a test task for the target storage unit, so as to realize the accurate evaluation of the single link under the fault condition;

[0116] Subsequently, the controller confirms the target fault test mode, taking the impedance mutation test mode as an example, the controller issues an impedance calibration signal to the fault simulation unit to establish a baseline for the impedance change of the link, and after completing the baseline calibration, the controller further issues an impedance mutation simulation control signal to make the fault simulation unit apply an impedance mutation with a preset amplitude, duration and trigger timing to the storage link;

[0117] Finally, after the link mutation is generated, the controller verifies the mutation amplitude and trigger timing, if the detection result does not match the expectation, the calibration process is returned to correct, if the detection result matches the expectation, the fault data of the storage unit under abnormal conditions is collected, and the corresponding fault test report is generated, thereby, the robustness and reliability verification of the storage link under the impedance mutation scene can be systematically completed.

[0118] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0119] As shown in Figure 5 The embodiment of the application also provides a data storage link, which comprises a system mainboard and a hard disk backboard, and the system mainboard and the hard disk backboard are connected through an expander, wherein,

[0120] The system mainboard is provided with a controller for receiving a fault test instruction, issuing an impedance calibration signal and a mutation simulation signal;

[0121] The hard disk backboard is integrated with a fault simulation unit and a storage unit;

[0122] The storage unit comprises a plurality of hard disks, preferably SATA hard disks;

[0123] The fault simulation unit is used to inject abnormalities at the protocol layer and the physical layer respectively to realize multi-level fault testing, wherein the fault simulation unit comprises:

[0124] A command queue simulator is used to construct an abnormal command sequence at the protocol layer to simulate a command processing abnormality;

[0125] A check code generator is used to generate an error CRC information at the protocol layer to simulate a data integrity fault;

[0126] A frame constructor is used to construct a deformed or incomplete data frame at the protocol layer to trigger a link parsing error;

[0127] A digital potentiometer array is used to apply a controllable impedance mutation at the physical layer to simulate a transient electrical abnormality in link transmission.

[0128] Specifically, through the structure shown in the embodiment, multi-level fault injection of the protocol layer and the physical layer can be realized, both soft error testing and impedance mutation scenarios in the physical link can be simulated, and thus the integrity and authenticity of the storage link fault testing are improved.

[0129] As shown in Figure 6 The embodiment also provides a fault testing process to show the interaction relationship among the controller, the fault simulation unit and the storage unit, including:

[0130] When the fault testing instruction is input, the controller determines an impedance calibration baseline, and sends an impedance calibration signal to the fault simulation unit, the fault simulation unit calibrates the link impedance after receiving the signal, and feeds back the result to the controller, so as to ensure that the amplitude of the subsequent mutation simulation matches the baseline;

[0131] The controller generates impedance mutation simulation parameters according to the feedback of the fault simulation unit, and sends the parameters to the fault simulation unit, the fault simulation unit applies impedance mutation in the link based on the impedance mutation simulation parameters, so that the storage unit appears controllable abnormal state in the read-write process;

[0132] At the same time of applying the impedance mutation, the controller monitors the data response from the storage unit, acquires fault data including error logs, abnormal frame information and data consistency results, records and outputs the collected data as test results, and evaluates the fault tolerance capability and recovery mechanism of the storage link under dynamic fault.

[0133] Specifically, the embodiment can realize the complete timing process from the test instruction triggering, the impedance mutation simulation to the result collection, so as to ensure the repeatability and reliability of the fault testing.

[0134] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present text can be realized in electronic hardware, computer software or combination of both, in order to clearly show the interchangeability of hardware and software, the composition and steps of each example have been described in the above description. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0135] The above describes in detail the fault test method provided by the present application. The principles and implementation manners of the present application are described by using specific examples, and the above description of the examples is only applicable to helping understand the method of the present application and the core idea thereof. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A method of fault testing, characterized by, A controller applied to a data storage link, the data storage link further comprising a storage unit and a fault simulation unit connected with the controller and the storage unit respectively, the method comprising: In response to receiving a fault test instruction, parsing the fault test instruction to determine a fault test mode; In response to the fault test mode being an impedance mutation test, obtaining storage parameters of the storage unit and determining an impedance baseline; Based on the impedance baseline, generating an impedance calibration signal and delivering it to the fault simulation unit to make the fault simulation unit perform impedance calibration; Obtaining an impedance calibration residual returned by the fault simulation unit, and determining an impedance mutation simulation parameter based on the impedance calibration residual; Based on the impedance mutation simulation parameter, generating an impedance mutation simulation control signal and delivering it to the fault simulation unit to make the fault simulation unit apply an impedance mutation in the data storage link according to the impedance mutation simulation control signal; In response to the data storage link being applied with an impedance mutation, recording the performance of the storage unit to obtain a fault test result.

2. The fault testing method according to claim 1, characterized in that, The obtaining of the storage parameters of the storage unit and the determination of the impedance baseline comprises: Parsing the storage parameters to obtain a storage unit interface type, a storage unit maximum transmission rate and a link wire length; According to the storage unit interface type and the storage unit maximum transmission rate, determining a link target impedance value and a tolerance range; According to the link wire length, obtaining a signal propagation delay and determining an impedance sampling window; According to pre-stored board-level design data, obtaining a link trace width and a link medium dielectric constant, and for a plurality of pre-set termination configurations, respectively calculating a plurality of link predicted impedance values of the termination configurations in the impedance sampling window, the termination configurations including adjustable resistance gears and terminal element combination operation schemes executable by the fault simulation unit; Comparing the link predicted impedance values with the link target impedance value to obtain an impedance deviation value, and if the impedance deviation value is within the tolerance range, the corresponding termination configuration is taken as a candidate termination configuration; Selecting one or more candidate termination configurations and delivering them to the fault simulation unit in sequence, and according to the element resistance value adjustment result fed back by the fault simulation unit, determining a baseline termination configuration and the corresponding impedance baseline.

3. The fault testing method according to claim 2, characterized in that, The selecting one or more candidate termination configurations and delivering them to the fault simulation unit in sequence, and according to the element resistance value adjustment result fed back by the fault simulation unit, determining a baseline termination configuration and the corresponding impedance baseline, comprises: Based on the selected one or more candidate termination configurations, generating configuration control signals in sequence and delivering them to the fault simulation unit, so that the fault simulation unit adjusts physical elements to achieve the corresponding link predicted impedance values; Within the impedance sampling window, the actual impedance value of the link is measured. The actual impedance value of the link is compared with the target impedance value of the link. The candidate termination configuration with the smallest difference between the actual impedance value of the link and the target impedance value of the link is determined as the baseline termination configuration. The actual impedance value of the link corresponding to the baseline termination configuration is taken as the impedance baseline.

4. The fault testing method according to claim 3, characterized in that, The fault simulation unit performs impedance calibration, including: In response to receiving the impedance calibration signal from the controller, the impedance baseline is parsed and the calibration target value is determined; Adjust its own resistance setting according to the calibration target value, and measure the current impedance value of the link; The difference between the current impedance value of the link and the calibration target value is used as the impedance calibration intermediate difference value and sent to the controller so that the controller can determine whether the impedance calibration intermediate difference value is within the tolerance range and generate the corresponding verification signal. In response to receiving a verification signal characterized as yes, the intermediate difference of impedance calibration is used as the impedance calibration residual and fed back to the controller in combination with the current timestamp; In response to receiving a verification signal indicating no, the self-resistance level is readjusted, the impedance calibration intermediate difference is updated, and the result is resent to the controller.

5. The fault testing method of claim 1, wherein, The fault simulation unit includes a digital potentiometer array. The step of acquiring the impedance calibration residual returned by the fault simulation unit and determining impedance change simulation parameters based on the impedance calibration residual includes: Based on the returned impedance calibration residual, the link impedance deviation vector is determined, which includes the link impedance deviation direction and the link impedance deviation magnitude. The value of the range adjustment of the digital potentiometer array is set to be proportional to the amplitude of the link impedance deviation, and the direction of the range adjustment is set to be consistent with the direction of the link impedance deviation. According to the device range parameters of the digital potentiometer array, the link impedance deviation vector is converted into the range adjustment. The impedance mutation simulation parameters are generated based on the gear adjustment amount, and a mutation simulation threshold is set for the impedance mutation simulation parameters. Based on the impedance change simulation parameters and the change simulation threshold, the impedance change simulation control signal is generated and sent to the digital potentiometer array.

6. The fault testing method according to claim 5, characterized in that, The digital potentiometer array includes several potentiometer channels, and the fault simulation unit applies an impedance change in the data storage link according to the impedance change simulation control signal, including: In response to receiving the impedance mutation simulation control signal, the impedance mutation simulation parameters, the mutation simulation threshold, the mutation trigger time and mutation duration specified by the controller are parsed and obtained. Based on the impedance mutation simulation parameters, the target resistance values ​​of several potentiometer channels are determined, and linear constraint programming is performed on the target resistance values ​​based on the mutation simulation threshold, so that the theoretical resistance mutation amplitude applied to several potentiometer channels is less than or equal to the mutation simulation threshold. In response to the system clock reaching the mutation trigger time, the resistance values of a plurality of the potentiometer channels are adjusted from initial values to the target resistance values and maintained until a mutation end time determined by the mutation trigger time and the mutation duration; In response to the system clock reaching the mutation end time, the resistance values of a plurality of the potentiometer channels are restored to the initial values.

7. The fault testing method of claim 1, wherein, Before the impedance mutation simulation control signal is generated and delivered to the fault simulation unit, the method further comprises: Obtaining historical data of the storage unit, combining the storage parameters of the storage unit, predicting the probability of subsequent impedance mutation failure of the storage unit, and generating a fault risk factor; According to the fault risk factor, the impedance mutation simulation parameters are mapped and scaled to obtain risk-related impedance mutation simulation parameters; Based on the risk-related impedance mutation simulation parameters, the impedance mutation simulation control signal is generated.

8. The fault testing method of claim 1, wherein, After the fault simulation unit applies the impedance mutation in the data storage link, the method further comprises: According to the impedance mutation simulation parameters, determining a link expected mutation amplitude; Monitoring the link actual mutation amplitude applied by the fault simulation unit, determining whether the direction of the link actual mutation amplitude is consistent with the link expected mutation amplitude, and whether the difference between the absolute value of the link actual mutation amplitude and the absolute value of the link expected mutation amplitude is less than or equal to a preset mutation effective threshold; Obtaining performance information of the storage unit, analyzing to obtain a performance anomaly record, and determining whether the occurrence time of the performance anomaly record is consistent with the time of the impedance mutation applied by the fault simulation unit; In response to the determination results being all yes, it is determined that the impedance mutation applied by the fault simulation unit meets the expectation, and in response to one or more determination results being no, it is determined that the impedance mutation applied by the fault simulation unit does not meet the expectation, and the impedance mutation simulation parameters are regenerated and the impedance mutation simulation control signal is updated.

9. The fault testing method of claim 1, wherein, The method further comprises: In response to the fault test mode being a protocol layer logic anomaly test, one or more soft error instructions are selected from a pre-stored soft error instruction set; Based on the soft error instructions, a soft error data frame is generated and sent to the fault simulation unit, so that the fault simulation unit applies a logic anomaly to the storage unit at the protocol layer according to the soft error data frame.

10. The fault testing method of claim 1, wherein, The data storage link comprises a plurality of storage units, and each of the plurality of storage units is connected with a plurality of fault simulation units, the fault simulation units are configured to simulate one or more preset fault types, and the method is applied to the controller, comprising: Analyzing the fault test instruction to determine a target storage unit and a corresponding target fault test mode; Based on the target fault test mode, determining a target fault simulation unit corresponding to the associated preset fault type; Generating a fault simulation control signal and delivering it to the target fault simulation unit, so that the target fault simulation unit applies a corresponding fault simulation operation to the target storage unit.

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