A dual-chip package structure and a preparation method thereof

Abstract

The application discloses a double-chip packaging structure and a preparation method thereof. The method comprises the following steps: manufacturing a first plastic sealing layer on a carrier plate, performing a first large opening on the middle part of the first plastic sealing layer; manufacturing a common back electrode metal wiring layer on the first large opening and pasting a first chip, and filling a first medium layer; manufacturing a second plastic sealing layer on the first chip, performing a first copper column opening on the first plastic sealing layer, and manufacturing a first copper column in the hole; performing a second large opening on the back of the first plastic sealing layer, pasting a second chip, and filling a second medium layer; performing a second copper column opening on the second medium layer, and forming a second copper column in the hole; manufacturing a first wiring metal layer to connect the second copper column and the first copper column on the inner side; manufacturing a third plastic sealing layer under the first plastic sealing layer, forming a second wiring metal layer, connecting the front surface of the second chip and the first copper column on the outer side; opening a hole on the second plastic sealing body, manufacturing a pin metal, forming a pad, and completing packaging. The application can improve the heat dissipation efficiency, reduce the parasitic effect, and realize the thin packaging.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a double-chip packaging structure and a preparation method thereof. BACKGROUND

[0002] The traditional double-chip packaging structure is a planar structure, mainly placing the chips in parallel on a frame, and then realizing the electrical signal connection through the wire bonding mode of the chip front pad and the pin. The traditional double-chip packaging has large parasitic parameters and cannot be thinned. At the same time, the device generates heat when working, especially the heat generated by the high-power device. If the heat cannot be transferred to the external environment in time, the performance of the high-power device will be affected, and even failure will occur. SUMMARY

[0003] The purpose of the present application is to provide a double-chip packaging structure and a preparation method thereof, which can improve the heat dissipation efficiency, reduce the parasitic effect, and realize the thin packaging.

[0004] One aspect of the present application provides a preparation method of a double-chip packaging structure, comprising:

[0005] Step S1, a first plastic encapsulation layer is made on a carrier plate, and a first large opening is made at the middle part of the first plastic encapsulation layer;

[0006] Step S2, the carrier plate is removed, a common back electrode metal wiring layer is made above the first large opening, the common back electrode metal wiring layer covers both sides of the middle part of the first plastic encapsulation layer and the inside of the first large opening, a first chip is pasted or welded on the common back electrode metal wiring layer inside the first large opening, and a first dielectric layer is filled in the first large opening;

[0007] Step S3, a second plastic encapsulation layer is made above the first dielectric layer, and the second plastic encapsulation layer covers the first dielectric layer and the first plastic encapsulation layer;

[0008] Step S4, four first copper column openings are made at both sides of the middle part of the first plastic encapsulation layer and below both ends of the first plastic encapsulation layer by etching, the openings at both sides of the middle part are etched to the common back electrode metal wiring layer, and the openings at both ends are etched to the second plastic encapsulation layer;

[0009] Step S5, a first copper column is made in each of the four first copper column openings, forming two first copper columns on the inside and two first copper columns on the outside;

[0010] Step S6, a second large opening is made at the middle part of the back of the first plastic encapsulation layer by etching, and the etching stops on the common back electrode metal wiring layer, the second large opening is opposite to the first large opening and the opening direction is opposite;

[0011] Step S7, sticking or soldering a second chip on the common back electrode metal wiring layer in the second large opening and filling the second dielectric layer in the second large opening;

[0012] Step S8, etching two second copper pillar openings in the second dielectric layer on both sides of the second chip, and stopping etching on the common back electrode metal wiring layer;

[0013] Step S9, making second copper pillars in the two second copper pillar openings to form two second copper pillars;

[0014] Step S10, making a first wiring metal layer to connect the two second copper pillars and the two first copper pillars adjacent to the two second copper pillars respectively;

[0015] Step S11, making a third plastic sealing layer below the first plastic sealing layer, making a second wiring metal layer to connect the front electrodes of the second chip and the two first copper pillars on the outside through the opening of the third plastic sealing layer;

[0016] Step S12, making an opening in the second plastic sealing body to expose the front electrodes of the first chip, the common back electrode metal wiring layer on both sides of the first large opening, and the two first copper pillars on the outside, and making a pin metal to form a solder pad, and completing the packaging.

[0017] Another aspect of the present application provides a double-chip packaging structure prepared by the above method.

[0018] According to the double-chip packaging structure and the preparation method thereof, the heat dissipation efficiency can be improved, the parasitic effect can be reduced, and the packaging can be thinned. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor:

[0020] Figure 1 is a schematic diagram of step S1 of the preparation method of the double-chip packaging structure of one embodiment of the present application;

[0021] Figure 2 is a schematic diagram of step S2 of the preparation method of the double-chip packaging structure of one embodiment of the present application;

[0022] Figure 3 is a schematic diagram of step S3 of the preparation method of the double-chip packaging structure of one embodiment of the present application;

[0023] Figure 4is a schematic diagram of step S4 of the preparation method of the dual-chip package structure of one embodiment of the present application;

[0024] Figure 5 is a schematic diagram of step S5 of the preparation method of the dual-chip package structure of one embodiment of the present application;

[0025] Figure 6 is a schematic diagram of step S6 of the preparation method of the dual-chip package structure of one embodiment of the present application;

[0026] Figure 7 is a schematic diagram of step S7 of the preparation method of the dual-chip package structure of one embodiment of the present application;

[0027] Figure 8 is a schematic diagram of step S8 of the preparation method of the dual-chip package structure of one embodiment of the present application;

[0028] Figure 9 is a schematic diagram of step S9 of the preparation method of the dual-chip package structure of one embodiment of the present application;

[0029] Figure 10 is a schematic diagram of step S10 of the preparation method of the dual-chip package structure of one embodiment of the present application;

[0030] Figure 11 is a schematic diagram of step S11 of the preparation method of the dual-chip package structure of one embodiment of the present application;

[0031] Figure 12 is a schematic diagram of step S12 of the preparation method of the dual-chip package structure of one embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely below with reference to the drawings, obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0033] One embodiment of the present application provides a preparation method of a dual-chip package structure, as shown in the figure, Figure 1 The preparation method of the dual-chip package structure of the embodiment of the present application includes steps S1-S12.

[0034] Step S1: as shown in the figure, Figure 1 A first plastic sealing layer 2 is made on a carrier plate 1, and a first large opening 3 is made in the middle part of the first plastic sealing layer 2, and the size of the first large opening 3 is large enough to put down a first chip.

[0035] Step S2: As Figure 2 As shown, the carrier board 1 is removed, and a common back electrode metal wiring layer 5 is prepared above the first large opening 3 using a sputtering process. The common back electrode metal wiring layer 5 covers the inside of the first large opening 3 and both sides of the middle part of the first molding layer 2 (both sides of the first large opening 3). Then, the first chip 4 is attached or soldered on the common back electrode metal wiring layer 5 inside the first large opening 3, so that the back electrode (not shown) of the first chip 4 is electrically connected to the common back electrode metal wiring layer 5. Then, the first dielectric layer 6 is filled into the first large opening 3, making it flush with the common back electrode metal wiring layer 5 on both sides of the first large opening 3.

[0036] Step S3: As Figure 3 As shown, a second molding layer 7 is prepared above the first dielectric layer 6, and the second molding layer 7 covers the first dielectric layer 6 and the first molding layer 2.

[0037] Step S4: As Figure 4 As shown, four first copper pillar openings 8 are made by etching below the first molding compound 2. There is one opening on each side of the middle part of the first molding compound 2 and one opening at each of the left and right ends of the first molding compound 2. The etching of the openings on both sides of the middle part stops on the common back electrode metal wiring layer 5, and the openings at the left and right ends are etched to the second molding compound 7.

[0038] Step S5: As Figure 5 As shown, the first copper pillars 9 are fabricated by filling the four openings 8 of the first copper pillars with first copper pillar metal, forming two inner first copper pillars and two outer first copper pillars. The main process is to use electroplating, first sputtering a seed layer, then photolithographic electroplating of copper metal, removing the photoresist and then removing the seed layer, and then grinding it flat so that the four first copper pillars 9 are flush with the bottom of the first molding layer 2.

[0039] Step S6: As Figure 6 As shown, a second large opening 10 is made in the middle part of the back side of the first molding layer 2 by etching. The etching stops on the common back electrode metal wiring layer 5. The second large opening 10 is opposite to the first large opening 3 in the upper and lower directions. The size of the second large opening 10 is large enough to accommodate the second chip 11.

[0040] Step S7: As Figure 7 As shown, a second chip 11 is attached or soldered onto the back electrode metal wiring layer 5 inside the second large opening 10, so that the back electrode (not shown) of the second chip 11 is electrically connected to the back electrode metal wiring layer 5 and simultaneously electrically connected to the back electrode of the first chip 4. Then, a second dielectric layer 12 is filled inside the second large opening 10.

[0041] Step S8: As Figure 8As shown, two second copper column openings 13 are made by etching openings on the second dielectric layer 12 on both sides of the second chip 11, and the etching stops on the common back electrode metal wiring layer 5.

[0042] Step S9: as shown, the second copper column metal is filled in the second copper column opening 13 to make the second copper column 14, and the main process is to use the electroplating process, first sputter a seed layer, then photoetch the copper metal, remove the photoresist and then remove the seed layer, and then polish to make the two second copper columns 14 flat with the bottom end of the first plastic sealing layer 2. Figure 9

[0043] Step S10: as shown, the first wiring metal layer 15 is made to connect the second copper column 14 and the two first copper columns 9 adjacent to it (the first copper columns 9 on both sides of the middle part of the first plastic sealing layer 2). Figure 10

[0044] Step S11: as shown, the third plastic sealing layer 16 is made below the first plastic sealing layer 2, and then the third plastic sealing layer 16 is opened to make the second wiring metal layer 17 to connect the front electrode 18 of the second chip 11 and the first copper columns 9 on the left and right ends (the first copper columns 9 on the left and right ends of the first plastic sealing layer 2). Figure 11

[0045] Step S12: as shown, the second plastic sealing layer 7 is opened to expose the front electrode 19 of the first chip 4, the common back electrode metal wiring layer 5 on both sides of the first large opening 3, and the first copper columns 9 on the left and right ends, and then make the pin metal 20 to form the solder pad 21, complete the final packaging, and get the double-chip packaging structure. Figure 12

[0046] The preparation method of the double-chip packaging structure of the embodiment of the application has the following advantages:

[0047] 1. The packaging product is thin;

[0048] 2. The packaging parasitic parameters of the double-chip are smaller;

[0049] 3. The heat can be quickly conducted to the external environment, thereby realizing high reliability of the product.

[0050] ​​​​Specifically, the method for fabricating the dual-chip package structure in this embodiment of the invention involves attaching or soldering a first chip and a second chip onto a common back electrode metal wiring layer in two large openings with opposite upper and lower openings. The back electrodes of the two chips are electrically connected to the back electrode metal wiring layer, thereby achieving back-side electrical connection between the two chips. The front electrode signal of the first chip is directly led out from the front, and the back electrode electrical signals of the two chips are led out through the common back electrode metal wiring layer. The front electrode electrical signals of the second chip are led out through the second wiring layer and the two outer first copper pillars. This enables product miniaturization and thinning, while minimizing parasitic parameters. Simultaneously, the first and second copper pillar structures connecting the common back electrode metal wiring layer and the first wiring layer enable rapid heat dissipation of the second chip. An integrated double-sided heat dissipation structure is formed, improving the heat dissipation efficiency of the package, making it suitable for high-power chip heat dissipation, and improving device reliability.

[0051] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a dual-chip packaging structure, characterized in that, include: Step S1: Create a first molding layer on the carrier board, and create a first large opening in the middle of the first molding layer; Step S2: Remove the carrier board, and fabricate a common back electrode metal wiring layer above the first large opening. The common back electrode metal wiring layer covers the inside of the first large opening and both sides of the middle part of the first molding layer. The first chip is attached or soldered on the common back electrode metal wiring layer inside the first large opening, and the first dielectric layer is filled inside the first large opening. Step S3: A second molding compound is formed on top of the first dielectric layer, and the second molding compound covers the first dielectric layer and the first molding compound. Step S4: Four first copper pillar openings are made by etching the middle part of the first molding layer on both sides and the lower left and right ends of the first molding layer. The openings on both sides of the middle part are etched to the common back electrode metal wiring layer, and the openings on both ends are etched to the second molding layer. Step S5: First copper pillars are made in the four openings of the first copper pillars respectively, forming two inner first copper pillars and two outer first copper pillars. Step S6: A second large opening is made in the middle part of the back side of the first molding layer by etching. The etching stops on the common back electrode metal wiring layer. The second large opening is vertically opposite to the first large opening and the opening direction is opposite. Step S7: Attach or solder the second chip onto the common back electrode metal wiring layer inside the second large opening and fill the second large opening with the second dielectric layer; Step S8: Two second copper pillar openings are made by etching in the second dielectric layer on both sides of the second chip, and the etching stops on the common back electrode metal wiring layer. Step S9: Make a second copper pillar inside the openings of the two second copper pillars to form two second copper pillars; Step S10: Create a first wiring metal layer to connect two second copper pillars and two adjacent inner first copper pillars respectively; Step S11: A third molding layer is fabricated below the first molding layer. An opening is made in the third molding layer, and a second wiring metal layer is fabricated to connect the front electrode of the second chip with the two outer first copper pillars. Step S12: Open a hole in the second molding compound to expose the front electrode of the first chip, the common back electrode metal wiring layer on both sides of the first large opening, and the two outer first copper pillars, and make lead metal to form pads to complete the encapsulation.

2. The method according to claim 1, characterized in that, In step S2, the back electrode of the first chip is electrically connected to the common back electrode metal wiring layer; in step S7, the back electrode of the second chip is electrically connected to the back electrode metal wiring layer, and at the same time, it is electrically connected to the back electrode of the first chip.

3. The method according to claim 1 or 2, characterized in that, In step S2, a common back electrode metal wiring layer is fabricated using a sputtering process.

4. The method according to claim 1 or 2, characterized in that, In step S5, an electroplating process is used. First, a seed layer is sputtered, then copper is electroplated by photolithography. After removing the photoresist, the seed layer is removed, and then the surface is polished so that the four first copper pillars are flush with the bottom of the first molding layer.

5. The method according to claim 1 or 2, characterized in that, In step S9, an electroplating process is used. First, a seed layer is sputtered, then copper is electroplated by photolithography. After removing the photoresist, the seed layer is removed, and then the surface is polished so that the two second copper pillars are flush with the bottom of the first molding layer.

6. A dual-chip packaging structure, characterized in that, It is prepared using the method described in any one of claims 1-5.

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