Contact hole and forming method thereof
By using dielectric layer structures with different densities and hardness during the contact hole formation process, the short circuit problem caused by the expansion at the bottom of the contact hole is solved, and a reliable electrical connection between the contact plug and the gate is achieved.
Patent Information
- Application Number
- CN202510910490.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-02
- Publication Date
- 2025-10-31
AI Technical Summary
In the process of manufacturing dynamic random access memory integrated circuits, the swelling at the bottom of the contact hole can cause a short circuit between the contact plug and the gate.
By forming a first dielectric layer and a second dielectric layer with different densities and hardness on the substrate, and utilizing the characteristics of different etching rates and hardness, contact holes are etched to form a bottom critical dimension smaller than the width of the top surface of the pad, thus avoiding lateral etching and bottom expansion.
It improves the shrinkage performance of the critical dimensions of the contact hole, solves the short circuit problem caused by the expansion of the bottom of the contact hole, and ensures the reliability of the electrical connection between the contact plug and the gate.
Smart Images
Figure CN120878634A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a contact hole and a method for forming the same. Background Technology
[0002] In Dynamic Random Access Memory (DRAM) integrated circuit manufacturing processes, deep via processes mainly include two core technologies: deep trench capacitor fabrication and vertical interconnect (TSV) technology, serving the needs of memory cell construction and 3D stacked packaging, respectively. The connection between DRAM PMD Contact (Pre-Metal Dielectric Contact) and 3D NAND deep vias is achieved through Silicon Via (TSV) technology. This technology allows for vertical electrical connections between different chip layers. A PMD Contact is a contact formed in the PMD layer, used to connect the source / drain of transistors (such as word lines and bit lines) to the first layer of metal wiring (such as aluminum or copper). 3D NAND achieves high-density storage by vertically stacking multiple layers of memory cells (such as 64-128 layers), requiring the resolution of vertical interconnect issues between these layers. Deep vias are vertical connection channels that penetrate the multi-layer structure, used for global interconnection of signals and power. However, the challenge of deep via technology lies in meeting the requirements of different aspect ratios, thereby satisfying gap fill process capabilities and electrical specifications. Common deep vias such as PMDContact are defined using Trilayer or APF processes. Trilayer (three-layer stacking) is a key design feature of the charge trapping layer (CTF) in 3D NAND, composed of oxide-nitride-oxide (ONO), used to optimize charge trapping efficiency and storage reliability. APF (Adaptive Process Flow) is a dynamic process control technology developed for high aspect ratio contact holes (>50:1) and multi-layer stacking.
[0003] In a single OX film scheme architecture, varying degrees of lateral etching occur during the Etch BT / ME / OE steps (anti-reflection layer etching, main etching, and over-etching), leading to deep via structures with enlarged bottom plated surfaces (CDs). When combined with misalignment, this can exacerbate the contact-to-poly short problem. The etching challenges are: excessive polymer gas can easily cause etching abort; insufficient polymer gas can cause CD enlargement, resulting in resistance differences in electrical behavior. Summary of the Invention
[0004] The purpose of this invention is to provide a contact hole and a method for forming the same, so as to solve the problem that the bottom of the contact hole expands, leading to a short circuit between the contact plug and the gate.
[0005] To solve the above-mentioned technical problems, the present invention provides a method for forming a contact hole, comprising:
[0006] A substrate is provided, on which a gate is formed, and on which a pad is formed;
[0007] A first dielectric layer is formed, the first dielectric layer covering the substrate and the pads;
[0008] A second dielectric layer is formed, which covers the first dielectric layer. The second dielectric layer and the first dielectric layer have a density difference and a hardness difference.
[0009] An etching process is performed to sequentially etch the second dielectric layer and the first dielectric layer to form a contact hole. The contact hole penetrates the second dielectric layer and the first dielectric layer and exposes the top surface of the pad. The bottom critical dimension width of the contact hole is smaller than the width of the top surface of the pad.
[0010] Optionally, both the second dielectric layer and the first dielectric layer are made of silicon oxide, and the density and hardness of the second dielectric layer are greater than those of the first dielectric layer.
[0011] Optionally, the second medium layer is LRFTEOS, and the first medium layer is TEOS.
[0012] Optionally, the thickness of the second dielectric layer is 1000 angstroms to 2000 angstroms.
[0013] Optionally, the second dielectric layer and the first dielectric layer are formed using a PECVD process, wherein the power of the PECVD process used to form the second dielectric layer and the first dielectric layer is different.
[0014] Optionally, the power of the PECVD process forming the second dielectric layer is 500W-900W, and the power of the PECVD process forming the first dielectric layer is 950W-2500W.
[0015] Optionally, a contact etch barrier layer is formed before forming the first dielectric layer, the contact etch barrier layer covering the substrate and the pads.
[0016] Optionally, the steps for performing the etching process include:
[0017] A photoresist layer is formed, wherein the photoresist layer covers the second dielectric layer;
[0018] The exposure and development processes are performed to form the patterned first photoresist layer;
[0019] An etching process is performed, using the patterned first photoresist layer as a mask, to sequentially etch the second dielectric layer and the first dielectric layer to form contact holes. The contact holes penetrate the second dielectric layer and the first dielectric layer and expose the pads.
[0020] Optionally, the etching rate of the second dielectric layer is lower than that of the first dielectric layer.
[0021] Based on the same inventive concept, the present invention also provides a contact hole, which is prepared by the contact hole forming method described in any of the above claims.
[0022] In a method for forming a contact hole provided by the present invention, a first dielectric layer is formed, which covers a substrate and a pad; a second dielectric layer is formed, which covers the first dielectric layer, and the second and first dielectric layers have a density difference and a hardness difference; an etching process is performed to sequentially etch the second and first dielectric layers to form a contact hole, the contact hole penetrating the second and first dielectric layers and exposing the pad, and the bottom critical dimension width of the contact hole is smaller than the width of the top surface of the pad. Due to the density and hardness difference between the second and first dielectric layers, under the same etching process conditions, the critical dimension shrinkage performance of the contact hole is improved, that is, the landing performance of the bottom critical dimension of the contact hole, solving the problem of short circuit between the contact plug and the gate caused by the bottom expansion of the contact hole. Attached Figure Description
[0023] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0024] Figure 1 This is a flowchart of a method for forming a contact hole according to an embodiment of the present invention.
[0025] Figures 2 to 4 This is a schematic diagram of the structure corresponding to the steps of the contact hole formation method in an embodiment of the present invention.
[0026] In the attached image:
[0027] 10-Substrate; 11-Gate; 12-Pad; 13-First contact etch barrier layer; 14-Second contact etch barrier layer; 15-First dielectric layer; 16-Second dielectric layer; 17-Patterned photoresist layer; 17a-Opening; 18-Contact hole. Detailed Implementation
[0028] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0029] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. Additionally, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, which can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0030] Figure 1 This is a flowchart illustrating a method for forming a contact hole according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for forming a contact hole, including:
[0031] Step S10: Provide a substrate, on which a gate is formed and on which a pad is formed;
[0032] Step S20: Form a first dielectric layer, the first dielectric layer covering the substrate and the pads;
[0033] Step S30: A second dielectric layer is formed, which covers the first dielectric layer. The second dielectric layer and the first dielectric layer have a density difference and a hardness difference.
[0034] Step S40: Perform an etching process to sequentially etch the second dielectric layer and the first dielectric layer to form a contact hole. The contact hole penetrates the second dielectric layer and the first dielectric layer and exposes the top surface of the pad. The bottom critical dimension width of the contact hole is smaller than the width of the top surface of the pad.
[0035] Figures 2 to 4 This is a schematic diagram showing the structural steps corresponding to the contact hole formation method of an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 4 Specific embodiments of the present invention will be described in detail below.
[0036] like Figure 2 As shown, a substrate 10 is provided. The substrate 10 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for supporting semiconductor integrated circuit components, such as a bare die or a wafer processed by epitaxial growth. Specifically, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. In this embodiment, the substrate 10 is a silicon substrate. The substrate 10 is the peripheral region of a DRAM device, i.e., the logic region of the device. A gate 11 is formed on the substrate 10, and a pad 12 is formed on the gate 11. The material of the gate 11 is, for example, polysilicon, formed by chemical vapor deposition. The material of the pad 12 is a metal, such as copper, aluminum, or tungsten. A fill layer is formed between adjacent gates 11, and the top surface of the fill layer is flush with the top surface of the pad 12.
[0037] Please continue to refer to this. Figure 2 A contact etch stop layer (CESL) is formed, which covers the pad 12 and the fill layer. In this embodiment, the contact etch stop layer includes a first contact etch stop layer 13 and a second contact etch stop layer 14. The first contact etch stop layer 13 is made of silicon nitride and can be formed using a chemical vapor deposition process. The second contact etch stop layer 14 is an HK layer (high-k material) and can also be formed using a chemical vapor deposition process.
[0038] Please continue to refer to this. Figure 2A first dielectric layer 15 is formed, which covers the contact etch barrier layer. The first dielectric layer 15 is made of oxide and is formed using a PECVD process. The material used in the PECVD process is TEOS. The density of the first dielectric layer 15 is, for example, 2.1–2.3 g / cm³. The hardness of the first dielectric layer 15 is, for example, 6 GPa–7 GPa. The deposition rate of the first dielectric layer 15 is, for example, 950 A / min–1500 A / min.
[0039] Please continue to refer to this. Figure 2 A second dielectric layer 16 is formed, which covers the first dielectric layer 15. The second dielectric layer 16 and the first dielectric layer 15 have a density difference and a hardness difference. The material of the second dielectric layer 16 is an oxide layer, formed using a PECVD process. The material used in the PECVD process is TEOS. However, the PECVD process operates at a low frequency (Low RF). In the PECVD process, the low frequency is achieved through low power process conditions. Therefore, the second dielectric layer 16 is LRFTEOS (Low RF TEOS, low-power TEOS silica). The lower the power, the lower the plasma strength and chamber pressure, the lower the deposition rate, and the higher the film density. Therefore, LRFTEOS has a low deposition rate and high density, and thus high hardness. The density of the second dielectric layer 16 is, for example, 2.4–2.6 g / cm³. The hardness of the second dielectric layer 16 is, for example, 8 GPa–9 GPa. The deposition rate of the second dielectric layer 16 is, for example, 650 A / min–900 A / min. The density and hardness of the second dielectric layer are both greater than those of the first dielectric layer. The thickness of the second dielectric layer is 1000 to 2000 angstroms. The power of the PECVD process used to form the second dielectric layer and the first dielectric layer is different, resulting in different plasma intensities and chamber pressures in the PECVD processes used to form the second dielectric layer and the first dielectric layer. The power of the PECVD process used to form the second dielectric layer is 500W-900W, and the power of the PECVD process used to form the first dielectric layer is 950W-2500W.
[0040] like Figure 2 and Figure 3As shown, an etching process is performed to sequentially etch the second dielectric layer 16 and the first dielectric layer 15 to form a contact hole 18. The contact hole 18 penetrates the second dielectric layer 16 and the first dielectric layer 15 and exposes the top surface of the pad 12. The bottom critical dimension width of the contact hole 18 is smaller than the width of the top surface of the pad 12. Specifically, the etching process includes: forming a photoresist layer covering the second dielectric layer 16; performing an exposure and development process to form a patterned first photoresist layer 17, in which an opening 17a is formed, exposing the second dielectric layer 16 above the pad; and performing an etching process, using the patterned first photoresist layer 17 as a mask, sequentially etching the second dielectric layer 16 and the first dielectric layer 15 along the opening 17a to form a contact hole 18, which penetrates the second dielectric layer 16 and the first dielectric layer 15, exposing the pad 12, and the bottom critical dimension width of the contact hole 18 is smaller than the width of the top surface of the pad 12. Because the second dielectric layer 16 has a higher density and hardness, in the same etching process, the etching rate of the second dielectric layer 16 is slower, and the etching shape is approximately vertical, mitigating the problem of lateral etching. The density and hardness of the first dielectric layer 15 are lower than those of the second dielectric layer 16. Therefore, in the same etching process, the etching rate of the first dielectric layer 15 is faster, ensuring the product's processing speed. The presence of the second dielectric layer 16 reduces the height of the first dielectric layer 15, meaning the height of the contact holes in the first dielectric layer 15 is lower. This reduces etching difficulty, minimizes deep-hole etching problems, avoids the problem of critical dimension expansion at the bottom of deep holes, and thus avoids short circuits between the contact plug and the gate.
[0041] like Figure 4 As shown, after the step of forming the contact hole, if the patterned photoresist layer 17 is not completely consumed, a photoresist removal process is required. The residual patterned photoresist layer 17 is usually removed by ashing or stripping.
[0042] like Figure 4As shown, this embodiment also provides a contact hole, which is fabricated using the contact hole formation method described in any of the above embodiments. It includes a substrate 10, on which a gate 11 and a pad 12 located on top of the gate 11 are formed. A fill layer is formed between adjacent gates 11, the top of which is flush with the top of the pad 12. A first contact etch stop layer 13, a second contact etch stop layer 14, a first dielectric layer 15, and a second dielectric layer 16 are sequentially formed on the pad 12. The contact hole 18 penetrates the second dielectric layer 16, the second dielectric layer 15, the second contact etch stop layer 14, and the first contact etch stop layer 13, exposing the top surface of the pad 12. The bottom critical dimension width of the contact hole 18 is smaller than the width of the top surface of the pad 12.
[0043] After the step of forming the contact hole, a contact plug is formed, which is located within the contact hole 18 and electrically connected to the pad 12. The contact plug is made of a metal, such as tungsten.
[0044] In summary, the contact hole formation method provided in this embodiment of the invention involves forming a first dielectric layer covering a substrate and a pad; forming a second dielectric layer covering the first dielectric layer, wherein the second and first dielectric layers have a density difference and a hardness difference; and performing an etching process to sequentially etch the second and first dielectric layers to form a contact hole, wherein the contact hole penetrates both the second and first dielectric layers and exposes the top surface of the pad, and the bottom critical dimension width of the contact hole is smaller than the width of the top surface of the pad. Due to the density and hardness difference between the second and first dielectric layers, under the same etching process conditions, the critical dimension shrinkage performance of the contact hole is improved, i.e., the landing performance of the bottom critical dimension of the contact hole, thus solving the problem of short circuit between the contact plug and the gate caused by bottom expansion of the contact hole.
[0045] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0046] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for forming a contact hole, characterized in that, include: A substrate is provided, on which a gate is formed, and on which a pad is formed; A first dielectric layer is formed, the first dielectric layer covering the substrate and the pads; A second dielectric layer is formed, which covers the first dielectric layer. The second dielectric layer and the first dielectric layer have a density difference and a hardness difference. An etching process is performed to sequentially etch the second dielectric layer and the first dielectric layer to form a contact hole. The contact hole penetrates the second dielectric layer and the first dielectric layer and exposes the top surface of the pad. The bottom critical dimension width of the contact hole is smaller than the width of the top surface of the pad.
2. The method for forming a contact hole according to claim 1, characterized in that, Both the second dielectric layer and the first dielectric layer are made of silicon oxide, and the density and hardness of the second dielectric layer are greater than those of the first dielectric layer.
3. The method for forming a contact hole according to claim 1, characterized in that, The second medium layer is LRFTEOS, and the first medium layer is TEOS.
4. The method for forming a contact hole according to claim 1, characterized in that, The thickness of the second dielectric layer is 1000 to 2000 angstroms.
5. The method for forming a contact hole according to claim 1, characterized in that, The second dielectric layer and the first dielectric layer are formed using a PECVD process, and the power of the PECVD process used to form the second dielectric layer and the first dielectric layer is different.
6. The method for forming a contact hole according to claim 1, characterized in that, The power of the PECVD process for forming the second dielectric layer is 500W-900W, and the power of the PECVD process for forming the first dielectric layer is 950W-2500W.
7. The method for forming a contact hole according to claim 1, characterized in that, Before forming the first dielectric layer, a contact etch barrier layer is formed, which covers the substrate and the pads.
8. The method for forming a contact hole according to claim 7, characterized in that, The steps involved in performing the etching process include: A photoresist layer is formed, wherein the photoresist layer covers the second dielectric layer; The exposure and development processes are performed to form the patterned first photoresist layer; An etching process is performed, using the patterned first photoresist layer as a mask, to sequentially etch the second dielectric layer and the first dielectric layer to form contact holes. The contact holes penetrate the second dielectric layer and the first dielectric layer and expose the pads.
9. The method for forming a contact hole according to claim 8, characterized in that, The etching rate of the second dielectric layer is less than that of the first dielectric layer.
10. A contact hole, characterized in that, It is prepared by the method for forming contact holes as described in any one of claims 1 to 9.