High-reliability low-noise amplifier chip
By incorporating an active bias circuit, a common-source cascode low-noise amplifier circuit, a feedback circuit, and a high input power protection circuit into the low-noise amplifier, the contradiction between high gain and the 1dB output compression point is resolved, reliability is improved, and transistor damage is prevented.
Patent Information
- Application Number
- CN202510913190.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-03
- Publication Date
- 2025-10-31
AI Technical Summary
Existing low-noise amplifiers have a trade-off between high gain and output 1dB compression point (OP1dB), and are prone to damage in high-power scenarios, affecting reliability.
An active bias circuit, a common-source cascode low-noise amplifier circuit, a feedback circuit, and a high input power protection circuit are employed. By adding a first diode D1, the Vgs of the fourth transistor M4 is raised, increasing the output compression point by 1dB. The high input power protection circuit provides a power discharge path for the fourth transistor to prevent damage.
It achieves a high output compression point of 1dB and a low noise figure, while improving the reliability of the low-noise amplifier and preventing transistor damage due to high-power signals.
Smart Images
Figure CN120880356A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of amplifier technology, and in particular to a high-reliability, low-noise amplifier chip. Background Technology
[0002] Typical RF systems require low-noise amplifiers (LNAs) to possess characteristics such as low noise, low power consumption, and a high 1dB compression point (OP1dB). The OP1dB is an important linearity indicator for LNAs, representing how the output power of the LNA is compressed as the input power increases. In conventional resistive feedback structures, low noise circuits require higher gain, but high gain contradicts the OP1 requirement. Therefore, improving the OP1 of the LNA without affecting the overall gain and noise figure of the circuit becomes a problem to be solved.
[0003] Meanwhile, the low-noise amplifier is located at the very beginning of the entire system's receiving link and is connected to the RF receiving antenna. When applied to some high-power scenarios, if a large power signal is applied to the signal input end, it can easily lead to damage to the low-noise amplifier. Therefore, the reliability of the low-noise amplifier cannot be ignored. Summary of the Invention
[0004] Based on this, the present invention provides a high-reliability low-noise amplifier chip with a high input power protection circuit, which solves the technical problem of the contradiction between low noise figure and high OP1, and improves the reliability of existing low-noise amplifiers. The high-reliability low-noise amplifier chip includes: an active bias circuit, a common-source common-gate low-noise amplifier circuit, a feedback circuit, and a high input power protection circuit;
[0005] The radio frequency signal input terminal RFin is connected to one end of the first DC blocking capacitor C6, and the other end of the first DC blocking capacitor C6 is connected to one end of the active bias circuit, one end of the feedback circuit, and the input terminal of the common source cascode low noise amplifier circuit.
[0006] The RF signal output terminal RFout is connected to one end of the second DC blocking capacitor C7, and the other end of the second DC blocking capacitor C7 is connected to the other end of the active bias circuit, the other end of the feedback circuit, and the output terminal of the common source cascode low noise amplifier circuit.
[0007] The high input power protection circuit is connected to the common source cascode low noise amplifier circuit, and the high input power protection circuit is used to protect the common source cascode low noise amplifier circuit.
[0008] This invention proposes a high-reliability, low-noise amplifier chip comprising: an active bias circuit, a common-source, common-gate low-noise amplifier circuit, a feedback circuit, and a high-input power protection circuit. A first diode D1 is added to the active bias circuit of the low-noise amplifier. The presence of the first diode D1 increases the Vgs of the fourth transistor M4. Increased Vgs raises the 1dB compression point of the circuit's output power, thus enabling the high-reliability, low-noise amplifier chip to achieve a high output 1dB compression point and a low noise figure. When a high-power signal is input, the high-input power protection circuit provides a power discharge path for the fourth transistor (M4), keeping the dynamic voltage swing of the fourth transistor (M4) within a normal range, thereby preventing the fourth transistor (M4) from burning out due to excessive input power. The presence of the twelfth resistor (R12) reduces the branch current of the high-input power protection circuit, protecting the subsequent diodes from burning out due to excessive current. Attached Figure Description
[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] in:
[0011] Figure 1 This is a schematic diagram of a circuit structure for a high-reliability, low-noise amplifier chip in one embodiment.
[0012] Figure 2 A comparison of simulation results for the fourth transistor M4Vgs in the active bias circuit with and without the first diode D1.
[0013] Figure 3 A comparison of simulation results of the 1dB compression point of the output power of a low-noise amplifier with and without the first diode D1 in an active bias circuit.
[0014] Figure 4 Simulation results for the fourth transistor M4Vdg in a high-reliability, low-noise amplifier chip without a high input power protection circuit when the input power is high;
[0015] Figure 5 The simulation results are for the fourth transistor M4Vdg when there is a high input power protection circuit for high input power. Detailed Implementation
[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.
[0017] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] Please see Figure 1 As shown, Figure 1 A circuit diagram of a high-reliability low-noise amplifier chip provided in an embodiment of the present invention includes: an active bias circuit, a common-source cascode low-noise amplifier circuit, a feedback circuit, and a high input power protection circuit;
[0020] The radio frequency signal input terminal RFin is connected to one end of the first DC blocking capacitor C6, and the other end of the first DC blocking capacitor C6 is connected to one end of the active bias circuit, one end of the feedback circuit, and the input terminal of the common source cascode low noise amplifier circuit.
[0021] The RF signal output terminal RFout is connected to one end of the second DC blocking capacitor C7, and the other end of the second DC blocking capacitor C7 is connected to the other end of the active bias circuit, the other end of the feedback circuit, and the output terminal of the common source cascode low noise amplifier circuit.
[0022] The high input power protection circuit is connected to the common source cascode low noise amplifier circuit, and the high input power protection circuit is used to protect the common source cascode low noise amplifier circuit.
[0023] In one embodiment, the active bias circuit includes a first transistor M1, a second transistor M2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, and a first diode D1. The source of the first transistor M1 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is grounded. The drain of the first transistor M1 is connected to the gate of the second transistor M2 and one end of the first resistor R1. The other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the drain of the second transistor M2. The gate of M1 is connected to one end of the first capacitor C1 and one end of the third resistor R3. The other end of the first capacitor C1 is grounded. The other end of the third resistor R3 is connected to one end of the fourth resistor R4 and one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to the other end of the first DC blocking capacitor C6. The other end of the fourth resistor R4 is connected to the source of the second transistor M2, the anode of the first diode D1, and one end of the second capacitor C2. The cathode of the first diode D1 and the other end of the second capacitor C2 are grounded. The other end of the sixth resistor R6 serves as one end of the active bias circuit, and one end of the second resistor R2 serves as the other end of the active bias circuit.
[0024] In one embodiment, the feedback circuit includes a third capacitor C3, a seventh resistor R7, and an eighth resistor R8. One end of the seventh resistor R7 is connected to one end of the second resistor R2 in the active bias circuit, and the other end of the seventh resistor R7 is connected to one end of the third capacitor C3. The other end of the third capacitor C3 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the other end of the first DC blocking capacitor C6. One end of the seventh resistor R7 serves as the other end of the feedback circuit, and the other end of the eighth resistor R8 serves as one end of the feedback circuit.
[0025] In one embodiment, the common-source cascode low-noise amplifier circuit includes a third transistor M3, a fourth transistor M4, a fourth capacitor C4, a fifth capacitor C5, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11. The source of the third transistor M3 is connected to the drain of the fourth transistor M4. The gate of the third transistor M3 is connected to one end of the ninth resistor R9, one end of the tenth resistor R10, one end of the eleventh resistor R11, and one end of the fifth capacitor C5. The other ends of the tenth resistor R10 and the fifth capacitor C5 are grounded. The other end of the eleventh resistor R11 is connected to the fourth capacitor C4 and then grounded. The drain of the third transistor M3 is connected to the other end of the ninth resistor R9. The gate of the fourth transistor M4 is connected to the other end of the first DC blocking capacitor C6. The source of the fourth transistor M4 is grounded. The drain of the third transistor M3 serves as the output terminal of the common-source cascode low-noise amplifier circuit, and the gate of the transistor M4 serves as the input terminal of the common-source cascode low-noise amplifier circuit.
[0026] In one embodiment, the high input power protection circuit includes a twelfth resistor R12, m forward-connected series diodes D2, and n reverse-connected series diodes D3, where m and n are integers greater than or equal to 1. One end of the twelfth resistor R12 is connected to the drain of the fourth transistor M4 in the cascode low-noise amplifier structure, and the other end of the twelfth resistor R12 is connected to the anode of the first diode D21 of the m forward-connected series diodes D2 and the last diode D3 of the n reverse-connected series diodes D3. n The cathodes are connected, and the last diode D2 of the m forward-connected series diodes D2 is connected. m The cathode of the diode and the anode of the first diode D31 of the n reverse-connected series diodes D3 are both grounded.
[0027] In one embodiment, the high-reliability low-noise amplifier chip further includes a choke inductor L1 and a filter capacitor C8. The drain of the third transistor M3 is connected to one end of the choke inductor L1 and one end of the second DC blocking capacitor C7. The other end of the second DC blocking capacitor C7 is connected to the radio frequency signal output terminal RFout. The other end of the choke inductor L1 is connected to the power supply terminal Vdd and one end of the filter capacitor C8, respectively. The other end of the filter capacitor C8 is connected to ground.
[0028] Please see Figure 2 As shown, Figure 2 The simulation results of the fourth transistor (M4) Vgs are compared with and without the first diode (D1) in the active bias circuit. The comparison results show that the addition of the first diode (D1) in this invention significantly increases the Vgs of the fourth transistor (M4).
[0029] Please see Figure 3 As shown, Figure 3 The simulation results of the output power 1dB compression point of the low noise amplifier with and without the first diode (D1) in the active bias circuit are compared. The comparison results show that the output 1dB compression point is significantly improved after adding the first diode (D1). This is because the presence of the first diode (D1) increases the Vgs of the fourth transistor (M4), and the increase of Vgs leads to the increase of OP1.
[0030] Please see Figure 4 , Figure 5 As shown, Figure 4 The simulation results for Vdg of the fourth transistor (M4) are given when there is no high input power protection circuit during high input power. Figure 5 The simulation results for Vdg of the fourth transistor (M4) with a high input power protection circuit are shown in the figure. As can be seen from the figure, when a high-power signal is input, the Vdg swing of the fourth transistor (M4) with the high input power protection circuit is small, and the voltage swing is within a normal range, indicating that the high input power protection circuit effectively protects the fourth transistor (M4). Based on the voltage regulation characteristics of diodes, the presence of m forward-connected series diodes (D2) and n reverse-connected series diodes (D3) provides a power discharge path for the fourth transistor (M4), reducing the risk of burnout due to excessive power. The number of m forward-connected series diodes (D2) and n reverse-connected series diodes (D3) needs to be calculated. The twelfth resistor (R12) reduces the branch current, protecting the downstream diodes from burnout due to excessive current.
[0031] This invention proposes a high-reliability, low-noise amplifier chip comprising: an active bias circuit, a common-source, common-gate low-noise amplifier circuit, a feedback circuit, and a high-input power protection circuit. A first diode D1 is added to the active bias circuit of the low-noise amplifier. The presence of the first diode D1 increases the Vgs of the fourth transistor M4. Increased Vgs increases the 1dB compression point of the circuit's output power, thus enabling the low-noise amplifier chip to achieve a high output 1dB compression point and a low noise figure. When a high-power signal is input, the high-input power protection circuit provides a power discharge path for the fourth transistor (M4), keeping the dynamic voltage swing of the fourth transistor (M4) within a normal range, thereby preventing the fourth transistor (M4) from burning out due to excessive input power. The presence of the twelfth resistor (R12) reduces the branch current of the high-input power protection circuit, protecting the subsequent diodes from burning out due to excessive current.
[0032] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A high-reliability, low-noise amplifier chip, characterized in that, The high-reliability low-noise amplifier chip includes: an active bias circuit, a common-source cascode low-noise amplifier circuit, a feedback circuit, and a high input power protection circuit; The radio frequency signal input terminal RFin is connected to one end of the first DC blocking capacitor C6, and the other end of the first DC blocking capacitor C6 is connected to one end of the active bias circuit, one end of the feedback circuit, and the input terminal of the common source cascode low noise amplifier circuit. The RF signal output terminal RFout is connected to one end of the second DC blocking capacitor C7, and the other end of the second DC blocking capacitor C7 is connected to the other end of the active bias circuit, the other end of the feedback circuit, and the output terminal of the common source cascode low noise amplifier circuit. The high input power protection circuit is connected to the common source cascode low noise amplifier circuit, and the high input power protection circuit is used to protect the common source cascode low noise amplifier circuit.
2. The high-reliability, low-noise amplifier chip according to claim 1, characterized in that, The active bias circuit includes a first transistor M1, a second transistor M2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, and a first diode D1. The source of the first transistor M1 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is grounded. The drain of the first transistor M1 is connected to the gate of the second transistor M2 and one end of the first resistor R1. The other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the drain of the second transistor M2. The gate is connected to one end of the first capacitor C1 and one end of the third resistor R3, respectively. The other end of the first capacitor C1 is grounded. The other end of the third resistor R3 is connected to one end of the fourth resistor R4 and one end of the sixth resistor R6, respectively. The other end of the sixth resistor R6 is connected to the other end of the first DC blocking capacitor C6, respectively. The other end of the fourth resistor R4 is connected to the source of the second transistor M2, the anode of the first diode D1, and one end of the second capacitor C2, respectively. The cathode of the first diode D1 and the other end of the second capacitor C2 are grounded. The other end of the sixth resistor R6 serves as one end of the active bias circuit, and one end of the second resistor R2 serves as the other end of the active bias circuit.
3. The high-reliability, low-noise amplifier chip according to claim 2, characterized in that, The feedback circuit includes a third capacitor C3, a seventh resistor R7, and an eighth resistor R8. One end of the seventh resistor R7 is connected to one end of the second resistor R2 in the active bias circuit, and the other end of the seventh resistor R7 is connected to one end of the third capacitor C3. The other end of the third capacitor C3 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the other end of the first DC blocking capacitor C6. One end of the seventh resistor R7 serves as the other end of the feedback circuit, and the other end of the eighth resistor R8 serves as one end of the feedback circuit.
4. The high-reliability, low-noise amplifier chip according to claim 3, characterized in that, The common-source cascode low-noise amplifier circuit includes a third transistor M3, a fourth transistor M4, a fourth capacitor C4, a fifth capacitor C5, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11. The source of the third transistor M3 is connected to the drain of the fourth transistor M4. The gate of the third transistor M3 is connected to one end of the ninth resistor R9, one end of the tenth resistor R10, one end of the eleventh resistor R11, and one end of the fifth capacitor C5. The other ends of the tenth resistor R10 and the fifth capacitor C5 are grounded. The other end of the eleventh resistor R11 is connected to the fourth capacitor C4 and then grounded. The drain of the third transistor M3 is connected to the other end of the ninth resistor R9. The gate of the fourth transistor M4 is connected to the other end of the first DC blocking capacitor C6. The source of the fourth transistor M4 is grounded. The drain of the third transistor M3 serves as the output terminal of the common-source cascode low-noise amplifier circuit, and the gate of the transistor M4 serves as the input terminal of the common-source cascode low-noise amplifier circuit.
5. The high-reliability, low-noise amplifier chip according to claim 4, characterized in that, The high input power protection circuit includes a twelfth resistor R12, m forward-connected series diodes D2, and n reverse-connected series diodes D3, where m and n are integers greater than or equal to 1. One end of the twelfth resistor R12 is connected to the drain of the fourth transistor M4 in the cascode low-noise amplifier structure, and the other end of the twelfth resistor R12 is connected to the anode of the first diode D21 of the m forward-connected series diodes D2 and the last diode D3 of the n reverse-connected series diodes D3. n The cathodes are connected, and the last diode D2 of the m forward-connected series diodes D2 is connected. m The cathode of the diode and the anode of the first diode D31 of the n reverse-connected series diodes D3 are both grounded.
6. The high-reliability, low-noise amplifier chip according to claim 5, characterized in that, The high-reliability, low-noise amplifier chip also includes a choke inductor L1 and a filter capacitor C8. The drain of the third transistor M3 is connected to one end of the choke inductor L1 and one end of the second DC blocking capacitor C7. The other end of the second DC blocking capacitor C7 is connected to the RF signal output terminal RFout. The other end of the choke inductor L1 is connected to the power supply terminal Vdd and one end of the filter capacitor C8. The other end of the filter capacitor C8 is connected to ground.