Operational amplifier circuit and liquid crystal display

Abstract

The invention provides an output stage design of an operational amplifier circuit without triple well digging, which comprises the design of two half-voltage operational amplifiers on the same P-type substrate, is used for reducing the manufacturing of a layer of photomask and related procedures, can also reduce the design of a high-voltage N-type well, and further reduces the area of an N-type transistor.

Description

Technical Field

[0001] This application belongs to the field of circuits and relates to operational amplifiers. Background Technology

[0002] Liquid crystal displays (LCDs) are currently the most important display technology. Operational amplifiers (OPAs) are the most frequently used analog circuit components in LCDs. To reduce the power consumption of OPAs, partitioned power supplies are used in applications to achieve this.

[0003] Please refer to Figure 1A The diagram shows the circuit architecture of a typical half-voltage range operational amplifier 110. The input voltage range of the input terminal VX 120 is between voltage VGMA1 and voltage VGMA11, which is less than the range between voltage AVDD and voltage VBOT. Generally, voltage VGMA1 is lower than the high operating voltage AVDD of operational amplifier 110, while voltage VGMA11 is higher than the low operating voltage VBOT of operational amplifier 110.

[0004] Please refer to Figure 1B The diagram shows the circuit architecture of a typical half-voltage range operational amplifier 130. The input voltage range of the input terminal VY 140 is between voltage VGMA12 and voltage VGMA22, which is less than the range between voltage VTOP and voltage AGND. Generally, VGMA12 is lower than the high operating voltage VTOP of operational amplifier 130, while VGMA22 is higher than the low operating voltage AGND of operational amplifier 140.

[0005] Please refer to Figure 1C As shown, it is Figure 1A and Figure 1B The diagram shows the operating voltage and input voltage ranges of the two operational amplifiers 110 and 130. As shown, the low operating voltage of operational amplifier 110 is VBOT, and the high operating voltage of operational amplifier 130 is VTOP. Generally speaking, voltage VBOT is equal to voltage VTOP, and also equal to half of voltage AVDD.

[0006] Please refer to Figure 2The diagram shows the circuit architecture of a commonly used operational amplifier circuit 200 with two half-voltage ranges. The operational amplifier 200 includes a first operational amplifier 210 and a second operational amplifier 230. The high operating voltage of the first operational amplifier 210 is AVDD. The low operating voltage of the second operational amplifier 230 is AGND. A power supply terminal 250 provides a medium voltage (AVDD / 2) that is the low operating voltage of the first operational amplifier 210 and the high operating voltage of the second operational amplifier 230. The current through the first operational amplifier 210 is I1. The current through the second operational amplifier 230 is I2. Therefore, the current supplied by the power supply terminal 250 is I1-I2. To minimize the current supplied by the power supply terminal 250, it is obvious that I1 should be equal to I2. The quiescent power P of the operational amplifier circuit 200 is... static It can be either AVDD*I1 or AVDD*I2.

[0007] When a liquid crystal display (LCD) requires N analog circuits, where N is a natural number, and each analog circuit uses a full-voltage operational amplifier, since the power of each full-voltage operational amplifier is the voltage AVDD multiplied by the current I, the total static power P of all full-voltage operational amplifiers in the LCD is... static It is AVDD*I*N.

[0008] When LCD monitors are redesigned Figure 2 When the operational amplifier circuit 200 is shown in two half-voltage ranges, N / 2 operational amplifier circuits 200 are required. In other words, the total quiescent power P of all operational amplifier circuits 200 in the liquid crystal display is... static It is AVDD*I1*N / 2 or AVDD*I2*N / 2. When the current I is close to the current I1 or I2, the liquid crystal display using the operational amplifier circuit 200 can save half of the static power.

[0009] Please refer to Figure 3 As shown, it is Figure 2 The diagram shows a schematic of the output stage circuit 300 of the operational amplifier circuit 200. This output stage circuit 300 is a part of the operational amplifier circuit 200 and is used to output signal Y. n and Y n+1 The output stage circuit of the first operational amplifier 210 includes a P-type metal-oxide-semiconductor (PMOS) 1 310 and an N-type metal-oxide-semiconductor (NMOS) 1 320 connected in series. Similarly, the output stage circuit of the second operational amplifier 230 includes a P-type metal-oxide-semiconductor (PMOS) 2 330 and an N-type metal-oxide-semiconductor (NMOS) 2 340 connected in series. The output signal Y is located at the junction of the PMOS 1 310 and NMOS 1 320. nSimilarly, the output signal Y is located at the connection point between PMOS2 330 and NMOS2 340. n+1 .

[0010] Please refer to Figure 4 As shown, it is Figure 3 The diagram shows a cross-sectional view of the metal-oxide-semiconductor (MOS) components of the output stage circuit 300. On the left side of this cross-sectional view is the output stage circuit of the first operational amplifier 210, and on the right side is the output stage circuit of the second operational amplifier 230. The output stage circuit of the first operational amplifier 210 sequentially includes the aforementioned PMOS1 310 and NMOS1 320. The output stage circuit of the second operational amplifier 230 sequentially includes the aforementioned PMOS2 330 and NMOS2 340.

[0011] Below the four transistors is a P-type substrate (P-Substrate, or simply P-sub), which is connected to the AGND ground potential of 0V. In the fabrication of this P-type substrate, PMOS1 310 and PMOS2 330 are designed in high-voltage N-type wells (HVNW), while NMOS1 320 and NMOS2 340 are designed in high-voltage P-type wells (HVPW). The high-voltage P-type well (HVPW) of NMOS2 340 is connected to the P-type substrate, and both can be connected to either AGND or 0V.

[0012] However, the NMOS1 320's bulk or body is not connected to the AGND potential, but rather to the aforementioned VBOT or AVDD / 2 voltage. Therefore, the NMOS1 320's bulk must be isolated from the P-type substrate connected to the AGND potential, which requires an underlying deep N-well (DNW) and an adjacent high-voltage N-type well (HVNW) to isolate the P-type substrate and the high-voltage P-type well (HVPW).

[0013] The NMOS1 320 employs a deep N-well design, which necessitates a triple-well process, adding an extra layer of photomask and related steps. Furthermore, the layout area of ​​the first operational amplifier 210 needs to be increased to accommodate the adjacent high-voltage P-type well (HVPW), all of which impact chip cost.

[0014] If the base (bulk or body) terminal of the NMOS1 320 is not biased using a deep N-well design, but instead shares the same AGND potential as the P-type substrate, a severe body effect will occur. This will increase the threshold voltage of the NMOS1 320, causing it to turn off. Consequently, the first operational amplifier 210 will not function properly. Similarly, when the base of the PMOS2 330 of the second operational amplifier 230 is connected to the voltage AVDD, it will also be affected by the body effect.

[0015] Please refer to Figure 5A The diagram shown illustrates the terminals of a traditional transistor. B represents the substrate, G the gate, S the source, and D the drain. Please refer to [reference needed]. Figure 5B The diagram illustrates the substrate effect of a metal-oxide-semiconductor (MOSFET). This MOSFET conducts when the voltage Vgs exceeds the critical voltage Vth. The higher the voltage Vbs between the source and substrate, the higher the critical voltage Vth. In other words, the higher the voltage Vgs required to turn on the transistor.

[0016] Please refer to Figure 6 The diagram shows a schematic of the output stage circuit 600 of a conventional operational amplifier circuit. This output stage circuit 600 includes a P-type metal-oxide-semiconductor transistor (PMOS) 610 and an N-type metal-oxide-semiconductor transistor (NMOS) 650. The output signal Vout of this output stage circuit is connected to the drain of the NMOS 650 and the source of the PMOS 610.

[0017] Those skilled in the art will understand that this output stage circuit 600 is only a part of the operational amplifier circuit. For example, please refer to... Figure 12 As shown, it is a circuit diagram of the output stage circuit of a traditional operational amplifier. Figure 6 The PMOS 610 shown can be Figure 12 The transistor M1, NMOS 650 can be Figure 12 The transistor M5.

[0018] For another example, please refer to Figure 13A The diagram shows a schematic of a conventional operational amplifier. Its output stage circuit includes a P-type metal-oxide-semiconductor transistor (MP6) and an N-type metal-oxide-semiconductor transistor (MN6). These two transistors, MP6 and MN6, operate between voltages AVDD and HAVDD. Figure 6 The PMOS 610 shown can be Figure 13A The transistor MP6 and NMOS650 can be Figure 13A The transistor MN6. As mentioned earlier. Figure 6The NMOS 650 shown requires a deep N-well process design with triple drilling.

[0019] Therefore, there is an urgent need for an operational amplifier output stage design that does not require triple well drilling, so as to save the production of one more photomask and its related processes, and also to reduce the design of high-voltage N-type wells, further reducing the area of ​​N-type transistors. Summary of the Invention

[0020] This application proposes an operational amplifier circuit to address the shortcomings of existing technologies, with the aim of reducing manufacturing costs.

[0021] According to an embodiment of this application, an operational amplifier circuit is provided, characterized in that it comprises: a first operational amplifier, the output stage of which further comprises a first P-type metal-oxide-semiconductor transistor (PMOS1) and a first N-type metal-oxide-semiconductor transistor (NMOS1), a first output signal of the first operational amplifier being connected to the source of the first P-type PMOS1 and the drain of the first N-type NMOS1, the drain of the first P-type PMOS1 being connected to voltage AVDD, and the source of the first N-type NMOS1 being connected to half voltage HAVDD, wherein the half voltage HAVDD is half of the voltage AVDD; and a second operational amplifier, the output stage of which is connected to the output stage of the first operational amplifier, the output stage of the second operational amplifier operating between the half voltage HAVDD and ground voltage GND, wherein the operational amplifier circuit is located on a P-type substrate, the first N-type NMOS1 does not contain a deep N-well, and the substrate of the first N-type NMOS1 and the P-type substrate are connected to the ground voltage GND.

[0022] To implement the operational amplifier circuit on the same P-type substrate, the output stage circuit of the second operational amplifier further includes a second P-type metal-oxide-semiconductor transistor (PMOS2) and a second N-type metal-oxide-semiconductor transistor (NMOS2). The second output signal of the second operational amplifier is connected to the source of the second P-type PMOS2 and the drain of the second N-type NMOS2. The drain of the second P-type PMOS2 is connected to the half voltage HAVDD, and the source of the second N-type NMOS2 is connected to the ground voltage GND. The second N-type NMOS2 does not contain a deep N-well.

[0023] In order for the operational amplifier circuit to operate normally during instantaneous charging and discharging, it is characterized by further including a first bias current source, which is connected between the first output signal and the common ground voltage VSS or the ground voltage GND.

[0024] In order for the operational amplifier circuit to operate normally during instantaneous charging and discharging, it is characterized by further including a third N-type metal-oxide-semiconductor transistor, the source of which is connected to the first output signal, and the drain of which is connected between the common ground voltage VSS and the ground voltage GND. The third N-type metal-oxide-semiconductor transistor does not contain a deep N-well.

[0025] In order for the operational amplifier circuit to operate normally during instantaneous charging and discharging, it is characterized by further including a second bias current source, which is connected between the voltage AVDD and the second output signal.

[0026] In order for the operational amplifier circuit to operate normally during instantaneous charging and discharging, the feature is that the substrate of the second P-type metal-oxide-semiconductor transistor PMOS2 is connected to the voltage AVDD.

[0027] To provide a rail-to-rail operational amplifier circuit, the operational amplifier circuit is characterized in that it is a rail-to-rail operational amplifier circuit.

[0028] According to an embodiment of this application, a liquid crystal display is provided, characterized in that it includes a plurality of liquid crystal display units; and a plurality of operational amplifier circuits as described above, for providing control signals to the plurality of liquid crystal display units respectively.

[0029] In summary, this application provides an output stage design for an operational amplifier circuit that does not require triple well drilling. The design includes two half-voltage operational amplifiers on the same P-type substrate, which reduces the fabrication of a photomask and related processes, and also eliminates the need for high-voltage N-type well design, further reducing the area of ​​N-type transistors. Attached Figure Description

[0030] Figure 1A This is a circuit diagram of a commonly used half-voltage range operational amplifier 110.

[0031] Figure 1B This is a circuit diagram of a commonly used half-voltage range operational amplifier 130.

[0032] Figure 1C for Figure 1A and Figure 1B The operating voltage and input voltage ranges of the two operational amplifiers 110 and 130 are shown.

[0033] Figure 2 This is a circuit architecture diagram of a commonly used operational amplifier circuit 200 with two half-voltage ranges.

[0034] Figure 3 for Figure 2 The circuit diagram of the output stage circuit 300 of the operational amplifier circuit 200 shown is shown.

[0035] Figure 4 for Figure 3 The diagram shows a cross-sectional view of the metal-oxide-semiconductor component of the output stage circuit 300.

[0036] Figure 5A This is a schematic diagram of the terminals of a traditional transistor.

[0037] Figure 5B This is a schematic diagram of the substrate effect in a metal-oxide-semiconductor transistor.

[0038] Figure 6 This is a circuit diagram of the output stage circuit 600 of a traditional operational amplifier circuit.

[0039] Figure 7 This is a circuit diagram of the output stage circuit 700 of an operational amplifier according to an embodiment of this application.

[0040] Figure 8 This is a circuit diagram of the output stage circuit 800 of an operational amplifier according to an embodiment of this application.

[0041] Figure 9 This is a circuit diagram of the output stage circuit 900 of an operational amplifier according to an embodiment of this application.

[0042] Figure 10 This is a timing diagram of the output stage signal of an operational amplifier according to an embodiment of the present application.

[0043] Figure 11 This is a circuit diagram of the output stage circuit 1100 of an operational amplifier according to an embodiment of this application.

[0044] Figure 12 This is a circuit diagram of the output stage of a traditional operational amplifier.

[0045] Figure 13A This is a circuit diagram of a traditional operational amplifier.

[0046] Figure 13B This is a circuit diagram of a traditional operational amplifier. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] The terms “first,” “second,” “third,” etc. (if present) in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described herein may be used interchangeably where appropriate. In the description of this application, “plural” means two or more, unless otherwise expressly and specifically defined. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. Such functional entities may be implemented in software, in one or more hardware circuits or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0049] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0050] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections via an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the aforementioned terms in this application according to the specific circumstances.

[0051] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the drawings and specific embodiments.

[0052] Please refer to Figure 7As shown, it is a circuit diagram of the output stage circuit 700 of an operational amplifier according to an embodiment of this application. Figure 7 The output stage circuit 700 of the operational amplifier shown is Figure 6 The illustrated operational amplifier output stage circuit 600 is an improvement. The improvements provided in this application are applicable to… Figure 12 and Figure 13A The output stage of the operational amplifier.

[0053] The output stage circuit 700 includes a P-type metal-oxide-semiconductor transistor (PMOS) 610 and an N-type metal-oxide-semiconductor transistor (NMOS) 750. The output signal Vout of this output stage circuit is connected to the drain of the NMOS 750 and the source of the PMOS 610.

[0054] Unlike the NMOS 650, the NMOS 750 is designed without a deep N-well. This allows for the reduction of one deep N-well photomask layer and related process steps in the manufacturing process. Furthermore, the NMOS 750 does not require a surrounding high-voltage N-well, resulting in a smaller chip area compared to the NMOS 650.

[0055] Because the NMOS 750 substrate is in contact with the P-type substrate, and the P-type substrate is connected to ground potential AGND, the NMOS 750 substrate must also be connected to ground potential AGND. This means the high-voltage P-type well (HVPW) under the NMOS 750 must also be connected to ground potential AGND. If the high-voltage P-type well (HVPW) under the NMOS 750 is connected to voltage VBOT, it will cause leakage current to the P-type substrate.

[0056] When the NMOS 750 substrate is connected to ground potential AGND, and the source terminal Vs is at voltage VBOT, HVADD, or AVDD / 2, then the voltage Vbs is also at voltage VBOT, HVADD, or AVDD / 2. Because the voltage Vbs is too high, the critical voltage Vth will also be too high. Figure 7 When the operational amplifier is in steady state, the NMOS 750 will turn off because Vgs is less than the critical voltage Vth.

[0057] Please refer to Figure 8 As shown, it is a circuit diagram of the output stage circuit 800 of an operational amplifier according to an embodiment of this application. Figure 8 The operational amplifier output stage circuit 800 shown is Figure 7 The illustrated operational amplifier output stage circuit 700 is an improvement. The improvements provided in this application are applicable to… Figure 12 and Figure 13A The output stage of the operational amplifier.

[0058] and Figure 7Compared to the output stage circuit 700 shown, Figure 8 The output stage circuit 800 shown includes an additional bias current source 810. This bias current source 810 is connected between the output signal Vout and the common ground voltage VSS. When the operational amplifier is in an unstable state, during the instantaneous transition of its input voltage, such as from a high voltage to a low voltage, the Vgs voltage of the NMOS 750 is increased. Since the Vgs voltage is greater than the threshold voltage Vth, the NMOS 750 can be turned on.

[0059] Once the NMOS 750 is turned on, it will provide sufficient current I. MN The voltage of the output signal Vout is pulled up. When the voltage of the output signal Vout approaches the input voltage of the operational amplifier, the voltage Vgs becomes less than the critical voltage Vth, and the NMOS750 turns off again. At this time, the bias current source 810 is responsible for pulling the output signal Vout to the set voltage and providing a stable bias current.

[0060] Please refer to Figure 9 As shown, it is a circuit diagram of the output stage circuit 900 of an operational amplifier according to an embodiment of this application. Figure 9 The output stage circuit 900 of the operational amplifier shown is Figure 7 The illustrated operational amplifier output stage circuit 700 is an improvement. The improvements provided in this application are applicable to… Figure 12 and Figure 13A The output stage of the operational amplifier.

[0061] and Figure 7 Compared to the output stage circuit 700 shown, Figure 9 The output stage circuit 900 shown includes an additional N-type metal-oxide-semiconductor transistor, NMOS3 910. This NMOS3 910 is connected between the output signal Vout and the ground voltage GND. The function of this NMOS 910 is... Figure 8 The bias current source 810 shown is similar.

[0062] When the operational amplifier is in an unstable state, the input voltage transitions instantaneously, such as from a high voltage to a low voltage, which will increase the Vgs voltage of the NMOS 750. Since the Vgs voltage is greater than the threshold voltage Vth, the NMOS 750 will turn on.

[0063] Once the NMOS 750 is turned on, it will provide sufficient current I. MN This causes the output signal Vout to rise. When the output signal Vout approaches the input voltage of the operational amplifier, the Vgs voltage falls below the critical voltage Vth, and the NMOS750 turns off again. At this time, the NMOS910 is responsible for maintaining the stable bias current I. BBy means of bias current I B This compensates for the transistors in the output stage, allowing the output stage transistors, which were originally affected by the substrate effect, to be properly biased, and their instantaneous charging and discharging behavior to operate normally, without being limited by the bias current in terms of driving capability.

[0064] Please refer to Figure 10 As shown, it is a timing diagram of the output stage signal of an operational amplifier according to an embodiment of this application. Figure 10 The diagram can be applied to Figure 8 or Figure 9 Examples of implementations. When applicable Figure 8 In the embodiment shown, the bias current source 810 is set to 5μA. It can be seen that I... chg Dynamic charge and discharge currents affect the Io of the PMOS 610. MP Current and I of NMOS 750 MN When the current is current, the bias current I B It provides a stable bias current.

[0065] Please refer to Figure 11 As shown, it is a circuit diagram of the output stage circuit 1100 of an operational amplifier according to an embodiment of this application. Figure 11 The output stage circuit 1100 of the operational amplifier shown is Figure 7 The output stage circuit 700 of the operational amplifier shown is an improvement. This output stage circuit 1100 operates between ground voltage VSS and voltage VTOP, or voltage HAVDD, or AVDD / 2.

[0066] The output stage circuit 1100 includes a P-type metal-oxide-semiconductor transistor (PMOS) 1110 and an NMOS 750. The improvements provided in this application are applicable to... Figure 13B The output stage of an operational amplifier. The PMOS1110 can be... Figure 13B The transistor shown is MP6, while the NMOS 750 could be... Figure 13B The transistor MN6 is shown. The output signal Vout of this output stage circuit is connected to the drain of the NMOS750 and the source of the PMOS1110.

[0067] The base of the PMOS1110 can be connected to voltage AVDD. When the base of the PMOS1110 is connected to voltage AVDD, and the source terminal Vs is voltage VBOT, HVADD, or AVDD / 2, then voltage Vbs is voltage VBOT, HVADD, or AVDD / 2. Because voltage Vbs is too high, the critical voltage Vth will also be too high. Figure 11 When the operational amplifier is in steady state, the PMOS1110 will turn off because Vgs is less than the threshold voltage Vth.

[0068] Figure 11 The output stage circuit 1100 shown includes an additional bias current source 1120. This bias current source 1120 is connected between the output signal Vout and the voltage AVDD. When the operational amplifier is in an unstable state, during the instantaneous transition of its input voltage, such as from a high voltage to a low voltage, the Vgs voltage of the PMOS 1110 is increased. Since the Vgs voltage is greater than the threshold voltage Vth, the PMOS 1110 can be turned on.

[0069] When the PMOS1110 is turned on, it will provide sufficient current I. P The voltage of the output signal Vout is pulled up. When the voltage of the output signal Vout approaches the input voltage of the operational amplifier, the voltage Vgs becomes less than the critical voltage Vth, and the PMOS1110 turns off again. At this time, the bias current source 1120 is responsible for pulling the output signal Vout to the set voltage and providing a stable bias current.

[0070] According to an embodiment of this application, an operational amplifier circuit is provided, characterized in that it comprises: a first operational amplifier, the output stage of which further comprises a first P-type metal-oxide-semiconductor transistor (PMOS1) and a first N-type metal-oxide-semiconductor transistor (NMOS1), a first output signal of the first operational amplifier being connected to the source of the first P-type PMOS1 and the drain of the first N-type NMOS1, the drain of the first P-type PMOS1 being connected to voltage AVDD, and the source of the first N-type NMOS1 being connected to half voltage HAVDD, wherein the half voltage HAVDD is half of the voltage AVDD; and a second operational amplifier, the output stage of which is connected to the output stage of the first operational amplifier, the output stage of the second operational amplifier operating between the half voltage HAVDD and ground voltage GND, wherein the operational amplifier circuit is located on a P-type substrate, the first N-type NMOS1 does not contain a deep N-well, and the substrate of the first N-type NMOS1 and the P-type substrate are connected to the ground voltage GND.

[0071] To implement the operational amplifier circuit on the same P-type substrate, the output stage circuit of the second operational amplifier further includes a second P-type metal-oxide-semiconductor transistor (PMOS2) and a second N-type metal-oxide-semiconductor transistor (NMOS2). The second output signal of the second operational amplifier is connected to the source of the second P-type PMOS2 and the drain of the second N-type NMOS2. The drain of the second P-type PMOS2 is connected to the half voltage HAVDD, and the source of the second N-type NMOS2 is connected to the ground voltage GND. The second N-type NMOS2 does not contain a deep N-well.

[0072] In order for the operational amplifier circuit to operate normally during instantaneous charging and discharging, it is characterized by further including a first bias current source, which is connected between the first output signal and the common ground voltage VSS or the ground voltage GND.

[0073] In order for the operational amplifier circuit to operate normally during instantaneous charging and discharging, it is characterized by further including a third N-type metal-oxide-semiconductor transistor, the source of which is connected to the first output signal, and the drain of which is connected between the common ground voltage VSS and the ground voltage GND. The third N-type metal-oxide-semiconductor transistor does not contain a deep N-well.

[0074] In order for the operational amplifier circuit to operate normally during instantaneous charging and discharging, it is characterized by further including a second bias current source, which is connected between the voltage AVDD and the second output signal.

[0075] In order for the operational amplifier circuit to operate normally during instantaneous charging and discharging, the feature is that the substrate of the second P-type metal-oxide-semiconductor transistor PMOS2 is connected to the voltage AVDD.

[0076] To provide a rail-to-rail operational amplifier circuit, the operational amplifier circuit is characterized in that it is a rail-to-rail operational amplifier circuit.

[0077] According to an embodiment of this application, a liquid crystal display is provided, characterized in that it includes a plurality of liquid crystal display units; and a plurality of operational amplifier circuits as described above, for providing control signals to the plurality of liquid crystal display units respectively.

[0078] In summary, this application provides an output stage design for an operational amplifier circuit that does not require triple well drilling. The design includes two half-voltage operational amplifiers on the same P-type substrate, which reduces the fabrication of a photomask and related processes, and also eliminates the need for high-voltage N-type well design, further reducing the area of ​​N-type transistors.

[0079] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this application, based on the technical solution and application concept of this application, should be included within the scope of protection of this application.

Claims

1. An operational amplifier circuit, characterized in that, Include: The first operational amplifier, its output stage circuit further includes a first P-type metal-oxide-semiconductor transistor (PMOS1) and a first N-type metal-oxide-semiconductor transistor (NMOS1). The first output signal of the first operational amplifier is connected to the source of the first P-type PMOS1 and the drain of the first N-type NMOS1. The drain of the first PMOS1 is connected to voltage AVDD, and the source of the first NMOS1 is connected to half-voltage HAVDD, where half-voltage HAVDD is half of voltage AVDD. The output stage of the second operational amplifier is connected to the output stage of the first operational amplifier, and the output stage of the second operational amplifier operates between the half-voltage HAVDD and the ground voltage GND. The operational amplifier circuit is located on a P-type substrate. The first N-type metal-oxide-semiconductor transistor NMOS1 does not contain a deep N-well, and the substrate of the first N-type metal-oxide-semiconductor transistor NMOS1 is connected to the ground voltage GND along with the P-type substrate.

2. The operational amplifier circuit as described in claim 1, characterized in that, The output stage circuit of the second operational amplifier further includes a second P-type metal-oxide-semiconductor transistor (PMOS2) and a second N-type metal-oxide-semiconductor transistor (NMOS2). The second output signal of the second operational amplifier is connected to the source of the second P-type PMOS2 and the drain of the second N-type NMOS2. The drain of the second P-type PMOS2 is connected to the half voltage HAVDD, and the source of the second N-type NMOS2 is connected to the ground voltage GND. The second N-type NMOS2 does not contain a deep N-well.

3. The operational amplifier circuit as described in claim 1, characterized in that, It further includes a first bias current source connected between the first output signal and the common ground voltage VSS or the ground voltage GND.

4. The operational amplifier circuit as described in claim 1, characterized in that, It further includes a third N-type metal-oxide-semiconductor transistor, the source of which is connected to the first output signal, and the drain of which is connected between the common ground voltage VSS and the ground voltage GND. The third N-type metal-oxide-semiconductor transistor does not include a deep N-well.

5. The operational amplifier circuit as described in claim 2, characterized in that, It further includes a second bias current source, which is connected between the voltage AVDD and the second output signal.

6. The operational amplifier circuit as described in claim 5, characterized in that, The substrate of the second P-type metal-oxide-semiconductor transistor PMOS2 is connected to the voltage AVDD.

7. The operational amplifier circuit as described in claim 1, characterized in that, The operational amplifier circuit mentioned above is a rail-to-rail operational amplifier circuit.

8. A liquid crystal display, characterized in that, It includes a plurality of liquid crystal display units; and a plurality of operational amplifier circuits as described in any one of claims 1 to 7, for providing control signals to the plurality of liquid crystal display units respectively.

Images