Power amplifier combiner

Abstract

The invention relates to a power amplifier combiner. An apparatus is described that includes a first amplifier having a first amplifier output and configured to provide a first signal having a first power level at the first amplifier output. The apparatus further includes a second amplifier having a second amplifier output and configured to provide a second signal having a second power level at the second amplifier output, the second power level being higher than the first power level. The apparatus further includes a combiner circuit having a quadrature phase terminal coupled to the first amplifier output, an in-phase terminal coupled to the second amplifier output, a reference terminal coupled to a combiner output, and an isolation terminal coupled to the combiner output. And the isolation terminal is coupled to a direct current voltage source.

Description

Technical Field

[0001] This application relates to a power amplifier combiner. Background Technology

[0002] High-capacity wireless communication, including 5G and later versions, presents challenges for power amplifiers (PAs) in processing signals with high peak-to-average power ratios (PAPR). High deep back-off efficiency and wideband operation are also desirable for power amplifiers to support wireless communication. Summary of the Invention

[0003] According to at least one example, a device is described having a first amplifier (carrier or main), the first amplifier having a first amplifier output and configured to provide a first signal having a first power level at the first amplifier output. In at least one example, the device further includes a second amplifier (peak or auxiliary), the second amplifier having a second amplifier output and configured to provide a second signal having a second power level at the second amplifier output, the second power level being higher than the first power level. In at least one example, the device further includes a combiner circuit having a quadrature terminal (through), a non-inverting terminal (coupled), a reference terminal (reference), and an isolation terminal (isolation). The non-inverting terminal is coupled to the first amplifier output, the quadrature terminal is coupled to the second amplifier output, the reference terminal is coupled to the combiner output, and the isolation terminal is coupled to a direct current (DC) voltage source.

[0004] A device is described comprising a transmission circuit having a transmission input, a first transmission output, and a second transmission output. In at least one embodiment, the device includes a first amplifier (carrier or main) having a first amplifier input and a first amplifier output, the first amplifier input being coupled to the first transmission output. In at least one embodiment, the device includes a second amplifier (peak or auxiliary) having a second amplifier input and a second amplifier output, the second amplifier input being coupled to the second transmission output, and the first amplifier and the second amplifier having different power levels in a saturated state. In at least one embodiment, the device includes a quadrature hybrid combiner coupled between the first amplifier output and the second amplifier output and the combiner output.

[0005] A method is described, comprising: receiving a first signal; and, in response to a power level of the first signal being below a threshold, providing a second signal having a first power level to a non-inverting terminal of a quadrature mixer using a first amplifier. In at least one embodiment, in response to a power level of the first signal being above the threshold, the method includes providing a third signal having a second power level to the non-inverting terminal using the first amplifier. In at least one embodiment, the method includes providing a fourth signal having a third power level to a quadrature phase terminal of the quadrature mixer using a second amplifier, the third power level being higher than both the first and second power levels. In at least one embodiment, the method includes providing a fifth signal as an output signal at a reference terminal of the quadrature mixer based on either the second signal or a combination of the third and fourth signals. Attached Figure Description

[0006] The examples will be more fully understood from the detailed description and accompanying drawings given below; however, the accompanying drawings should not be construed as limiting this disclosure to the specific examples, but are intended for explanation and understanding only.

[0007] Figure 1 This is a schematic diagram of a power amplifier based on at least one example.

[0008] Figure 2A It is a graph showing the transient peak and average power of the communication signal received at the input of the power amplifier according to at least one example.

[0009] Figure 2B It is a graph showing the power density function and efficiency as a function of the power amplifier's back-off power, based on at least one example.

[0010] Figure 3 It is based on at least one instance Figure 1 A schematic diagram of the quadrature hybrid coupler of the power amplifier.

[0011] Figure 4 It is based on at least one instance Figure 1 A schematic diagram of the branch coupler of the power amplifier.

[0012] Figure 5 It is based on at least one instance Figure 1 A schematic diagram of the Lange coupler for a power amplifier.

[0013] Figure 6 It is based on at least one instance Figure 1 A schematic diagram of the transformer coupler of the power amplifier.

[0014] Figure 7It is a schematic diagram of a circuit including a transformer coupler and a capacitor at the port, based on at least one example. The circuit may be... Figure 1 It is part of the power amplifier.

[0015] Figure 8A Figure B is a graph showing the first coupling factor and the associated phase imbalance as a function of frequency, according to at least some examples.

[0016] Figure 8C Figure D is a graph showing the second coupling factor and the associated phase imbalance as a function of frequency, according to at least some examples.

[0017] Figure 8E F is a graph showing the variation of the third coupling factor and the associated phase imbalance with frequency, according to at least some examples.

[0018] Figure 9 This is a schematic diagram of a power amplifier with a transformer coupler and a capacitor at the port, based on at least one example.

[0019] Figure 10A It is shown according to at least one instance Figure 9 The curves showing the current distribution of the main amplifier and auxiliary amplifier of the power amplifier as the back-off power changes.

[0020] Figure 10B It is a graph showing the percentage contribution of the power of the main amplifier and auxiliary amplifier to the input power as the input power or output power increases, according to at least one example.

[0021] Figure 11 It is shown according to at least one instance Figure 9 The graph shows the efficiency of the power amplifier at different frequencies as a function of backoff power.

[0022] Figure 12 It is a schematic diagram of a power amplifier according to at least one example, the power amplifier having a transformer coupler with a center tap and coupling capacitors at the port and the center tap.

[0023] Figure 13A It is shown according to at least one instance Figure 12 The graph shows the efficiency of the power amplifier at different frequencies as a function of backoff power.

[0024] Figure 13B This illustrates, based on at least one instance, different back-off powers at the center frequency f0. Figure 12 The graph shows the efficiency of the power amplifier.

[0025] Figure 14It is a schematic diagram of a power amplifier according to at least one example, the power amplifier having a transformer coupler with a center tap and coupling capacitors at the port and the center tap.

[0026] Figure 15 It is a schematic diagram of a power amplifier according to at least one example, the power amplifier having a transformer coupler with a center tap and coupling capacitors at the port and the center tap, and having a 1:n transformer.

[0027] Figure 16A Figure C is a schematic diagram of power amplifiers with different coupling coefficients, transformer sizes and back-off power, based on at least some examples.

[0028] Figure 17 These are a set of graphs illustrating the effect of second harmonic impedance.

[0029] Figure 18A This is a schematic diagram illustrating the setup for determining the input impedance at the through port and the coupled port at the second harmonic frequency, according to at least one example.

[0030] Figure 18B This is a set of Smith charts showing the load impedance of an amplifier connected to the coupling port and through port of a power amplifier at the second harmonic frequency, according to at least one example.

[0031] Figure 19 This is a schematic diagram of a power amplifier with a selectable combiner, based on at least one example.

[0032] Figure 20 It is a flowchart of a method for operating a power amplifier based on at least one instance. Detailed Implementation

[0033] As described above, high-capacity wireless communication in 5G and later versions presents challenges for power amplifiers (PAs) in processing signals with peak-to-average power ratios (PAPR). Power amplifiers may also need to provide high deep back-off efficiency and wideband operation to support wireless communication.

[0034] In at least one instance, a power amplifier is described that includes a transformer-based quadrature hybrid combiner. The transformer-based quadrature hybrid combiner is a four-port device including a reference port, a through port, a coupling port, and an isolation port. In at least one instance, a load is coupled to the reference port, and the isolation port is coupled to ground or a power rail. In at least one instance, the power amplifier includes an asymmetric amplifier coupled to both the through port and the coupling port of the transformer-based quadrature hybrid combiner.

[0035] An asymmetric amplifier comprises a main amplifier (or carrier amplifier) ​​and an auxiliary amplifier (or peak amplifier). In at least one instance, the amplifiers are asymmetric because they (e.g., based on different bias currents, different transistor sizes, etc.) are configured to provide different output power levels in saturation. In at least one instance, the auxiliary amplifier has a higher output power level than the main amplifier in saturation. In at least one instance, the main amplifier is coupled to a coupling port of a transformer-based quadrature hybrid combiner, and the auxiliary amplifier is coupled to a through port. In at least one instance, a coupling capacitor is provided, coupled between the inductor terminals (e.g., primary and secondary windings) of the transformer-based quadrature hybrid combiner. In at least one instance, an additional capacitor is coupled between the inductor terminals and a reference rail (e.g., ground). In at least one instance, the main amplifier is a Class AB amplifier. In at least one instance, the auxiliary amplifier is a Class C amplifier.

[0036] In at least one instance, the input power signal (e.g., a 5G signal with any suitable modulation) is received by a power divider that divides the input power signal for input to a main amplifier and an auxiliary amplifier. For example, the input power signal is divided into a first signal and a second signal, wherein the first signal is provided to the main amplifier and the second signal is provided to the auxiliary amplifier. In at least one instance, the main amplifier operates by amplifying the first signal while the auxiliary amplifier is off. Upon exceeding a power threshold, the auxiliary amplifier turns on and amplifies the second signal, while the main amplifier operates in saturation. The outputs of the main amplifier and the auxiliary amplifier are combined by a transformer-based quadrature hybrid combiner and provided to a reference port of the coupled load.

[0037] In at least one instance, any back-off power (e.g., 6 dB to deep back-off level) is achieved by the power amplifier by modifying the capacitance ratio of the capacitors in the inductors coupled to the transformer-based quadrature hybrid combiner, by changing the coupling coefficient between the inductors, and / or the power levels of the main and auxiliary amplifiers. The use of transformers can reduce the size of the power amplifier (e.g., compared to other implementations using transmission lines as matching networks). Transformer-based couplers or combiners for amplifiers also provide higher bandwidth and efficiency compared to transmission lines designed for narrowband operation. In at least one instance, the isolation port of the transformer-based quadrature hybrid combiner is shorted to ground (or coupled to the power rail), allowing the outputs of the main and auxiliary amplifiers to be combined at the reference port (output port) with no (or reduced) loss.

[0038] The power amplifier examples described herein can provide deep back-off enhancement (e.g., >6 dB), enabling the power amplifier to efficiently process signals with a peak-to-average power ratio (PAPR). This is achieved when the input power level is below a threshold, the main amplifier (with a lower output power level) is enabled and the auxiliary amplifier (with a higher output power level) is disabled; and when the input power level exceeds the threshold, the auxiliary amplifier is enabled. Furthermore, the transformer-based quadrature hybrid combiner has a smaller footprint and wider bandwidth (e.g., compared to combiners with transmission lines or combiners with multiple transformers), allowing the power amplifier to be integrated within a semiconductor package and supporting broadband operation.

[0039] In the drawings, the same reference numerals always refer to the same elements, and various features are not necessarily drawn to scale. Here, the same reference numerals or other reference indicators are used in the drawings to indicate features that are (functionally and / or structurally) the same or similar.

[0040] Figure 1 This is a schematic diagram of a power amplifier (PA) 100 according to at least one embodiment. In at least one embodiment, the power amplifier 100 includes a transmission circuit 101, a first power amplifier 102, a second power amplifier 103, and a combiner 104 coupled to a load 105. The power amplifier 100 may have a Doherty amplifier configuration. The transmission circuit 101 is a power divider or power splitter that receives an input signal and divides or separates the input signal into a first signal and a second signal. The input signal can be any signal, such as a modulated 5G communication signal with 256 quadrature amplitude modulation (QAM). The input signal may have a peak-to-average power ratio (PAPR), such as 6 dB and higher.

[0041] In at least one instance, combiner 104 is a 4-port network comprising a reference port, a through port, a coupling port, and an isolation port. In at least one instance, load 105 is coupled to the reference port, and the isolation port is coupled to ground or a power rail. In at least one instance, combiner 104 is an orthogonal hybrid power combiner. In at least one instance, the orthogonal hybrid power combiner is implemented as a transformer having a primary winding and a secondary winding. In at least one instance, combiner 104 is a branch hybrid power combiner. In at least one instance, combiner 104 is a Lange hybrid power combiner.

[0042] In at least one instance, the first amplifier 102 and the second amplifier 103 are asymmetric amplifiers, configured (e.g., based on different DC bias currents, different transistor sizes, etc.) to have different output power levels in saturation. In at least one instance, a first signal is provided to the first amplifier 102 (e.g., a main amplifier) ​​and coupled to the non-inverting port (or coupled port) of the combiner 104. In at least one instance, a second signal is provided to the second amplifier 103 (e.g., an auxiliary amplifier), which is coupled to the through port of the combiner 104. In at least one instance, the first amplifier 102 is configured to provide a first output power level in saturation, and the second amplifier 103 is configured to provide a second output power level in saturation, wherein the second output power level is higher than the first output power level. In at least one instance, the first amplifier 102 operates by amplifying the first signal, while the second amplifier 103 is off. After the input signal power increases above a threshold, the second amplifier 103 turns on and amplifies the second signal, while the first amplifier 102 operates by amplifying the first signal. In at least one instance, the output power level of the first amplifier 102 increases as the input signal power increases. The outputs of the first power amplifier 102 and the second power amplifier 103 are combined by the combiner 104 and provided to a reference port of the coupled load 105. In at least one instance, the first power amplifier 102, the second power amplifier 103, and the combiner 104 are part of an integrated circuit (IC).

[0043] Figure 2A This is graph 200 showing the transient peak and average power of the communication signal received at the input of the power amplifier according to at least one example. Here, the x-axis is time, and the y-axis is the normalized amplitude. Figure 2B Graph 220 shows the power density function and efficiency as a function of the power amplifier's back-off power, according to at least one example. Here, the x-axis is the back-off power level, and the y-axis is the power amplifier's efficiency and power density function (PDF). The modulated input signal 201 can have a high PAPR, indicated by the difference between amplitude levels 202 and 203. Since most signals do not operate at peak levels, the power amplifier is designed to operate at back-off power levels (e.g., back-off level 221) to amplify the input signal where most signals reside. Waveform 222 of graph 220 indicates that the PA's efficiency decreases as the power decreases. The examples of power amplifiers described herein can maintain high efficiency at a variety of back-off power levels.

[0044] Figure 3 This is a schematic diagram of an orthogonal hybrid coupler 300 based on at least one example, the orthogonal hybrid coupler being... Figure 1Examples of combiner 104. In at least one example, quadrature hybrid coupler 300 is a 4-port network comprising a reference port 301, a through port 302 (quadrature port), a coupling port 303 (in-phase port), and an isolation port 304. These four ports are coupled to combiner 310. In at least one example, quadrature hybrid coupler 300 is a 90-degree hybrid coupler. A 90-degree hybrid coupler is operable to separate an input signal into two paths with a 90-degree phase shift between them, or to combine two signals while maintaining high isolation between them. For example, an input signal is received at reference port 301 and divided by the 90-degree hybrid coupler between through port 302 (first output port) and coupling port 303 (second output port), with half the power flowing to coupling port 303 (in-phase or 0° phase shift port) and the other half flowing to through port 302 (quadrature or 90° phase shift port). In at least one instance, the quadrature hybrid coupler 300 is configured as a combiner, wherein a first input signal is provided to a coupling port 303 (in-phase or 0° phase shift port), and a second input signal is provided to a through port 302 (quadrature or 90° phase shift port), and an output signal combining the first and second input signals is provided to a reference port 301.

[0045] In at least one instance, the output of the first power amplifier 102 is coupled to the coupling port 303, and the output of the second power amplifier 103 is coupled to the through port 302. In at least one instance, the load 105 is coupled to the reference port 301. In at least one instance, the isolation port 304 is coupled to ground or a power rail.

[0046] Figure 4 This is a schematic diagram of a branch coupler 400 of a power amplifier according to at least one embodiment. In at least one embodiment, the combiner 310 includes the branch coupler 400. In at least one embodiment, the reference port 301, the through port 302 (quadrature port), the coupling port 303 (non-inverting port), the isolation port 304, and the combiner 310 are implemented as microstrip lines patterned on a dielectric substrate, where Z0 is the characteristic impedance of the microstrip line. In at least one embodiment, each microstrip line within the combiner 310 has a quarter wavelength (λ / 4) at a target frequency. The two microstrip lines of the combiner 310 have [missing information - likely a specific configuration or feature] between the reference port 301 and the through port 302, and between the coupling port 303 and the isolation port 304. Impedance. The two microstrip lines of combiner 310 have Z1 between reference port 301 and through port 302, and between coupling port 303 and isolation port 304, where Z1 is different from Z0. Furthermore, it has... The spacing between the two microstrip lines with impedance Z1 is λ / 4, and the spacing between the two microstrip lines with impedance Z1 is a distance d different from λ / 4. This arrangement can provide unequal S31 and S21 parameters, as described below, which allows tuning the coupling factor K to introduce amplitude imbalance.

[0047] Figure 5 This is a schematic diagram of a Lange coupler 500 for a power amplifier according to at least one embodiment. In at least one embodiment, the combiner 310 includes a Lange coupler 500, which is an example of an orthogonal hybrid coupler. The Lange coupler 500 is a 4-port interdigitated structure, where coupling originates from closely spaced metal lines, such as microstrip lines. In at least one embodiment, the number of conductors in the fingers of the combiner 310 is even. The length of the fingers is set by the center frequency (f0). In at least one embodiment, the finger length is equal to a quarter wavelength of f0, such that the Lange coupler 500 is designed for targeted coupling (e.g., 3 dB or any dB) between the reference port 301 and the coupling port 303 and isolation port 304. In at least one embodiment, the distance 'd' between the spaced metal lines can be adjusted to control the coupling factor of the Lange coupler 500. In at least one embodiment, the distance 'd' is adjusted to achieve asymmetric orthogonal hybridization, where dB(S21) is not equal to dB(S31).

[0048] Figure 6 This is a schematic diagram of a transformer coupler 600 for a power amplifier according to at least one embodiment. In at least one embodiment, the combiner 310 includes the transformer coupler 600, which contains a transformer configured as a quadrature hybrid coupler. In at least one embodiment, a reference port 301, a through port 302 (quadrature port), a coupling port 303 (in-phase port), an isolation port 304, and the combiner 310 are implemented in two windings or coils 610a and 610b. In at least one embodiment, the windings or coils 610a and 610b may at least partially overlap. The windings or coils 610a and 610b may use any shape. In at least one embodiment, a capacitor is coupled to the center tap of the windings or coils 610a and 610b. For example, one end of the capacitor 612a is coupled to the center tap 611a of the winding or coil 610a, while the other end is coupled to ground or a power rail. In at least one instance, one end of capacitor 612b is coupled to the center tap 611b of winding or coil 610b, while the other end is coupled to ground or power rail.

[0049] Figure 7This is a schematic diagram of a circuit 700 having a transformer coupler and coupling capacitors at the ports, according to at least one example. In at least one example, circuit 700 includes a transformer as a combiner 310. One such example of a transformer is a transformer coupler 600, where 'k' is the coupling coefficient between windings or coils 610a and 610b. In some examples, combiner 310 may include... Figure 4 Examples of the combiner described in Figure 2. Here, winding or coil 610a has inductance L1, and winding or coil 610a has inductance L2. In at least one example, a first capacitor 701 with capacitance C2 is coupled to reference port 301 and ground. In at least one example, a second capacitor 702 with capacitance C2 is coupled to through port 302 and ground. In at least one example, a third capacitor 703 with capacitance C2 is coupled to coupling port 303 and ground. In at least one example, a fourth capacitor 704 with capacitance C2 is coupled to isolation port 304 and ground. In at least one example, circuit 700 includes a capacitor coupled between the terminals of winding or coil 610a and 610b. In at least one example, a first capacitor 713 with capacitance C1 is coupled between reference port 301 and coupling port 303. In at least one example, a second coupling capacitor 724 with capacitance C1 is coupled between through port 302 and isolation port 304. In at least one embodiment, the corresponding first capacitor 701, second capacitor 702, third capacitor 703, and fourth capacitor 704, as well as the corresponding first coupling capacitor 724 and second coupling capacitor 713, provide additional control means (knob) to regulate the back-off power of the power amplifier 700. In at least one embodiment, the first power amplifier 102 is coupled to the coupling port 303, while the second power amplifier 103 is coupled to the through port 302.

[0050] In at least one instance, one or more of the corresponding first capacitor 701, second capacitor 702, third capacitor 703, and fourth capacitor 704 and / or first coupling capacitor 724 and second coupling capacitor 713 are variable capacitors with adjustable capacitance. In at least one instance, one or more of the corresponding first capacitor 701, second capacitor 702, third capacitor 703, and fourth capacitor 704 and / or first capacitor 724 and second capacitor 713 have adjustable capacitance. For example, one or more of the corresponding first capacitor 701, second capacitor 702, third capacitor 703, and fourth capacitor 704 and / or first capacitor 724 and second capacitor 713 may have a network of programmable capacitor segments between two capacitor terminals, and the capacitor segments can be connected to or disconnected from the capacitor terminals by switches (e.g., transistors) to decrease or increase the total capacitance between the capacitor terminals.

[0051] In at least one instance, the combiner 310 / 104 is fabricated within a package substrate of a packaged integrated circuit, the packaged integrated circuit comprising... Figure 1 Amplifiers 102 and 103 and transmission circuit 101. In at least one embodiment, combiner 310 / 104 are fabricated on the same semiconductor die, the semiconductor die containing Figure 1 Amplifiers 102 and 103 and transmission circuit 101. In at least one example, combiner 310 / 104 is external to a packaged integrated circuit containing... Figure 1 Amplifiers 102 and 103 and transmission circuitry 101. In such examples, combiner 310 / 104 may be discrete components on a circuit board and electrically coupled to amplifiers 102 and 103 via the circuit board.

[0052] In at least one instance, one or more of the corresponding first capacitor 701, second capacitor 702, third capacitor 703, and fourth capacitor 704 and / or first capacitor 724 and second capacitor 713 are on-die capacitors (e.g., in a capacitor containing...). Figure 1 (On the same semiconductor die as amplifiers 102 and 103 and transmission circuit 101). In at least one instance, one or more of the corresponding first capacitor 701, second capacitor 702, third capacitor 703 and fourth capacitor 704 and / or first capacitor 724 and second capacitor 713 are within an integrated circuit package. In at least one instance, one or more of the corresponding first capacitor 701, second capacitor 702, third capacitor 703 and fourth capacitor 704 and / or first capacitor 724 and second capacitor 713 are off-chip capacitors, and are contained within... Figure 1 The amplifiers 102 and 103 and the transmission circuit 101 are external to the packaged integrated circuit.

[0053] Figure 6 and 7 Orthogonal hybrid couplers can have a smaller footprint than couplers based on transmission lines with similar properties. In some examples, an orthogonal hybrid coupler incorporating an 8-type transformer can have a size of 190 μm × 192 μm for combining 50 GHz signals. In contrast, a transmission line used to provide a 90-degree phase shift at 50 GHz has a length of approximately 750 μm (6000 μm / 4 / sqrt(4)) and a width of approximately 20 μm. In the case of a coupler containing multiple transmission lines, the total length of the transmission lines will be a multiple of 750 μm, which is much larger than the area of ​​an orthogonal hybrid coupler incorporating an 8-type transformer.

[0054] Figure 8AFigures 800 and 820 show the first coupling factor and the associated phase imbalance as a function of frequency, respectively, according to at least some examples. Figure 8C Figures 830 and 840 show the second coupling factor and the associated phase imbalance as a function of frequency, respectively, according to at least some examples. Figure 8E Figures 850 and 860 show the variation of the third coupling factor and the associated phase imbalance with frequency, according to at least some examples. These figures illustrate the effect of changing or adjusting the coupling coefficient k between windings or coils 610a and 610b while maintaining broadband operation as indicated by the phase imbalance. For example, by reducing the coupling coefficient k, the scattering parameters S21 and S31, as indicated by waveforms 801 and 802, are dispersed as indicated by waveforms 831 and 832 and waveforms 851 and 852. Here, S31 is 20Log10(k).

[0055] S31 is the scattering parameter between the first amplifier 102 from the coupling port 303 and the reference port 301 and the load 105. S21 is the scattering parameter between the second amplifier 103 from the through port 302 to the reference port 301 and the load 105. By adjusting the equivalent power ratio between the first amplifier 102 and the second amplifier 103, and the correct turn-on sequence and current distribution from the two amplifiers, a load modulation trajectory is observed in each amplifier, and the entire amplifier can operate together at different back-off efficiency enhancement points. According to at least one example, this allows the stronger second amplifier 103 under equivalent conditions to achieve deeper back-off enhancement. At least one example uses a quadrature hybrid coupler to control the relative strength of the first amplifier 102 and the second amplifier 103. In at least one example, choosing a smaller coupling coefficient k (between the coils of the transformer in the quadrature hybrid coupler) allows more energy to be coupled from the side or port coupled to the second amplifier 103 to the output (or makes the second amplifier 103 stronger), thus achieving deeper back-off.

[0056] Figure 9 This is a schematic diagram of a power amplifier 900 having a transformer coupler and a capacitor at the port, according to at least one example. The connection from the port to circuit 700 is shown here. The power amplifier 900 can be... Figure 1 An example of power amplifier 100, and combiner 310 may be Figure 1 An example of combiner 104. In at least one example, reference port 301 is coupled to load 105 (modeled as resistor R). LThe first amplifier 102 is coupled to coupling port 303, the second amplifier 103 is coupled to through port 302, and the isolation port 304 is coupled to ground. In at least one instance, the first amplifier 102 and the second amplifier 103 have programmable or adjustable sizes. For example, transistors can be used to increase the width of the transistor cell by turning on / off parallel-coupled transistors, and thus modify the output power of the transistor cell.

[0057] In at least one instance, the back-off power depth (e.g., -6dB, -9.5dB, -11dB, etc.) varies with the power or current drive (Ifa) of the first amplifier 102. max ) and the power or current drive of the second amplifier 103 (Isa max The power drawdown varies. In at least one instance, the second amplifier 103 provides higher output power than the first amplifier 102. In at least one instance, the back-off power depth (e.g., -6dB, -9.5dB, -11dB, etc.) varies with the supply voltage (Vdd) of the first amplifier 102. fa ) and the power supply voltage (Vdd) of the second amplifier 103 sa The coupling coefficient k varies with the back-off power. In at least one instance, the capacitance C1 of the corresponding first coupling capacitor 713 and the second coupling capacitor 724 is inversely proportional to the load impedance of the load 105 and varies with the back-off power. In at least one instance, the capacitance C2 of the corresponding first capacitor 701, second capacitor 702, third capacitor 703 and fourth capacitor 704 is inversely proportional to the load impedance of the load 105 and varies with the back-off power. In at least one instance, the corresponding inductances L1 and L2 of the windings or coils 610a and 610b are directly proportional to the load impedance of the load 105 and inversely proportional to the back-off power.

[0058] Table 1 shows various parameters affecting the backoff level of power amplifier 900 when the impedance of load 105 is 50 ohms and the center of the operating frequency is 10 GHz, according to one example.

[0059] Table 1

[0060]

[0061] Figure 10AThis is a graph 1000 showing the current distribution of a first amplifier 102 (e.g., a main amplifier) ​​and a second amplifier 103 (e.g., an auxiliary amplifier) ​​of a power amplifier 900 according to at least one example as a function of back-off power. Here, the x-axis is the output power level of the Dougherty PA, and the y-axis is the output current of the amplifier. As discussed herein, the first amplifier 102 and the second amplifier 103 are asymmetric amplifiers, wherein the second amplifier 103 is configured to provide a higher output power than the first amplifier 102 in saturation. Initially, the first amplifier 102 is turned on and amplifies a first signal (which is separated from the input signal). This is indicated by the current distribution 1001 of the first amplifier 102. As the input power and output power increase, the first amplifier 102 shows a continuous increase in output current. The second amplifier 103 is initially turned off, as indicated by the current distribution 1002 of the second amplifier 103. When the output power level increases above the back-off power level (e.g., ...), the output current increases. Figure 10A When the output power level is between -9.5dB backoff (or any target backoff level) and the target backoff level, the second amplifier 103 is turned on. The current slope of the second amplifier 103 varies as the second amplifier is turned on. Figure 10A At approximately -3.5 dB, the output power level of the first amplifier 102 is higher than that of the second amplifier 103. At -3.5 dB or above, the output power level of the second amplifier 103 exceeds that of the first amplifier 102. At the maximum output power level (e.g., 0 dB power), the maximum current (Isa) of the second amplifier 103 is... max (Ifa) is higher than the maximum current of the first amplifier 102. max Furthermore, the output power level of the second amplifier 103 can be twice that of the first amplifier 103. The maximum current of each amplifier can define the output power level of the amplifier in saturation. In at least one instance, the ratio... The current distribution in various examples, combined with the combined function between the combiner, enhances the power amplifier's back-off efficiency at back-off power levels.

[0062] Figure 10BThis is a graph 1020 showing the percentage contribution of the power of the first amplifier 102 (e.g., the main amplifier) ​​and the second amplifier 103 (e.g., the auxiliary amplifier) ​​to the input power as the input power or output power increases, according to at least one example. Waveform 1021 is the power ratio of the first amplifier 102 (e.g., the power of the first amplifier 102 to the total power). Waveform 1022 is the power ratio of the second amplifier 103 (e.g., the power of the second amplifier 103 to the total power). In this example, below 9.5 dB, 100% of the power comes from the first amplifier 102 because the second amplifier 103 is off. When the second amplifier 103 is on, the percentage contribution from the first amplifier 102 decreases, while the contribution from the first amplifier 102 increases. Below the crossover point (approximately -3.5 dB), the first amplifier 102 contributes more power than the second amplifier 103. In saturation (0 dB backoff), the second amplifier 103 contributes twice the power of the first amplifier 102. According to at least one instance, this is because the size difference allows the second amplifier 103 to have a larger saturation power compared to the first amplifier 102.

[0063] Figure 11 It is shown according to at least one instance Figure 9 Graph 1100 shows the efficiency of power amplifier 900 at different frequencies as a function of back-off power. Here, the x-axis represents back-off power, and the y-axis represents efficiency. Graph 1100 shows that, at the same power back-off level, the efficiency level decreases between different operating frequencies of 0.875f0, f0, and 1.125f0, as indicated by waveforms 1101, 1102, and 1103, respectively. Here, waveform 1102 is the center operating frequency f0. In this example of power amplifier 900, for the same back-off power (e.g., -9.5 dB back-off), the efficiency decreases from 80% to approximately 50% as the frequency increases.

[0064] Figure 12This is a schematic diagram of a power amplifier 1200 according to at least one embodiment, the power amplifier having a transformer coupler with a center tap and coupling capacitors at the ports and the center tap. In at least one embodiment, the combiner 310 includes a transformer 1210 with a center tap and a fifth capacitor 1201 and a sixth capacitor 1202 coupled to the center tap. In at least one embodiment, the transformer 1210 includes windings or coils 1210a and 1210b. For example, winding or coil 1210a is a primary coil, and winding or coil 1210b is a secondary coil. In at least one embodiment, individual winding coils may be fabricated within a substrate to provide isolation between the ports. In at least one embodiment, winding or coil 1210a has a center tap 1211a, and winding or coil 1210b has a center tap 1211b. In at least one embodiment, a third coupling capacitor 1212 with a capacitance 2C1 is coupled between winding or coil 1210a and winding or coil 1210b. In at least one instance, a fifth capacitor 1201 with capacitance 2C2 is coupled between center tap 1211a and ground. In at least one instance, a sixth capacitor 1202 with capacitance 2C2 is coupled between center tap 1211b and ground.

[0065] Compared to power amplifier 900, power amplifier 1200 provides higher inductance and additional control means in the form of a fifth capacitor 1201, a sixth capacitor 1202 and a third coupling capacitor 1212, thereby achieving deeper back-off with higher efficiency.

[0066] Table 2 shows various parameters affecting the backoff level of power amplifier 1200 according to an example, when the impedance of load 105 is 50 ohms and the center of the operating frequency is 10 GHz.

[0067] Table 2

[0068]

[0069] Transformer 1210 can be viewed as a cascade of two combiners (e.g., combiner 310), and the inductance and capacitance of the transformer network can be selected according to the required backoff level and bandwidth. In at least one instance, multiple stages of such combiners can be cascaded to achieve a higher-order power amplifier with a wider bandwidth. In at least one instance, between each stage of the cascaded combiner, coupling capacitors (e.g., third coupling capacitor 1212) and associated capacitors (e.g., corresponding fifth capacitor 1201 and sixth capacitor 1202) are coupled between the stage of the cascaded combiner and ground.

[0070] Figure 13A It is shown according to at least one instance Figure 12The efficiency of the power amplifier 1200 as a function of back-off power is shown in graph 1300. Compared to graph 1100, the efficiency of the power amplifier 1200 is generally flat at the frequencies indicated by waveforms 1301, 1302, and 1303. Here, waveform 1302 is the center operating frequency f0. For example, for the same back-off power (e.g., -9.5 dB back-off), the efficiency decreases from 80% to approximately 70% as the frequency increases. The power amplifier 1200 can be scaled to any operating frequency.

[0071] Figure 13B This illustrates, based on at least one instance, different back-off powers at the center frequency f0. Figure 12 The efficiency curve of the power amplifier 1200 is shown in graph 1320. Graph 1320 illustrates the wideband operation of the power amplifier 1200 for different backoff power levels. For example, waveform 1321 corresponds to -7dB backoff, waveform 1322 corresponds to -8dB backoff, waveform 1323 corresponds to -9dB backoff, and waveform 1324 corresponds to -10dB backoff. Here, the power amplifier 1200 achieves 80% efficiency across various backoff power levels.

[0072] Figure 14 This is a schematic diagram of a power amplifier 1400 according to at least one embodiment, the power amplifier having a transformer coupler with a center tap and coupling capacitors at the ports and the center tap. Power amplifier 1400 is an embodiment of power amplifier 1200 according to at least one embodiment. In at least one embodiment, winding or coil 1210a is a horseshoe coil in a first dielectric layer, and winding or coil 1210b is another horseshoe coil in a second dielectric layer. Although power amplifier 1400 shows horseshoe coils, winding or coils 1210a and 1210b can use any shape. In at least one embodiment, winding or coils 1210a and 1210b have a symmetrical shape with the center tap as the point of symmetry. For example, winding or coil 1210a has a center tap 1211a, which is also a point of symmetry, and winding or coil 1210b has a center tap 1211b.

[0073] In at least one embodiment, the first amplifier 102 includes an n-type transistor MN1 having a source terminal coupled to ground and a drain terminal coupled to a coupling port 303 of a winding or coil 1210a. In at least one embodiment, the gate terminal of the n-type transistor MN1 is controllable by a first signal. In at least one embodiment, an isolation port 304 of the winding or coil 1210a is coupled to a first power supply VCCCR. In at least one embodiment, the second amplifier 103 includes an n-type transistor MN2 having a source terminal coupled to ground and a drain terminal coupled to a coupling port 303 of a winding or coil 1210b, and a bias line 1403, which in turn is coupled to a second power supply VCCPK. In at least one embodiment, the gate terminal of the n-type transistor MN2 is controllable by a second signal. In at least one embodiment, to achieve a back-off power of -9.5 dB, the voltage ratio of VCCPK to VCCCR is 1.4.

[0074] As discussed herein, the first amplifier 102 (e.g., a main amplifier) ​​and the second amplifier 103 (e.g., an auxiliary amplifier) ​​are asymmetric amplifiers. In at least one instance, the first amplifier 102 is a Class AB amplifier, and the second amplifier 103 is a Class C amplifier. The first amplifier 102 receives a first signal at the gate terminal of transistor MN1 and is coupled to the coupling port 303 of the quadrature mixer 1210. In at least one instance, a second signal is provided to the gate terminal of transistor MN2 of the second amplifier 103, which is coupled to the through port 302 of the quadrature mixer 1210. In at least one instance, the first amplifier 102 is configured to provide a first output power level in a saturated state, and the second amplifier 103 is configured to provide a second output power level in a saturated state, wherein the second power level is higher than the first power level. In at least one instance, the first amplifier 102 operates by amplifying the first signal, while the second amplifier 103 is turned off. When the input power level exceeds the power threshold (or the output power level exceeds the backoff power threshold), the second amplifier 103 turns on and amplifies the second signal, while the first amplifier 102 continues to operate. The outputs of the first amplifier 102 and the second amplifier 103 are combined by the quadrature mixer 1210 and provided to the reference port 301 of the coupled load 105.

[0075] Figure 15This is a schematic diagram of a power amplifier 1500 according to at least one example, the power amplifier having a transformer coupler with a center tap and coupling capacitors at the ports and the center tap, and having a 1:n transformer. In at least one example, the power amplifier 1500 uses different supply voltages VCCCR and VCPK for a first amplifier 102 and a second amplifier 103, respectively. In at least one example, by using a 1:n transformer 1501 coupled to the second amplifier 103, a single supply voltage VCC can be used for the first amplifier 102 and the second amplifier 103, instead of using different supply voltages VCCCR and VCPK, where 'n' varies with the backoff level and can be an integer or a fraction. In at least one example, the 1:n transformer 1501 is used to power the first amplifier 103. In at least one example, the turns 'n' of the transformer 1501 vary with the backoff power level. In at least one example, the 1:n transformer 1501 provides a voltage multiplication from the supply voltage VCC, instead of using two separate supply voltages VCCCR and VCPK. In at least one instance, VCC is the lower of the supply voltage VCCCR and VCCPK.

[0076] In at least one embodiment, the drain terminal of the second amplifier 103 is coupled to the first terminal of the first coil or inductor of the 1:n transformer 1501, and the second terminal of the first coil or inductor of the 1:n transformer 1501 is coupled to the power rail VCC, which in turn is coupled to the isolation port 304. In at least one embodiment, the first terminal of the second coil or inductor of the 1:n transformer 1501 is coupled to the through port 302, while the second terminal of the second coil or inductor of the 1:n transformer 1501 is coupled to ground, wherein the ratio of the number of coils in the first coil or inductor to the number of coils in the second coil or inductor is 1:n.

[0077] Figure 16A Figures C to C are schematic diagrams of power amplifiers 1600, 1620, and 1630, respectively, according to at least one embodiment, having different coupling coefficients, transformer sizes, and back-off power. In at least one embodiment, deeper back-off power is achieved by reducing the coupling coefficient k. In at least one embodiment, the coupling coefficient k is reduced by reducing the overlap area between windings or coils. Here, windings or coils 1210a and 1210b have the largest overlap and therefore have a higher coupling coefficient k and lower back-off power, while windings or coils 1620a and 1620b have a greater overlap than... Figure 16A The windings or coils have less overlap and therefore a smaller coupling coefficient k and higher (e.g., deeper) back-off power, and the windings or coils 1630a and 1630b have a higher overlap than... Figure 16BThe windings or coils have less overlap and therefore a smaller coupling coefficient k and higher (e.g., deeper) back-off power. While reference Figure 14 Examples of power amplifiers shown are power amplifiers 1600, 1620, and 1630, but the same concept applies to... Figure 15 Power amplifier.

[0078] Figure 17 These are a set of graphs 1700, 1720, and 1730, illustrating the effect of second harmonic impedance on the device model shown in the illustration. According to at least one example, impedance Z2f0 needs to be in the capacitive region for better output power and efficiency performance. Utilizing the second harmonic at the drain terminals of the first amplifier transistor MN1 and the second amplifier transistor MN2, respectively, is an effective way to improve power efficiency. According to at least one example, this is achieved by configuring the waveforms to reduce the alignment between the current and voltage waveforms. For gallium nitride (GaN) power devices, the inherent second harmonic impedance required for high efficiency lies in the capacitive region of the Smith chart. While conventional matching networks or combiners may require the addition of additional harmonic slots or filter networks to achieve the desired harmonic load on the transistors, the orthogonal hybrid combiners of various examples naturally allow for proper capacitive second harmonic termination without the need to manually add additional harmonic networks (e.g., using the inherent LC lumped configuration of a 90° mixer).

[0079] Graph 1700 is a Smith chart with inductor region 1701 and capacitor region 1702. Graph 1720 shows the output power of the GaN transistor as a function of the phase of the second harmonic impedance Z2f0. The second harmonic impedance varies across the outer edge of the Smith chart of graph 1700; therefore, the phase transition of the second harmonic impedance changes from 0 degrees to 360 degrees. Graph 1730 shows the power-to-efficiency ratio of the GaN transistor as a function of the phase of the second harmonic impedance. In at least one instance, a trap region 1731 exists for both output power and efficiency, which may be undesirable because trap region 1731 reduces efficiency by 15% and power by 1.5 dB. Trap region 1731 corresponds to inductor region 1701 in the Smith chart of graph 1700. In at least one instance, the second harmonic impedance phase 1732 is desirable and is located within capacitor region 1702.

[0080] Figure 18A This is a schematic diagram illustrating setup 1800 for determining the input second harmonic impedance Z2f0 at the through port 302 and the coupling port 303, according to at least one example. The second harmonic input impedance Z2f0 is the load impedance of the first amplifier transistor MN1 and the second amplifier transistor MN2. Figure 18BBased on at least one example, a set of Smith charts 1802 and 1803 shows the load impedance (Z2f0) of an amplifier connected to coupling port 303 and through port 302 of a power amplifier at the second harmonic frequency. Smith charts 1802 and 1803 show the input impedance of a 90° hybrid coupler. It should be noted that the input impedance of the quadrature hybrid coupler is the load of the device. At the second harmonic, this impedance Z2f0 lies in the capacitive region of the Smith charts for both amplifiers. See reference... Figure 17 As discussed, the second harmonic load impedance of transistors MN1 and MN2 should be in the capacitance region, and the 1800 combiner network naturally provides the required second harmonic impedance for transistors MN1 and MN2.

[0081] Figure 19 This is a schematic diagram of a power amplifier 1900 with selectable combiners according to at least one embodiment. In at least one embodiment, the power amplifier 1900 includes a multiplexer 1901 and multiple combiners (e.g., combiners 1904a, 1904b, 1904c…). In at least one embodiment, the multiplexer 1901 includes pairs of switches, such as switches sw1a, sw2a, sw1b, sw2b, sw1c, sw2c, etc. In at least one embodiment, the switches are implemented as transistors. In at least one embodiment, the gate of the transistor is controlled by a control signal generated by on-die or off-die logic. In at least one embodiment, one switch in the pair is coupled to coupling port 303 and the output of the first amplifier 102, while the other switch in the pair is coupled to through port 302 and the second amplifier 103. In at least one embodiment, depending on the depth of the target back-off power, a combiner with a desired coupling coefficient k is selected and coupled to the first amplifier 102 and the second amplifier 103.

[0082] Figure 20 This is a flowchart of a method for operating a power amplifier according to at least one example, 2000. Although the various blocks are shown in a specific order, the order can be modified. For example, some blocks may be executed before others, while some blocks may be executed simultaneously.

[0083] At block 2001, a quadrature hybrid combiner (e.g., combiner 310, 1210, or other combiners discussed herein) receives a first signal. At block 2002, it is determined whether the power level of the first signal exceeds a threshold (e.g., a backoff level target). If the power level of the first signal does not exceed the threshold, then at block 2003, a second signal having the first power level is provided by a first amplifier 102 to coupling port 303 (e.g., a non-inverting port) of the quadrature hybrid combiner. If the power level of the first signal exceeds the threshold, then at block 2004, a third signal is provided by the first amplifier 102 to coupling port 303 (e.g., a non-inverting port) of the quadrature hybrid combiner. At block 2005, a fourth signal is provided to the quadrature hybrid combiner using a second amplifier 103. The power level of the fourth signal is higher than the power level of the third signal. At block 2006, based on the second signal or a combination of the third and fourth signals, a fifth signal is provided at reference port 301 as an output signal to load 105.

[0084] The following are additional examples provided in view of the embodiments described above. Here, one or more features of a single or combined example may be combined with one or more features of one or more other examples to form other examples that also fall within the scope of this disclosure. Thus, an embodiment can be combined with one or more other embodiments without changing the scope of this disclosure.

[0085] Example 1 is a device comprising: a first amplifier CR having a first amplifier output and configured to provide a first signal having a first power level at the first amplifier output; a second amplifier PK having a second amplifier output and configured to provide a second signal having a second power level at the second amplifier output, the second power level being higher than the first power level; and a combiner circuit having a quadrature terminal (through), a non-inverting terminal (coupled), a reference terminal (reference), and an isolation terminal (isolation), the non-inverting terminal being coupled to the first amplifier output, the quadrature terminal being coupled to the second amplifier output, the reference terminal being coupled to the combiner output, and the isolation terminal being coupled to a direct current (DC) voltage source.

[0086] Example 2 is the device according to any example in this document, particularly Example 1, wherein the combiner circuitry comprises an orthogonal hybrid combiner.

[0087] Example 3 is a device according to any example herein, particularly Example 1, wherein the combiner circuit includes a first coil electrically coupled between the reference terminal and the quadrature phase terminal and a second coil electrically coupled between the in-phase terminal and the isolation terminal, the first coil being magnetically coupled to the second coil.

[0088] Example 4 is a device according to any example herein, particularly Example 3, further comprising: a first capacitor coupled between the in-phase terminal and the DC terminal; a second capacitor coupled between the quadrature terminal and the DC terminal; a third capacitor coupled between the reference terminal and the DC terminal; a fourth capacitor coupled between the isolation terminal and the DC terminal; a fifth capacitor coupled between the quadrature terminal and the isolation terminal; and a sixth capacitor coupled between the in-phase terminal and the reference terminal.

[0089] Example 5 is the device described according to any example herein, particularly Example 4, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are on-chip capacitors.

[0090] Example 6 is the device described according to any example herein, particularly Example 4, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are off-chip capacitors.

[0091] Example 7 is a device according to any example herein, particularly Example 3, wherein the first coil has a first center tap terminal, the second coil has a second center tap terminal, and the device further includes: a first capacitor coupled between the in-phase terminal and the DC terminal; a second capacitor coupled between the quadrature terminal and the DC terminal; a third capacitor coupled between the reference terminal and the DC terminal; a fourth capacitor coupled between the isolation terminal and the DC terminal; a fifth capacitor coupled between the first center tap terminal and the DC terminal; a sixth capacitor coupled between the second center tap terminal and the DC terminal; a seventh capacitor coupled between the quadrature terminal and the isolation terminal; an eighth capacitor coupled between the in-phase terminal and the reference terminal; and a ninth capacitor coupled between the first center tap terminal and the second center tap terminal.

[0092] Example 8 is the device described according to any example herein, particularly Example 7, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are on-chip capacitors.

[0093] Example 9 is the device described according to any example herein, particularly Example 7, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are off-chip capacitors.

[0094] Example 10 is the device described according to any example in this document, particularly Example 3, wherein the first coil and the second coil are part of a transformer.

[0095] Example 11 is the device described according to any example herein, particularly Example 3, wherein the inductance of each of the first coil and the second coil is based on the target backoff level at the combiner output, the load impedance at the combiner output, and the operating frequency of the device.

[0096] Example 12 is a device according to any example herein, particularly Example 1, wherein the combiner circuit comprises at least one of the following: a branch hybrid coupler or a Lange hybrid coupler.

[0097] Example 13 is a device according to any example in this document, particularly Example 2, wherein the coupling factor of the quadrature hybrid combiner is based on the target power back-off level at the combiner output.

[0098] Example 14 is the device according to any example herein, particularly Example 1, wherein the second amplifier is configured to have a higher output power level than the first amplifier in a saturated state.

[0099] Example 15 is a device according to any example herein, particularly Example 1, wherein the combiner circuit is a first combiner circuit, the quadrature terminal is a first quadrature terminal, the non-inverting terminal is a first non-inverting terminal, the reference terminal is a first reference terminal, and the isolation terminal is a first isolation terminal; wherein the device further comprises: a second combiner circuit having a second quadrature terminal, a second non-inverting terminal, a second reference terminal, and a second isolation terminal, the second reference terminal being coupled to the combiner output, and the second isolation terminal being coupled to the DC voltage source; a first switching network coupled between the first amplifier output and the first non-inverting terminal and the second non-inverting terminal; and a second switching network coupled between the second amplifier output and the first quadrature terminal and the second quadrature terminal.

[0100] Example 16 is the device described in any example herein, particularly Example 1, wherein the combiner circuit, the first amplifier, and the second amplifier are part of an integrated circuit (IC).

[0101] Example 17 is a device according to any example herein, particularly Example 1, which further includes a transformer having a first coil and a second coil, wherein a first terminal of the first coil is coupled to the DC voltage source, wherein the quadrature phase terminal is coupled to the output of the second amplifier via the transformer, wherein a second terminal of the first coil is coupled to the output of the second amplifier, wherein a first terminal of the second coil is coupled to ground, and wherein a second terminal of the second coil is coupled to the quadrature phase terminal.

[0102] Example 18 is the device described according to any example herein, particularly Example 17, wherein the first coil and the second coil have the same number of turns.

[0103] Example 19 is the device described according to any example herein, particularly Example 17, wherein the first coil and the second coil have different numbers of turns.

[0104] Example 20 is the device described according to any example herein, particularly Example 17, wherein the first coil has a first number of turns, wherein the second coil has a second number of turns, and wherein the ratio of the first number of turns to the second number of turns varies with the back-off power level.

[0105] Example 21 is a device comprising: a transmission circuit having a transmission input, a first transmission output, and a second transmission output; a first amplifier having a first amplifier input and a first amplifier output, the first amplifier input being coupled to the first transmission output; a second amplifier having a second amplifier input and a second amplifier output, the second amplifier input being coupled to the second transmission output, and the first amplifier and the second amplifier having different power levels in a saturated state; and an orthogonal hybrid combiner coupled between the first amplifier output and the second amplifier output and the combiner output.

[0106] Example 22 is the device according to any example herein, particularly Example 21, wherein the quadrature hybrid combiner includes a quadrature phase terminal (through), a non-phase terminal (coupled), a reference terminal (reference), and an isolation terminal (isolation), the non-phase terminal being coupled to the output of the first amplifier, the quadrature phase terminal being coupled to the output of the second amplifier, the reference terminal being coupled to the output of the quadrature hybrid combiner, and the isolation terminal being coupled to a DC voltage source.

[0107] Example 23 is a device according to any example herein, particularly Example 22, wherein the quadrature hybrid combiner includes a first coil electrically coupled between the reference terminal and the quadrature phase terminal and a second coil electrically coupled between the in-phase terminal and the isolation terminal, the first coil being magnetically coupled to the second coil.

[0108] Example 24 is a device according to any example herein, particularly Example 23, further comprising: a first capacitor coupled between the in-phase terminal and the DC terminal; a second capacitor coupled between the quadrature terminal and the DC terminal; a third capacitor coupled between the reference terminal and the DC terminal; a fourth capacitor coupled between the isolation terminal and the DC terminal; a fifth capacitor coupled between the quadrature terminal and the isolation terminal; and a sixth capacitor coupled between the in-phase terminal and the reference terminal.

[0109] Example 25 is the device described according to any example herein, particularly Example 24, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are on-chip capacitors.

[0110] Example 26 is the device described according to any example herein, particularly Example 24, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are off-chip capacitors.

[0111] Example 27 is a device according to any example herein, particularly Example 23, wherein the first coil has a first center tap terminal, the second coil has a second center tap terminal, and the device further includes: a first capacitor coupled between the in-phase terminal and the DC terminal; a second capacitor coupled between the quadrature terminal and the DC terminal; a third capacitor coupled between the reference terminal and the DC terminal; a fourth capacitor coupled between the isolation terminal and the DC terminal; a fifth capacitor coupled between the first center tap terminal and the DC terminal; a sixth capacitor coupled between the second center tap terminal and the DC terminal; a seventh capacitor coupled between the quadrature terminal and the isolation terminal; an eighth capacitor coupled between the in-phase terminal and the reference terminal; and a ninth capacitor coupled between the first center tap terminal and the second center tap terminal.

[0112] Example 28 is a method comprising: receiving a first signal; in response to a power level of the first signal being below a threshold: providing a second signal having a first power level to the in-phase terminal of a quadrature mixer using a first amplifier; in response to a power level of the first signal being above the threshold: providing a third signal having a second power level to the in-phase terminal using the first amplifier; and providing a fourth signal having a third power level to the quadrature phase terminal of the quadrature mixer using a second amplifier, the third power level being higher than the first power level and the second power level; and providing a fifth signal as an output signal at a reference terminal of the quadrature mixer based on the second signal or a combination of the third signal and the fourth signal.

[0113] In addition to the content described herein, various modifications may be made to disclose implementation schemes and their implementation schemes without departing from their scope. Therefore, the descriptions of implementation schemes herein should be interpreted as examples and not as limitations on the scope of this disclosure.

[0114] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0115] In this specification and claims, unless otherwise indicated, the terms "comprising" and "having," and their variations, are intended to be included in a manner similar to the term "comprising." Additionally, the terms "coupled," "coupled," or "couples" refer to indirect or direct electrical or mechanical connections.

[0116] Furthermore, in this specification, the term "based on" means "at least partially based on". Therefore, if X is based on Y, then X can vary with Y and any number of other factors.

[0117] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnects, or a combination thereof.

[0118] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0119] The circuits or devices described herein as containing certain components may alternatively be adapted to be coupled to those components to form the described circuits or devices. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0120] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuitry. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, such as NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0121] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0122] While some elements in the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as external to the integrated circuit may be contained within the integrated circuit, and / or some features shown as internal to the integrated circuit may be external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0123] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "generally" preceding a parameter means within + / - 10% of said parameter, or, if the parameter is zero, within a reasonable range of values ​​near zero.

Claims

1. An apparatus comprising: A first amplifier having a first amplifier output and configured to provide a first signal having a first power level at the first amplifier output; A second amplifier having a second amplifier output and configured to provide a second signal having a second power level at the second amplifier output, the second power level being higher than the first power level; as well as A combiner circuit having a quadrature phase terminal, a non-phase terminal, a reference terminal, and an isolation terminal, wherein the non-phase terminal is coupled to the output of a first amplifier, the quadrature phase terminal is coupled to the output of a second amplifier, the reference terminal is coupled to the output of the combiner, and the isolation terminal is coupled to a DC voltage source.

2. The device of claim 1, wherein the combiner circuit comprises an orthogonal hybrid combiner.

3. The device of claim 1, wherein the combiner circuit includes a first coil electrically coupled between the reference terminal and the quadrature phase terminal and a second coil electrically coupled between the in-phase terminal and the isolation terminal, the first coil being magnetically coupled to the second coil.

4. The device according to claim 3, further comprising: A first capacitor is coupled between the in-phase terminal and the DC terminal; A second capacitor is coupled between the quadrature phase terminal and the DC terminal; A third capacitor is coupled between the reference terminal and the DC terminal; A fourth capacitor is coupled between the isolation terminal and the DC terminal; A fifth capacitor is coupled between the quadrature phase terminal and the isolation terminal; as well as A sixth capacitor is coupled between the in-phase terminal and the reference terminal.

5. The device of claim 4, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor, and the sixth capacitor are on-chip capacitors.

6. The device according to claim 4, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor are off-chip capacitors.

7. The device of claim 3, wherein the first coil has a first center tap terminal, the second coil has a second center tap terminal, and the device further comprises: A first capacitor is coupled between the in-phase terminal and the DC terminal; A second capacitor is coupled between the quadrature phase terminal and the DC terminal; A third capacitor is coupled between the reference terminal and the DC terminal; A fourth capacitor is coupled between the isolation terminal and the DC terminal; A fifth capacitor is coupled between the first center tap terminal and the DC terminal; A sixth capacitor is coupled between the second center tap terminal and the DC terminal; A seventh capacitor is coupled between the quadrature phase terminal and the isolation terminal; The eighth capacitor is coupled between the in-phase terminal and the reference terminal; as well as A ninth capacitor is coupled between the first center tap terminal and the second center tap terminal.

8. The device of claim 7, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor are on-chip capacitors.

9. The device of claim 7, wherein the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the fifth capacitor and the sixth capacitor are off-chip capacitors.

10. The device of claim 3, wherein the first coil and the second coil are part of a transformer.

11. The device of claim 3, wherein the inductance of each of the first coil and the second coil is based on the target backoff level at the combiner output, the load impedance at the combiner output, and the operating frequency of the device.

12. The device of claim 1, wherein the combiner circuit comprises at least one of the following: a branch hybrid coupler or a Lange hybrid coupler.

13. The device of claim 2, wherein the coupling factor of the quadrature hybrid combiner is based on the target power back-off level at the output of the combiner.

14. The device of claim 1, wherein the second amplifier is configured to have a higher output power level than the first amplifier in a saturated state.

15. The device according to claim 1, wherein the combiner circuit is a first combiner circuit, the quadrature phase terminal is a first quadrature phase terminal, the non-phase terminal is a first non-phase terminal, the reference terminal is a first reference terminal, and the isolation terminal is a first isolation terminal; The device further includes: The second combiner circuit has a second quadrature phase terminal, a second non-phase terminal, a second reference terminal, and a second isolation terminal, wherein the second reference terminal is coupled to the combiner output and the second isolation terminal is coupled to the DC voltage source. A first switching network is coupled between the output of the first amplifier and the first non-inverting terminal and the second non-inverting terminal; and A second switching network is coupled between the output of the second amplifier and the first quadrature phase terminal and the second quadrature phase terminal.

16. The device of claim 1, wherein the combiner circuit, the first amplifier, and the second amplifier are part of an integrated circuit (IC).

17. The device of claim 1, further comprising a transformer having a first coil and a second coil, wherein a first terminal of the first coil is coupled to the DC voltage source, wherein the quadrature terminal is coupled to the output of the second amplifier via the transformer, wherein a second terminal of the first coil is coupled to the output of the second amplifier, wherein a first terminal of the second coil is coupled to ground, and wherein a second terminal of the second coil is coupled to the quadrature terminal.

18. The device of claim 17, wherein the first coil and the second coil have the same number of turns.

19. The device of claim 17, wherein the first coil and the second coil have different numbers of turns.

20. The device of claim 17, wherein the first coil has a first number of turns, wherein the second coil has a second number of turns, wherein the ratio of the first number of turns to the second number of turns varies with the backoff power level.

21. An apparatus comprising: A transmission circuit having a transmission input, a first transmission output, and a second transmission output; A first amplifier having a first amplifier input and a first amplifier output, the first amplifier input being coupled to the first transmission output; The second amplifier has a second amplifier input and a second amplifier output, the second amplifier input being coupled to the second transmission output, and the first amplifier and the second amplifier having different power levels in saturation state; as well as An orthogonal hybrid combiner coupled between the output of the first amplifier and the output of the second amplifier and the combiner output.

22. The device of claim 21, wherein the quadrature hybrid combiner includes a quadrature phase terminal, a non-phase terminal, a reference terminal, and an isolation terminal, the non-phase terminal being coupled to the output of the first amplifier, the quadrature phase terminal being coupled to the output of the second amplifier, the reference terminal being coupled to the output of the quadrature hybrid combiner, and the isolation terminal being coupled to a DC voltage source.

23. The device of claim 22, wherein the quadrature hybrid combiner includes a first coil electrically coupled between the reference terminal and the quadrature phase terminal and a second coil electrically coupled between the in-phase terminal and the isolation terminal, the first coil being magnetically coupled to the second coil.

24. The device according to claim 23, further comprising: A first capacitor is coupled between the in-phase terminal and the DC terminal; A second capacitor is coupled between the quadrature phase terminal and the DC terminal; A third capacitor is coupled between the reference terminal and the DC terminal; A fourth capacitor is coupled between the isolation terminal and the DC terminal; A fifth capacitor is coupled between the quadrature phase terminal and the isolation terminal; as well as A sixth capacitor is coupled between the in-phase terminal and the reference terminal.

25. The device of claim 23, wherein the first coil has a first center tap terminal, the second coil has a second center tap terminal, and the device further comprises: A first capacitor is coupled between the in-phase terminal and the DC terminal; A second capacitor is coupled between the quadrature phase terminal and the DC terminal; A third capacitor is coupled between the reference terminal and the DC terminal; A fourth capacitor is coupled between the isolation terminal and the DC terminal; A fifth capacitor is coupled between the first center tap terminal and the DC terminal; A sixth capacitor is coupled between the second center tap terminal and the DC terminal; A seventh capacitor is coupled between the quadrature phase terminal and the isolation terminal; The eighth capacitor is coupled between the in-phase terminal and the reference terminal; as well as A ninth capacitor is coupled between the first center tap terminal and the second center tap terminal.

26. A method comprising: Receive the first signal; In response to the power level of the first signal being lower than a threshold: The first amplifier is used to provide a second signal with a first power level to the in-phase terminal of the quadrature mixer; In response to the power level of the first signal being higher than the threshold: The first amplifier is used to provide a third signal with a second power level to the in-phase terminal; as well as A fourth signal with a third power level is provided to the quadrature phase terminal of the quadrature hybrid combiner using a second amplifier, the third power level being higher than the first power level and the second power level; as well as Based on the second signal or a combination of the third signal and the fourth signal, a fifth signal is provided as an output signal at the reference terminal of the quadrature hybrid combiner.

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