Low-voltage high-speed latch type sensitive amplifier circuit and memory

Abstract

The invention relates to a low-voltage high-speed latch type sensitive amplifier circuit and a memory, which are characterized in that a positive feedback structure is added on the basis of a traditional current latch type sensitive amplifier circuit and is used for improving the reading speed of a sensitive amplifier, and meanwhile, a new cascade structure is designed; compared with a traditional current latch type sensitive amplifier, a transistor cascade structure from a power supply to the ground is reduced, so that a circuit of the sensitive amplifier can be used as a power supply voltage for normal work, and the power supply voltage is smaller than that of the traditional current latch type sensitive amplifier; and finally, the performance requirements of low working voltage and high-speed working of the sensitive amplifier are met at the same time.

Description

Technical Field

[0001] This invention belongs to the field of circuit design technology and relates to a low-voltage, high-speed latch-type sensitive amplifier circuit and memory. Background Technology

[0002] With the continuous development of information technology, the read speed of memories such as SRAM and PROM is getting faster and faster. Therefore, the read speed requirements for sensitive amplifiers in memory are also increasing. The circuit structure of traditional current latch-type sensitive amplifiers can be as follows: Figure 1 As shown, this sensitive amplifier has four cascaded transistors from power supply to ground (e.g., transistors M8 and M9 in the first stage, transistor M5 in the second stage, transistor M3 in the third stage, and transistor M1 in the fourth stage). As the operating voltage of the sensitive amplifier in the memory gradually decreases, maintaining the normal operation of traditional current-latch type sensitive amplifiers faces new and significant challenges. Therefore, how to improve the circuit structure of this type of sensitive amplifier to adapt to the high-speed operation requirements under low power supply voltage has become one of the current technical problems to be solved. Summary of the Invention

[0003] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a latch-type sensitive amplifier circuit with low voltage and high speed, as well as a memory, which can effectively adapt to the high-speed operation requirements under low power supply voltage.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a low-voltage, high-speed latch-type sensitive amplifier circuit is provided, including a differential amplifier unit, a feedback transmission switch unit, a first switch logic unit, and a second switch logic unit; The first differential input terminal of the differential amplifier unit is connected to the output terminal of the first switching logic unit. The second differential input terminal of the differential amplifier unit is connected to the input terminal of the feedback transmission switch unit and the output terminal of the second switching logic unit, respectively. The output terminal of the feedback transmission switch unit is connected to the first differential output terminal of the differential amplifier unit. The input terminal of the first switching logic unit is used to receive the differential signal BL from the memory, and the input terminal of the second switching logic unit is used to receive the differential signal BLB from the memory. During the pre-charging phase, the feedback transmission switch unit is used to disconnect the positive feedback connection between the second differential input terminal and the first differential output terminal of the differential amplifier unit, the first switch logic unit is used to disconnect the differential signal BL from the differential amplifier unit, and the second switch logic unit is used to disconnect the differential signal BLB from the differential amplifier unit. During the data reading phase, the feedback transmission switch unit is used to connect the positive feedback connection between the second differential input terminal and the first differential output terminal of the differential amplifier unit. The first switch logic unit is used to connect the differential signal BL to the differential amplifier unit, and the second switch logic unit is used to connect the differential signal BLB to the differential amplifier unit.

[0005] In one embodiment, the first switching logic unit includes transistor M. N1 Transistor M P1 and transistor M N3 ; transistor M N1 The source is grounded, transistor M N1 The drains of the transistors are connected to transistor M respectively. P1 The drain and transistor M N3 The gate of the transistor M N3 The drain of transistor M is connected to the first differential input terminal of the differential amplifier unit. N3 The source is grounded, transistor M N1 Gate and transistor M P1 The gates of all are used to receive the inverted enable signal ENB.

[0006] In one embodiment, the second switching logic unit includes transistor M. N2 Transistor M P2 and transistor M N4 ; transistor M N2 The source is grounded, transistor M N2 The drains of the transistors are connected to transistor M respectively. P3 The drain and transistor M N4 The gate of the transistor M N4 The drain of transistor M is connected to the second differential input terminal of the differential amplifier unit. N4 The source is grounded, transistor M N2 Gate and transistor M P2 The gates of all are used to receive the inverted enable signal ENB.

[0007] In one embodiment, the feedback transmission switching unit includes transistor M. N7 Transistor M N8 Transistor M P7 and transistor M N9 ; transistor M N7 The source and transistor M P7 The sources of both transistors are connected to the second differential input terminal of the differential amplifier unit, and transistor M... N7 The drain and transistor M P7 The drains of both transistors are connected to transistor M. N9 The gate of the transistor MN7 The gate of transistor M is used to receive the enable signal EN. P7 The gate is used to receive the inverted enable signal ENB; transistor M N9 The drain of transistor M is connected to the first differential output terminal of the differential amplifier unit. N9 The source and transistor M N8 The sources of transistor M are all grounded. N8 Drain-connected transistor M N9 The gate of the transistor M N8 The gate is used to receive the inverted enable signal ENB.

[0008] On the other hand, a memory is also provided, wherein the read circuit of the memory includes any of the aforementioned low-voltage, high-speed latch-type sensitive amplifier circuits.

[0009] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned low-voltage, high-speed latching sensitive amplifier circuit and memory improve the read speed of the sensitive amplifier by adding a positive feedback structure to the traditional current latching sensitive amplifier circuit. At the same time, a new cascade structure is designed, which reduces the transistor cascade structure from the power supply to ground compared to the traditional current latching sensitive amplifier. As a result, the power supply voltage at which the sensitive amplifier circuit can operate normally is lower than that of the traditional current latching sensitive amplifier, ultimately meeting the performance requirements of both low operating voltage and high-speed operation of the sensitive amplifier. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the circuit structure of a traditional current latch-type sensitive amplifier; Figure 2 This is a schematic diagram of a low-voltage, high-speed latch-type sensitive amplifier circuit in one embodiment; Figure 3 This is a schematic diagram of the logic structure of a low-voltage, high-speed latch-type sensitive amplifier circuit in one embodiment; Figure 4 This is a schematic diagram of a low-voltage, high-speed latch-type sensitive amplifier circuit operating in the pre-charge phase in one embodiment. Figure 5This is a schematic diagram of a low-voltage, high-speed latch-type sensitive amplifier circuit operating in the data reading stage in one embodiment. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0013] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0014] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0015] The circuit structure of a traditional current latch-type sensitive amplifier is as follows: Figure 1 As shown, it is mainly composed of MOS transistors, including transistors M1, M2, M3, M4, M5, M6, M7, M8, and M9. Among them, transistors M4 and M5, and transistors M7 and M8 respectively form two inverters to form a differential amplifier unit (also known as a load current mirror). It can effectively suppress common-mode noise and amplify the differential current of the differential input pair (composed of N-channel NMOS transistors M2 and M3). After converting the differential current into a voltage difference, the amplified differential signal is output from the output terminals OUT1 and OUT2.

[0016] The differential input pair receives complementary differential signals BL (bit line) and BLB (bit line inverted) from the memory cells. When the data in the memory cells differs, a small voltage difference appears between BL and BLB (e.g., BL=1, BLB=0, or vice versa), driving transistors M2 and M3 to generate differential currents. EN is the enable signal used to control the circuit's on / off state. Transistor M1 acts as the main enable switch, while transistors M6 and M9 are used for auxiliary enable. Working in conjunction with transistor M1, they ensure a complete path from power supply VDD to ground when EN is active, while also optimizing the transient response during enable switching (avoiding signal glitches).

[0017] In one embodiment, such as Figure 2 As shown, a low-voltage, high-speed latch-type sensitive amplifier circuit is provided, including a differential amplifier unit 12, a feedback transmission switch unit 14, a first switch logic unit 16, and a second switch logic unit 18. The first differential input terminal N1 of the differential amplifier unit 12 is connected to the output terminal of the first switch logic unit 16, and the second differential input terminal N2 of the differential amplifier unit 12 is connected to the input terminal of the feedback transmission switch unit 14 and the output terminal of the second switch logic unit 18, respectively. The output terminal of the feedback transmission switch unit 14 is connected to the first differential output terminal OUT1 of the differential amplifier unit 12. The input terminal of the first switch logic unit 16 is used to receive a differential signal BL from a memory. The input terminal of the second switch logic unit 18 is used to receive a differential signal BLB from a memory.

[0018] During the pre-charging phase, the feedback transmission switch unit 14 disconnects the positive feedback connection between the second differential input terminal and the first differential output terminal OUT1 of the differential amplifier unit 12. The first switch logic unit 16 disconnects the differential signal BL from the differential amplifier unit 12, and the second switch logic unit 18 disconnects the differential signal BLB from the differential amplifier unit 12. During the data reading phase, the feedback transmission switch unit 14 connects the positive feedback connection between the second differential input terminal N2 and the first differential output terminal OUT1 of the differential amplifier unit 12. The first switch logic unit 16 connects the differential signal BL to the differential amplifier unit 12, and the second switch logic unit 18 connects the differential signal BLB to the differential amplifier unit 12.

[0019] Understandable, such as Figure 2As shown, the structure of the differential amplifier unit 12 is the same as that of a traditional differential amplifier unit. Its function and working principle can be understood by referring to the traditional differential amplifier unit. The first differential output terminal OUT1 and the second differential output terminal OUT2 of the differential amplifier unit 12 are used to output the amplified differential signal, respectively. The first differential input terminal N1 and the first differential output terminal OUT1 of the differential amplifier unit 12 are connected by a feedback transmission switch unit 14. The feedback transmission switch unit 14 serves as a positive feedback structure from the first differential input terminal N1 to the first differential output terminal OUT1 of the differential amplifier unit 12. Under the control of the enable signal EN and the inverted enable signal ENB, it disconnects the positive feedback loop during the pre-charging stage to avoid interference with the voltage pull-up of the first differential output terminal OUT1 (to complete the pre-charging). During the data reading stage, it quickly pulls down the voltage of the first differential output terminal OUT1 through the positive feedback loop, so that the two inverters inside the differential amplifier unit 12 start working quickly, thereby shortening the data reading time and improving the reading speed of the sensitive amplifier.

[0020] Correspondingly, the first switching logic unit 16 and the second switching logic unit 18 replace the traditional differential input pairs (such as...). Figure 1 Transistors M2 and M3 in the transistor and the main enable switch (such as transistor M2 and M3 in the transistor) ... Figure 1 In the differential amplifier unit 12, the first switching logic unit 16 and the second switching logic unit 18, under the control of the same inverted enable signal ENB, independently and synchronously control the differential current input of the two differential input terminals. This shortens the power supply to ground structure from the traditional four-stage transistor cascade structure to a three-stage transistor cascade structure, thereby reducing the power supply voltage required for the circuit to operate normally. The feedback transmission switching unit 14, the first switching logic unit 16, and the second switching logic unit 18 are all constructed using MOS transistors, as long as they can achieve their respective functions as described above.

[0021] The aforementioned low-voltage, high-speed latch-type sensitive amplifier circuit improves the read speed of the sensitive amplifier by adding a positive feedback structure to the traditional current latch-type sensitive amplifier circuit. Simultaneously, a new cascade structure is designed, reducing the number of transistor cascades from power supply to ground compared to the traditional current latch-type sensitive amplifier. This allows the sensitive amplifier circuit to operate at a lower power supply voltage than the traditional current latch-type sensitive amplifier, ultimately satisfying both the low operating voltage and high-speed performance requirements of the sensitive amplifier.

[0022] In one embodiment, such as Figure 3 As shown, the first switching logic unit 16 includes transistor M N1 Transistor M P1 and transistor M N3Transistor M N1 The source is grounded, transistor M N1 The drains of the transistors are connected to transistor M respectively. P1 The drain and transistor M N3 The gate of the transistor M N3 The drain of transistor M is connected to the first differential input terminal of differential amplifier unit 12. N3 The source of transistor M is grounded. N1 Gate and transistor M P1 The gates of all are used to receive the inverted enable signal ENB.

[0023] It is understood that this embodiment employs... Figure 3 The first switching logic unit 16, as shown, uses a simplified structure of two NMOS transistors and one PMOS transistor to provide the necessary switching circuitry and transmit bit line signals. This improves the path from power supply VDD to ground on the first differential branch of the differential amplifier unit 12 from a traditional four-stage transistor cascade to a three-stage transistor cascade. This allows the sensitive amplifier circuit to operate normally at a lower power supply voltage and avoids significantly increasing the circuit's structural complexity. Two nodes in the circuit use the same L1 label to indicate that they are connected.

[0024] It should be noted that those skilled in the art can, based on the functions required to be implemented by the first switching logic unit 16 described above, employ a method different from the transistor M in this embodiment. N1 Transistor M P1 and transistor M N3 Other alternative structures include, but are not limited to, adding an inverter, through which the enable signal EN passes before being connected to transistor M. N1 and transistor M P1 Alternatively, directly use transistor M N1 and transistor M P1 Replace with CMOS transmission gates, while ensuring the M transistor N3 The overall control logic remains unchanged.

[0025] In one embodiment, such as Figure 3 As shown, the second switching logic unit 18 includes transistor M N2 Transistor M P2 and transistor M N4 Transistor M N2 The source is grounded, transistor M N2 The drains of the transistors are connected to transistor M respectively. P3 The drain and transistor M N4 The gate of the transistor M N4 The drain of transistor M is connected to the second differential input terminal of differential amplifier unit 12.N4 The source of transistor M is grounded. N2 Gate and transistor M P2 The gates of all are used to receive the inverted enable signal ENB.

[0026] It is understood that this embodiment employs... Figure 3 The second switching logic unit 18, as shown, uses a simplified structure of two NMOS transistors and one PMOS transistor to provide the switching circuit and transmit the bit line inverted signal. This improves the path from power supply VDD to ground on the second differential branch of the differential amplifier unit 12 from the traditional four-stage transistor cascade to a three-stage transistor cascade. This allows the sensitive amplifier circuit to operate normally at a lower power supply voltage and avoids significantly increasing the structural complexity of the circuit.

[0027] It should be noted that those skilled in the art can, based on the functions required to be implemented by the second switching logic unit 18 described above, employ a method different from the transistor M in this embodiment. N2 Transistor M P2 and transistor M N4 Other alternative structures include, but are not limited to, adding an inverter, through which the enable signal EN passes before being connected to transistor M. N2 and transistor M P2 Alternatively, directly use transistor M N2 and transistor M P2 Replace with CMOS transmission gates, while ensuring the M transistor N4 The overall control logic remains unchanged. Among them, M P The class designation indicates that the corresponding transistor is a P-channel transistor, M N The class designation indicates that the corresponding transistor is an N-channel MOS transistor.

[0028] In one embodiment, such as Figure 3 As shown, the feedback transmission switching unit 14 includes transistor M N7 Transistor M N8 Transistor M P7 and transistor M N9 Transistor M N7 The source and transistor M P7 The sources of both transistors are connected to the second differential input terminal of the differential amplifier unit 12, and transistor M... N7 The drain and transistor M P7 The drains of both transistors are connected to transistor M. N9 The gate of the transistor M N7 The gate of transistor M is used to receive the enable signal EN. P7 The gate of transistor M is used to receive the inverted enable signal ENB.N9 The drain of transistor M is connected to the first differential output terminal of differential amplifier unit 12. N9 The source and transistor M N8 The sources of transistor M are all grounded. N8 Drain-connected transistor M N9 The gate of the transistor M N8 The gate is used to receive the inverted enable signal ENB.

[0029] It is understood that in this embodiment, the following is adopted: Figure 3 The feedback transmission switch unit 14 shown in the diagram provides the positive feedback loop required from the first differential input terminal N1 to the first differential output terminal OUT1 of the differential amplifier unit 12 through a simplified structure of one transmission gate and two NMOS transistors. It achieves the pre-charging anti-interference and voltage pull-up effects of the first differential output terminal OUT1 with a simple transmission circuit structure, significantly shortens the data readout time, and further avoids significantly increasing the structural complexity of the circuit.

[0030] To more clearly demonstrate the operation of the low-voltage, high-speed latch-type sensitive amplifier circuit, please refer to [reference needed]. Figure 4 and Figure 5 ,by Figure 3 Taking the preferred circuit structure shown as an example: During the pre-charging stage, the enable signal EN is 0, and the inverted enable signal ENB is 1. The circuit operation diagram at this time is as follows. Figure 4 As shown, transistor M N1 and transistor M N2 Turn on, pull down its drain voltage, transistor M N3 and transistor M N4 When in the off state, the entire circuit is in standby mode. Transistor M N7 and transistor M P7 The positive feedback signal transmission path is closed, transistor M is off. N8 Turn on, transistor M N8 The drain voltage of transistor M is pulled low. N9 When the transistor is off, the positive feedback signal is not transmitted to the output terminal OUT1. P3 and transistor M P4 When enabled, the voltage of output terminals OUT1 and OUT2 is pulled up to the power supply voltage VDD, so that output terminals OUT1 and OUT2 can be pre-charged.

[0031] During the data reading phase, the enable signal EN is 1, and the inverted enable signal ENB is 0. Assuming the bit line BL terminal is 1 and the bit line inverted BLB terminal is 0, the circuit operates in read mode. Figure 5 As shown. Transistor M P1 and transistor M P2When turned on, the voltages at the BL and BLB terminals are transferred to transistor M respectively. N3 Gate and transistor M N4 The gate of the transistor M N3 When the transistor is turned on, the voltage at node N1 is pulled low. N4 Not enabled; the voltage at node N2 remains high. With enable signal EN at 1 and the inverted enable signal ENB at 0, transistor M, acting as the transmission transistor... N7 and transistor M P7 Enable, transmitting the high level at node N2 to transistor M. N9 The gate of transistor M makes transistor M N9 When the transistor is turned on, the voltage at the output terminal OUT1 is quickly pulled low, and transistor M... N5 Transistor M N6 Transistor M P5 and transistor M P6 The differential amplifier unit 12, as configured, begins to operate, in M N4 When the gate voltage is high, the positive feedback loop is closed, the output terminal OUT1 is high, and transistor M... N6 The voltage at the output terminal OUT2 is quickly pulled down, and the two inverters inside the differential amplifier unit 12 quickly start working to complete the data reading.

[0032] In one embodiment, a memory is also provided, the read circuit of which includes any of the above-described low-voltage, high-speed latch-type sensitive amplifier circuits.

[0033] The aforementioned memory, by applying the low-voltage, high-speed latch-type sensitive amplifier circuit in its read circuit, can not only operate normally under low power supply voltage, but also support high-speed data read operations, thereby effectively improving the performance of the memory.

[0034] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0035] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A low-voltage, high-speed latch-type sensitive amplifier circuit, characterized in that, It includes a differential amplifier unit, a feedback transmission switch unit, a first switch logic unit, and a second switch logic unit; The first differential input terminal of the differential amplifier unit is connected to the output terminal of the first switching logic unit. The second differential input terminal of the differential amplifier unit is connected to the input terminal of the feedback transmission switch unit and the output terminal of the second switching logic unit, respectively. The output terminal of the feedback transmission switch unit is connected to the first differential output terminal of the differential amplifier unit. The input terminal of the first switching logic unit is used to receive the differential signal BL from the memory, and the input terminal of the second switching logic unit is used to receive the differential signal BLB from the memory. During the pre-charging phase, the feedback transmission switch unit is used to disconnect the positive feedback connection between the second differential input terminal and the first differential output terminal of the differential amplifier unit, the first switch logic unit is used to disconnect the differential signal BL from the differential amplifier unit, and the second switch logic unit is used to disconnect the differential signal BLB from the differential amplifier unit. During the data reading phase, the feedback transmission switch unit is used to connect the positive feedback connection between the second differential input terminal and the first differential output terminal of the differential amplifier unit. The first switch logic unit is used to connect the differential signal BL to the differential amplifier unit, and the second switch logic unit is used to connect the differential signal BLB to the differential amplifier unit.

2. The low-voltage, high-speed latch-type sensitive amplifier circuit according to claim 1, characterized in that, The first switching logic unit includes transistor M. N1 Transistor M P1 and transistor M N3 ; transistor M N1 The source is grounded, transistor M N1 The drains of the transistors are connected to transistor M respectively. P1 The drain and transistor M N3 The gate of the transistor M N3 The drain of transistor M is connected to the first differential input terminal of the differential amplifier unit. N3 The source is grounded, transistor M N1 Gate and transistor M P1 The gates of all are used to receive the inverted enable signal ENB.

3. The low-voltage, high-speed latch-type sensitive amplifier circuit according to claim 1, characterized in that, The second switching logic unit includes transistor M. N2 Transistor M P2 and transistor M N4 ; transistor M N2 The source is grounded, transistor M N2 The drains of the transistors are connected to transistor M respectively. P3 The drain and transistor M N4 The gate of the transistor M N4 The drain of transistor M is connected to the second differential input terminal of the differential amplifier unit. N4 The source is grounded, transistor M N2 Gate and transistor M P2 The gates of all are used to receive the inverted enable signal ENB.

4. The low-voltage, high-speed latch-type sensitive amplifier circuit according to any one of claims 1 to 3, characterized in that, The feedback transmission switching unit includes transistor M N7 Transistor M N8 Transistor M P7 and transistor M N9 ; transistor M N7 The source and transistor M P7 The sources of both transistors are connected to the second differential input terminal of the differential amplifier unit, and transistor M... N7 The drain and transistor M P7 The drains of both transistors are connected to transistor M. N9 The gate of the transistor M N7 The gate of transistor M is used to receive the enable signal EN. P7 The gate is used to receive the inverted enable signal ENB; transistor M N9 The drain of transistor M is connected to the first differential output terminal of the differential amplifier unit. N9 The source and transistor M N8 The sources of transistor M are all grounded. N8 Drain-connected transistor M N9 The gate of the transistor M N8 The gate is used to receive the inverted enable signal ENB.

5. A memory, characterized in that, The read circuit of the memory includes the low-voltage, high-speed latch-type sensitive amplifier circuit as described in any one of claims 1 to 4.

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