Signal processing method and apparatus, clock data recovery circuit, and electronic device

Abstract

The application discloses a signal processing method and device, a clock data recovery circuit, and electronic equipment. The signal processing method comprises the following steps: acquiring signal data; determining first phase information of the signal data based on the signal data and a signal transmission mode; when it is determined that the signal data is in a phase non-offset state, changing the phase information of the signal data into a phase offset state; when the signal data is in the phase offset state, controlling the clock data recovery circuit to be open-loop, adjusting the signal data to move by a first preset phase; controlling the clock data recovery circuit to be closed-loop, continuing to adjust the signal data to move by a second preset phase, determining second phase information of the adjusted signal data; and adjusting the signal data to move by a third preset phase based on the first phase information and the second phase information, wherein the third preset phase is opposite to the moving directions of the first preset phase and the second preset phase. The application has the technical effect of improving the processing efficiency of the clock data recovery circuit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of clock data recovery, and in particular, to a signal processing method and device, a clock data recovery circuit, and an electronic device. BACKGROUND

[0002] In a passive optical network (PON) and a high-speed serial link (SerDes) system, a receiving end needs to perform clock and data recovery (CDR) on a burst multi-rate data signal from a network. However, with the continuous increase in data rate and the short burst packet switching requirement existing in a service scenario, the lock time of the clock data recovery circuit is limited by loop bandwidth, phase discriminator metastability, and digital decision delay, making it difficult to meet the fast switching requirement of current technology development. Therefore, the problem of long lock time in the clock data recovery process is worth attention. SUMMARY

[0003] In view of this, embodiments of the present application provide a signal processing method and device, a clock data recovery circuit, and an electronic device to improve the processing efficiency of the clock data recovery circuit. In a first aspect, a signal processing method is provided, applied to a clock data recovery circuit, including: obtaining signal data; determining first phase information of the signal data based on the signal data and a signal transmission mode, the first phase information including: a phase offset state or a phase non-offset state, the phase offset state including: phase delay or phase advance; when it is determined that the signal data is in the phase non-offset state, changing the phase information of the signal data to the phase offset state; when the signal data is in the phase offset state, controlling the clock data recovery circuit to be open-loop, adjusting the signal data to move by a first preset phase; controlling the clock data recovery circuit to be closed-loop, continuing to adjust the signal data to move by a second preset phase, and determining second phase information of the adjusted signal data; based on the first phase information and the second phase information, adjusting the signal data to move by a third preset phase, the third preset phase being opposite in moving direction to the first preset phase and the second preset phase, and the phase value of the third preset phase being smaller than the phase value of the second preset phase, and the phase value of the second preset phase being smaller than the phase value of the first preset phase.

[0004] Optionally, when it is determined that the signal data is in a burst mode, the first phase information of the signal data is determined based on the signal data, and further including: waiting for a first preset number of periods, and when the signal data reaches the first preset number of periods, determining the first phase information based on the signal data.

[0005] Optionally, the determining the first phase information of the signal data based on the signal data comprises: determining the first phase information of the signal data in a second preset number of periods of the signal data; and determining that the signal data is in a phase non-offset state when each of the second preset number of periods does not satisfy the phase offset state.

[0006] Optionally, the adjusting the signal data to move by a first preset phase comprises: adjusting the signal data to move by the first preset phase based on a third preset period; and the adjusting the signal data to move by a second preset phase comprises: adjusting the signal data to move by the second preset phase based on a fourth preset number of periods.

[0007] Optionally, the adjusting the signal data to move by a third preset phase based on the first phase information and the second phase information comprises: adjusting the signal data to move by the third preset phase when the second phase information is opposite to the first phase information.

[0008] Optionally, a phase value of the second preset phase is determined based on a loop delay and a phase gain of the clock data recovery circuit.

[0009] Optionally, the determining the first phase information of the signal data based on the signal data and the signal transmission mode comprises: determining a transmission mode of the signal data based on a preamble in the signal data, the transmission mode comprising: a burst mode and a continuous mode; and determining the first phase information of the signal data when the signal data is determined to be in the burst mode.

[0010] In a second aspect, a signal processing apparatus is provided, comprising: an acquisition unit configured to acquire signal data; a first determination unit configured to determine first phase information of the signal data based on the signal data and a signal transmission mode, the first phase information comprising: a phase offset state or a phase non-offset state, the phase offset state comprising: a phase delay or a phase advance; a first adjustment unit configured to adjust the signal data to move by a first preset phase to change phase information of the signal data to the phase offset state when the first determination unit determines that the signal data is in the phase non-offset state; a second adjustment unit configured to adjust the signal data to move by a second preset phase when the first determination unit determines that the signal data is in the phase offset state; a second determination unit configured to determine second phase information of the adjusted signal data, the second phase information being acquired later than the first phase information; and a third adjustment unit configured to adjust the signal data to move by a third preset phase based on the first phase information and the second phase information, the third preset phase being opposite in moving direction to the first preset phase and the second preset phase, wherein a phase value of the third preset phase is smaller than a phase value of the second preset phase, and the phase value of the second preset phase is smaller than a phase value of the first preset phase.

[0011] In a third aspect, a clock data recovery circuit is provided, comprising: a phase detection circuit, a state machine, and a digital filter; the phase detection circuit is configured to obtain signal data, and determine first phase information of the signal data based on the signal data and a signal transmission mode, the first phase information comprising: a phase offset state or a phase non-offset state, the phase offset state comprising: a phase delay or a phase advance; the state machine is configured to change the phase information of the signal data to the phase offset state when the phase detection circuit determines that the signal data is in the phase non-offset state; and further configured to control a phase interpolator to adjust the signal data to move a first preset phase by the digital filter when the phase detection circuit determines that the signal data is in the phase offset state; and further configured to control the clock data recovery circuit to be in a closed loop, continue to control the phase interpolator to adjust the signal data to move a second preset phase by the digital filter, and determine second phase information of the adjusted signal data; and further configured to control the phase interpolator to adjust the signal data to move a third preset phase by the digital filter based on the first phase information and the second phase information, the third preset phase being opposite in moving direction to the first preset phase and the second preset phase, wherein a phase value of the third preset phase is smaller than a phase value of the second preset phase, and the phase value of the second preset phase is smaller than a phase value of the first preset phase.

[0012] In a fourth aspect, an electronic device is provided, comprising: the clock data recovery circuit provided in the third aspect. BRIEF DESCRIPTION OF DRAWINGS

[0013] The drawings used in the following description of embodiments of the present disclosure are briefly described as follows:

[0014] Figure 1 FIG. 1 shows a circuit structure schematic diagram of a clock data recovery circuit provided in some embodiments of the present application;

[0015] Figure 2 FIG. 2 shows a flowchart of a signal processing method provided in some embodiments of the present application;

[0016] Figure 3 FIG. 3 shows a relationship between a period and a unit time interval provided in some embodiments of the present application;

[0017] Figure 4 FIG. 4 shows a flowchart of another signal processing method provided in some embodiments of the present application;

[0018] Figure 5 FIG. 5 shows a structure schematic diagram of a signal processing device provided in some embodiments of the present application. DETAILED DESCRIPTION

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will describe the embodiments of the present disclosure with reference to the drawings. The drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained from these drawings without creative labor, and other embodiments can be obtained, and the adjustments and improvements made without departing from the concept of the present disclosure are within the protection scope of the present disclosure.

[0020] In order to make the drawings simple, each drawing only schematically shows the part related to the embodiments, and it does not represent the actual structure of the product. In addition, in order to make the drawings simple and easy to understand, in some drawings, only some parts with the same structure or function are schematically shown, and there can be more or less parts with the same structure or function.

[0021] In the present disclosure, unless otherwise explicitly specified and limited, ordinal words such as "first", "second", etc. are only used to distinguish the description of the associated objects, and cannot be understood as indicating or implying the relative importance or order between the associated objects; in addition, it also does not represent the number of the associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between the associated objects, which represents the "or" relationship between the associated objects. "And / or" is used to describe the relationship between the associated objects, which includes any combination relationship between the associated objects, for example, "a and / or b" includes: "a alone", "b alone", or "a and b". "One or more" or "at least one" of multiple objects means any object or any combination of multiple objects, for example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "a1 alone", "a2 alone", "a3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0022] Clock data recovery circuit is an important part of high-speed serial link system, which is often used for clock and data recovery in high-speed serial link system receiver. In passive optical communication network, in order to meet the use of multiple users, data transmission usually takes two forms of time division multiplexing and wavelength division multiplexing. For the above two application scenarios, the data received by the receiver is divided into multiple short data packets, and each data packet includes a preamble, valid data and a stop symbol. The rate and phase between different data packets may be different, so the clock data recovery circuit needs to re-phase lock the data every time the data is received. In modern passive optical networks and high-speed serial links, the receiving end must accurately align the received serial signal with the local reference clock through the clock data recovery loop to achieve reliable sampling. The clock data recovery circuit adopts a closed-loop feedback structure of phase detector, loop filter and phase interpolator to gradually correct the phase deviation, but due to the limitation of loop bandwidth to jitter suppression and stability requirements, it is difficult to quickly respond to large phase errors, and the phase detector is easy to fall into the metastable state of uncertain decision at the critical zero-crossing point. The decision of the digital processing logic (such as FPGA or ASIC) on the phase detection result and the driving of the phase interpolator have a non-negligible delay, so when multiple rates of short data packets need to be quickly switched, the clock data recovery process often cannot complete the phase locking in the extremely short preamble window, thereby affecting the error code performance and service continuity of the overall communication system. On the one hand, in the clock data recovery circuit, when the phase detector samples near the zero-crossing point of the signal data, the input signal is very close to zero crossing with the sampling clock, and the phase detector cannot reliably distinguish between "advance" or "delay" states, thereby outputting a period of uncertain decisions or no decisions. At this time, the loop cannot continue to fine-tune in a closed loop or enter normal locking, causing the locking process to be delayed or stuck. On the other hand, the loop bandwidth of the clock data recovery circuit determines its response speed to phase error changes. The narrower the bandwidth, the more the loop filter will attenuate high-frequency (rapidly changing) phase error signals, allowing only very slow offset components to pass. This means that each phase adjustment can only be made in very small steps and requires multiple feedback-filtering-correction cycles to gradually compress large initial phase deviations to zero. At each step, the phase interpolator must be driven after the error signal is smoothed by the filter, and the entire process often takes tens to hundreds of clock cycles, so the locking time is naturally very long. Therefore, when a burst packet causes a large phase deviation, the "slow response" and "multiple iterations" caused by narrow-band filtering of the loop lengthens the total time taken from the start of clock data recovery to the final accurate alignment. Therefore, the present application provides a signal processing method and device, a clock data recovery circuit and an electronic device, which adjusts the phase of the local clock by setting a state machine to take over the clock data recovery loop after the start of the burst mode of signal transmission, thereby improving the processing efficiency of the clock data recovery circuit.

[0023] The application will be described in more detail below with reference to the drawings.

[0024] Figure 1 A circuit structure schematic diagram of a clock data recovery circuit provided in some embodiments of the application is shown. The clock data recovery circuit 100 includes a phase detection circuit 110, a state machine 120 and a digital filter 130. The phase detection circuit 110 can determine the phase difference between the zero crossing point of the signal data from the receiver front end 20 and the current sampling clock, and output the phase state information of the signal data to the state machine 120. The state machine 120 can control the gain state of the digital filter 130 according to the determination result of the phase detection circuit 110 and the preset period logic, and further adjust the phase of the local clock, and realize the loop locking and release of the clock data recovery circuit. The digital filter 130 can generate a voltage driving the phase interpolator 30 based on the phase adjustment instruction of the state machine 120, and the voltage is directly output as the control input of the phase interpolator 30.

[0025] Figure 2 A flowchart of a signal processing method provided in some embodiments of the application is shown. The signal processing method is applied to a clock data recovery circuit, and includes:

[0026] S210: obtaining signal data;

[0027] S220: determining first phase information of the signal data based on the signal data and the signal transmission mode, the first phase information including: a phase offset state or a phase non-offset state, the phase offset state including: a phase delay or a phase advance;

[0028] S230: when it is determined that the signal data is in the phase non-offset state, changing the phase information of the signal data to the phase offset state;

[0029] S240: when the signal data is in the phase offset state, controlling the clock data recovery circuit to be open-loop, and adjusting the local clock to move by a first preset phase;

[0030] S250: controlling the clock data recovery circuit to be closed-loop, continuing to adjust the local clock to move by a second preset phase, and determining second phase information of the adjusted signal data;

[0031] S260: adjusting the local clock to move by a third preset phase based on the first phase information and the second phase information, the third preset phase being opposite in moving direction to the first preset phase and the second preset phase, and the phase value of the third preset phase being smaller than the phase value of the second preset phase, and the phase value of the second preset phase being smaller than the phase value of the first preset phase.

[0032] In the embodiment of the above signal processing method, first, serial signal data is continuously collected from a signal input port, and when the first phase information of the signal data is determined based on the signal data and the signal transmission mode, the first valid sampling point of the signal data and the reference time of the local clock are compared to determine whether the first phase information of the signal data belongs to a phase offset state or a phase non-offset state. The phase offset state can include a phase delay (late) or a phase advance (early), and the determination result is latched as the first phase information. If the first phase information is a phase non-offset state, the system can immediately rewrite the internal state marker of the signal data to "phase delay" or "phase advance" to ensure that the subsequent phase adjustment process is carried out in the predetermined direction, and the internal state marker can be selected as either of the above two phase offset states, thereby promoting the signal data determined to be in a metastable state to escape from the metastable state. Further, the system can control the clock data recovery circuit to open loop and temporarily suspend the feedback correction mechanism, so as to adjust the local clock to move a first preset phase, and accumulate driving the local clock to offset the first preset phase by a certain amplitude per cycle in the next several clock cycles, so that the phase of the local clock is moved by a large step at one time, and the clock data recovery loop escapes from the metastable state. After completing the large step movement to escape from the metastable state, the clock data recovery circuit can be locked, and the loop gain cannot be too large during locking, otherwise the phase difference between the final locking point and the ideal locking point is large, resulting in that the locking point is far away from the actual locking point. Therefore, the local clock is further adjusted to move a second preset phase, the second preset phase is smaller than the first preset phase, the second phase information of the signal data at this time is determined again, and then the first phase information and the second phase information are compared. If the directions are opposite, the required fine adjustment amount (third preset phase) is calculated, and reverse fine adjustment is completed through closed loop micro driving in one or several clock cycles, so as to finally accurately align the local clock. After the process is completed, the clock data recovery circuit returns to the normal working mode, and the fast locking is completed. The longest locking time of the clock data recovery circuit is when the sampling clock is near the zero crossing point, and the shortest locking time is when the clock phase coincides with the center locking point (at this time, it almost tends to 0 or equals to 0). In order to reduce the longest locking time, the loop gain of the clock data recovery circuit is adjusted to the maximum gain that the clock data recovery circuit can tolerate, and then the local clock phase is first moved by the first preset phase, so that the phase of the local clock is moved by a large step at one time. The second phase information determined in the subsequent working process is compared with the first phase information read for the first time. If the result opposite to the first read phase appears, it indicates that the local clock phase has been flipped from one end of the center locking point to the other end, and the clock data recovery circuit is close to the optimal locking point.Since there is a delay in the phase update of the local clock, the phase of the sampling clock of the current phase detection circuit is transmitted by the phase interpolator a plurality of cycles ago, and therefore, the local clock phase needs to be backed off to the phase corresponding to the local clock before the flip, that is, the local clock is adjusted by a third preset phase. Through this embodiment, the local clock is moved by a first preset phase in an open loop, a second preset phase is adjusted in a closed loop, and a third preset phase is fine-tuned in a reverse direction based on the first and second phase information, so that the loop of the clock data recovery circuit can be quickly locked under a signal data transmission burst, the metastable state can be quickly escaped, high-precision alignment can be achieved in a small step in the last stage, the metastable state and the loop bandwidth limitation can be effectively avoided, the adaptability to multi-rate burst data packets can be improved, the lock time can be significantly shortened, and the system stability and reliability can be improved.

[0033] In some embodiments of the present application, the first phase information of the signal data is determined based on the signal data and the signal transmission mode, and further includes: waiting for a first preset number of cycles, and when the signal data reaches the first preset number of cycles, determining the first phase information based on the signal data.

[0034] In this embodiment, after determining that the signal data is transmitted in a burst mode according to the signal data and the signal transmission mode, the first phase information is not immediately determined, but a cycle count is performed, for example, the phase is detected after waiting for 2 clock cycles, so that the signal data is fully established inside the receiving end, and the abnormality of the determination result is avoided. When the receiving window spans a preset first number of cycles, the determination result at this moment is latched as the first phase information, so as to avoid misjudging the phase state when the preamble just enters the eye diagram and the signal is not stable. By delaying the determination, it is ensured that the input signal data is filtered and time-stabilized before the phase is determined, so as to improve the reliability of the phase information and reduce the risk of misjudgment.

[0035] In some embodiments of the present application, the first phase information of the signal data is determined based on the signal data, and further includes: determining the first phase information of the signal data in a second preset number of cycles of the signal data; and when each cycle in the second preset number of cycles does not satisfy the phase offset state, determining that the signal data is in a phase non-offset state.

[0036] In this embodiment, after the signal data is obtained, the phase information of the signal data can be continuously determined in the second preset number of cycles, and the result is latched as the first phase information as long as there is an early or late determination. If the phase detector continuously determines that there is no delay or advance in the second preset period, it is determined that there is a metastable state, and the first phase information of the signal data is forcibly set to the phase offset state to prepare for phase adjustment.

[0037] In some embodiments of the present application, adjusting the local clock to move by the first preset phase includes: adjusting the local clock to move by the first preset phase based on a third preset number of periods; and adjusting the local clock to move by the second preset phase includes: adjusting the local clock to move by the second preset phase based on a fourth preset number of periods.

[0038] In the present embodiment, in order to make the clock data recovery circuit escape from the metastable state, in the open-loop coarse adjustment phase, a phase offset instruction can be issued to the phase interpolator every period for a third preset number of periods, so that the local clock is adjusted by a large step, thereby shortening the lock-in time; then in the closed-loop fine adjustment phase, a phase offset instruction is issued for a fourth preset number of periods, and a small step is adjusted every period until the collection of the second phase information is completed. By limiting the number of adjustment periods in each phase, the execution time of coarse adjustment and fine adjustment is controllable, and the closed loop is stable.

[0039] In some embodiments of the present application, based on the first phase information and the second phase information, adjusting the local clock to move by a third preset phase includes: when the second phase information is opposite to the first phase information, adjusting the local clock to move by the third preset phase.

[0040] When the second phase information is opposite to the first phase information, it indicates that the phase of the local clock has been flipped from one end of the center lock point to the other end, and the clock data recovery circuit is close to the optimal lock point. Since there is a delay in updating the phase of the local clock, the phase of the sampling clock of the current phase detection circuit is transmitted by the phase interpolator a plurality of periods ago, and therefore, the phase of the local clock needs to be rolled back to the phase corresponding to the local clock before the flip, that is, the local clock is adjusted by the third preset phase. Then the clock data recovery circuit returns to the normal working mode and reports the end of the burst mode. By comparing the latched first phase information and the second phase information, if the directions of the two are opposite, the phase of the local clock is adjusted in the opposite direction by the third preset phase calculated in advance, so as to compensate for the "out-of-bound" error caused by the loop delay.

[0041] In some embodiments of the present application, the phase value of the second preset phase is determined based on the loop delay and the phase gain of the clock data recovery circuit.

[0042] The loop delay refers to the total delay of a closed loop path from outputting a decision of the phase detection circuit to the decision signal being processed by the state machine and the digital filter and finally driving the phase interpolator to change the phase, which may include, for example, the decision delay of the phase detection circuit itself, the state machine latching and state switching delay, or the processing delay of the digital filter. The phase gain refers to the ability of the CDR to change the phase of the phase decision result, that is, how many UIs of phase movement can be caused by each obtained phase decision result. When it is determined that the first phase information and the second phase information are opposite, the ideal compensation phase amount can be the product of the loop delay and the phase gain, and then the state machine outputs the corresponding voltage to the phase interpolator through the digital filter to make it move reversely to make accurate compensation. By accurately matching the third preset phase with the loop characteristics, faster convergence to the optimal locking point can be achieved in the callback phase.

[0043] In some embodiments of the present application, based on the signal data and the signal transmission mode, the first phase information of the signal data is determined, including: determining the transmission mode of the signal data based on the preamble in the signal data, the transmission mode including: burst mode and continuous mode; when it is determined that the signal data is in the burst mode, the first phase information of the signal data is determined.

[0044] With reference to the foregoing Figure 1 , the phase detection circuit 110 is configured to acquire signal data and determine the first phase information of the signal data based on the signal data and the signal transmission mode, the first phase information including: a phase offset state or a phase non-offset state, the phase offset state including: a phase delay or a phase advance; the state machine 120 is configured to change the phase information of the signal data to the phase offset state when the phase detection circuit determines that the signal data is in the phase non-offset state; and further configured to control the phase interpolator to adjust the local clock to move a first preset phase through the digital filter 130 when the phase detection circuit determines that the signal data is in the phase offset state; and further configured to control the clock data recovery circuit to close loop and continue to control the phase interpolator 30 to adjust the local clock to move a second preset phase through the digital filter 130, to determine the second phase information of the adjusted signal data; and further configured to control the phase interpolator 30 to adjust the local clock to move a third preset phase through the digital filter 130 based on the first phase information and the second phase information, the third preset phase being opposite in moving direction to the first preset phase and the second preset phase, wherein the phase value of the third preset phase is smaller than the phase value of the second preset phase, and the phase value of the second preset phase is smaller than the phase value of the first preset phase.

[0045] The phase detection circuit 110 detects the start of the burst and waits for 2 clock cycles to start detecting the phase. Here, the waiting for 2 cycles is to make the signal fully established inside the receiving end to avoid abnormal decision results. Figure 3This diagram illustrates the relationship between a period and a unit interval (UI) as provided in some embodiments of this application. The unit interval (UI) represents the duration of one bit period or one symbol period and is used to measure the magnitude of phase offset or delay. For example, a deviation of 1 / 2UI means that the clock phase differs from the ideal sampling point by half a bit period. The phase detection circuit 110 begins detecting phase information and determines whether an advance or delay has occurred. After the phase detection circuit 110 detects an advance or delay, the state machine 120 latches the current result. If no advance or delay occurs for four consecutive periods, the state machine 120 forcibly writes a delay (or advance) to the phase detection circuit 110 and latches the result. Then, the state machine 120 disconnects the loop of the clock data recovery circuit and controls the phase interpolator 30 to adjust the phase by 1 / 16UI each period through the digital filter 130. After four periods, the state machine 120 releases the loop control over the clock recovery circuit (i.e.,...). Figure 3 (As shown at the point of departure from the merging point), the phase detection circuit 110 normally outputs phase information, only adjusting the gain of the digital filter 130 so that the phase interpolator 30 moves at 1 / 64UI phase per cycle. After re-timing for 4 cycles, the state machine 120 begins to read the phase information output by the phase detection circuit 110 and checks whether a phase opposite to the first detected phase appears. The 4-cycle wait is because the phase written to the phase interpolator 30 in the previous step requires 4 cycles to return to the phase detection circuit 110. When opposite phase information is detected (i.e.,...) Figure 3 (As shown in the backoff clock phase diagram), state machine 120 controls digital filter 130 to cause phase interpolator 30 to move in the reverse direction. The magnitude of the shifted phase corresponds to the product of the loop delay and phase gain of the clock data recovery circuit. Simultaneously, state machine 120 relinquishes control of the clock data recovery circuit, which then enters its normal operating mode and reports the end of the burst lockout process. The phase detection circuit 110, state machine 120, and digital filter 130 can be implemented using analog circuits, thereby increasing the clock rate and shortening the lockout time of the clock data recovery circuit. Figure 4 This paper illustrates a flowchart of another signal processing method provided in some embodiments of this application. This method can be implemented using the clock data recovery circuit 100 described above, and includes the following steps:

[0046] S410: Acquire signal data and determine the start of burst mode;

[0047] S420: Wait for 2 cycles and start detecting phase information;

[0048] S430: Detect phase information for 4 consecutive cycles and determine in real time whether there is a delay or advance; if there is no delay or advance, execute step S431; if there is a delay or advance, execute step S432.

[0049] S431: Force the phase information to be delayed;

[0050] S432: Control the clock data recovery circuit gain adjustment to 1 / 16 UI per step for 4 cycles, and store the first read phase information;

[0051] S440: Control the clock data recovery circuit gain adjustment to 1 / 64 UI per step for 8 cycles;

[0052] S450: Detect whether different phase information from the first stored phase information appears;

[0053] S460: Back up the clock data recovery circuit gain loop corresponding phase, and adjust the gain to 1 / 512 UI.

[0054] The specific content and beneficial effects of the above flow steps can refer to the specific content of the above signal processing method embodiments, and will not be repeated here.

[0055] Figure 5 A structure diagram of a signal processing device provided in some embodiments of the present application is shown, and the signal processing device 500 includes: an acquisition unit 510 configured to acquire signal data; a first determination unit 520 configured to determine first phase information of the signal data based on the signal data and a signal transmission mode, the first phase information including: a phase offset state or a phase non-offset state, the phase offset state including: a phase delay or a phase advance; a first adjustment unit 530 configured to adjust a local clock to move a first preset phase when the first determination unit 520 determines that the signal data is in the phase non-offset state, so that the phase information of the signal data is changed to the phase offset state; a second adjustment unit 540 configured to adjust the local clock to move a second preset phase when the first determination unit 520 determines that the signal data is in the phase offset state; a second determination unit 550 configured to determine second phase information of the adjusted signal data; and a third adjustment unit 560 configured to adjust the local clock to move a third preset phase based on the first phase information and the second phase information, the third preset phase being opposite in moving direction to the first preset phase and the second preset phase, and the phase value of the third preset phase being smaller than the phase value of the second preset phase, and the phase value of the second preset phase being smaller than the phase value of the first preset phase.

[0056] The division of the above units is only a logical function division, and all or part of the units can be integrated into a physical entity or physically separated when actually implemented. In addition, the above units can be implemented in the form of processor calling software; for example, the signal processing device includes a processor, the processor is connected with a memory, the memory stores instructions, and the processor calls the instructions stored in the memory to implement any of the above methods or to realize the functions of each unit, wherein the processor is, for example, a general processor, such as a central processing unit (CPU), and the memory is a memory in the device or a memory outside the device. Alternatively, the above units can be implemented in the form of hardware circuit, and the functions of part or all of the units can be realized by designing the hardware circuit, which can be understood as one or more processors; for example, in some embodiments, the hardware circuit is an application specific integrated circuit (ASIC), and the functions of part or all of the units are realized by designing the logical relationship of elements in the circuit; for example, in another implementation, the hardware circuit is a programmable logic device (PLD) that can be implemented, which can include a large number of logic gate circuits, and the logical relationship between the logic gate circuits is configured by a configuration file, so as to realize the functions of part or all of the units. All units of the above device can be implemented in the form of processor calling program, or all units can be implemented in the form of hardware circuit, or part of the units are implemented in the form of processor calling program, and the remaining part is implemented in the form of hardware circuit.

[0057] Based on the same technical concept, the present application also provides an electronic device, comprising: the clock data recovery circuit provided in the above embodiments.

[0058] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A signal processing method, characterized in that, Applications in clock data recovery circuits include: Acquire signal data; Based on the signal data and signal transmission mode, first phase information of the signal data is determined. The first phase information includes: phase offset state or phase no offset state. The phase offset state includes: phase delay or phase advance. The signal transmission mode includes: burst mode and continuous mode. When it is determined that the signal data is in the phase-no-offset state, the phase information of the signal data is changed to the phase-offset state. When the signal data is in the phase offset state, control the clock data recovery circuit to open the loop and adjust the local clock to move the first preset phase; The clock data recovery circuit is controlled to close the loop, and the local clock is further adjusted to move a second preset phase. The second phase information of the adjusted signal data is determined, and the second phase information includes: phase delay or phase advance. Based on the first phase information and the second phase information, adjusting the local clock to move a third preset phase includes: when the second phase information is opposite to the first phase information, adjusting the local clock to move the third preset phase; wherein the third preset phase moves in the opposite direction to the first preset phase and the second preset phase, and wherein the phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

2. The signal processing method according to claim 1, characterized in that, The step of determining the first phase information of the signal data based on the signal data and the signal transmission mode further includes: Wait for a first preset number of cycles. When the signal data reaches the first preset number of cycles, determine the first phase information based on the signal data.

3. The signal processing method according to claim 2, characterized in that, The step of determining the first phase information of the signal data based on the signal data further includes: determining the first phase information of the signal data within a second preset number of cycles of the signal data; If the phase offset state is not satisfied in each of the second preset number of cycles, the signal data is determined to be in a phase-offset state.

4. The signal processing method according to claim 3, characterized in that, The adjustment of the local clock to move a first preset phase includes: The local clock is adjusted to move the first preset phase based on a third preset number of cycles; The adjustment of the local clock to move a second preset phase includes: The local clock is adjusted to move the second preset phase based on the fourth preset number of cycles.

5. The signal processing method according to any one of claims 1 to 4, characterized in that, The phase value of the second preset phase is determined based on the loop delay and phase gain of the clock data recovery circuit.

6. The signal processing method according to any one of claims 1 to 4, characterized in that, The step of determining the first phase information of the signal data based on the signal data and the signal transmission mode includes: Based on the preamble in the signal data, determine the transmission mode of the signal data; When the signal data is determined to be in the burst mode, the first phase information of the signal data is determined.

7. A signal processing apparatus, characterized in that, include: Acquisition unit, used to acquire signal data; The first determining unit is configured to determine first phase information of the signal data based on the signal data and the signal transmission mode. The first phase information includes: phase offset state or phase no offset state. The phase offset state includes: phase delay or phase advance. The signal transmission mode includes: burst mode and continuous mode. The first adjustment unit is used to adjust the local clock to move a first preset phase when the first determining unit determines that the signal data is in the phase-no-offset state, so that the phase information of the signal data is changed to the phase-offset state. The second adjustment unit is used to adjust the local clock to move a second preset phase when the first determining unit determines that the signal data is in the phase offset state. The second determining unit is used to determine the second phase information of the adjusted signal data, the second phase information including: phase delay or phase advance; The third adjustment unit is used to adjust the local clock to move a third preset phase based on the first phase information and the second phase information, including: adjusting the local clock to move the third preset phase when the second phase information is opposite to the first phase information; wherein the third preset phase moves in the opposite direction to the first preset phase and the second preset phase, and wherein the phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

8. A clock data recovery circuit, characterized in that, include: Phase detection circuit, state machine, and digital filter; The phase detection circuit is used to acquire signal data and determine first phase information of the signal data based on the signal data and the signal transmission mode. The first phase information includes: phase offset state or phase no offset state. The phase offset state includes: phase delay or phase advance. The signal transmission mode includes: burst mode and continuous mode. The state machine is configured to: change the phase information of the signal data to the phase-offset state when the phase detection circuit determines that the signal data is in the phase-free state; also be configured to: control the phase interpolator through the digital filter to adjust the local clock by a first preset phase when the phase detection circuit determines that the signal data is in the phase-offset state; and control the clock data recovery circuit to close the loop, continue to control the phase interpolator through the digital filter to adjust the local clock by a second preset phase, and determine the second phase information of the adjusted signal data, wherein the second phase information includes: phase delay or phase advance. And for adjusting the local clock to move a third preset phase by controlling the phase interpolator through the digital filter based on the first phase information and the second phase information, including: adjusting the local clock to move the third preset phase when the second phase information is opposite to the first phase information; wherein the third preset phase moves in the opposite direction to the first preset phase and the second preset phase, wherein the phase value of the third preset phase is less than the phase value of the second preset phase, and the phase value of the second preset phase is less than the phase value of the first preset phase.

9. An electronic device, characterized in that, include: The clock data recovery circuit as described in claim 8.

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