Clock data recovery circuit, chip and electronic equipment

Abstract

The utility model provides a clock data recovery circuit, a chip and electronic equipment, and the clock data recovery circuit comprises a clock extraction unit which extracts a first clock signal in an input data signal according to a first selection window signal; the voltage-controlled delay unit outputs a second clock signal according to the control signal, the second selection window signal and the output signal thereof; the reference clock generator is used for outputting multiple paths of reference clock signals required by other modules according to the second clock signal; the adjusting unit and the locking detection unit respectively output a control signal and a locking indication signal according to the frequency and phase difference of the first clock signal and the feedback clock signal; the sampler outputs data in the input data signal according to the sampling clock signal. According to the scheme, the CDR circuit is based on the MDLL first-order system, the system design is simple, the whole CDR circuit does not have the stability problem, the large bandwidth can be achieved, and the loop locking efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, in particular to a clock data recovery circuit, a chip and an electronic device. BACKGROUND

[0002] The CDR (Clock Data Recovery) circuit is a circuit for extracting a clock signal from a digital signal and recovering data. The CDR circuit is usually used in high-speed serial communication systems, such as optical fiber communication, Ethernet, PCI Express, etc. In these systems, the data transmission rate is very high, and clock offset may cause data transmission errors, so the CDR circuit is needed to recover and shape the data to the next module to ensure reliable data transmission.

[0003] For example, in a digital communication system, the clocks of the sending end and the receiving end may have a certain offset, which causes the receiving end to be unable to accurately parse the data sent by the sending end. The CDR circuit can be integrated in the transceiver, which extracts the clock signal from the input data, resamples the input data, and outputs the resampled signal, and can output the clock when needed. The resampled data can be recovered in signal amplitude, and the jitter is filtered when the input data jitter is large, reducing the output jitter. The clock signal used for extraction and generation of resampling needs to go through frequency locking and phase locking processes, and the maximum range guarantees the stable completion of the frequency locking and phase locking processes, and the loss of lock caused by all possible factors can recover the circuit locking as soon as possible, and at the same time ensure that the jitter of the circuit output is minimized. It is the difficulty of the architecture design of the clock data recovery circuit. CONTENT OF THE UTILITY MODEL

[0004] In order to solve the above technical problems, the present application provides a clock data recovery circuit, a chip and an electronic device, which aims to reduce the complexity of the CDR circuit in recovering the sampling clock and data and the complexity of the circuit structure, and improve the loop locking efficiency.

[0005] According to the first aspect of the present application, a clock data recovery circuit is provided, comprising:

[0006] The clock extraction unit receives an input data signal, a first selection window signal and a first reference clock signal, and outputs a first clock signal in the input data signal according to the first selection window signal;

[0007] The voltage-controlled delay unit receives the first clock signal, a second selection window signal and a control signal, and outputs a second clock signal according to the second selection window signal, the frequency of the second clock signal being equal to n+1 times the frequency of the first clock signal, n being an integer greater than 1;

[0008] The reference clock generator receives the second clock signal and outputs the first reference clock signal, the second reference clock signal, the third reference clock signal, the feedback clock signal and the sampling clock signal.

[0009] The adjusting unit receives the first clock signal and the feedback clock signal, and outputs the control signal according to the frequency and phase difference of the first clock signal and the feedback clock signal.

[0010] The lock detection unit receives the first clock signal and the feedback clock signal, and outputs a lock indication signal by detecting the frequency and phase difference of the first clock signal and the feedback clock signal.

[0011] The sampler receives the input data signal and the sampling clock signal, and outputs data in the input data signal according to the sampling clock signal.

[0012] The first selection signal generation unit receives the second reference clock signal and the lock indication signal, and outputs the first selection window signal.

[0013] The second selection signal generation unit receives the third reference clock signal, and outputs the second selection window signal.

[0014] Optionally, the input data signal has a clock indication bit between every n bits of data, and the logic value of the clock indication bit is opposite to that of the previous bit.

[0015] Optionally, the flip-flop is a double-edge flip-flop.

[0016] Optionally, the input data signal has a fixed logic value 01 inserted between every n bits of data.

[0017] Optionally, the flip-flop is a single-edge flip-flop.

[0018] Optionally, the clock extraction unit comprises:

[0019] The flip-flop receives an input data signal at a data input end and receives the first selection window signal at a clock input end, and outputs a rising edge of the input data signal according to the first selection window signal.

[0020] The first selector is connected with the output end of the flip-flop at a first input end, receives the first reference clock signal at a second input end, and receives the first selection window signal at a selection control end, and outputs the first clock signal in the input data signal according to the first selection window signal.

[0021] Optionally, the voltage-controlled delay unit comprises:

[0022] a second selector, a first input end of which is connected with an output end of the first selector to receive the first clock signal, a selection control end of which receives a second selection window signal, and an output end of which outputs a frequency multiplication signal of the first clock signal;

[0023] a voltage-controlled delay line, a clock input end of which is connected with an output end of the second selector, and a control end of which receives the control signal, an output end of the voltage-controlled delay line being connected with a second input end of the second selector, the voltage-controlled delay line being configured to perform delay processing on the frequency multiplication signal according to the control signal, and output the second clock signal.

[0024] Optionally, the adjusting unit comprises:

[0025] a phase frequency detector, a first input end of which receives the first clock signal, and a second input end of which receives the feedback clock signal, an output end of the phase frequency detector outputting a phase difference value signal of the first clock signal and the feedback clock signal;

[0026] a control signal generation unit, an input end of which is connected with an output end of the phase frequency detector, the CPLPF being configured to output the control signal according to the phase difference value signal.

[0027] Optionally, the control signal generation unit comprises:

[0028] a first current source, configured to provide a charging current;

[0029] a second current source, configured to provide a discharging current;

[0030] a capacitor, configured to receive the charging current and / or the discharging current, and generate the control signal.

[0031] According to a second aspect of the present application, an electronic device is provided, comprising:

[0032] a receiving circuit; and

[0033] a sending circuit, configured to send data to the receiving circuit through a channel,

[0034] wherein the receiving circuit comprises the clock data recovery circuit according to any one of the embodiments of the present application.

[0035] According to a third aspect of the present application, a chip is provided, the chip being integrated with the clock data recovery circuit according to any one of the embodiments of the present application.

[0036] The present application has at least the following beneficial effects:

[0037] The clock extraction unit, the voltage-controlled delay unit, the reference clock generator, the adjusting unit, the lock detection unit, the sampler, the first selection signal generation unit and the second selection signal generation unit and the connection relationship therebetween are used to construct a clock data recovery circuit (hereinafter referred to as a CDR circuit) according to the embodiments of the present application. Compared with the prior art, the present application provides a CDR circuit based on a first-order system of MDLL (Multiplying delay-locked loop, frequency multiplication delay-locked loop). The frequency locking and phase locking of the CDR circuit in the present application are performed simultaneously in the training stage, and there is no problem of switching between two loops. In addition, there is no need for complex loop stability analysis, and the system design is simple. The entire CDR circuit has no stability problem, and a larger bandwidth can be achieved.

[0038] In addition, the loop filter of the MDLL has only one capacitor, so the size of the capacitor can be reduced by reducing the charge pump current in proportion, thereby greatly reducing the area of the CDR circuit.

[0039] It should be noted that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A structural block diagram of a data sending and receiving system according to the embodiments of the present application is shown;

[0041] Figure 2 A structural schematic diagram of a CDR circuit without reference clock in the related art is shown;

[0042] Figure 3 A structural schematic diagram of a CDR circuit with reference clock in the related art is shown;

[0043] Figure 4 A structural schematic diagram of a CDR circuit according to the embodiments of the present application is shown;

[0044] Figure 5 A structural schematic diagram of a CDR circuit according to the embodiments of the present application is shown; Figure 4 A structural schematic diagram of a CDR circuit according to the embodiments of the present application is shown;

[0045] Figure 6 A timing waveform diagram of part of the signals in the CDR circuit according to the embodiments of the present application is shown;

[0046] Figure 7 A structural block diagram of a device containing the CDR circuit according to the embodiments of the present application is shown;

[0047] Figure 8 A structural block diagram of another device containing the CDR circuit according to the embodiments of the present application is shown. Detailed Implementation

[0048] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0049] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0050] In the description of this application, words such as "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. The term "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist, for example, A and / or B, which can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that terms such as "first" and "second" do not necessarily imply differences.

[0051] Furthermore, the same reference numerals in the figures denote the same or similar structures, thus repeated descriptions of them will be omitted. That is, the various parts in this specification are described using a combination of parallel and progressive methods, with each part focusing on its differences from the others. Similar or identical parts can be referred to interchangeably. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.

[0052] Figure 1A block diagram illustrating a structure of a data transmitting and receiving system according to an embodiment of the present application is shown with reference to FIG. 1. Figure 1 The data transmitting and receiving system can include a first device 110, a second device 120, and a transmission line 130.

[0053] The first device 110 for transmitting data can transmit data to the second device 120 via the transmission line 130 through a transmitting circuit 112. In an embodiment, the first device 110 can transmit data to the second device 120 only, can separately encode data to transmit encoded data, or can transmit data with a clock signal.

[0054] In some embodiments, the first device 110 can further include a serializer 111. The serializer 111 can divide data to be transmitted to the second device 120 according to a predetermined unit, and can transmit the data as burst data according to a high-speed serial interface.

[0055] The second device 120 can receive data transmitted by the first device 110 through the transmission line 130 and a receiving circuit 121. In an embodiment, the second device 120 can further include a decoder for decrypting encoded data. In various embodiments, the first device 110 can be referred to as a transmitting device, and the second device 120 can be referred to as a receiving device.

[0056] In some embodiments, the second device 120 can further include a deserializer 123. The deserializer 123 can receive an input data signal including a bit sequence to generate an output data signal including parallel data.

[0057] In some embodiments, the second device 120 can further include a clock data recovery circuit (hereinafter, referred to as a CDR circuit) 122. The CDR circuit 122 can receive an input data signal transmitted by the first device 110 in a serial communication method, and can generate an output data signal from the input data signal. The output data signal can be referred to as a recovered data signal. The input data signal can include a string of bits, i.e., a bit sequence. For example, the input data signal can include a grouping of a plurality of bits listed in order. The CDR circuit 122 can identify serial data included in the input data signal by sampling the bit sequence included in the input data signal, and can generate an output data signal including parallel data from the serial data.

[0058] Optionally, the input data signal can include a clock signal and serial data. The data signal including the serial data can be received from the first device 110 through the transmission line 130, and the clock signal can be received through a clock line (not shown) separate from the transmission line 130. In some embodiments, the first device 110 can have the clock signal included in the data signal, and the second device 120 can recover the clock signal included in the data signal to identify the serial data. The second device 120 can sample the bit sequence by recovering the clock signal including the data signal variation, so that the data transmission rate can be increased. The clock signal included in the input data signal can be referred to as an embedded clock.

[0059] In various embodiments, the transmission line 130 can be referred to as one of various terms including a transmission channel and a data channel. In addition, as shown in FIG. 1, the transmission line 130 is used for physical or electrical connection. However, the present application concept is not limited thereto. According to various embodiments, the transmission line 130 can refer to a channel for wirelessly transmitting data. Figure 1

[0060] Figure 2 A structure diagram of a CDR circuit of a related art without a reference clock is shown in FIG. 2. As shown in FIG. 2, the CDR circuit includes a phase detector 210, a loop filter 220, a voltage controlled oscillator (VCO) 230, and a phase interpolator 240. Figure 2 ​As shown, the CDR circuit includes: a FD (Frequency Detector) 201, a PD (Phase Detector) 205, CPs (Charge pumps) 202 and 206, a LF (loop filter) 203, and a VCO (Voltage Controlled Oscillator) 204. Among them, the FD 201, the CP 202, the LF 203, and the VCO 204 constitute a frequency tracking loop, and the frequency is locked through the FD 201; the PD 205, the CP 206, the LF 203, and the VCO 204 constitute a phase tracking loop, and the frequency is locked through the PD 206. In addition, the FD 201 compares the phase of the input data signal D(in) with the clock signal Recovered Clock output by the VCO 204, thereby saving the introduction of an external reference signal. During the startup of the CDR circuit or the loss of the phase-locked loop, the FD 201 is triggered, and the control voltage is raised through the CP 202 and the LF 203, so as to adjust the oscillation frequency of the VCO 204 to a frequency band matched with the input data rate. If the frequency difference between the input data signal D(in) and the clock signal output by the VCO 204 exceeds the detection range of the phase detection loop, the output of the PD 206 will control the VCO 204 to make a more fine adjustment, so that the VCO 204 designs the output clock phase to be locked on the phase of the input data signal. After phase locking, the CDR circuit outputs the recovered data signal Retimed Data through the PD 205.

[0061] However, Figure 2 In the CDR circuit shown, during the process in which the FD 201 transfers the frequency control to the PD 206, the frequency detection loop and the phase detection loop may interfere with each other, thereby causing an inaccurate phase locking, or even causing a ripple on the control signal of the VCO 204. Secondly, if the input data signal D(in) is composed of a random continuous same level (“0” or “1”), or the rising edge and the falling edge of the received signal are disturbed by external or internal noise during transmission, the FD 201 may suddenly fail, “confuse” the actual input data rate, and cause the CDR to lose lock, thereby affecting the operation of the system.

[0062] Figure 3 A structure diagram of a CDR circuit with a reference clock in the related art is shown as follows: Figure 3As shown, the CDR circuit needs an external reference clock F(ref) input, and adopts a coarse tracking loop and fine tracking loop scheme. The CDR circuit specifically comprises: a PFD (Phase Frequency Detector) 301, a CP2 302, a LF2 303, a VCO2 304, a frequency divider (÷M) 305, a LF 306, a PD 307, a CP1 308, a LF1 309, and a VCO1 310, wherein the PFD 301, the CP2 302, the LF2 303, the VCO2 304, and the frequency divider 305 constitute a frequency tracking loop, frequency locking is performed through the PFD 301, the PD 307, the CP1 308, the LF1 309, and the VCO1 310 constitute a phase tracking loop, and frequency locking is performed through the PD 307. The frequency tracking loop of the PFD 301 locks the output clock phase of the VCO2 304 to the same phase as the external reference clock F(ref), which is equivalent to a clock multiplication circuit, the VCO2 304 and the VCO1 310 have the same structure, and the presence of the frequency divider 305 in the frequency tracking loop can reduce the frequency requirement of the external reference clock F(ref). Since the VCO1 310 and the VCO2 304 are completely the same, the control voltage Coarse output from the LF 306 to the VCO2 304 can be used as the coarse control input of the VCO1 310, so that the oscillation frequency of the VCO1 310 is very close to or equal to the rate of the input data signal D(in). Therefore, the frequency tracking loop provides a coarse control signal for the VCO1 310. The phase tracking loop locks the phase of the clock signal Recoversd Clock1 output by the VCO1 310 to the phase of the input data signal D(in), thereby generating a fine control signal Fine for the VCO1 310. Compared with the frequency tracking loop, the gain of the phase tracking loop must be relatively low to maintain the fine control of the VCO1 310. After phase locking, the CDR circuit outputs a recovered data signal Retimed Data through the PD 307.

[0063] However, Figure 3 In the CDR circuit as shown, any mismatch between the VCO1 310 and the VCO2 304 can cause a difference in oscillation frequency. Secondly, the data rate of the high-speed serial link in the asynchronous operation mode usually allows a certain frequency offset between the transmission data rate and the local clock frequency of the receiver, thereby causing a frequency offset between the VCO1 310 and the VCO2 304, which can cause the VCO1 310 to deviate from the received data rate and be biased towards M*F(ref), which can cause a particularly serious problem when the spread spectrum clock (SSC) scheme needs to be adopted.

[0064] To solve the above problems, the application provides a CDR circuit based on MDLL (Multiplying delay-locked loop, multiplying delay-locked loop), the frequency locking and phase locking processes are simultaneously performed in the training stage, so that the problem of switching of two loops does not exist. Meanwhile, since the MDLL is a first-order system, complex loop stability analysis is not needed, the system design is simple, the entire CDR circuit has no stability problem, and a larger bandwidth can be achieved.

[0065] Figure 4 The structure schematic diagram of the CDR circuit provided by the embodiment of the application is shown, in the embodiment, the CDR circuit comprises a clock extraction unit 410, a voltage-controlled delay unit 420, a reference clock generator 430, an adjusting unit 440, a lock detection unit 450, a sampler 460, a first selection signal generation unit 470 and a second selection signal generation unit 480. Figure 4

[0066] The clock extraction unit 410 comprises a first input end, a second input end, a third input end and an output end, wherein the first input end of the clock extraction unit 410 receives an input data signal Data, the second input end is connected with one of the output ends of the reference clock generator 430 and receives a first reference clock signal clk1, the third input end receives a first selection window signal w_cdr, and the clock extraction unit 410 outputs a first clock signal ref_clk in the input data signal Data as an embedded clock according to the first selection window signal w_cdr from the output end, so as to serve as a reference clock signal of the next unit module, i.e., the voltage-controlled delay unit 420.

[0067] The voltage-controlled delay unit 420 comprises a first input end, a second input end, a third input end, a fourth input end and an output end, wherein the first input end of the voltage-controlled delay unit 420 is connected with the output end of the clock extraction unit 410 and receives the first clock signal ref_clk output by the clock extraction unit 410, the second input end of the voltage-controlled delay unit 420 is connected with the output end of the voltage-controlled delay unit 420 and receives a second clock signal clk0 output by the receiver, the third input end of the voltage-controlled delay unit 420 receives a second selection window signal w_clk, the fourth input end of the voltage-controlled delay unit 420 receives a control signal vctrl, and the voltage-controlled delay unit 420 is configured to output the second clock signal clk0 according to the second selection window signal w_clk and the control signal vctrl, wherein the frequency of the second clock signal w_clk is equal to n+1 times of the frequency of the first clock signal w_cdr, and n is an integer greater than 1.

[0068] ​The reference clock generator 430 includes one input terminal and multiple output terminals, wherein the input terminal of the reference clock generator 430 is connected with the output terminal of the voltage-controlled delay unit 420 to receive the second clock signal clk0 outputted by the voltage-controlled delay unit 420, and the reference clock generator 430 is configured to output a first reference clock signal clk1, a second reference clock signal clk2, a third reference clock signal clk3, a feedback clock signal fb_clk and a sampling clock signal s_clk to corresponding units / devices at the multiple output terminals respectively according to the second clock signal clk0.

[0069] The adjustment unit 440 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the adjustment unit 440 is connected with the output terminal of the clock extraction unit 410 to receive the first clock signal ref_clk, the second input terminal of the adjustment unit 440 is connected with one of the output terminals of the reference clock generator 430 to receive the feedback clock signal fb_clk, and the adjustment unit 440 is configured to output a control signal vctrl from the output terminal according to the frequency and phase difference of the first clock signal ref_clk and the feedback clock signal fb_clk.

[0070] The lock detection unit 450 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the lock detection unit 450 is connected with the output terminal of the clock extraction unit 410 to receive the first clock signal ref_clk, the second input terminal of the lock detection unit 450 is connected with one of the output terminals of the reference clock generator 430 to receive the feedback clock signal fb_clk, and the lock detection unit 450 is configured to detect the frequency and phase difference of the first clock signal ref_clk and the feedback clock signal fb_clk and output a lock indication signal Lock.

[0071] The sampler 460 includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the sampler 460 receives an input data signal Data, the second input terminal of the sampler 460 is connected with one of the output terminals of the reference clock generator 430 to receive the sampling clock signal s_clk, and the sampler 460 is configured to output data in the input data signal Data according to the sampling clock signal s_clk. In the embodiment, the sampling clock signal s_clk outputted by the reference clock generator 430 includes multiple clock signals with different phases.

[0072] The first selection signal generating unit 470 comprises a first input end, a second input end and an output end, wherein the first input end of the first selection signal generating unit 470 is connected with one of the output ends of the reference clock generator 430 to receive the second reference clock signal clk2, the second input end of the first selection signal generating unit 470 is connected with the output end of the lock detection unit 450 to receive the lock indication signal Lock, and the output end of the first selection signal generating unit 470 outputs the first selection window signal w_cdr to the third input end of the clock extracting unit 410. In the embodiment, the first selection window signal w_cdr is in an active state (e.g. high level state) in the first time when the input data signal Data outputs a transition edge or a rising edge, in other words, the first selection window signal w_cdr outputted by the first selection signal generating unit 470 is configured to ensure that the transition edge or the rising edge in the input data signal Data can be detected in its active period (e.g. high level period).

[0073] The second selection signal generating unit 480 comprises a first input end and an output end, wherein the first input end of the second selection signal generating unit 480 is connected with one of the output ends of the reference clock generator 430 to receive the third reference clock signal clk3, and the output end of the second selection signal generating unit 480 outputs the second selection window signal w_clk to the third input end of the voltage-controlled delay unit 420. In the embodiment, the second selection window signal w_clk is in an active state (e.g. high level state) in the active period (e.g. high level period) of the first selection window signal w_cdr, specifically, the second selection window signal w_clk is in an active state (e.g. high level state) in the second time when the first clock signal ref_clk outputs a rising edge, and the second time is less than or equal to the first time, in other words, the second selection window signal w_clk outputted by the second selection signal generating unit 480 is configured to ensure that the rising edge of the first clock signal ref_clk can be detected in its active period (e.g. high level period).

[0074] In the implementation, the first selection window signal w_cdr outputted by the first selection signal generating unit 470 is configured to ensure that the transition edge or the rising edge in the input data signal Data can be detected in its active period (e.g. high level period). Figure 4In the shown embodiment, the clock extraction unit 410 further comprises a flip-flop 411 and a first selector 412. The data input terminal of the flip-flop 411 is configured as a first input terminal of the clock extraction unit 410 and receives the input data signal Data, the clock input terminal of the flip-flop 411 is configured as a third input terminal of the clock extraction unit 410 and receives the first selection window signal w_cdr, and the flip-flop 411 is configured to output a rising edge of the input data signal Data according to the first selection window signal w_cdr. The first input terminal of the first selector 412 is connected with the output terminal of the flip-flop 411, the second input terminal of the first selector 412 is configured as a second input terminal of the clock extraction unit 410 and receives the first reference clock signal clk1, the selection control terminal of the first selector 412 is also configured as a third input terminal of the clock extraction unit 410 and receives the first selection window signal w_cdr, and the first selector 412 outputs a first clock signal ref_clk in the input data signal Data according to the first selection window signal w_cdr.

[0075] The voltage-controlled delay unit 420 further comprises a second selector 421 and a voltage-controlled delay line 422. The first input terminal of the second selector 421 is configured as a first input terminal of the voltage-controlled delay unit 420 and is connected with the output terminal of the first selector 412 to receive the first clock signal ref_clk, the second input terminal of the second selector 421 is configured as a second input terminal of the voltage-controlled delay unit 420, the selection control terminal of the second selector 421 is configured as a third input terminal of the voltage-controlled delay unit 420 and receives the second selection window signal w_clk, and the output terminal of the second selector 421 outputs a frequency multiplication signal ck_mux of the first clock signal ref_clk. The clock input terminal of the voltage-controlled delay line 422 is connected with the output terminal of the second selector 421, the control terminal of the voltage-controlled delay line 422 is configured as a fourth input terminal of the voltage-controlled delay unit 420 and receives the control signal vctrl, and the output terminal of the voltage-controlled delay line 422 is configured as an output terminal of the voltage-controlled delay unit 420 and is connected with the second input terminal of the second selector 421. The voltage-controlled delay line 422 is configured to perform delay processing on the frequency multiplication signal ck_mux according to the control signal vctrl and output the second clock signal clk0.

[0076] The adjusting unit 440 further comprises a frequency and phase discriminator (FPD) 441 and a control signal generating unit (for example, a CPLPF) 442. The first input end of the frequency and phase discriminator 441 is the first input end of the adjusting unit 440 and receives the first clock signal ref clk. The second input end of the frequency and phase discriminator 441 is the second input end of the adjusting unit 440 and receives the feedback clock signal fb clk. The output end of the frequency and phase discriminator 441 outputs a phase difference value signal of the first clock signal ref clk and the feedback clock signal fb clk. The input end of the control signal generating unit (CPLPF) 442 is connected with the output end of the frequency and phase discriminator 441. The output end of the control signal generating unit (CPLPF) 442 is the output end of the adjusting unit 440. The control signal generating unit (CPLPF) 442 is configured to output a control signal vctrl according to the phase difference value signal output by the frequency and phase discriminator 441.

[0077] Further, referring to Figure 5 , the control signal generating unit (CPLPF) 442 further comprises a first current source I1, a second current source I2 and a capacitor C1. The first current source I1 and the second current source I2 are connected in series between the power supply end Vcc and the reference ground in sequence. The first current source I1 is configured to provide a charging current. The second current source I2 is configured to provide a discharging current. The capacitor C1 is connected between the common connection node of the first current source I1 and the second current source I2 and the reference ground, receives the charging current and / or the discharging current, and generates the control signal vctrl. It can be understood that, in the control signal generating unit (CPLPF) 442, the first current source I1 and the second current source I2 are used as a charge pump, and the capacitor C1 is used as a loop filter, that is, in the CDR circuit 122 disclosed in the embodiment, the loop filter is implemented by only one capacitor C1. Therefore, the size of the capacitor can be reduced by reducing the current of the charge pump in proportion, so that the area of the CDR circuit is greatly reduced.

[0078] Optionally, in some embodiments, the input data signal Data has a clock indication bit between every n bits of data. The logic value of the clock indication bit is opposite to the logic value of the previous bit of the clock indication bit. Taking n=8 as an example, the input data signal Data is equivalent to using 8b / 9b encoding (b7, b6, b5, b4, b3, b2, b1, b0, ~b0). The last bit is the inverse of the previous bit, so that a fixed transition edge (including a rising edge or a falling edge) is formed between every 8 bits of data. At this time, the flip-flop 411 in the clock extraction unit 410 is selected as a double-edge flip-flop, so as to convert the transition edge in the input data signal Data into a rising edge by the double-edge flip-flop, as the reference clock of the next stage unit.

[0079] In some other embodiments, a fixed logic value 01 is inserted between every n-bit data in the input data signal Data. Taking n=8 as an example, a fixed rising edge can be formed between every 8-bit data in the input data signal Data by inserting a fixed 01 (b7, b6, b5, b4, b3, b2, b1, b0, 0, 1). At this time, the flip-flop 411 in the clock extraction unit 410 will be selected as a single-edge flip-flop, and no conversion from a transition edge to a rising edge is needed. The reference clock of the next stage can be directly selected by the first selection window signal w_cdr.

[0080] In combination with Figure 4 , Figure 5 and Figure 6 , the working principle of the CDR circuit 122 disclosed in the embodiments is as follows:

[0081] First, the flip-flop 411 receives a training sample of the input data signal Data (for example, including sequentially listed groups of bit data, each group of bit data is 111100001 in the case of using 8b / 9b encoding, or 1111000001 in the case of inserting a fixed 01), and the transition edge or rising edge between every n-bit data in the input data signal Data is pre-labeled in the training sample. During the valid period (for example, the high period) of the first selection window signal w_cdr, the flip-flop 411 directly or after conversion outputs the rising edge of the input data signal Data. At the same time, during the valid period (for example, the high period) of the first selection window signal w_cdr, the first selector 612 outputs the rising edge, and during the invalid period (for example, the low period) of the first selection window signal w_cdr, the first selector 612 outputs the first reference clock signal clk1. The first reference clock signal clk1 has the same timing waveform as the sequentially listed groups of n-bit bit data in the input data signal Data, thereby realizing the equivalent output of the first clock signal ref_clk in the input data signal Data, that is, the embedded clock.

[0082] Then, during the period when the second selection window signal w_clk is valid (e.g., high), the second selector 421 outputs the rising edge of the first clock signal ref_clk, and during the period when the second selection window signal w_clk is invalid (e.g., low), the second selector 421 and the delay control line 422 form a voltage-controlled oscillator structure, so that the second selector 421 can equivalently output a frequency multiplication signal ck_mux that is n+1 times the frequency of the first clock signal ref_clk, and the delay control line 422 outputs the second clock signal clk0 to the reference clock generator 430 after performing corresponding delay processing on the frequency multiplication signal ck_mux according to the received control signal vctrl, so that the reference clock generator 430 can generate the first reference clock signal clk1, the second reference clock signal clk2, the third reference clock signal clk3, the feedback clock signal fb_clk, and the sampling clock signal s_clk based on the second clock signal clk0.

[0083] Meanwhile, the FPD 441 compares the frequencies and phases of the first clock signal ref_clk and the feedback clock signal fb_clk, and controls the CPLPF 442 to generate a control signal vctrl that can represent the difference between the frequencies and phases of the first clock signal ref_clk and the feedback clock signal fb_clk, so as to adjust the delay duration of the delay control line 422 when performing delay processing on the frequency multiplication signal ck_mux, thereby adjusting the phase of the second clock signal clk0, and further adjusting the phases of the clock signals output by the reference clock generator 430. When the frequencies and phases of the first clock signal ref_clk and the feedback clock signal fb_clk are equal, the lock detection unit 450 outputs a high-level lock indication signal Lock to indicate that the CDR circuit is in a locked state at this time. In the locked state, the first selection window signal w_cdr output by the first selector 470 is fixed, and at this time the sending end can be notified to start sending the required input data signal Data. Meanwhile, in the locked state, the sampler 460 selects a clock signal with a suitable phase (e.g., a clock signal with a phase close to the middle position of the corresponding data bit) from the sampling clock signal s_clk output by the reference clock generator 430 to sample the data in the input data signal Data, and obtains the recovered data Retimed Data.

[0084] It should be noted that during normal operation of the CDR circuit 122, the lock indication signal Lock is continuously in an active state (e.g., high level), and if the lock indication signal Lock becomes invalid (e.g., low level) at a certain moment, the sending end needs to be notified to resend the training samples for retraining the CDR circuit 122.

[0085] It can be understood that the clock extraction unit, the voltage-controlled delay unit, the reference clock generator, the adjusting unit, the lock detection unit, the sampler, the first selection signal generation unit and the second selection signal generation unit and the connection relationship therebetween are used to construct a clock data recovery circuit (hereinafter also referred to as a CDR circuit) in the embodiments of the present application. Compared with the prior art, the present application provides a CDR circuit based on a first-order system of MDLL. The frequency locking and phase locking of the CDR circuit in the present application are performed simultaneously in the training stage, and there is no problem of switching between two loops. In addition, there is no need for complex loop stability analysis, the system design is simple, there is no stability problem in the entire CDR circuit, and a larger bandwidth can be achieved.

[0086] In addition, the loop filter of the MDLL has only one capacitor, so the size of the capacitor can be reduced by reducing the charge pump current in proportion, thereby greatly reducing the area of the CDR circuit.

[0087] Figure 7 A structural block diagram of a device including the CDR circuit provided by the embodiments of the present application is shown.

[0088] In the present embodiment, as shown in Figure 7 The device 700 can be a computing system including a display panel 720, and can be a fixed system (for example, a desktop computer, a server, a television or a billboard) or a mobile system (for example, a notebook computer, a mobile phone, a tablet computer or a wearable device) as non-limiting examples. For example, the device 700 can include a mainboard 710 and the display panel 720, and an input data signal Data can be transmitted from the mainboard 710 to the display panel 720 through a data line 730.

[0089] The mainboard 710 can include a processor 711, and the processor 711 can include a transmitting circuit (TX circuit) 712. The processor 711 can refer to a processing unit performing a computing operation, for example, a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). In some embodiments, the processor 711 can be a video graphics processor, for example, a graphics processing unit (GPU). The processor 711 can generate image data corresponding to an image output through a display 722 included in the display panel 720, and can provide the image data to the transmitting circuit 712.

[0090] The transmitting circuit 712 can output the input data signal Data to the receiving circuit (RX circuit) 723, enabling the receiving circuit 723 to perform clock data recovery operations. The display panel 720 may include a display controller 721 and a display 722. The display controller 721 can receive the input data signal Data from the motherboard 1300 and can perform clock data recovery operations using the input data signal Data. In some embodiments, the display controller 721 may provide display signals SIG for controlling pixels included in the display 722, and the display controller may be referred to as a display driver integrated circuit (DDI).

[0091] The display controller 721 may include a receiving circuit 723, which can receive an input data signal Data. The receiving circuit 723 may include a clock data recovery circuit (CDR circuit) 122 as disclosed in any embodiment of this application, and can generate a recovered clock signal and recovered data from the input data signal Data.

[0092] Display 722 may include any type of display, such as, as non-limiting examples, a liquid crystal display (LCD), a light-emitting diode (LED) display, an electroluminescent display (ELD), a cathode ray tube (CRT) display, a plasma display panel (PDP) display, or a liquid crystal on silicon (LCoS) display. Figure 7 In the illustration, device 700 is shown as including a display panel 720. However, in some embodiments, the device may include two or more display panels, i.e., two or more displays.

[0093] Figure 8 A structural block diagram of another device including the CDR circuit provided in the embodiments of this application is shown.

[0094] refer to Figure 8 In this embodiment, the device 800 may include a host 810 and a storage device 820. The storage device 820 may be referred to as a memory system or storage system, and may include a signal connector 821, a plurality of non-volatile memories 826_1 to 826_m, a buffer memory 822, and a controller 823, where m is an integer greater than 1. For example, the controller 823 may be referred to as a memory controller or storage controller.

[0095] The storage device 820 can transmit and receive a signal to and from the host 810 through a signal connector 821. The host 810 and the storage device 820 can communicate with each other through electrical and / or optical signals, and as non-limiting examples, the host 810 and the storage device 820 can communicate with each other through a Universal Flash Storage (UFS) interface, a Serial Advanced Technology Attachment (SATA) interface, a SATA Express (SATAe) interface, a Small Computer System Interface (SCSI) interface, a Serial Attached SCSI (SAS) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Non-Volatile Memory Express (NVMe) interface, an Advanced Host Controller Interface (AHCI) interface, or a combination of the above communication interfaces.

[0096] The controller 823 can control the plurality of non-volatile memories 826_1 to 826_m in response to a signal received from the host 810. The controller 823 can include a serial communication interface circuit 824 for transmitting and receiving data, and can include the clock data recovery circuit (CDR circuit) 122 disclosed in any of the embodiments of the present application for recovering a clock signal and data of a received serial data signal. The serial communication interface circuit 824 can provide a communication interface such as a UFS interface, a SATA interface, a SATAe interface, a SCSI interface, a SAS interface, a PCIe interface, an NVMe interface, an AHCI interface, or the like. The buffer memory 822 can operate for the storage device 820. On the other hand, the host 810 can include a serial communication interface circuit 811 for transmitting and receiving data, and the clock data recovery circuit (CDR circuit) 122 disclosed in any of the embodiments of the present application.

[0097] Each of the plurality of non-volatile memories 826_1 to 826_m can include a memory cell array, which can include memory blocks, each of which can be divided into pages, and each of which can include non-volatile memory cells, for example, at least one NAND flash memory cell.

[0098] Further, the embodiments of the present application also provide a chip in which the clock data recovery circuit (CDR circuit) 122 disclosed in any of the embodiments of the present application is integrated.

[0099] Finally, it should be noted that: obviously, the above embodiments are only examples for clearly illustrating the present application, and are not intended to limit the implementation modes. Based on the above description, other different forms of changes or variations can also be made by those of ordinary skill in the art. Here, it is not necessary and impossible to enumerate all the implementation modes. The obvious changes or variations derived therefrom are still within the scope of the present application.

Claims

1. A clock data recovery circuit, characterized by, The application relates to a clock extraction unit, a voltage-controlled delay unit, a reference clock generator, an adjustment unit, a lock detection unit, a sampler, a first selection signal generation unit and a second selection signal generation unit. The clock extraction unit receives an input data signal, a first selection window signal and a first reference clock signal, and outputs a first clock signal in the input data signal according to the first selection window signal. The voltage-controlled delay unit receives the first clock signal, a second selection window signal and a control signal, and outputs a second clock signal according to the second selection window signal, wherein the frequency of the second clock signal is (n+1) times the frequency of the first clock signal, and n is an integer greater than 1. The reference clock generator receives the second clock signal, and outputs the first reference clock signal, a second reference clock signal, a third reference clock signal, a feedback clock signal and a sampling clock signal. The adjustment unit receives the first clock signal and the feedback clock signal, and outputs the control signal according to the frequency and phase difference between the first clock signal and the feedback clock signal. The lock detection unit receives the first clock signal and the feedback clock signal, detects the frequency and phase difference between the first clock signal and the feedback clock signal, and outputs a lock indication signal. The sampler receives the input data signal and the sampling clock signal, and outputs data in the input data signal according to the sampling clock signal. The first selection signal generation unit receives the second reference clock signal and the lock indication signal, and outputs the first selection window signal. The second selection signal generation unit receives the third reference clock signal, and outputs the second selection window signal.

2. The clock data recovery circuit of claim 1, wherein, In the input data signal, a clock indication bit is arranged between every n data bits, and the logic value of the clock indication bit is opposite to that of the previous bit.

3. The clock data recovery circuit of claim 2, wherein, The flip-flop is a double-edge flip-flop.

4. The clock data recovery circuit of claim 1, wherein, In the input data signal, a fixed logic value 01 is inserted between every n data bits.

5. The clock data recovery circuit of claim 4, wherein, The flip-flop is a single-edge flip-flop.

6. The clock data recovery circuit of any of claims 1-4, wherein, The clock extraction unit comprises: a flip-flop, a data input end of the flip-flop receiving an input data signal, a clock input end of the flip-flop receiving a first selection window signal, the flip-flop being used for outputting a rising edge of the input data signal according to the first selection window signal; a first selector, a first input end of the first selector being connected with an output end of the flip-flop, a second input end of the first selector receiving the first reference clock signal, a selection control end of the first selector receiving the first selection window signal, the first selector being used for outputting a first clock signal in the input data signal according to the first selection window signal.

7. The clock data recovery circuit of any of claims 1-4, wherein, The voltage-controlled delay unit comprises: a second selector, a first input end of the second selector being connected with an output end of the first selector to receive the first clock signal, a selection control end of the second selector receiving a second selection window signal, and an output end of the second selector outputting a frequency multiplication signal of the first clock signal; a voltage-controlled delay line, a clock input end of the voltage-controlled delay line being connected with the output end of the second selector, a control end of the voltage-controlled delay line receiving the control signal, and an output end of the voltage-controlled delay line being connected with the second input end of the second selector, the voltage-controlled delay line being used for delaying the frequency multiplication signal according to the control signal, and outputting the second clock signal.

8. The clock data recovery circuit of any of claims 1-4, wherein, The adjustment unit comprises: a phase frequency detector, a first input end of the phase frequency detector receiving the first clock signal, a second input end of the phase frequency detector receiving the feedback clock signal, and an output end of the phase frequency detector outputting a phase difference value signal of the first clock signal and the feedback clock signal; a control signal generation unit, an input end of the control signal generation unit being connected with the output end of the phase frequency detector, and the CPLPF being configured to output the control signal according to the phase difference value signal.

9. The clock data recovery circuit of claim 8, wherein, The control signal generation unit comprises: a first current source, configured to provide a charging current; a second current source, configured to provide a discharging current; a capacitor, configured to receive the charging current and / or the discharging current, and generate the control signal.

10. An electronic device, comprising: comprises: a receiving circuit; and a transmitting circuit, configured to transmit data to the receiving circuit through a channel, wherein the receiving circuit comprises the clock data recovery circuit according to any one of claims 1-9.

11. A chip, characterized by The chip is integrated with the clock data recovery circuit according to any one of claims 1-9.

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