Beam former, ultrasonic chip and calibration method

Abstract

The invention relates to the technical field of chip calibration, in particular to a beam former, an ultrasonic chip and a calibration method.The beam former comprises a calibration circuit coupled with a sampling circuit, and the relation between a sampling capacitor Cs and a stray capacitor Cp is determined through the calibration circuit; therefore, the calibration of the relationship between the input signal and the output signal of the sampling circuit is realized, the influence of parasitic capacitance and the bandwidth of the output signal of the ultrasonic chip is avoided, the decoupling of the limited relationship between the parasitic capacitance and the bandwidth of the output signal of the ultrasonic chip is realized, and a switched capacitor circuit of the ultrasonic chip can adopt a smaller sampling capacitor; the layout is simpler, and meanwhile, enough bandwidth is achieved; the smaller sampling capacitor greatly reduces the area of the chip, and reduces the load of a pre-stage circuit, thereby reducing the power consumption of the chip.

Description

Technical Field

[0001] This invention relates to the field of chip calibration technology, and in particular to a beamformer, an ultrasonic chip, and a calibration method. Background Technology

[0002] Ultrasonic technology is widely used in medicine, the Internet of Things, industrial inspection, automation, and robotics. The ultrasonic chip is one of the core components, primarily responsible for signal generation and reception, signal processing, and data transmission and control. Switched-capacitor sampling circuits are widely used in ultrasonic chips, but their parasitic capacitance limits the bandwidth and accuracy of the output signal. This phenomenon is particularly pronounced in two-dimensional array ultrasonic chips employing subarray beamforming (microbeamforming, sub-aperture beamforming), as these chips have high signal quality requirements.

[0003] In order to reduce the impact of parasitic capacitance in the switched capacitor sampling circuit on the output signal of the ultrasonic chip, the usual approaches are (1) to increase the size of the sampling capacitor, but this increases the chip area and power consumption; (2) to optimize the layout and reduce the parasitic capacitance, but the parasitic capacitance still exists and cannot be completely eliminated, so the impact of parasitic capacitance cannot be completely solved; (3) to add a reset switch at the node with large parasitic capacitance, but this makes the digital control timing of the chip more complicated and requires the addition of more auxiliary circuits. Summary of the Invention

[0004] The purpose of this invention is to address the problems existing in the background art by proposing a beamformer, an ultrasonic chip, and a calibration method.

[0005] The beamformer provided by the present invention includes:

[0006] The sampling circuit includes at least a sampling capacitor C. s and parasitic capacitance C p ;

[0007] Switch S2 is connected to the parasitic capacitance C p Between the output port of the sampling circuit and the parasitic capacitance C, the parasitic capacitance C is switched. p Connection to the output port or calibration circuit;

[0008] The calibration circuit is connected to the switch S2 and the parasitic capacitance C. p Between, used for parasitic capacitance C p and sampling capacitor C s To charge or discharge;

[0009] The calibration circuit is used to determine the input signal V of the sampling circuit.in and output signal V out The associated calibration coefficient K is used to achieve the output signal V. out The calibration includes:

[0010] Power supply terminal V dd Used for parasitic capacitance C p and / or sampling capacitor C s To charge or discharge;

[0011] A comparator is used to compare voltage changes during charging or discharging and output a signal to control switch RD in the sampling circuit to close switch RD.

[0012] Switch S1 is used to control the parasitic capacitance C. p and / or sampling capacitor C s The connection to the non-inverting input of the comparator.

[0013] Preferably, the sampling circuit includes:

[0014] The input port is used to receive the input signal V. in ;

[0015] Output port, used to output signal V out ;

[0016] Switch WT and switch RD are connected in series between the input port and the output port;

[0017] Sampling capacitor C s The sampling capacitor C s One end is connected between switch WT and switch RD, and the other end is grounded;

[0018] Parasitic capacitance C p The sampling capacitor C p One end is connected between switch RD and the output port, and the other end is grounded.

[0019] Preferably, the inverting input terminal of the comparator is connected to the reference voltage terminal V. ref .

[0020] Preferably, it also includes a current source I. ref The current source I ref One end is connected between the switch RD and the switch S2, and the other end is connected to the power supply terminal V. dd .

[0021] Preferably, the calibration circuit further includes a switch UP and a switch DN;

[0022] The current source I refThe switch RD and the switch S2 are connected by the switch UP;

[0023] One end of the switch DN is connected between the switch RD and the switch S2, and the other end is grounded.

[0024] Preferably, one end of the switch S1 is connected between the switch RD and the switch S2, and the other end is connected to the non-inverting input of the comparator.

[0025] Preferably, the calibration circuit further includes capacitors C1 and C2;

[0026] One end of capacitor C1 is connected to capacitor C p One end of the switch RD is connected to the non-inverting input of the comparator, and the other end is connected to the non-inverting input of the comparator.

[0027] The switch S1 is connected in parallel across the two ends of the capacitor C1;

[0028] One end of the switch S2 is connected to the non-inverting input of the comparator, and the other end is connected to the output of the comparator through the capacitor C1.

[0029] Preferably, it further includes a digital counter; the output of the comparator is connected to an output port D through the digital counter. out ;

[0030] The output port D out， Used to output the RD switch signal to control the RD switch to close.

[0031] Preferably, the sampling circuit includes:

[0032] The input port is used to receive the input signal V. in <n-1:0>;

[0033] Output port, output signal V out ;

[0034] Multiple switch groups WT and RD It is connected in series between the input port and the output port;

[0035] Multiple sampling capacitors C u One end is connected to the corresponding switch group WT and RD Between the two ends, one end is grounded or connected to the power supply terminal V via a digitally controlled switch SW. dd , used to sample the input signal;

[0036] Parasitic capacitance C p One end is connected to switch RD and output V out Between the two ends, the other end is grounded;

[0037] Parasitic capacitance C p The sampling capacitor C p One end is connected between switch RD and the output port, and the other end is grounded;

[0038] N sets of sampling capacitors C u With switch group WT and RD The connection structure is connected in parallel;

[0039] Where N is the number of sub-aperture channels, and M is the unit sampling capacitance C per channel. u Quantity, V in and V out These are the input and output of the switched-capacitor sampling circuit, C. p This is a parasitic capacitance.

[0040] Preferably, the time-domain formula of the sampling circuit is:

[0041] V out [n] = (1 + K)V in [n]-KV in [n-α]

[0042] Among them, V in [n] represents the voltage input time series, V out [n] represents the voltage output time series; n is the nth sampling time; α is the ratio of the ADC sampling frequency to the sampling frequency of the switched capacitor sampling circuit, specifically:

[0043]

[0044] Among them, f sadc f is the ADC sampling frequency. ssc This refers to the sampling frequency of the switched capacitor sampling circuit.

[0045] K is the calibration coefficient, and the formula is as follows:

[0046]

[0047] The ultrasonic chip provided according to the present invention includes the aforementioned beamformer.

[0048] The calibration method for an ultrasonic chip according to the present invention includes the following steps:

[0049] Step S1: Model the switched capacitor sampling circuit and determine the input signal V. in and output signal V out The relationship associated with the coefficient K;

[0050] Step S2: Control switch S2 is opened and switch S1 is closed, so that the calibration circuit can adjust the parasitic capacitance C. p and / or sampling capacitor C s Perform charging or discharging to determine the coefficient K;

[0051] Step S3: Determine the output signal V based on the coefficient K. out .

[0052] Compared with the prior art, the present invention has the following beneficial technical effects:

[0053] This invention includes a calibration circuit coupled to the sampling circuit, through which the sampling capacitance C is accurately determined. s and parasitic capacitance C p The relationship between the input and output signals of the sampling circuit is calibrated to avoid the influence of parasitic capacitance and the bandwidth of the ultrasonic chip's output signal. This decouples the limiting relationship between parasitic capacitance and the bandwidth of the ultrasonic chip's output signal, allowing the switched capacitor circuit of the ultrasonic chip to use a smaller sampling capacitor and a simpler layout while achieving sufficient bandwidth. The smaller sampling capacitor greatly reduces the chip area and the load on the front-end circuit, thereby reducing the chip's power consumption. In addition, the proposed method is simple and requires very little computation, so it can work in almost all digital circuits, has the advantages of wide applicability and flexible deployment, and thus improves the quality of the ultrasonic chip's output signal at a very low cost. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0055] Figure 1 This is an equivalent circuit diagram of a common switched-capacitor sampling circuit in an embodiment of the present invention;

[0056] Figure 2 This is an equivalent circuit diagram of the switched-capacitor sampling circuit of the two-dimensional array ultrasonic chip using sub-aperture beamforming in an embodiment of the present invention.

[0057] Figure 3 This is a diagram showing the location of the calibration method in the ultrasonic signal link of the simulated output ultrasonic chip in this embodiment of the invention;

[0058] Figure 4 This is one of the location diagrams of the calibration method in the ultrasonic signal link in the digital output ultrasonic chip of the present invention;

[0059] Figure 5 This is the second diagram showing the location of the calibration method in the ultrasonic signal link of the digital output ultrasonic chip in this embodiment of the invention;

[0060] Figure 6 This is a circuit diagram used to determine the calibration coefficient K of a common switched capacitor sampling circuit in an embodiment of the present invention;

[0061] Figure 7 As described in the embodiments of the present invention Figure 6 The timing diagram;

[0062] Figure 8 This is a circuit diagram used to determine the calibration coefficient K of a common switched capacitor sampling circuit in an embodiment of the present invention;

[0063] Figure 9 This is a circuit diagram of the calibration coefficient K of the switched-capacitor sampling circuit of the two-dimensional array ultrasonic chip using sub-aperture beamforming in an embodiment of the present invention.

[0064] Figure 10 This is a circuit diagram of the calibration coefficient K of the switched-capacitor sampling circuit of the two-dimensional array ultrasonic chip using sub-aperture beamforming in an embodiment of the present invention.

[0065] Figure 11 This is a circuit diagram of the calibration coefficient K of the switched-capacitor sampling circuit of the two-dimensional array ultrasonic chip using sub-aperture beamforming in an embodiment of the present invention.

[0066] Figure 12 This is a circuit diagram of the calibration coefficient K of the switched-capacitor sampling circuit of the two-dimensional array ultrasonic chip using sub-aperture beamforming in an embodiment of the present invention.

[0067] Figure 13 This is a timing diagram of the switched-capacitor sampling circuit of a two-dimensional array ultrasonic chip using sub-aperture beamforming in an embodiment of the present invention. Detailed Implementation

[0068] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0069] like Figure 6 As shown, in an embodiment of the present invention, the beamformer provided by the present invention includes:

[0070] The sampling circuit includes at least a sampling capacitor C. s and parasitic capacitance C p ;

[0071] Switch S2 is connected to the parasitic capacitance C p Between the output port of the sampling circuit and the parasitic capacitance C, the parasitic capacitance C is switched. p Connection to the output port or calibration circuit;

[0072] The calibration circuit is connected to the switch S2 and the parasitic capacitance C. p Between, used for parasitic capacitance C p and sampling capacitor C s To charge or discharge;

[0073] The calibration circuit includes:

[0074] Power supply terminal V dd Used for parasitic capacitance C p and / or sampling capacitor C s To charge or discharge;

[0075] A comparator is used to compare voltage changes during charging or discharging and output a signal to control switch RD in the sampling circuit to close switch RD.

[0076] Switch S1 is used to control the parasitic capacitance C. p and / or sampling capacitor C s The connection to the non-inverting input of the comparator.

[0077] like Figure 1 As shown, one type of sampling circuit includes:

[0078] The input port is used to receive the input signal V. in ;

[0079] Output port, used to output signal V out ;

[0080] Switch WT and switch RD are connected in series between the input port and the output port;

[0081] Sampling capacitor C s The sampling capacitor C s One end is connected between switch WT and switch RD, and the other end is grounded;

[0082] Parasitic capacitance C p The sampling capacitor C p One end is connected between switch RD and the output port, and the other end is grounded.

[0083] The input V of the sampling circuit in The output V is after connecting the series switches WT and RD. out Sampling capacitor C s One end is connected between switches WT and RD, and the other end is grounded; parasitic capacitance C p One end is connected between switch RD and output Vout, and the other end is grounded;

[0084] Among them, V in and V out These are the input and output signals of the switched capacitor sampling circuit, respectively. WT and RD are digital signal switches that control the sampling capacitor C. s Write and read.

[0085] like Figure 2 As shown, in an optional embodiment of the present invention, the sampling circuit employs a two-dimensional array ultrasonic chip switched-capacitor sampling circuit with sub-aperture beamforming, using, as... Figure 2 The circuit shown is modeled, including:

[0086] The input port is used to receive the input signal V. in <n-1:0>;

[0087] Output port, output signal V out ;

[0088] Multiple switch groups WT and RD It is connected in series between the input port and the output port;

[0089] Multiple sampling capacitors C u One end is connected to the corresponding switch group WT and RD Between the two ends, one end is grounded or connected to the power supply terminal V via a digitally controlled switch SW. dd , used to sample the input signal;

[0090] Parasitic capacitance C p One end is connected to switch RD and output V out Between the two ends, the other end is grounded;

[0091] Parasitic capacitance C p The sampling capacitor C p One end is connected between switch RD and the output port, and the other end is grounded;

[0092] N sets of sampling capacitors C u With switch group WT and RD The connection structure is connected in parallel;

[0093] Where N is the number of sub-aperture channels, and M is the unit sampling capacitance C per channel. u Quantity, V in and V out These are the input and output of the switched-capacitor sampling circuit, C. p This is a parasitic capacitance.

[0094] The input port is connected in series with multiple digital signal switch groups WT and RD ((i=0,1,…,M-1)) is then connected to the output port; digital signal switch WT 、RD Control the write and read operations of the corresponding sampling capacitor Cu respectively;

[0095] This two-dimensional array ultrasonic chip with sub-aperture beamforming employs a switched-capacitor sampling circuit to achieve sampling of multiple input signals V. in <n-1:0>Sampling and output.

[0096] like Figure 6 As shown, the calibration circuit further includes:

[0097] Current source I ref The current source I ref One end is connected between the switch RD and the switch S2, and the other end is connected to the power supply terminal V. dd .

[0098] The current source I ref The switch RD and the switch S2 are connected by the switch UP;

[0099] One end of the switch DN is connected between the switch RD and the switch S2, and the other end is grounded.

[0100] Digital counter; the output of the comparator is connected to an output port D through the digital counter. out ;

[0101] The output port D out It is used to output the RD switch signal to control the RD switch to close.

[0102] The inverting input of the comparator is connected to the reference voltage terminal V. ref .

[0103] When using the beamformer provided by this invention to calibrate the sampling circuit, its time-domain formula is as follows:

[0104] V out [n] = (1 + K)V in [n]-KV in [n-α]

[0105] The frequency domain formula is generated by performing a z-transform on the time-domain formula:

[0106] H comp = (1+K)-Kz -α

[0107] Where V in [n] represents the voltage input time series, V out [n] represents the voltage output time series; n is the nth sampling time; α is the ratio of the ADC sampling frequency to the sampling frequency of the switched capacitor sampling circuit, as shown in the following formula:

[0108]

[0109] Among them, f sadc f is the ADC sampling frequency. ssc This is the sampling frequency of the switched capacitor sampling circuit.

[0110] K is the calibration coefficient, and the formula is as follows:

[0111]

[0112] The calibration of the switched-capacitor sampling circuit of the two-dimensional array ultrasonic chip using sub-aperture beamforming is as follows:

[0113] V out [n] = (1 + K)V in [n]-KV in [n-α]

[0114] The formula corresponding to the frequency domain is:

[0115] H comp = (1+K)-Kz -α

[0116] Where V in [n] represents the voltage input time series, V out [n] represents the voltage output time series; n is the nth sampling time; α is the ratio of the ADC sampling frequency to the sampling frequency of the switched capacitor sampling circuit, as shown in the following formula:

[0117]

[0118] K is the calibration coefficient, and the formula is as follows:

[0119]

[0120] The transfer function for a conventional switched-capacitor sampling circuit that does not employ the calibration circuit of this embodiment is:

[0121]

[0122] The transfer function of the switched-capacitor sampling circuit of the two-dimensional array ultrasonic chip using sub-aperture beamforming is:

[0123]

[0124] In this embodiment of the invention, the transfer function of the conventional switched-capacitor sampling circuit is:

[0125] H 1comp =H1·H comp =1, where α equals 1

[0126] The transfer function for the switched-capacitor sampling circuit of a two-dimensional array ultrasonic chip employing sub-aperture beamforming is:

[0127] H 2comp =H2·H comp =1, where α equals 1

[0128] In comparison, the transfer functions H1 and H2 of the switching circuit in the prior art are both less than 1 when the frequency is not 0, resulting in a decrease in the gain and bandwidth of the switching circuit. However, in the embodiment of this invention, H... 1comp H 2comp All values ​​are equal to 1, with no gain or bandwidth loss.

[0129] like Figure 6 As shown, when using the beamformer provided by this invention to determine the calibration coefficient K of a conventional switched-capacitor sampling circuit, the specific steps are as follows:

[0130] When the chip is operating normally, switch S2 is closed and S1 is open. When the chip is used to determine the calibration coefficient K, switch S2 is open, S1 is closed, switch UP is closed, and current source I... ref The parasitic capacitance C will be checked first. p To begin charging, after switch UP is turned off, switch DN is opened, and current source I... ref For parasitic capacitance C p During the discharge process, the comparator's output D... compout It will be higher or lower than V ref The voltage flips. Then the read control signal RD is set to 1, thus closing the read switch RD, and the switch UP closes the current source I. ref This will affect the sampling capacitor C s and parasitic capacitance C p To begin charging, after switch UP is turned off, switch DN is opened, and current source I... ref For sampling capacitor C s and parasitic capacitance C p Discharge, repeat the aforementioned measurement procedure, and the timing diagram is as follows. Figure 7 As shown. Given current source I... ref The magnitude of the calibration coefficient K can be calculated by measuring the rise and fall times of two capacitor charge and discharge cycles.

[0131]

[0132] like Figure 8 As shown, the comparator can reuse the amplifier in the chip's signal chain. Figure 8 Switch configuration and timing in Figure 7 In this case, the calibration circuit also includes capacitors C1 and C2.

[0133] One end of capacitor C1 is connected to capacitor C p One end of the switch RD is connected to the non-inverting input of the comparator, and the other end is connected to the non-inverting input of the comparator.

[0134] The switch S1 is connected in parallel across the two ends of the capacitor C1;

[0135] One end of the switch S2 is connected to the non-inverting input of the comparator, and the other end is connected to the output of the comparator through the capacitor C1.

[0136] like Figure 8 As shown, when the chip is working normally, switch S2 is closed and S1 is open. When the chip is used to determine the calibration coefficient K, switch S2 is open, S1 is closed, switch UP is closed, and current source I... ref The parasitic capacitance C will be checked first. p To begin charging, after switch UP is turned off, switch DN is opened, and current source I... ref For parasitic capacitance C p During the discharge process, the comparator's output D... compout It will be higher or lower than V ref The voltage flips. Then the read control signal RD is set to 1, thus closing the read switch RD, and the switch UP closes the current source I. ref This will affect the sampling capacitor C s and parasitic capacitance C p To begin charging, after switch UP is turned off, switch DN is opened, and current source I... ref For sampling capacitor C s Discharge the parasitic capacitance C, repeat the aforementioned measurement procedure, and the timing diagram is as follows. Figure 7 As shown. Figure 9 The diagram shown illustrates the circuit used to determine the calibration coefficient K of a switched-capacitor sampling circuit for a two-dimensional array ultrasonic chip employing sub-aperture beamforming. The measurement scheme and timing are essentially the same as those for determining the calibration coefficient K of a conventional switched-capacitor sampling circuit. The difference lies in that during the second charge / discharge cycle, only one read control signal is set to 1, for example, RD. <0> .

[0137] like Figure 10 As shown, Figure 9 The comparators in the chip can also reuse amplifiers from the chip's signal chain. Figure 10 Switch configuration and timing in Figure 7 Totally consistent.

[0138] like Figure 11 As shown, when multiple sampling capacitors C u One end is connected to the corresponding switch group WT and RD Between the two ends, one end is grounded or connected to the power supply terminal V via a digitally controlled switch SW. dd When the chip is operating normally, switch S2 is closed and S1 is open. When the chip is used to determine the calibration coefficient K, switch S2 is open and S1 is closed, and the unit sampling capacitance C... u The lower plate voltage level is controlled by the digital signal switch SW. During the measurement process, all WT signals are set to 0, and the RD signal is set to an arbitrary unique thermometer code. When any switch SW is closed, switch RD closes, and SW gradually increases according to the thermometer code, controlling a corresponding switch SW to close each time. At a certain moment, the comparator output flips, and the back-end digital processing circuit records the SW value corresponding to the flipping moment. toggle ,like Figure 10 According to SW toggle Unit sampling capacitance C u Number of sub-aperture channels N, power supply voltage V dd and reference voltage V ref The calibration coefficient K can be calculated:

[0139]

[0140] like Figure 12 As shown, Figure 11 The comparators in the chip can also reuse amplifiers from the chip's signal chain. Figure 12 The switch configuration and timing are as follows: Figure 13 As shown.

[0141] In an embodiment of the present invention, the ultrasonic chip proposed in the present invention includes the aforementioned beamformer.

[0142] In an optional embodiment, such as Figure 3 As shown, for an analog output ultrasound chip, the calibration circuit is implemented after the off-chip ADC of the ultrasound chip.

[0143] In an alternative embodiment, for a digitally output ultrasonic chip, such as Figure 4 As shown, the calibration circuit is implemented outside the ultrasonic chip, as follows: Figure 5 As shown, the calibration circuit is implemented on the ultrasonic chip.

[0144] In this embodiment of the invention, the calibration method for the ultrasonic chip provided by the present invention includes the following steps:

[0145] Step S1: Model the switched capacitor sampling circuit and determine the input signal V. in and output signal V out The relationship associated with the coefficient K;

[0146] Step S2: Control switch S2 is opened and switch S1 is closed, so that the calibration circuit can adjust the parasitic capacitance C. p and / or sampling capacitor C s Perform charging or discharging to determine the coefficient K;

[0147] Step S3: Determine the output signal V based on the coefficient K. out .

[0148] When the calibration method for the ultrasonic chip provided by this invention is applied to the switched capacitor sampling circuit of a two-dimensional array ultrasonic chip using sub-aperture beamforming, the limiting relationship between parasitic capacitance and the bandwidth of the ultrasonic chip output signal can be decoupled.

[0149] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0150] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A beamformer, characterized in that, include: The sampling circuit includes at least a sampling capacitor C. s and parasitic capacitance C p ; Switch S2 is connected to the parasitic capacitance C p Between the output port of the sampling circuit and the parasitic capacitance C, the parasitic capacitance C is switched. p Connection to the output port or calibration circuit; The calibration circuit is connected to the switch S2 and the parasitic capacitance C. p Between, used for parasitic capacitance C p and sampling capacitor C s To charge or discharge; The calibration circuit is used to determine the input signal V of the sampling circuit. in and output signal V out The associated calibration coefficient K is used to achieve the output signal V. out The calibration includes: Power supply terminal V dd Used for parasitic capacitance C p and / or sampling capacitor C s To charge or discharge; A comparator is used to compare voltage changes during charging or discharging and output a signal to control switch RD in the sampling circuit to close switch RD. Switch S1 is used to control the parasitic capacitance C. p and / or sampling capacitor C s The connection to the non-inverting input of the comparator.

2. The beamformer according to claim 1, characterized in that, The sampling circuit includes: The input port is used to receive the input signal V. in ; Output port, used to output signal V out ; Switch WT and switch RD are connected in series between the input port and the output port; Sampling capacitor C s The sampling capacitor C s One end is connected between switch WT and switch RD, and the other end is grounded; Parasitic capacitance C p The sampling capacitor C p One end is connected between switch RD and the output port, and the other end is grounded.

3. The beamformer according to claim 2, characterized in that, The inverting input of the comparator is connected to the reference voltage terminal V. ref .

4. The beamformer according to claim 2, characterized in that, It also includes current source I ref The current source I ref One end is connected between the switch RD and the switch S2, and the other end is connected to the power supply terminal V. dd .

5. The beamformer according to claim 4, characterized in that, The calibration circuit also includes a switch UP and a switch DN; The current source I ref The switch RD and the switch S2 are connected by the switch UP; One end of the switch DN is connected between the switch RD and the switch S2, and the other end is grounded.

6. The beamformer according to claim 1, characterized in that, One end of the switch S1 is connected between the switch RD and the switch S2, and the other end is connected to the non-inverting input of the comparator.

7. The beamformer according to claim 1, characterized in that, The calibration circuit also includes capacitors C1 and C2; One end of capacitor C1 is connected to capacitor C p One end of the switch RD is connected to the non-inverting input of the comparator, and the other end is connected to the non-inverting input of the comparator. The switch S1 is connected in parallel across the two ends of the capacitor C1; One end of the switch S2 is connected to the non-inverting input of the comparator, and the other end is connected to the output of the comparator through the capacitor C1.

8. The beamformer according to claim 1, characterized in that, It also includes a digital counter; the output of the comparator is connected to an output port D through the digital counter. out ; The output port D out， Used to output the RD switch signal to control the RD switch to close.

9. The beamformer according to claim 1, characterized in that, The sampling circuit includes: The input port is used to receive the input signal V. in <n-1:0> ；< / n-1:0> Output port, output signal V out ; Multiple switch groups WT and RD It is connected in series between the input port and the output port; Multiple sampling capacitors C u One end is connected to the corresponding switch group WT and RD Between the two ends, one end is grounded or connected to the power supply terminal V via a digitally controlled switch SW. dd , used to sample the input signal; Parasitic capacitance C p One end is connected to switch RD and output V out Between the two ends, the other end is grounded; Parasitic capacitance C p The sampling capacitor C p One end is connected between switch RD and the output port, and the other end is grounded; N sets of sampling capacitors C u With switch group WT and RD The connection structure is connected in parallel; Where N is the number of sub-aperture channels, and M is the unit sampling capacitance C per channel. u Quantity, V in and V out These are the input and output of the switched-capacitor sampling circuit, C. p This is a parasitic capacitance.

10. The beamformer according to claim 1, characterized in that, The time-domain formula for the sampling circuit is: V out [n]=(1+K)V in [n]-KV in [n-α] Among them, V in [n] represents the voltage input time series, V out [n] represents the voltage output time series; n is the nth sampling time; α is the ratio of the ADC sampling frequency to the sampling frequency of the switched capacitor sampling circuit, specifically: Among them, f sadc f is the ADC sampling frequency. ssc This refers to the sampling frequency of the switched capacitor sampling circuit. K is the calibration coefficient, and the formula is as follows:

11. An ultrasonic chip, characterized in that, Includes the beamformer according to any one of claims 1 to 10.

12. A calibration method for the ultrasonic chip of claim 11, characterized in that, Includes the following steps: Step S1: Model the switched capacitor sampling circuit and determine the input signal V. in and output signal V out The relationship associated with the coefficient K; Step S2: Control switch S2 is opened and switch S1 is closed, so that the calibration circuit can adjust the parasitic capacitance C. p and / or sampling capacitor C s Perform charging or discharging to determine the coefficient K; Step S3: Determine the output signal V based on the coefficient K. out .

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