Modular multiplication chip and digital cryptographic system

Abstract

The application provides a modular multiplication chip and a digital password system, and belongs to the technical field of information security. The modular multiplication chip receives two multipliers to be operated sent by a previous stage circuit through a decomposition multiplier module; each decomposition and recombination unit decomposes and recombines the two input multipliers to obtain multiple groups of output data and respectively outputs the output data to one decomposition and recombination unit in a next stage decomposition and recombination submodule; each recombination operation unit is used for bit decomposition and cross multiplication of the two multipliers from the corresponding decomposition and recombination unit in the last stage decomposition and recombination submodule to obtain a multiplication result; a recombination module recombines the multiplication result and inputs a recombination result into a fast modulo reduction module to perform a modulo operation, so as to obtain a final modular multiplication result. The application can improve the modular multiplication operation efficiency, reduce the number of occupied digital signal processing multipliers, and further improve the hardware resource utilization rate of the digital password system.

Description

Technical Field

[0001] This application relates to the field of information security technology, and more specifically, to a modular multiplication chip and a digital cryptography system. Background Technology

[0002] In the digital age, information security has become a crucial pillar of economic and social development. The SM2 asymmetric cryptography algorithm, as an important component of modern cryptography, not only possesses encryption technology but also provides security services such as digital signatures and signature authentication, further enhancing the information security protection capabilities of cryptographic systems. Compared to the traditional RSA asymmetric encryption algorithm, the SM2 asymmetric cryptography algorithm has a shorter key length and higher computational efficiency at the same security strength, making it more suitable for resource-constrained scenarios such as mobile internet and the Internet of Things. However, despite its high computational efficiency, the SM2 asymmetric cryptography algorithm is a computationally intensive application, leading to drawbacks such as insufficient efficiency and vulnerability to attacks in software implementation. To address this, hardware acceleration is often employed to improve the computational efficiency of the SM2 asymmetric cryptography algorithm, thereby overcoming the limitations of software computation efficiency. For example, Field Programmable Gate Array (FPGA) chips are used to enhance the computational efficiency of the SM2 asymmetric cryptography algorithm.

[0003] In the SM2 asymmetric cryptography algorithm, modular multiplication over finite fields is crucial, accounting for approximately 90% of the total computation time. The efficiency of modular multiplication directly impacts the overall computational efficiency of the SM2 algorithm. Therefore, improving the efficiency of modular multiplication is a problem that needs to be addressed. Summary of the Invention

[0004] The purpose of this application is to provide a modular multiplication chip and a digital cryptography system that can improve the efficiency of modular multiplication operations while reducing the number of digital signal processing multipliers, thereby improving the hardware resource utilization of the digital cryptography system.

[0005] The embodiments of this application are implemented as follows:

[0006] A first aspect of this application provides a modular multiplication chip, which includes: a decomposition multiplier module, a recombination module, and a fast modular reduction module;

[0007] The first input terminal of the decomposition multiplier module is connected to the preceding circuit to receive the two multipliers to be operated on. The decomposition multiplier module includes a series of decomposition and recombination sub-modules and a recombination operation sub-module connected in sequence. Each decomposition and recombination sub-module includes at least one decomposition and recombination unit. The recombination operation sub-module includes multiple recombination operation units. The output terminal of each decomposition and recombination unit in each decomposition and recombination sub-module is connected to the input terminal of multiple decomposition and recombination units in the next decomposition and recombination sub-module. The output terminal of each decomposition and recombination unit in the last decomposition and recombination sub-module is correspondingly connected to the input terminal of one recombination operation unit in the recombination operation sub-module.

[0008] Each decomposition and recombination unit is used to decompose and recombine the two input multipliers to obtain multiple sets of output data, and output each set of output data to a decomposition and recombination unit in the next level decomposition and recombination submodule. Each set of output data includes the two split multipliers.

[0009] Each recombination operation unit is used to perform bitwise decomposition and cross-multiplication on the two multipliers from the corresponding decomposition and recombination unit in the last-level decomposition and recombination submodule to obtain the multiplication result;

[0010] The input terminal of the recombination module is connected to the output terminal of each recombination operation unit, the output terminal of the recombination module is connected to the input terminal of the fast modulo reduction module, and the output terminal of the fast modulo reduction module is connected to the subsequent circuit.

[0011] As one possible implementation, the above-mentioned multi-level decomposition and recombination submodule includes: a first-level decomposition and recombination submodule and a second-level decomposition and recombination submodule;

[0012] The first-level decomposition and recombination submodule includes one first-level decomposition and recombination unit, and the output of the first-level decomposition and recombination unit is connected to the inputs of M second-level decomposition and recombination units in the second-level decomposition and recombination submodule.

[0013] The output of each secondary decomposition and recombination unit is connected to the input of the corresponding recombination operation unit in the recombination operation submodule.

[0014] As one possible implementation, the aforementioned first-level decomposition and recombination unit is specifically used for:

[0015] Receive the first and second multipliers from the preceding circuitry;

[0016] The first multiplier and the second multiplier are decomposed into multiple first-level data according to the first preset bit width;

[0017] Based on multiple primary data, multiple sets of primary multipliers are obtained by recombination, and each set of primary multipliers includes two multipliers;

[0018] Input the first-level multipliers of each group into the respective second-level decomposition and recombination units.

[0019] As one possible implementation, each secondary decomposition and recombination unit is specifically used for:

[0020] Receive the third and fourth multipliers from the first-level decomposition and recombination unit;

[0021] The third and fourth multipliers are decomposed into multiple second-level data according to the second preset bit width;

[0022] Based on multiple secondary data, multiple sets of secondary multipliers are obtained by recombination, and each set of secondary multipliers includes two multipliers;

[0023] Each group of second-order multipliers is input into the corresponding recombination operation unit.

[0024] As one possible implementation, each recombination operation unit includes: a dynamic bit-width recombination subunit and an operation subunit;

[0025] The dynamic bit-width recombination subunit is used to perform bit-by-bit decomposition on the received fifth and sixth multipliers to obtain multiple first and third-level data corresponding to the fifth multiplier and multiple second and third-level data corresponding to the sixth multiplier;

[0026] The operation subunit is used to cross-multiply multiple first- and third-level data with multiple second- and third-level data to obtain the multiplication result.

[0027] As one possible implementation, the above-mentioned arithmetic subunit includes: multiple digital signal processing multipliers;

[0028] Each digital signal processing multiplier is used to acquire a first-level third-level data and a second-level third-level data, and to perform multiplication operations on the first-level third-level data and the second-level third-level data to obtain the multiplication result corresponding to the digital signal processing multiplier.

[0029] As one possible implementation, the above-mentioned reorganization module is used for:

[0030] The multiplication results from all digital signal processing multipliers in all recombination units are shifted and added / subtracted to obtain the recombination result.

[0031] As one possible implementation, the above-mentioned fast modulo reduction module includes: a decomposition unit, a recombination unit, and an arithmetic unit. The arithmetic unit includes: multiple carry-retaining adders and multiple full adders.

[0032] The input of the decomposition unit is connected to the output of the recombination module, the output of the decomposition unit is connected to the input of the recombination unit, and the output of the recombination unit is connected to the input of the arithmetic unit.

[0033] The decomposition unit receives the recombination result from the recombination module and decomposes the recombination result according to the third preset bit width to obtain multiple decomposed data.

[0034] The recombination unit recombines multiple decomposed data according to a preset format to obtain multiple data sequences;

[0035] The arithmetic unit performs modulo operations on each data sequence through multiple carry-holding adders and multiple full adders to obtain the final modular multiplication result.

[0036] As one possible implementation, the aforementioned modular multiplication chip also includes: a control module;

[0037] The output of the control module is connected to the second input of the decomposer multiplier module. The control module is used to send control signals to the decomposer multiplier module. The decomposer multiplier module responds to the control signals to perform modular multiplication. The control signals include at least one of the following: modular multiplication start signal, clock signal, reset signal, and modular multiplication end signal.

[0038] A second aspect of this application provides a digital cryptography system, which includes a main controller, an SM2 module, an SM3 module, and an SM4 module, wherein the SM2 module includes the modular multiplication chip described in the first aspect.

[0039] The beneficial effects of the embodiments of this application include:

[0040] This application provides a modular multiplication chip, which includes a decomposition multiplier module, a recombination module, and a fast modular reduction module. The decomposition multiplier module includes a series of multi-level decomposition and recombination sub-modules and a recombination operation sub-module connected in sequence. Each level of the decomposition and recombination sub-module includes at least one decomposition and recombination unit, and each recombination operation sub-module includes multiple recombination operation units. Each decomposition and recombination unit in each level of the decomposition and recombination sub-module corresponds to multiple decomposition and recombination units in the next level of the decomposition and recombination sub-module. Each decomposition and recombination unit in the last level of the decomposition and recombination sub-module corresponds to one recombination operation unit in the recombination operation sub-module. The multi-level decomposition and recombination sub-module decomposes and recombines the large-bit-width input multiplier data based on the divide-and-conquer approach, so that the data input to the recombination operation unit for multiplication is small-bit-width data, reducing the computational power consumption of the recombination operation unit. The output terminals of all recombination operation units are connected to the recombination module, which concatenates and recombines the multiplication results output by all recombination operation units to obtain the final recombination result. The input terminal of the fast modular reduction module is connected to the output terminal of the recombination module, which performs a modulo operation on the recombination result to obtain the final modular multiplication result and transmits it to the subsequent circuit. Furthermore, the recombination unit performs bitwise decomposition on the two multipliers in the output data of the corresponding decomposition and recombination unit in the last-level decomposition and recombination module. This decomposed data is then adapted to the specifications of the underlying hardware processing device of the modular multiplication chip. The underlying hardware processing device of the modular multiplication chip then performs cross-multiplication. This improves the efficiency of modular multiplication while reducing the number of digital signal processing multipliers, thereby increasing the hardware resource utilization of the digital cryptography system. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the structure of the first modular multiplication chip provided in the embodiments of this application;

[0043] Figure 2 This is a schematic diagram of the structure of the second type of modular multiplication chip provided in the embodiments of this application;

[0044] Figure 3 A flowchart illustrating the operation of a first-level decomposition unit provided in this application embodiment;

[0045] Figure 4 A flowchart illustrating the operation of a two-level decomposition unit provided in this application embodiment;

[0046] Figure 5 This is a schematic diagram of the structure of the third type of modular multiplication chip provided in the embodiments of this application;

[0047] Figure 6 A schematic diagram of a cross-multiplication operation provided in an embodiment of this application;

[0048] Figure 7 This is a schematic diagram of the structure of the fourth modular multiplication chip provided in the embodiments of this application;

[0049] Figure 8 This application provides a schematic diagram of a modulo operation of an arithmetic unit.

[0050] Figure 9 This is a schematic diagram of the structure of the fifth modular multiplication chip provided in the embodiments of this application;

[0051] Figure 10 This is a schematic diagram illustrating the result of a modular multiplication operation provided in an embodiment of this application;

[0052] Figure 11 A waveform diagram of a control module provided in an embodiment of this application;

[0053] Figure 12 This is a schematic diagram of the structure of a digital cryptography system provided in an embodiment of this application.

[0054] Figure Descriptions: 10: Modular multiplication chip; 101: Decomposition multiplier module; 1011: Decomposition and recombination submodule; 111: First-level decomposition and recombination submodule; 1111: First-level decomposition and recombination unit; 112: Second-level decomposition and recombination submodule; 1121: Second-level decomposition and recombination unit; 1012: Recombination operation submodule; 121: Recombination operation unit; 1211: Dynamic bit-width recombination subunit; 1212: Operation subunit; 12121: Digital signal processing multiplier; 102: Recombination module; 103: Fast modular reduction module; 1031: Decomposition unit; 1032: Recombination unit; 1033: Operation unit; 331: Carry-retaining adder; 332: Full adder; 104: Control module; 20: Digital cryptography system; 201: Main controller; 202: SM2 module; 203: SM3 module; 204: SM4 module. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0056] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0057] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0058] In the description of this application, it should be noted that the terms "first", "second", "third", "fourth", "fifth", "sixth", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0059] The SM2 algorithm is a domestically developed commercial asymmetric cryptography standard belonging to the elliptic curve cryptography system. It is used for digital signatures, key exchange, and public-key encryption. Notably, at the same security strength, its key length is significantly shorter than that required by the RSA algorithm (SM2 requires only 256 bits, while RSA requires 3072 bits). The SM2 algorithm offers 4-6 times higher computational efficiency compared to RSA, making it more suitable for resource-constrained scenarios such as IoT devices.

[0060] Among them, the SM2 algorithm is effective in the prime number field F. q The equation of the elliptic curve on the curve is shown in the following formula:

[0061] (1)

[0062] It is worth noting that a and b are specific parameters of the elliptic curve in a finite field. And satisfy The set of all points satisfying the above formula (1) and the point O at infinity together form an elliptic curve, i.e. .

[0063] The most complex and time-consuming computation in the SM2 algorithm is the modular multiplication operation in the finite field. Existing solutions often use three-level parallel schemes based on the Jacobi-weighted projective coordinate system, the Montgomery modular multiplication scheme, the Karatsuba optimization scheme, and dual-field modular multipliers to pre-optimize the modular multiplication operation.

[0064] A Field Programmable Gate Array (FPGA) chip is a hardware-reconfigurable semiconductor chip that allows users to define its internal circuit structure through custom programming to achieve specific functions. Furthermore, the reprogrammable nature of FPGA chips enables rapid iteration of their hardware functions through software configuration, flexibly adapting to changing user needs.

[0065] Therefore, existing technologies often employ FPGA chips to accelerate elliptic curve operations to improve the computational efficiency of the SM2 asymmetric cryptography algorithm. Among these operations, modular multiplication over finite fields is the core operation of the SM2 asymmetric cryptography algorithm, accounting for approximately 90% of its computation time. This means that the efficiency of modular multiplication directly impacts the overall computational efficiency of the SM2 asymmetric cryptography algorithm. Therefore, improving the efficiency of modular multiplication in the SM2 algorithm is a bottleneck that needs to be overcome.

[0066] To address this, this application provides an analog multiplication chip comprising: a decomposition multiplier module, a recombination module, and a fast reduction module. In the decomposition multiplier module, each decomposition and recombination unit in the primary decomposition and recombination submodule decomposes and recombines the two multipliers input from the preceding circuit to obtain multiple sets of output data, which are then output to a decomposition and recombination unit in the next-level decomposition and recombination submodule. The recombination unit performs bitwise decomposition and cross-multiplication on the two multipliers in the output data from the corresponding decomposition and recombination unit in the last-level decomposition and recombination submodule to obtain the multiplication result. The recombination module performs shift and addition / subtraction operations on all multiplication results to obtain the recombination result. The fast modulo reduction module performs modulo operations on the recombination result to obtain the final analog multiplication result. Furthermore, this application decomposes the two multipliers input from the preceding circuit through a multi-level decomposition multiplier module, resulting in a smaller output data bit width in each decomposition and recombination unit of the last-level decomposition and recombination submodule. The recombination unit then performs bitwise decomposition on the output data, ensuring that the final cross-multiplication data bit width matches the bit width of the digital signal processing multiplier, thus reducing computational complexity. In this way, the efficiency of modular multiplication can be improved while reducing the number of digital signal processing multipliers required, thereby improving the utilization rate of hardware resources in the digital cryptography system.

[0067] It is worth noting that the modular multiplication chip provided in this application is a more efficient modular multiplication chip obtained by further optimizing the Karatsuba divide-and-conquer optimization idea and the underlying digital signal processing (DSP) multiplier of the field programmable gate array (FPGA) chip.

[0068] The Karatsuba divide-and-conquer optimization strategy is as follows:

[0069] If the bit width of both multiplier A and multiplier B is 2n, when multiplying multiplier A and multiplier B, multiplier A and multiplier B are divided into corresponding high-bit and low-bit parts, as shown in the following formula (2):

[0070] (2)

[0071] Multiplying the decomposed multipliers A and B together yields the following formula (3):

[0072] (3)

[0073] The above formula (3) is transformed by the Karatsuba divide-and-conquer optimization idea to obtain the following formula (4):

[0074] (4)

[0075] Combining the above formula (4), it can be seen that the computational complexity of multiplying multiplier A and multiplier B directly is one multiplication operation with a bit width of 2n. After decomposition, the computational complexity of multiplying directly is four multiplication operations with a bit width of n. The computational complexity after the Karatsuba divide-and-conquer optimization idea is three multiplication operations with a bit width of n and some additional addition and subtraction. For large bit width integer operations in the field of cryptography, reducing the bit width can greatly reduce the computational cost of multiplication. The computational cost of addition and subtraction is negligible compared to the computational cost of multiplication.

[0076] Therefore, the modular multiplication chip in this application improves the modular multiplication efficiency of the SM2 algorithm by reducing the bit width of large-bit-width data.

[0077] The following description, in conjunction with the accompanying drawings, provides a detailed explanation of the modular multiplication chip provided in the embodiments of this application and the digital cryptography system using the modular multiplication chip.

[0078] Figure 1 See the schematic diagram of a modular multiplication chip provided in this application. Figure 1 This application provides a modular multiplication chip 10, which includes: a decomposition multiplier module 101, a recombination module 102, and a fast modular reduction module 103.

[0079] The modular multiplication chip 10 is mainly used to implement the modular multiplication operation in the SM2 algorithm. The modular multiplication chip 10 is specifically implemented by a programmable FPGA chip. The modular multiplication operation program in the modular multiplication chip 10 can be modified by the user according to the requirements. This application does not make any specific restrictions on this.

[0080] The first input terminal of the decomposition multiplier module 101 is connected to the preceding circuit to receive the two multipliers to be operated on. The decomposition multiplier module 101 includes a multi-stage decomposition and recombination sub-module 1011 and a recombination operation sub-module 1012 connected in sequence. Each stage of the decomposition and recombination sub-module 1011 includes at least one decomposition and recombination unit. The recombination operation sub-module 1012 includes multiple recombination operation units 121. The output terminal of each decomposition and recombination unit in each stage of the decomposition and recombination sub-module 1011 is connected to the input terminal of multiple decomposition and recombination units in the next stage of the decomposition and recombination sub-module 111. The output terminal of each decomposition and recombination unit in the last stage of the decomposition and recombination sub-module 111 is correspondingly connected to the input terminal of one recombination operation unit 121 in the recombination operation sub-module 1012.

[0081] Optionally, the first input terminal of the decomposer multiplier module 101 is connected to the front-end circuit. The decomposer multiplier module 101 obtains the two multipliers to be operated on from the front-end circuit via the first input terminal. The two multipliers to be operated on refer to the two data that need to be modularly multiplied. The bit width of the two multipliers to be operated on is large, such as 256 bits or 512 bits. This application does not make specific limitations on this.

[0082] Optionally, the decomposition multiplier module 101 includes a series of decomposition and recombination submodules 1011 and recombination operation submodules 1012 connected in sequence. Each decomposition and recombination submodule 1011 includes at least one decomposition and recombination unit, and each recombination operation submodule 1012 includes multiple recombination operation units 121. Each decomposition and recombination unit in each decomposition and recombination submodule 1011 decomposes the two input multipliers based on the Karatsuba divide-and-conquer optimization idea to obtain multiple small-bit-width data. Then, based on the Karatsuba divide-and-conquer optimization idea, the multiplication relationship between the two multipliers is combined and input into multiple decomposition and recombination units in the corresponding next-level decomposition and recombination submodule 1011, until the last level decomposition and recombination submodule 1011.

[0083] Furthermore, in the final-level decomposition and recombination submodule 1011, multiple decomposition and recombination units decompose and recombine the two input multipliers based on the Karatsuba divide-and-conquer optimization idea. The two recombined multipliers are then input into the corresponding recombination operation unit 121. The recombination operation unit 121 performs bitwise decomposition and cross-multiplication on the received two multipliers to obtain the final multiplication result of the decomposition multiplier module.

[0084] Each decomposition and recombination unit is used to decompose and recombine the two input multipliers to obtain multiple sets of output data, and output each set of output data to a decomposition and recombination unit in the next-level decomposition and recombination submodule 1011. Each set of output data includes the two split multipliers.

[0085] Optionally, the bit widths of the two multipliers received by each decomposition and recombination submodule 1011 are different. The primary decomposition and recombination submodule 1011 receives the two multipliers with the largest bit width, while the last-level decomposition and recombination submodule 1011 receives the two multipliers with smaller bit widths. Each decomposition and recombination submodule 1011 decomposes the two input multipliers according to different bit widths. For example, the primary decomposition and recombination submodule X decomposes and recombines two 256-bit multipliers, and the last-level recombination submodule Y decomposes and recombines two 87-bit multipliers, etc. This application does not make specific limitations in this regard.

[0086] Furthermore, the primary decomposition and recombination submodule 1011 refers to the decomposition and recombination submodule in which the modular multiplication chip 10 first decomposes and recombines the two multipliers to be operated on from the input of the preceding circuit, and the last-stage decomposition and recombination submodule 1011 refers to the last-stage decomposition and recombination submodule in the modular multiplication chip 10 that decomposes and recombines the two input multipliers based on the Karatsuba divide-and-conquer optimization idea.

[0087] It is worth noting that the primary decomposition and recombination submodule 1011 decomposes and recombines the two multipliers to be operated on from the input of the previous stage circuit based on the Karatsuba divide-and-conquer optimization idea, and obtains multiple sets of output data. Each set of output data includes two multipliers. Each set of output data is sent to a decomposition and recombination unit of the next-level decomposition and recombination submodule 1011. Each decomposition and recombination unit in the next-level decomposition and recombination submodule 1011 decomposes and recombines the two multipliers it receives based on the Karatsuba divide-and-conquer optimization idea, and so on, until the last-level decomposition and recombination submodule 1011 has completed the decomposition and recombination.

[0088] In addition, the decomposition bit widths corresponding to each level of decomposition and recombination submodule 1011 are different, but the decomposition bit widths corresponding to each decomposition and recombination unit in the same level of decomposition and recombination submodule 1011 are the same.

[0089] For example, the decomposition and recombination unit X1 in the primary decomposition and recombination submodule X decomposes the received multiplier A and multiplier B according to the bit width M to obtain multiple sets of output data m1, m2, m3, etc., where m1 includes multiplier p1 and multiplier q1; the decomposition and recombination unit S1 in the next-level decomposition and recombination submodule S decomposes the received multiplier p1 and multiplier q1 according to the bit width N to obtain multiple sets of output data n1, n2, n3, etc., where n1 includes multiplier r1 and t1. The bit width N < the bit width M, and this application does not specifically limit this.

[0090] Each recombination operation unit 121 is used to perform bitwise decomposition and cross-multiplication on the two multipliers from the corresponding decomposition and recombination unit in the last-level decomposition and recombination submodule 1011 to obtain the multiplication result.

[0091] Optionally, each recombination operation unit 121 corresponds one-to-one with each decomposition and recombination unit in the last-level decomposition and recombination submodule 1011. Each recombination operation unit 121 receives two multipliers output from the corresponding decomposition and recombination unit in the last-level decomposition and recombination submodule 1011, performs bitwise decomposition on the two multipliers, and performs cross-multiplication on the results of the bitwise decomposition to obtain the multiplication result.

[0092] The input terminal of the recombination module 102 is connected to the output terminal of each recombination operation unit 121, the output terminal of the recombination module 102 is connected to the input terminal of the fast modulo reduction module 103, and the output terminal of the fast modulo reduction module 103 is connected to the subsequent circuit.

[0093] Optionally, the input terminal of the recombination module 102 is connected to the output terminal of all recombination operation units 121. The recombination module 102 receives the multiplication results output by all recombination operation units 121 and concatenates and recombines all the multiplication results to obtain the recombination result.

[0094] Optionally, the output of the recombination module 102 is connected to the input of the fast modulo reduction module 103. The fast modulo reduction module 103 performs a modulo operation on the received recombination result to obtain the final modulo multiplication result, and outputs it to the subsequent circuit.

[0095] In this embodiment, the modular multiplication chip includes a decomposition multiplier module, a recombination module, and a fast modular reduction module. The decomposition multiplier module includes a series of multi-level decomposition and recombination sub-modules and a recombination operation sub-module connected sequentially. Each level of the decomposition and recombination sub-module includes at least one decomposition and recombination unit, and each level of the recombination operation sub-module includes multiple recombination operation units. Each decomposition and recombination unit in each level of the decomposition and recombination sub-module corresponds to multiple decomposition and recombination units in the next level of the decomposition and recombination sub-module. Each decomposition and recombination unit in the last level of the decomposition and recombination sub-module corresponds to one recombination operation unit in the recombination operation sub-module. The multi-level decomposition and recombination sub-module decomposes and recombines the large-bit-width input multiplier data based on the divide-and-conquer approach, so that the data input to the recombination operation unit for multiplication is small-bit-width data, reducing the computational power consumption of the recombination operation unit. The output terminals of all recombination operation units are connected to the recombination module, which concatenates and recombines the multiplication results output by all recombination operation units to obtain the final recombination result. The input terminal of the fast modular reduction module is connected to the output terminal of the recombination module, which performs a modulo operation on the recombination result to obtain the final modular multiplication result and transmits it to the subsequent circuit. Furthermore, the recombination unit performs bitwise decomposition on the two multipliers in the output data of the corresponding decomposition and recombination unit in the last-level decomposition and recombination module. This decomposed data is then adapted to the specifications of the underlying hardware processing device of the modular multiplication chip. The underlying hardware processing device of the modular multiplication chip then performs cross-multiplication. This improves the efficiency of modular multiplication while reducing the number of digital signal processing multipliers, thereby increasing the hardware resource utilization of the digital cryptography system.

[0096] In one alternative implementation, see [link to implementation details]. Figure 2 The multi-level decomposition and recombination submodule in the decomposition multiplier module 101 of the modular multiplication chip 10 provided in this application embodiment includes: a first-level decomposition and recombination submodule 111 and a second-level decomposition and recombination submodule 112.

[0097] Optionally, the multi-level decomposition and recombination submodule 1011 includes: a first-level decomposition and recombination submodule 111 and a second-level decomposition and recombination submodule 112, that is, the decomposition multiplier module 101 performs two-level decomposition and recombination on the two multipliers to be operated on by the input of the previous circuit based on the Karatsuba divide-and-conquer optimization idea.

[0098] The first-level decomposition and recombination submodule 111 includes a first-level decomposition and recombination unit 1111, and the output of the first-level decomposition and recombination unit 1111 is connected to the input of M second-level decomposition and recombination units 1121 in the second-level decomposition and recombination submodule 112.

[0099] Optionally, M can be two, three, four, etc. This application takes three as an example, which does not mean that one primary decomposition and recombination unit 1111 can only be connected to three secondary decomposition and recombination units 1121. The specific connection depends on the actual application scenario, and this application does not make any specific limitation on this.

[0100] The output of each secondary decomposition and recombination unit 1121 is connected to the input of the corresponding recombination operation unit 121 in the recombination operation submodule 1012.

[0101] Optionally, the output of each secondary decomposition and recombination unit 1121 is connected to a recombination operation unit 121 in the recombination operation submodule 1012, and the recombination operation unit 121 performs bitwise decomposition and recombination and cross-multiplication on the output data of its corresponding secondary decomposition and recombination unit 1121.

[0102] In one alternative implementation, see [link to implementation details]. Figure 3 The first-level decomposition and recombination unit 1111 in the first-level decomposition and recombination submodule 111 of the modular multiplication chip 10 provided in this application embodiment is specifically used for:

[0103] S301 receives the first and second multipliers from the preceding circuit.

[0104] Optionally, the first multiplier and the second multiplier are large-bit-width data input to the analog multiplier chip 10 of the front-end circuit. The first multiplier can be a 256-bit multiplier A and the second multiplier can be a 256-bit multiplier B. This application does not make specific limitations on this.

[0105] S302. Decompose the first multiplier and the second multiplier into multiple first-level data according to the first preset bit width.

[0106] Optionally, the first preset bit width is a decomposition bit width preset by the user. The first preset bit width can be 86 bits or other bit widths. This application does not specifically limit this.

[0107] Optionally, the first-level decomposition and recombination unit 1111 decomposes the first multiplier and the second multiplier input to the preceding circuit based on the first preset bit width to obtain multiple first-level data corresponding to the first multiplier and multiple first-level data corresponding to the second multiplier.

[0108] For example, the first preset bit width w1 = 86 bits, and the analog multiplier chip receives two multipliers from the front-end circuit, namely a 256-bit multiplier A and a 256-bit multiplier B, respectively. Multiplier A is decomposed into... according to the first preset bit width. , as well as Three primary data points, and simultaneously, the multiplier B is decomposed according to the first preset bit width into , as well as Three primary data points.

[0109] S303. Based on multiple first-level data, reorganize to obtain multiple sets of first-level multipliers, each set of first-level multipliers including two multipliers.

[0110] Optionally, the first-level decomposition and recombination unit 1111 recombines multiple first-level data based on the Karatsuba divide-and-conquer optimization idea, which can obtain multiple sets of first-level multipliers. Here, a first-level multiplier refers to a data pair with a multiplicative relationship obtained after the first-level decomposition and recombination unit 1111 decomposes and recombines the data.

[0111] For example, the first-level decomposition and recombination unit decomposes and recombines the first multiplier A and the second multiplier B based on the Karatsuba divide-and-conquer optimization idea, wherein the first multiplier A is decomposed according to a bit width of w1=86 bits. , as well as The three primary data points, and the second multiplier B, are decomposed according to a bit width of w1 = 86 bits. , as well as The decomposition and recombination process of the three primary data points is shown in the following formula (5):

[0112] (5)

[0113] According to the above formula (5), the first multiplier A and the second multiplier B can be decomposed into 6 groups of 86-bit × 86-bit first-order multipliers, and the six groups of first-order multipliers are as follows: , , , , , .

[0114] It should be noted that, in order to avoid bit width overflow of the adder, the bit width of the first-level multiplier above needs to be increased by one bit, that is, to obtain 6 sets of 87-bit × 87-bit first-level multipliers.

[0115] in, , , , , , The addition operation of equal multipliers is completed in the first-level decomposition and recombination unit 1111.

[0116] S304. Input the first-level multipliers of each group into each second-level decomposition and recombination unit 1121.

[0117] In one alternative implementation, see [link to implementation details]. Figure 4The secondary decomposition and recombination units 1121 in the secondary decomposition and recombination submodule 112 of the modular multiplication chip 10 provided in this application embodiment are specifically used for:

[0118] S401, Receive the third and fourth multipliers from the first-level decomposition and recombination unit 1111.

[0119] Optionally, the third and fourth multipliers refer to any one of the multiple sets of first-level multipliers obtained from the decomposition and recombination of the first-level decomposition and recombination unit 1111, such as the third multiplier being... , , , , as well as For any one of them, the fourth multiplier is , , , , as well as Any one of them, but this application does not specifically limit it.

[0120] S402. Decompose the third and fourth multipliers into multiple secondary data according to the second preset bit width.

[0121] Optionally, the second preset bit width is a decomposition bit width preset by the user. The second preset bit width is smaller than the first preset bit width. The second preset bit width can be 44 bits or other bit widths. This application does not specifically limit this.

[0122] Optionally, the secondary decomposition and recombination unit 1121 decomposes the third and fourth multipliers input by the primary decomposition and recombination unit 1111 based on the second preset bit width to obtain multiple secondary data corresponding to the third multiplier and multiple secondary data corresponding to the fourth multiplier.

[0123] For example, the second preset bit width w2 = 44 bits, and the second-level decomposition and recombination unit receives the third multiplier sent by the first-level decomposition and recombination unit as follows: The fourth multiplier is The third multiplier is calculated according to the second preset bit width. Decomposed into and Two secondary data points, and simultaneously, the third multiplier is calculated according to the second preset bit width. Decomposed into as well as Two secondary data points.

[0124] S403. Based on multiple secondary data, reorganize to obtain multiple sets of secondary multipliers, each set of secondary multipliers including two multipliers.

[0125] Optionally, the secondary decomposition and recombination unit 1121 recombines multiple secondary data based on the Karatsuba divide-and-conquer optimization idea, which can obtain multiple sets of secondary multipliers. Here, the secondary multiplier refers to the data pairs with multiplicative relationships obtained after the secondary decomposition and recombination unit 1121 decomposes and recombines the data.

[0126] For example, the second-level decomposition and recombination unit uses the Karatsuba divide-and-conquer optimization idea to optimize the third multiplier. and the fourth multiplier Decomposition and recombination are performed, in which the third multiplier... Decomposed according to the bit width of w2=44 bits and Two second-level data points, fourth multiplier Decomposed according to the bit width of w2=44 bits and The decomposition and recombination process of the two secondary data is shown in the following formula (6):

[0127]

[0128] (6)

[0129] According to the above formula (6), the third multiplier can be... and the fourth multiplier It is decomposed into three sets of 44-bit × 44-bit second-order multipliers, and the three sets of second-order multipliers are as follows: , , .

[0130] It should be noted that, in order to avoid bit width overflow of the adder, the bit width of the above-mentioned second-order multiplier needs to be increased by one bit, that is, to obtain three sets of 45-bit × 45-bit second-order multipliers.

[0131] in, , The addition operation of equal multipliers is performed in the second-level decomposition and recombination unit 1121.

[0132] S404. Input each group of second-order multipliers into the corresponding recombination operation unit 121.

[0133] In one alternative implementation, see [link to implementation details]. Figure 5 The modular multiplication chip 10 provided in this application embodiment includes a dynamic bit-width recombination subunit 1211 and an operation subunit 1212 in the recombination operation submodule 1012.

[0134] The dynamic bit-width recombination subunit 1211 is used to perform bit-by-bit decomposition on the received fifth and sixth multipliers to obtain multiple first and third-level data corresponding to the fifth multiplier and multiple second and third-level data corresponding to the sixth multiplier.

[0135] Optionally, the dynamic bit-width recombination subunit 1211 receives the fifth and sixth multipliers sent by the corresponding secondary decomposition and recombination unit 1121, and performs bitwise decomposition on the fifth and sixth multipliers to obtain multiple first and third-level data corresponding to the fifth multiplier and multiple second and third-level data corresponding to the sixth multiplier. Here, the fifth and sixth multipliers refer to any set of secondary multipliers sent by the secondary decomposition and recombination unit 1121 corresponding to the recombination operation unit 121. The fifth multiplier can be... , , The sixth multiplier can be any one of the following: , , Any one of them, etc., this application does not specifically limit it.

[0136] For example, if the fifth multiplier received by the dynamic bit-width recombining subunit is The sixth multiplier is The multiplication relationship between the fifth and sixth multipliers is a 45-bit × 45-bit multiplication. The operation subunit 1212 can support multiplication operations of 25 bits × 18 bits. Therefore, the fifth multiplier is multiplied according to the 45-bit width. Divided into , , Three first and third level data, and at the same time, the sixth multiplier is divided into 45 bits. Decomposed into , Two sets of data at the second and third levels. Among them, Its bit width is 16 bits. Its bit width is 16 bits. The bit width is 13 bits; Its bit width is 24 bits. Its bit width is 21 bits.

[0137] The operation subunit 1212 is used to perform cross-multiplication of multiple first-level and third-level data with multiple second-level and third-level data to obtain the multiplication result.

[0138] Optionally, the operation subunit 1212 is used to perform cross-multiplication on multiple first-level and third-level data and multiple second-level and third-level data to obtain multiple multiplication results.

[0139] In one alternative implementation, see [link to implementation details]. Figure 5The recombination operation unit 121 in the modular multiplication chip 10 provided in this application embodiment includes an operation subunit 1212, which includes a plurality of digital signal processing multipliers 12121.

[0140] Each digital signal processing multiplier 12121 is used to acquire a first-level third-level data and a second-level third-level data, and to perform multiplication operations on the first-level third-level data and the second-level third-level data to obtain the multiplication result corresponding to the digital signal processing multiplier 12121.

[0141] Optionally, the operation subunit 1212 is implemented by multiple digital signal processing multipliers 12121, that is, the operation subunit 1212 is implemented by multiple DSP multipliers. Each DSP multiplier obtains a first third-level data and a second third-level data, and performs multiplication operations on the obtained first third-level data and second third-level data to obtain the corresponding multiplication result.

[0142] Figure 6 For a schematic diagram of cross-multiplication provided in this application, see [link to diagram]. Figure 6 The cross-multiplication of the recombination operation unit 121 in the modular multiplication chip provided in this application embodiment is specifically implemented by the first DSP multiplier (DSP1). Multiplication operation, implementation of the second DSP multiplier (DSP2) Multiplication operation, implementation of the third DSP multiplier (DSP3) Multiplication operation, implementation of the fourth DSP multiplier (DSP4) Multiplication operations are implemented by the fifth DSP multiplier (DSP5). Multiplication operation, implementation of the sixth DSP multiplier (DSP6) Multiplication operations.

[0143] In one optional implementation, the recombination module 102 in the modular multiplication chip 10 provided in this application embodiment is used for:

[0144] The multiplication results output by all digital signal processing multipliers 12121 in all recombination operation units 121 are shifted and added / subtracted to obtain the recombination result.

[0145] Optionally, the recombination module 102 performs corresponding addition, subtraction, and bit operations on each multiplication result according to the decomposition method to obtain the recombination result. For example, the 54 multiplication results output by 54 DSP multipliers are recombinated into a 512-bit wide recombination result C.

[0146] In one alternative implementation, see [link to implementation details]. Figure 7The fast modular reduction module 103 in the modular multiplication chip 10 provided in this application embodiment includes: a decomposition unit 1031, a recombination unit 1032, and an operation unit 1033. The operation unit 1033 includes: multiple carry-retaining adders 331 and multiple full adders 332.

[0147] The input terminal of the decomposition unit 1031 is connected to the output terminal of the recombination module 102, the output terminal of the decomposition unit 1031 is connected to the input terminal of the recombination unit 1032, and the output terminal of the recombination unit 1032 is connected to the input terminal of the arithmetic unit 1033.

[0148] The decomposition unit 1031 receives the recombination result from the recombination module 102 and decomposes the recombination result according to the third preset bit width to obtain multiple decomposed data.

[0149] Optionally, the decomposition unit 1031 decomposes the recombination result C obtained by the recombination module 102 according to the third preset bit width to obtain multiple decomposed data. The third preset bit width is a bit width preset by the user. The third preset bit width can be 32 bits or other bit widths. This application does not specifically limit it.

[0150] For example, the third preset bit width is 32 bits, and the recombination result C received by the decomposition unit is 512 bits wide. According to the third preset bit width, the recombination result C can be divided into 16 decomposition data of equal bit width. each The bit width is 32 bits.

[0151] The recombination unit 1032 recombines multiple decomposed data according to a preset format to obtain multiple data sequences.

[0152] Optionally, the preset format is a grouping format pre-set by the user. The recombination unit 1032 randomly recombines multiple decomposed data based on the preset format to obtain multiple data sequences.

[0153] For example, the decomposed data is processed according to a preset format. The data is structured into 14 data sequences, each 256 bits wide. The 14 data sequences are as follows:

[0154] ;

[0155] ;

[0156] ;

[0157] ;

[0158] ;

[0159] ;

[0160] ;

[0161] ;

[0162] ;

[0163] ;

[0164] ;

[0165] ;

[0166] ;

[0167] .

[0168] It is worth noting that the "0" in the above data sequence is used to represent a 32-bit wide 0.

[0169] The arithmetic unit 1033 performs modulo operations on each data sequence via multiple carry-holding adders 331 and multiple full adders 332 to obtain the final modular multiplication result.

[0170] Optionally, the above data sequence is input into the arithmetic unit 1033, and the arithmetic unit 1033 performs modulo operation on the data sequence via multiple carry-holding adders 331 and multiple full adders 332 to obtain the final modular multiplication result.

[0171] Figure 8 A schematic diagram of a modulo operation of an arithmetic unit provided in this application is shown below. Figure 8 The arithmetic unit 1033 provided in this application embodiment consists of multiple carry-holding adders 331 and multiple full adders 332. The carry-holding adder is represented by CSA, which has three input terminals and two output terminals. The CSA takes three 256-bit data as input and outputs two 256-bit data. The full adder is represented by FA, ​​which has two input terminals and one output terminal. The FA takes two 256-bit operands as input and outputs a 256-bit modular multiplication result.

[0172] In one alternative implementation, see [link to implementation details]. Figure 9 The modular multiplication chip 10 provided in this application embodiment further includes a control module 104, wherein the output terminal of the control module 104 is connected to the second input terminal of the decomposer multiplier module 101.

[0173] The control module 104 is used to send control signals to the decomposer multiplier module 101. The decomposer multiplier module 101 responds to the control signals to perform modular multiplication operations. The control signals include at least one of the following: modular multiplication start signal, clock signal, reset signal, and modular multiplication end signal.

[0174] Optionally, the control module 104 can be the main controller of the digital cryptography system or a microcontroller on the modular multiplication chip 10, used only to control the modular multiplication operation of the modular multiplication chip 10.

[0175] Optionally, the control module 104 can send a modular multiplication start signal, a clock signal, a reset signal, and a modular multiplication end signal to the decomposition multiplier module 101. The modular multiplication start signal (Mult_vld_in) informs the modular multiplication chip 10 to begin performing modular multiplication operations, the modular multiplication end signal (Mult_vld_out) informs the modular multiplication chip 10 to stop performing modular multiplication operations, the clock signal controls the parallel and serial time of the modular multiplication chip 10, and the reset signal controls the zeroing operation of the modular multiplication chip 10 after completing the modular multiplication operation.

[0176] Figure 10 A schematic diagram illustrating the result of a modular multiplication operation provided in this application is shown below. Figure 10 One modular multiplication operation is as follows:

[0177] First multiplier A:

[0178] 421debd61b62eab6746434ebc3cc315e32220b3badd50bdc4c4e6c147fedd43d;

[0179] Second multiplier B:

[0180] 0ae55229283cd96aee4d87da90d8c66ceb372da83fc9c6363d579c46f6de18f2;

[0181] Modulus p:

[0182] fffffffeffffffffffffffffffffffffffffff00000000ffffffffffffffff;

[0183] Expected modular multiplication result:

[0184] b05881850dac5c7726cfe579420892aaaf83e949a73061d6165bc37ea8a70db.

[0185] Figure 11A waveform diagram of a control module provided in this application is shown below. Figure 11 When the Mult_vld_in signal goes high, the modular multiplication chip begins to perform modular multiplication calculations. The result of the modular multiplication module is as follows: Figure 10 As shown, the modular multiplication calculation is completed when the Mult_vld_out signal goes high, and the comparison results are in line with expectations.

[0186] Figure 12 A schematic diagram of the structure of a digital cryptography system provided in this application is shown below. Figure 12 The digital cryptography system 20 provided in this application includes a main controller 201, an SM2 module 202, an SM3 module 203, and an SM4 module 204. The SM2 module 202 includes the aforementioned modular multiplication chip 10. The SM2 module 202 performs finite field modular multiplication operations via the modular multiplication chip 10. The specific implementation process is consistent with the above embodiment and will not be described in detail here.

[0187] Furthermore, the main controller 201 is connected to the SM2 module 202, the SM3 module 203 and the SM4 module 204 respectively. The main controller 201 is used to realize data interaction between the SM2 module 202, the SM3 module 203 and the SM4 module 204. This application does not make specific limitations in this regard.

[0188] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0189] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A modular multiplication chip, characterized in that, The modular multiplication chip includes: a decomposition multiplier module, a recombination module, and a fast modular reduction module; The first input terminal of the decomposition multiplier module is connected to the preceding circuit to receive the two multipliers to be operated on. The decomposition multiplier module includes a series of decomposition and recombination submodules and recombination operation submodules connected in sequence. Each decomposition and recombination submodule includes at least one decomposition and recombination unit. The recombination operation submodule includes multiple recombination operation units. The output terminal of each decomposition and recombination unit in each decomposition and recombination submodule is connected to the input terminal of multiple decomposition and recombination units in the next level decomposition and recombination submodule. The output terminal of each decomposition and recombination unit in the last level decomposition and recombination submodule is correspondingly connected to the input terminal of one recombination operation unit in the recombination operation submodule. Each decomposition and recombination unit is used to decompose and recombine the two input multipliers to obtain multiple sets of output data, and output each set of output data to a decomposition and recombination unit in the next level decomposition and recombination submodule. Each set of output data includes the two split multipliers. Each recombination operation unit is used to perform bitwise decomposition and cross-multiplication on the two multipliers from the corresponding decomposition and recombination unit in the last-level decomposition and recombination submodule to obtain the multiplication result; The input terminal of the recombination module is connected to the output terminal of each recombination operation unit, the output terminal of the recombination module is connected to the input terminal of the fast modulo reduction module, and the output terminal of the fast modulo reduction module is connected to the subsequent circuit.

2. The modular multiplication chip according to claim 1, characterized in that, The multi-level decomposition and recombination submodule includes: a first-level decomposition and recombination submodule and a second-level decomposition and recombination submodule; The first-level decomposition and recombination submodule includes a first-level decomposition and recombination unit, and the output of the first-level decomposition and recombination unit is connected to the inputs of M second-level decomposition and recombination units in the second-level decomposition and recombination submodule. The output of each secondary decomposition and recombination unit is connected to the input of the corresponding recombination operation unit in the recombination operation submodule.

3. The modular multiplication chip according to claim 2, characterized in that, The primary decomposition and recombination unit is specifically used for: Receive the first and second multipliers from the preceding circuitry; The first multiplier and the second multiplier are decomposed into multiple first-level data according to the first preset bit width; Based on the multiple first-level data, multiple sets of first-level multipliers are obtained by recombination, and each set of first-level multipliers includes two multipliers; Each group of first-level multipliers is input into each of the second-level decomposition and recombination units.

4. The modular multiplication chip according to claim 2, characterized in that, Each of the aforementioned secondary decomposition and recombination units is specifically used for: Receive the third and fourth multipliers from the first-level decomposition and recombination unit; The third multiplier and the fourth multiplier are decomposed into multiple secondary data according to the second preset bit width; Based on the multiple secondary data, multiple sets of secondary multipliers are obtained by recombination, and each set of secondary multipliers includes two multipliers; Each group of second-order multipliers is input into the corresponding recombination operation unit.

5. The modular multiplication chip according to claim 1, characterized in that, Each of the aforementioned recombination operation units includes: a dynamic bit-width recombination subunit and an operation subunit; The dynamic bit-width recombination subunit is used to perform bit-by-bit decomposition on the received fifth and sixth multipliers to obtain multiple first-level and third-level data corresponding to the fifth multiplier and multiple second-level and third-level data corresponding to the sixth multiplier. The operation subunit is used to perform cross-multiplication of the plurality of first-level and third-level data with the plurality of second-level and third-level data to obtain the multiplication result.

6. The modular multiplication chip according to claim 5, characterized in that, The arithmetic subunit includes: multiple digital signal processing multipliers; Each of the digital signal processing multipliers is used to acquire a first level 3 data and a second level 3 data, and to perform a multiplication operation on the first level 3 data and the second level 3 data to obtain the multiplication result corresponding to the digital signal processing multiplier.

7. The modular multiplication chip according to claim 6, characterized in that, The recombination module is used for: The multiplication results from all digital signal processing multipliers in all recombination units are shifted and added / subtracted to obtain the recombination result.

8. The modular multiplication chip according to claim 1, characterized in that, The fast modular reduction module includes: a decomposition unit, a recombination unit, and an arithmetic unit. The arithmetic unit includes: multiple carry-retaining adders and multiple full adders. The input terminal of the decomposition unit is connected to the output terminal of the recombination module, the output terminal of the decomposition unit is connected to the input terminal of the recombination unit, and the output terminal of the recombination unit is connected to the input terminal of the arithmetic unit. The decomposition unit receives the recombination result from the recombination module and decomposes the recombination result according to a third preset bit width to obtain multiple decomposed data. The recombination unit recombines multiple decomposed data according to a preset format to obtain multiple data sequences; The arithmetic unit performs modulo operations on each of the data sequences via multiple carry-holding adders and multiple full adders to obtain the final modular multiplication result.

9. The modular multiplication chip according to any one of claims 1-8, characterized in that, The modular multiplication chip also includes: a control module; The output terminal of the control module is connected to the second input terminal of the decomposition multiplier module. The control module is used to send control signals to the decomposition multiplier module, and the decomposition multiplier module responds to the control signals to perform modular multiplication. The control signals include at least one of the following: modular multiplication start signal, clock signal, reset signal, and modular multiplication end signal.

10. A digital cryptography system, characterized in that, The digital cryptography system includes: a main controller, an SM2 module, an SM3 module, and an SM4 module, wherein the SM2 module includes the modular multiplication chip as described in any one of claims 1-9.

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