Semiconductor device, manufacturing method thereof and electronic equipment
By designing a dual-gate memory cell structure and simplifying the manufacturing process, the challenge of increasing the number of memory cells on a limited substrate was solved, realizing a semiconductor device with high storage density and low resistance.
Patent Information
- Application Number
- CN202410533836.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-29
- Publication Date
- 2025-10-31
AI Technical Summary
With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the impact of minute differences on device performance is increasing. How to manufacture more high-performance memory cells on a limited substrate has become a challenge.
A semiconductor device containing multiple memory cells was designed, employing a dual-gate read transistor structure, including read word lines and side gate electrodes. The memory cells are stacked and distributed along a direction perpendicular to the substrate, and the manufacturing process is simplified by eliminating the step of removing parasitic MOS transistors.
It increases storage density, reduces the footprint and link resistance of storage cells, simplifies the manufacturing process, and enables multi-bit storage and good read control.
Smart Images
Figure CN120881998A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.
[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.
[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. The semiconductor device has high storage density and a simple manufacturing process.
[0006] This application provides a semiconductor device, including:
[0007] Multiple memory cells are distributed across different layers and stacked along a direction perpendicular to the substrate;
[0008] Read and write lines of the memory cells extending in a direction perpendicular to the substrate and penetrating different layers;
[0009] A first semiconductor layer and a plurality of second semiconductor layers extend in a direction perpendicular to the substrate, the first semiconductor layer at least partially surrounding the read line and the second semiconductor layers at least partially surrounding the write line; the first semiconductor layer is continuously disposed in a direction perpendicular to the substrate, and the plurality of second semiconductor layers are spaced apart and disconnected in a direction perpendicular to the substrate; a first conductive layer is provided between the first semiconductor layer and the second semiconductor layers;
[0010] A first gate electrode and a side gate electrode are respectively located on both sides of the first semiconductor layer; the first gate electrode is part of the read word line; a first conductive layer is provided between the side gate electrode and the first semiconductor layer; a gate insulating layer is provided between the side gate electrode and the first conductive layer, between the first conductive layer and the first semiconductor layer, and between the first semiconductor layer and the gate electrode.
[0011] In some embodiments of this application, the first semiconductor layer includes a plurality of channels spaced apart along a direction perpendicular to the substrate and a connection portion connecting two adjacent channels. The channels extend along a direction perpendicular to the substrate and a horizontal direction, and the connection portion extends along a direction perpendicular to the substrate. The orthographic projection of the connection portion on the substrate falls within the range of the orthographic projection of the channel on the substrate.
[0012] In some embodiments of this application, the thickness of the channel film is greater than the thickness of the second semiconductor layer.
[0013] In some embodiments of this application, the first conductive layer at least partially surrounds the channel, the first conductive layer is present between the channel and the second semiconductor layer, and the first conductive layer is present between the channel and the side gate electrode.
[0014] In some embodiments of this application, the storage unit includes a read transistor and a write transistor; wherein,
[0015] The read transistor includes the channel, the first gate electrode, and the side gate electrode, the channel at least partially surrounding the first gate electrode, the first gate electrode being a portion of the read word line; and / or
[0016] The write transistor includes a second semiconductor layer and a second gate electrode, the second semiconductor layer at least partially surrounding the second gate electrode, and the second gate electrode being part of the write word line.
[0017] In some embodiments of this application, the side gate electrodes of a row of read transistors located on the same layer and spaced apart in a second direction parallel to the substrate are a single structure.
[0018] In some embodiments of this application, the semiconductor device further includes a trench located between two adjacent rows of memory cells in a first direction parallel to the substrate, the trench extending along a second direction parallel to the substrate and a direction perpendicular to the substrate, the trench including a groove extending along the first direction toward the first conductive layer, the side gate electrode being located within the groove, and the trench having an insulating layer.
[0019] In some embodiments of this application, the semiconductor device further includes a reference electrode layer;
[0020] The reference electrode layer is located between the substrate and the memory cell, and is in contact with the first semiconductor layer of each memory cell.
[0021] In some embodiments of this application, the semiconductor device further includes a read bit line located on the side of the memory cell away from the reference electrode layer and connected to the first semiconductor layer;
[0022] The read bit line is provided as a single continuous conductive film layer, or multiple read bit lines are provided at intervals.
[0023] This application also provides a method for manufacturing a semiconductor device, including:
[0024] A stacked structure is obtained by sequentially and alternately depositing a first insulating layer and a second insulating layer on a substrate.
[0025] A first through-hole extending toward the substrate is formed in the stacked structure, and the second insulating layer is laterally etched in the first through-hole to expand the first through-hole toward the second insulating layer.
[0026] A first conductive layer and a gate insulating layer are sequentially formed on the sidewall of the first through hole located in the second insulating layer;
[0027] A first semiconductor layer, a gate insulating layer, and a read line are sequentially formed within the first through-hole;
[0028] A gate insulating layer and a side gate electrode are sequentially formed on the side of the first conductive layer away from the first semiconductor layer;
[0029] A write transistor and a write word line are formed that are connected to the first conductive layer.
[0030] In some embodiments of this application, the step of sequentially forming a first conductive layer and a gate insulating layer on the sidewall of the first via located in the second insulating layer includes:
[0031] The first conductive layer and the sacrificial layer are sequentially formed on the inner wall of the first through hole;
[0032] Remove the sacrificial layer on the sidewall of the first through hole in the first insulating layer to expose the first conductive layer on the sidewall of the first through hole in the first insulating layer.
[0033] Remove the exposed first conductive layer;
[0034] Remove all of the sacrificial layer to expose the first conductive layer located on the sidewall of the first through-hole in the second insulating layer;
[0035] A gate insulating layer is formed on the exposed surface of the first conductive layer.
[0036] In some embodiments of this application, the step of sequentially forming a gate insulating layer and a side gate electrode on the side of the first conductive layer away from the first semiconductor layer includes:
[0037] The stacked structure is etched along the direction toward the substrate to form trenches extending along a second direction parallel to the substrate between two adjacent columns of the first vias spaced apart along a first direction parallel to the substrate, the first direction intersecting the second direction;
[0038] The second insulating layer of the stacked structure is laterally etched in the trench, causing the trench to expand toward the second insulating layer, so that the expanded trench exposes the first conductive layer located in the first through hole of the second insulating layer.
[0039] The gate insulating layer and the second conductive layer are sequentially formed on the inner wall of the trench;
[0040] Remove the second conductive layer on the trench sidewall of the first insulating layer of the stacked structure, and the remaining second conductive layer serves as the side gate electrode;
[0041] The trench is filled with a third insulating layer.
[0042] In some embodiments of this application, the formation of the write transistor and write word line connected to the first conductive layer includes:
[0043] The stacked structure is etched along the direction toward the substrate to form a second via on one side of each first via. The exposed second insulating layer is laterally etched in the second via, so that the second via expands toward the second insulating layer.
[0044] A second semiconductor layer is formed on the inner wall of the second via. The second semiconductor layer located in the second via of the first insulating layer of the stacked structure is removed, so that the second semiconductor layer is disconnected at the first insulating layer of the stacked structure. A gate insulating layer is formed in the second via, and a write line is formed by filling it with conductive material, thereby obtaining the write transistor.
[0045] In some embodiments of this application, before sequentially depositing a first insulating layer and a second insulating layer on a substrate to obtain a stacked structure, the manufacturing method further includes forming a reference electrode layer on the surface of the substrate facing the stacked structure.
[0046] This application also provides an electronic device, which includes the semiconductor device provided in this application, or a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in this application.
[0047] The semiconductor device in this application embodiment designs the read transistor of the memory cell as a double-gate structure. In addition to the read word line formed by the first gate electrode, it also includes a side gate electrode. The double gate does not occupy the area of the memory cell, thereby reducing the area occupied by the memory cell, reducing the link resistance, and enabling multi-bit storage.
[0048] In addition, the semiconductor device of this application embodiment can use a dual-gate to better control the read transistor, so there is no need to remove the parasitic MOS transistor (hereinafter referred to as parasitic MOS) between the read transistors located in different layers. This allows the first semiconductor layer of the read transistors located in different layers to be continuously arranged in a direction perpendicular to the substrate. Since the process of removing the parasitic MOS is eliminated, the manufacturing process of the device is greatly simplified and the manufacturing difficulty of the device is reduced.
[0049] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description
[0050] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0051] Figure 1A A schematic diagram of the cross-sectional structure of a semiconductor device in a horizontal section, which is an exemplary embodiment of this application;
[0052] Figure 1B for Figure 1A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0053] Figure 1C for Figure 1A The diagram shows a longitudinal section of the semiconductor structure on the vertical BB section.
[0054] Figure 2 for Figure 1A The diagram shows the structure of the semiconductor device.
[0055] Figure 3 A process flow diagram of a method for manufacturing a semiconductor device provided as an exemplary embodiment of this application;
[0056] Figure 4 This is a schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a reference electrode layer, on a section perpendicular to the substrate.
[0057] Figure 5 A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after forming a stacked structure, on a section perpendicular to the substrate;
[0058] Figure 6A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application after forming a first through-hole;
[0059] Figure 6B for Figure 6A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0060] Figure 7A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application after expanding a first through-hole;
[0061] Figure 7B for Figure 7A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0062] Figure 8A A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a first conductive layer;
[0063] Figure 8B for Figure 8A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0064] Figure 9A A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after depositing a sacrificial layer in a first via;
[0065] Figure 9B for Figure 9A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0066] Figure 10A A schematic cross-sectional view of a semiconductor device manufacturing method after partial removal of the sacrificial layer, which is an exemplary embodiment of this application;
[0067] Figure 10B for Figure 10A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0068] Figure 11AA schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after removing a portion of the first conductive layer;
[0069] Figure 11B for Figure 11A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0070] Figure 12A A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after all sacrificial layers have been removed, on a horizontal cross-section.
[0071] Figure 12B for Figure 12A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0072] Figure 13 A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after a first insulating layer is formed on the surface of the first conductive layer;
[0073] Figure 14A A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after a semiconductor layer is re-formed in a first via;
[0074] Figure 14B for Figure 14A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0075] Figure 14C A schematic diagram of the longitudinal section structure on the vertical AA section after a semiconductor layer is formed again in the first via, which is an exemplary embodiment of this application;
[0076] Figure 15A A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the first through-hole is filled with a second conductive layer;
[0077] Figure 15B for Figure 15A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0078] Figure 15C This is a schematic diagram of the longitudinal section structure on a vertical AA section after the second conductive layer is filled into the first through-hole, which is an exemplary embodiment of this application.
[0079] Figure 16AThis is a schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method after trench formation, which is an exemplary embodiment of this application.
[0080] Figure 16B for Figure 16A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0081] Figure 16C for Figure 16A The diagram shows a longitudinal section of the semiconductor structure on the vertical BB section.
[0082] Figure 17A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the trench is expanded, on a horizontal cross section;
[0083] Figure 17B for Figure 17A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0084] Figure 17C for Figure 17A The diagram shows a longitudinal section of the semiconductor structure on the vertical BB section.
[0085] Figure 18A A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after a second conductive layer is formed in a trench, on a horizontal cross section;
[0086] Figure 18B for Figure 18A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0087] Figure 18C for Figure 18A The diagram shows a longitudinal section of the semiconductor structure on the vertical BB section.
[0088] Figure 19A This is a schematic diagram of the longitudinal section structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application after removing a portion of the second conductive layer in the trench, on a vertical AA section.
[0089] Figure 19B for Figure 19A The diagram shows a longitudinal section of the semiconductor structure on the vertical BB section.
[0090] Figure 20A A schematic diagram of the cross-sectional structure of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the trench is filled with a third insulating layer;
[0091] Figure 20B for Figure 20A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section.
[0092] Figure 20C for Figure 20A The diagram shows a longitudinal section of the semiconductor structure on the vertical BB section.
[0093] Figure 21A A schematic cross-sectional view of a semiconductor device manufacturing method according to an exemplary embodiment of this application, after the formation of a second through-hole, on a horizontal cross-section;
[0094] Figure 21B for Figure 21A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section. Detailed Implementation
[0095] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.
[0096] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values shown in the drawings.
[0097] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the first semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.
[0098] The ordinal numbers such as "first" and "second" in this application are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.
[0099] In this application, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the application is not limited to the terms described in the disclosure and may be appropriately replaced as appropriate.
[0100] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0101] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.
[0102] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.
[0103] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0104] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0105] In this application, the terms "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".
[0106] The phrase "A and B are arranged in the same layer" in this application refers to A and B being distributed on the same horizontal plane, or although not on the same horizontal plane, both being in different areas of the same supporting surface. One embodiment involves A and B being formed simultaneously on the same film layer using the same patterning process.
[0107] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.
[0108] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functions or circuits are already distributed. The device involved in the inventive construction of the embodiments of this application is disposed on the main surface of the support structure.
[0109] In this application, the spacing distribution can be understood as a separate distribution, which can be achieved through physical structural breaks or electrical characteristic breaks. For example, the first semiconductor layer between the effective channels of two transistors is modified to achieve insulation, thereby realizing the electrical spacing between the two channels.
[0110] This application provides a semiconductor device. Figure 1A A schematic diagram of the cross-sectional structure of a semiconductor device in a horizontal section, which is an exemplary embodiment of this application; Figure 1B for Figure 1A The diagram shows a longitudinal section of the semiconductor structure on the vertical AA section. Figure 1C for Figure 1A The diagram shows a longitudinal section of the semiconductor structure on the vertical BB section. Figure 2 for Figure 1A The diagram shows the structure of the semiconductor device.
[0111] like Figures 1A to 2 As shown, the semiconductor device includes: a plurality of memory cells 100, read word lines RWL, write word lines WWL, a first semiconductor layer 14, a plurality of second semiconductor layers 17, a first gate electrode 31, and a side gate electrode 30;
[0112] Multiple memory cells 100 are distributed in different layers and stacked along a direction perpendicular to the substrate 10;
[0113] Both the read line RWL and the write line WWL extend in a direction perpendicular to the substrate 10 and penetrate the memory cells 100 of different layers;
[0114] The first semiconductor layer 14 and the plurality of second semiconductor layers 17 both extend in a direction perpendicular to the substrate 10. The first semiconductor layer 14 at least partially surrounds the read word line RWL, and the second semiconductor layers 17 at least partially surround the write word line WWL. The first semiconductor layer 14 is continuously disposed in a direction perpendicular to the substrate 10, and the plurality of second semiconductor layers 17 are spaced apart and disconnected in a direction perpendicular to the substrate 10. A first conductive layer 13 is provided between the first semiconductor layer 14 and the second semiconductor layers 17.
[0115] The first gate electrode 31 and the side gate electrode 30 are located on both sides of the first semiconductor layer 14, respectively; the first gate electrode 31 is part of the read word line RWL; a first conductive layer 13 is provided between the side gate electrode 30 and the first semiconductor layer 14; a gate insulating layer 33 is provided between the side gate electrode 30 and the first conductive layer 13, between the first conductive layer 13 and the first semiconductor layer 14, between the first semiconductor layer 14 and the read word line RWL, and between the second semiconductor layer 17 and the write word line WWL.
[0116] The side gate electrode 30, the first conductive layer 13 near the side gate electrode 30, and the gate insulating layer 33 between the first conductive layer 13 and the side gate electrode 30 can constitute a storage node SN for storing charge.
[0117] The semiconductor device in this application embodiment designs the read transistor of the memory cell as a double-gate structure. In addition to the read word line formed by the first gate electrode, it also includes a side gate electrode. The double gate does not occupy additional area of the memory cell. For example, the side gate electrode in the double gate can be integrated into the insulating layer on the side of the read transistor away from the write transistor in the memory cell, without the need to set a separate location for the side gate electrode.
[0118] In addition, the semiconductor device of this application embodiment can use a dual-gate to better control the read transistor, so there is no need to remove the parasitic MOS transistor (hereinafter referred to as parasitic MOS) between the read transistors located in different layers. This allows the first semiconductor layer of the read transistors located in different layers to be continuously arranged in a direction perpendicular to the substrate. Since the process of removing the parasitic MOS is eliminated, the manufacturing process of the device is greatly simplified and the manufacturing difficulty of the device is reduced.
[0119] The control principle of the dual-gate read transistor is as follows: When reading data, an enable signal is applied to the read word line RWL and side gate electrode corresponding to the memory cell to be accessed, while a non-select signal is applied to the side gate electrode corresponding to other memory cells. At this time, the read transistor R_Tr in the memory cell corresponding to the dual-gate selection is turned on, and its corresponding parasitic MOS transistor is also turned on. The read transistors corresponding to other memory cells are turned off. However, the resistance of the parasitic MOS transistor in the turned-on state is small and can be regarded as a wire. Therefore, the dual-gate structure of this application effectively reduces the parasitic resistance during data reading. When the enable signal is stopped from being applied to the read word line RWL or when no enable signal is applied to the read word line RWL and side gate electrode, the dual-gate is non-selected, and the read transistor R_Tr and its parasitic MOS transistor are turned off. The resistance of the parasitic MOS transistor in the turned-off state is large, which hinders the current from passing through the parasitic MOS transistor. Therefore, extremely low leakage current of the link in the non-read state can be achieved. In addition, the link resistance can be efficiently reduced by adjusting the ratio of the channel resistance of the parasitic MOS transistor and the channel resistance of the read transistor R_Tr on the link. Furthermore, the storage node SN can not only store charge but also be viewed as the floating gate of the read transistor (similar to a 3D NAND structure). Different amounts of charge stored in SN are equivalent to applying different voltages to SN, i.e., applying different voltages to the floating gate of the read transistor R_Tr. This modulates the read transistor R_Tr, resulting in the reading of different currents. Based on the different current readings, it can be determined whether the charge stored in the storage node SN is multi-bit. Therefore, the semiconductor device of this application can read and distinguish multi-bit data.
[0120] Furthermore, the dual-gate control capability of the readout transistor can be adjusted, for example, by adjusting parameters such as the material / growth conditions / thickness / doping of the channel, the material / growth conditions / thickness of the gate insulating layer, and the material / growth conditions / thickness / doping of the gate electrode.
[0121] In some embodiments of this application, such as Figure 1B As shown, the first semiconductor layer 14 includes a plurality of channels 141 spaced apart along a direction perpendicular to the substrate 10 and a connection portion 142 connecting two adjacent channels 141. The channels 141 extend along a direction perpendicular to the substrate 10 and a horizontal direction, and the connection portion 142 extends along a direction perpendicular to the substrate 10. The orthographic projection of the connection portion 142 on the substrate 10 falls within the range of the orthographic projection of the channel 141 on the substrate 10.
[0122] In some embodiments of this application, such as Figure 1B As shown, the thickness of the channel 141 is greater than the thickness of the second semiconductor layer 17.
[0123] In some embodiments of this application, such as Figure 1BAs shown, the first conductive layer 13 at least partially surrounds the channel 141, the first conductive layer 13 is present between the channel 141 and the second semiconductor layer 17, and the first conductive layer 13 is present between the channel 141 and the side gate electrode 30.
[0124] In some embodiments of this application, such as Figure 1A , Figure 1B and Figure 2 As shown, the storage cell 100 includes a read transistor R_Tr and a write transistor W_Tr; wherein,
[0125] The read transistor R_Tr includes a channel 141, a first gate electrode 31, and a side gate electrode 30. The channel 141 at least partially surrounds the first gate electrode 31, which is part of the read word line RWL.
[0126] The write transistor W_Tr includes a second semiconductor layer 17 and a second gate electrode 32, the second semiconductor layer 17 at least partially surrounding the second gate electrode 32, the second gate electrode 32 being part of the write word line WWL.
[0127] In some embodiments of this application, such as Figure 1B and Figure 1C As shown, the side gate electrodes 30 of a column of read transistors R_Tr located on the same layer and spaced apart in a second direction parallel to the substrate 10 are a single-piece structure, meaning the side gate electrodes 30 can extend along the second direction. The second direction can also be called the column direction, and can be as follows: Figure 1A Y direction shown.
[0128] In some embodiments of this application, such as Figures 1A to 1C As shown, the semiconductor device may further include a trench 16 located between two adjacent rows of memory cells 100 in a first direction parallel to the substrate. The trench 16 includes a recess 161 extending along the first direction toward the first conductive layer 13. A side gate electrode 30 is located within the recess 161. Other areas of the trench 16 are filled with an insulating layer, such as... Figures 1A to 1C The third insulating layer 18 shown has a first insulating layer 11 between two adjacent side gate electrodes 30 in a direction perpendicular to the substrate; the material of the third insulating layer 18 can be the same as the material of the first insulating layer 11. In this application, the side gate electrodes 30 are disposed between the first insulating layers 11 that separate two adjacent memory cells, so the placement of the side gate electrodes 30 does not increase the occupied area of the memory cells.
[0129] In some embodiments of this application, such as Figures 1A to 2As shown, the write transistor may include a first electrode 21 and a second electrode 22 located on both sides of the second semiconductor layer 17. One of the first electrode 21 and the second electrode 22 is a source electrode, and the other is a drain electrode. For example, the first electrode 21 is the source electrode, and the second electrode 22 is the drain electrode. The first electrode 21 is connected to the write bit line WBL, and the first electrode 21 and the write bit line WBL can be an integral structure. The first conductive layer 13 may include the second electrode 22.
[0130] In such Figures 1A to 1C In the semiconductor device shown, a first semiconductor layer 14, in which a plurality of read transistors R_Tr are stacked in a direction perpendicular to the substrate 10, is connected at one end to a reference electrode layer (GND, also known as a common source line) 20, and at the other end to a read bit line RBL (not shown in the figure).
[0131] In some embodiments of this application, the semiconductor device further includes a read bit line located on the side of the memory cell away from the reference electrode layer and connected to the first semiconductor layer; wherein, only one read bit line is provided, and the read bit line is a continuous conductive film layer, or multiple read bit lines are provided at intervals.
[0132] In embodiments of this application, a first semiconductor layer 14 at least partially surrounds the read word line RWL, and a second semiconductor layer 17 at least partially surrounds the write word line WWL. Here, "surround" can be understood as partially surrounding or completely surrounding. In some embodiments, the surrounding can be completely surrounding, that is, the entire sidewall of the word line is surrounded by the semiconductor layer, and the cross-section of the semiconductor layer after surrounding is a closed ring. The cross-section is taken along the horizontal direction. In some embodiments, the surrounding can be partially surrounding, that is, part of the sidewall of the word line is surrounded by the semiconductor layer, and the cross-section after surrounding is not closed, but presents a ring shape. For example, a ring with openings or two separate semiconductor layers. For example, opposite side surfaces of the word line are surrounded by semiconductor layers, in which case the cross-section of the semiconductor layer is a ring with two openings.
[0133] In the description of this application, "around" refers to the semiconductor layer surrounding the word line in the circumferential direction, rather than surrounding it in a direction perpendicular to the substrate.
[0134] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized, but only its function is emphasized.
[0135] For example, the materials of the first semiconductor layer and the second semiconductor layer can be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or wide band gap materials, such as metal oxide materials with a band gap of greater than 1.65 eV.
[0136] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.
[0137] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.
[0138] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.
[0139] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.
[0140] For example, the materials of the read bit line and the write bit line can each be independently selected from any one or more other metallic materials with similar properties, such as tungsten, molybdenum, and cobalt. The read bit line and the write bit line can each be independently a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).
[0141] In some embodiments of this application, the electrode materials of the first gate electrode, the second gate electrode, and the side gate electrode can each be independently selected from any one or more of the following different types of materials:
[0142] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.
[0143] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), and other metal oxide materials with high conductivity; such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.
[0144] Of course, it can also be polycrystalline silicon; it can also be a conductive material doped with a semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; and other materials that exhibit conductivity, etc.
[0145] In some embodiments of this application, the gate insulating layer may comprise one or more Low-K and / or High-K dielectric materials, or comprise two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of this application will be illustrated below by way of example.
[0146] Low-K materials, such as silicon oxide.
[0147] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, they may include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.
[0148] For example, the semiconductor device can be a 3D memory, such as a 3D DRAM. The 3D memory can be a 2TOC structure.
[0149] This application also provides a method for manufacturing a semiconductor device, and the semiconductor device described in the above embodiment can be manufactured by this method.
[0150] Figure 3 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application.
[0151] like Figure 3 As shown, the manufacturing method includes:
[0152] A stacked structure is obtained by sequentially and alternately depositing a first insulating layer and a second insulating layer on a substrate.
[0153] A first through-hole extending toward the substrate is formed in the stacked structure, and the second insulating layer is laterally etched in the first through-hole to expand the first through-hole toward the second insulating layer.
[0154] A first conductive layer and a gate insulating layer are sequentially formed on the sidewall of the first through hole located in the second insulating layer;
[0155] A first semiconductor layer, a gate insulating layer, and a read line are sequentially formed within the first through-hole;
[0156] A gate insulating layer and a side gate electrode are sequentially formed on the side of the first conductive layer away from the first semiconductor layer;
[0157] A write transistor and a write word line are formed that are connected to the first conductive layer.
[0158] In some embodiments of this application, the step of sequentially forming a first conductive layer and a gate insulating layer on the sidewall of the first via located in the second insulating layer includes:
[0159] The first conductive layer and the sacrificial layer are sequentially formed on the inner wall of the first through hole;
[0160] Remove the sacrificial layer on the sidewall of the first through hole in the first insulating layer to expose the first conductive layer on the sidewall of the first through hole in the first insulating layer.
[0161] Remove the exposed first conductive layer;
[0162] Remove all of the sacrificial layer to expose the first conductive layer located on the sidewall of the first through-hole in the second insulating layer;
[0163] A gate insulating layer is formed on the exposed surface of the first conductive layer.
[0164] In some embodiments of this application, the step of sequentially forming a gate insulating layer and a side gate electrode on the side of the first conductive layer away from the first semiconductor layer includes:
[0165] The stacked structure is etched along the direction toward the substrate to form trenches extending along a second direction parallel to the substrate between two adjacent columns of the first vias spaced apart along a first direction parallel to the substrate, the first direction intersecting the second direction;
[0166] The second insulating layer of the stacked structure is laterally etched in the trench, causing the trench to expand toward the second insulating layer, so that the expanded trench exposes the first conductive layer located in the first through hole of the second insulating layer.
[0167] The gate insulating layer and the second conductive layer are sequentially formed on the inner wall of the trench;
[0168] Remove the second conductive layer on the trench sidewall of the first insulating layer of the stacked structure, and the remaining second conductive layer serves as the side gate electrode;
[0169] The trench is filled with a third insulating layer.
[0170] In some embodiments of this application, the formation of the write transistor and write word line connected to the first conductive layer includes:
[0171] The stacked structure is etched along the direction toward the substrate to form a second via on one side of each first via. The exposed second insulating layer is laterally etched in the second via, so that the second via expands toward the second insulating layer.
[0172] A second semiconductor layer is sequentially formed on the inner wall of the second via. The second semiconductor layer located in the second via of the first insulating layer of the stacked structure is removed, so that the second semiconductor layer is disconnected at the first insulating layer of the stacked structure. A gate insulating layer is formed in the second via, and a write line is formed by filling it with conductive material, thereby obtaining the write transistor.
[0173] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.
[0174] like Figures 4 to 21B As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.
[0175] S10: Provide a substrate 10, in which an exposed reference electrode layer 20 is formed, such as Figure 4 As shown.
[0176] S20: A first insulating layer 11 and a second insulating layer 12 are sequentially and alternately deposited on the substrate 10 to obtain a stacked structure composed of multiple first insulating layers 11 and multiple second insulating layers 12; wherein, the bottommost first insulating layer 11 is in contact with the reference electrode layer 20, such as... Figure 5 As shown.
[0177] In some embodiments of this application, the material forming the first insulating layer can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing films.
[0178] For example, the material of the second insulating layer can be any one or more of silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN), and the materials of the second insulating layer and the first insulating layer are different so that when one of the first insulating layer and the second insulating layer is subsequently etched away, the first insulating layer and the second insulating layer can have different etching rates, thereby removing the desired insulating layer. For example, in this embodiment, the material of the first insulating layer can be silicon oxide, and the material of the second insulating layer can be silicon nitride.
[0179] Figure 5 The stacked structure shown includes three first insulating layers 11 and two second insulating layers 12. This is only an example. In other embodiments, the stacked structure may include more or fewer alternating layers of first insulating layers 11 and second insulating layers 12.
[0180] S30: Along the direction toward the substrate 10, a first via K1 is etched in the stacked structure to form a first via K1, exposing the reference electrode layer 20, as shown. Figure 6A and Figure 6B As shown.
[0181] For example, such as Figure 6A As shown, a plurality of first vias K1 can be formed in the stacked structure, distributed in an array along a first direction and a second direction parallel to the substrate 10. The plurality of first vias K1 are spaced apart, and the first direction intersects the second direction. For example, the first direction and the second direction can be perpendicular to each other. The first direction can also be referred to as the row direction, and can be as follows: Figure 6A The X direction is shown; the second direction can also be called the column direction, and can be as follows: Figure 6A The Y direction is shown. Multiple components distributed along the first direction can be referred to as a row of components, for example, a row of first through holes K1; multiple components distributed along the second direction can be referred to as a column of components, for example, a column of first through holes K1.
[0182] For example, the first via K1 may be perpendicular to the substrate 10.
[0183] S40: Laterally etch the second insulating layer 12 within the first through-hole K1, causing the first through-hole K1 to expand toward the second insulating layer 12, such as... Figure 7A and Figure 7B As shown. Among them, Figure 7AThe dashed box in the figure represents the outer contour of the expanded first through hole K1 within the second insulating layer 12.
[0184] S50: A first conductive layer 13 is deposited on the inner wall (including the sidewall and bottom wall) of the first through hole K1, such as... Figure 8A and Figure 8B As shown.
[0185] For example, the first conductive layer 13 can be a conductive material containing metal, or for example, a multilayer structure of tungsten (W) or titanium nitride (TiN) and W.
[0186] S60: A sacrificial layer 19 is deposited on the inner wall (including the sidewalls and bottom wall) of the first through hole K1, such as... Figure 9A and Figure 9B As shown.
[0187] like Figure 9A and Figure 9B As shown, the sacrificial layer 19 may not completely fill the first through hole K1.
[0188] For example, the material of the sacrificial layer 19 is different from the materials of the first conductive layer 13 and the first insulating layer 11, so that when the sacrificial layer 19 is subsequently etched away, the etching rate of the sacrificial layer 19 is different from that of the first conductive layer 13 and the first insulating layer 11, thus avoiding damage to the first conductive layer 13 and the first insulating layer 11. For example, the material of the sacrificial layer 19 can be polycrystalline silicon, aluminum oxide (e.g., Al2O3), etc.
[0189] S70: Etching removes the sacrificial layer 19 located on the sidewall of the first through-hole K1 in the first insulating layer 11, exposing the first conductive layer 13 located on the sidewall of the first through-hole K1 in the first insulating layer 11, such as... Figure 10A and Figure 10B As shown. Among them, Figure 10A The dashed box in the figure represents the first conductive layer 13 located on the sidewall of the first through-hole K1 in the second insulating layer 12. (The following text...) Figure 11A , Figure 12A , Figures 14A to 18A , Figure 20A The meaning of the dashed box in the middle and Figure 10A same.
[0190] S80: Etching removes the first conductive layer 13 located on the sidewall of the first through-hole K1 in the first insulating layer 11, exposing the first insulating layer 11, such as Figure 11A and Figure 11B As shown.
[0191] S90: Etch away all of the sacrificial layer 19, exposing the first conductive layer 13 located on the sidewall of the first via K1 in the second insulating layer 12, such as Figure 12A and Figure 12B As shown.
[0192] S100: A gate insulating layer 33 (e.g., formed using the same material as the first insulating layer 11) is deposited on the exposed surface of the first conductive layer 13, and the gate insulating layer 33 is made to wrap around the end face of the first conductive layer 13 to prevent the first conductive layer 13 from contacting the subsequently deposited first semiconductor layer 14, such as... Figure 13 As shown. Figure 13 The schematic diagram of the cross-sectional structure of the device structure shown in the horizontal section is similar to... Figure 12A same.
[0193] S110: A first semiconductor layer 14 is deposited again on the inner wall of the first via K1, such that the first semiconductor layer 14 covers the first insulating layer 11 and the gate insulating layer 33 that were originally exposed by the first via K1, as shown. Figure 14A and Figure 14B As shown.
[0194] S120: Deposit a gate insulating layer 33 (e.g., it can be formed using the same material as the first insulating layer) on the sidewall of the first via K1, and fill the first via K1 with a second conductive layer 15, such as... Figure 15A and Figure 15B As shown.
[0195] In other embodiments, step S110 may form a structure having, as shown in the figure Figure 14C The first semiconductor layer 14 has the shape shown; at this time, the gate insulating layer 33 and the second conductive layer 15 formed in step S120 are as follows: Figure 15C As shown.
[0196] For example, such as Figure 15B and Figure 15C As shown, the material of the second conductive layer 15 can be the same as the material of the reference electrode layer 20. For example, both can be conductive materials containing metals, or for example, a multilayer structure of tungsten (W) or titanium nitride (TiN) and W. For example, in one embodiment, the material of the first conductive layer 13 can be TiN, and the material of the second conductive layer 15 can be a bilayer structure of TiN and W.
[0197] S130: The stacked structure is etched along the direction toward the substrate 10 to form trenches 16 extending along the second direction between two adjacent columns of first vias K1 spaced apart along the first direction. The trenches 16 expose the reference electrode layer 20. Figures 16A to 16C As shown. The sidewalls of the trench 16 alternately expose the first insulating layer 11 and the second insulating layer 12 of the stacked structure in a direction perpendicular to the substrate.
[0198] For example, the trench 16 may be perpendicular to the substrate 10.
[0199] S140: Laterally etch the second insulating layer 12 within the trench 16, causing the trench 16 to expand towards the second insulating layer 12 to form a groove 161. The expanded trench 16 exposes the first conductive layer 13 located within the first through-hole K1 of the second insulating layer 12. Figures 17A to 17C As shown. Among them, Figure 17A The dashed line in the diagram represents the outer contour of the expanded trench 16 in the second insulating layer 12. (The following text...) Figure 18A , Figure 20A and Figure 21A The meaning of the straight line shown by the dashed line in the middle is the same as... Figure 17A same.
[0200] S150: A gate insulating layer 33 (e.g., formed using the same material as the first insulating layer 11) and a second conductive layer 15 are sequentially deposited on the inner wall (including the sidewalls and bottom wall) of the trench 16, such as... Figures 18A to 18C As shown.
[0201] S160: Etching removes the second conductive layer 15 located on the sidewall of the trench 16 of the first insulating layer 11, exposing the first insulating layer 11 of the stacked structure, such as Figure 19A and Figure 19B As shown. Figure 19A and Figure 19B The schematic diagram of the cross-sectional structure of the device structure shown in the horizontal section is similar to... Figure 17A same, Figure 19A AA section and Figure 19B The location of the BB section in the middle and Figure 17A same.
[0202] S170: Fill the trench 16 with the third insulating layer 18, such as Figures 20A to 20C As shown.
[0203] For example, the material of the third insulating layer 18 may be the same as or different from the material of the first insulating layer 11, and the material of the third insulating layer 18 may be the same as or different from the material of the second insulating layer 12. For example, the material of the third insulating layer 18 may be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN).
[0204] S180: Form a write transistor W_Tr connected to the first conductive layer 13.
[0205] For example, step S180 may include:
[0206] S181: The stacked structure is etched along the direction toward the substrate 10, forming a second via K2 on one side of each first via K1. The sidewalls of the second via K2 expose the first insulating layer 11 and the second insulating layer 12 alternately. Laterally etch the exposed second insulating layer 12 within the second via K2, causing the second via K2 to expand toward the second insulating layer 12. The expanded second via K2 exposes the first conductive layer 13 located on the sidewall of the first via K1 in the second insulating layer 12. Figure 21A and Figure 21B As shown. Figure 21A The thick dashed box in the figure represents the first conductive layer 13 located on the side wall of the first through hole K1 in the second insulating layer 12, and the thin dashed box represents the outer contour of the expanded second through hole K2 in the second insulating layer 12.
[0207] S182: A second semiconductor layer 17 is formed on the inner wall of the second via K2. The second semiconductor layer 17 located within the second via K2 of the first insulating layer 11 of the stacked structure is removed, causing the second semiconductor layer 17 to be disconnected at the first insulating layer 11 of the stacked structure, i.e., the parasitic MOS is removed. A gate insulating layer 33 (e.g., it can be formed using the same material as the first insulating layer 11) is formed within the second via K2, and a write word line WWL is formed by filling it with conductive material, thus obtaining the write transistor W_Tr. Figures 1A to 1C As shown.
[0208] In addition, after forming the write transistor, a write bit line can be formed on the side of the write transistor away from the read transistor, and a read bit line can be formed on the side of the memory cell away from the substrate.
[0209] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.
Claims
1. A semiconductor device, characterized in that, include: Multiple memory cells are distributed across different layers and stacked along a direction perpendicular to the substrate; Read and write lines of the memory cells extending in a direction perpendicular to the substrate and penetrating different layers; A first semiconductor layer and a plurality of second semiconductor layers extend in a direction perpendicular to the substrate, the first semiconductor layer at least partially surrounding the read line and the second semiconductor layers at least partially surrounding the write line; the first semiconductor layer is continuously disposed in a direction perpendicular to the substrate, and the plurality of second semiconductor layers are spaced apart and disconnected in a direction perpendicular to the substrate; a first conductive layer is provided between the first semiconductor layer and the second semiconductor layers; A first gate electrode and a side gate electrode are respectively located on both sides of the first semiconductor layer; the first gate electrode is part of the read word line; a first conductive layer is provided between the side gate electrode and the first semiconductor layer; a gate insulating layer is provided between the side gate electrode and the first conductive layer, between the first conductive layer and the first semiconductor layer, and between the first semiconductor layer and the gate electrode.
2. The semiconductor device according to claim 1, characterized in that, The first semiconductor layer includes a plurality of channels spaced apart along a direction perpendicular to the substrate and a connection portion connecting two adjacent channels. The channels extend along a direction perpendicular to the substrate and a horizontal direction, and the connection portion extends along a direction perpendicular to the substrate. The orthographic projection of the connection portion on the substrate falls within the range of the orthographic projection of the channel on the substrate.
3. The semiconductor device according to claim 2, characterized in that, The thickness of the film layer in the channel is greater than the thickness of the second semiconductor layer.
4. The semiconductor device according to claim 3, characterized in that, The first conductive layer at least partially surrounds the channel, and the first conductive layer is present between the channel and the second semiconductor layer, and between the channel and the side gate electrode.
5. The semiconductor device according to any one of claims 2 to 4, characterized in that, The storage unit includes a read transistor and a write transistor; wherein... The read transistor includes the channel, the first gate electrode, and the side gate electrode, the channel at least partially surrounding the first gate electrode, the first gate electrode being a portion of the read word line; and / or The write transistor includes a second semiconductor layer and a second gate electrode, the second semiconductor layer at least partially surrounding the second gate electrode, and the second gate electrode being part of the write word line.
6. The semiconductor device according to claim 5, characterized in that, The side gate electrodes of the read transistors, which are located on the same layer and spaced apart in a second direction parallel to the substrate, are a single-piece structure.
7. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes trenches located between two adjacent rows of memory cells in a first direction parallel to the substrate, the trenches extending along a second direction parallel to the substrate and a direction perpendicular to the substrate, the trenches including grooves extending toward the first conductive layer along the first direction, the side gate electrodes being located within the grooves, and the trenches having an insulating layer.
8. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes a reference electrode layer; The reference electrode layer is located between the substrate and the memory cell, and is in contact with the first semiconductor layer of each memory cell.
9. The semiconductor device according to claim 8, characterized in that, It also includes read lines, which are located on the side of the memory cell away from the reference electrode layer and are connected to the first semiconductor layer; The read bit line is provided only once, and the read bit line is a continuous conductive film layer, or multiple read bit lines are provided at intervals.
10. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure is obtained by sequentially and alternately depositing a first insulating layer and a second insulating layer on a substrate. A first through-hole extending toward the substrate is formed in the stacked structure, and the second insulating layer is laterally etched in the first through-hole to make the first through-hole expand toward the second insulating layer. A first conductive layer and a gate insulating layer are sequentially formed on the sidewall of the first through-hole located in the second insulating layer; A first semiconductor layer, a gate insulating layer, and a read line are sequentially formed within the first through-hole; A gate insulating layer and a side gate electrode are sequentially formed on the side of the first conductive layer away from the first semiconductor layer; A write transistor and a write word line are formed that are connected to the first conductive layer.
11. The manufacturing method according to claim 10, characterized in that, The step of sequentially forming a first conductive layer and a gate insulating layer on the sidewall of the first through-hole located in the second insulating layer includes: The first conductive layer and the sacrificial layer are sequentially formed on the inner wall of the first through hole; Remove the sacrificial layer on the sidewall of the first through hole in the first insulating layer to expose the first conductive layer on the sidewall of the first through hole in the first insulating layer. Remove the exposed first conductive layer; Remove all of the sacrificial layer to expose the first conductive layer located on the sidewall of the first through-hole in the second insulating layer; A gate insulating layer is formed on the exposed surface of the first conductive layer.
12. The manufacturing method according to claim 10, characterized in that, The step of sequentially forming a gate insulating layer and a side gate electrode on the side of the first conductive layer away from the first semiconductor layer includes: The stacked structure is etched along the direction toward the substrate to form trenches extending along a second direction parallel to the substrate between two adjacent columns of the first vias spaced apart along a first direction parallel to the substrate, the first direction intersecting the second direction; The second insulating layer of the stacked structure is laterally etched in the trench, causing the trench to expand toward the second insulating layer, so that the expanded trench exposes the first conductive layer located in the first through hole of the second insulating layer. The gate insulating layer and the second conductive layer are sequentially formed on the inner wall of the trench; Remove the second conductive layer on the trench sidewall of the first insulating layer of the stacked structure, and the remaining second conductive layer serves as the side gate electrode; The trench is filled with a third insulating layer.
13. The manufacturing method according to any one of claims 10 to 12, characterized in that, The write transistor and write word line connected to the first conductive layer include: The stacked structure is etched along the direction toward the substrate to form a second via on one side of each first via. The exposed second insulating layer is laterally etched in the second via, so that the second via expands toward the second insulating layer. A second semiconductor layer is formed on the inner wall of the second via. The second semiconductor layer located in the second via of the first insulating layer of the stacked structure is removed, so that the second semiconductor layer is disconnected at the first insulating layer of the stacked structure. A gate insulating layer is formed in the second via, and a write line is formed by filling it with conductive material, thereby obtaining the write transistor.
14. The manufacturing method according to claim 10, characterized in that, Before obtaining the stacked structure by sequentially and alternately depositing a first insulating layer and a second insulating layer on the substrate, the process further includes: A reference electrode layer is formed on the surface of the substrate facing the stacked structure.
15. An electronic device, characterized in that, The semiconductor device includes any one of claims 1 to 9, or a semiconductor device manufactured by the method of manufacturing a semiconductor device according to any one of claims 10 to 14.