Memory device and forming method thereof

Abstract

The invention discloses a memory device and a forming method thereof. The active strip-shaped column is located on the substrate and comprises a first region and a second region, and an isolation gap is formed between the first region and the second region; the isolation column is located in the active strip-shaped column and divides the second region into a first channel part and a second channel part, and the isolation gap exposes the isolation column; the isolation layer is located on the substrate, and the isolation gaps in the active strip-shaped columns are filled with the isolation layer; and a plurality of memory cells formed based on the second region. The first channel part and the second channel part are electrically isolated through the isolation column, so that direct crosstalk paths of channels on different sides are cut off, and crosstalk generated between the channels on the different sides can be effectively prevented. In addition, after the isolation gaps are filled with the isolation layers, an indirect crosstalk path formed by electrons bypassing the isolation columns from the first region can be cut off, and connection between the first channel part and the substrate and connection between the second channel part and the substrate can be cut off, so that the problem of electric leakage of the substrate is avoided, and the reliability of the electrical performance of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory device and a method for forming the same. Background Technology

[0002] Non-volatile memory (NVM) is a storage technology that retains data even after power is lost, and it is widely used in computer systems, embedded devices, and mobile terminals. Its main difference from volatile memory (such as dynamic random access memory, DRAM) lies in the persistence of data.

[0003] Common non-volatile memories include flash memory, hard disk storage, and read-only memory (ROM). Flash memory is one of the most widely used non-volatile memories, found in devices such as USB flash drives, solid-state drives (SSDs), and smartphones. Flash memory is mainly divided into two types: NOR flash memory and NAND flash memory. NOR flash memory supports random access, has a fast read speed, and is suitable for storing directly executable code, often used in the boot programs of embedded systems. Its structure is similar to traditional semiconductor memory, with each memory cell connected to the address and data buses for easy direct reading. NAND flash memory is characterized by high storage density and fast write and erase speeds. It uses a block storage method, and data must be read and written in blocks, making it unsuitable for random access. Its memory cell connection method is more complex, but it has a large capacity and low cost, making it suitable for large-capacity storage needs.

[0004] However, existing flash memory devices still have many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a storage device and a method for forming the same, so as to improve the reliability of the device's electrical performance.

[0006] To address the aforementioned problems, the present invention provides a storage device comprising: a substrate; a plurality of active strip pillars arranged parallel to each other along a first direction on the substrate, the active strip pillars extending along a second direction, the first direction being perpendicular to the second direction, each active strip pillar including a first region and a second region located on the first region, the first region and the second region having an isolation gap; isolation pillars located within the active strip pillars, the isolation pillars extending along the second direction to divide the second region into a first channel portion and a second channel portion arranged along the first direction, the isolation pillars extending into the first region to support the second region, the isolation gap exposing the isolation pillars; an isolation layer located on the substrate, the isolation layer covering the first region of the active strip pillars and filling the isolation gap in the active strip pillars; and a plurality of storage cells formed based on the second region, the storage cells being located on the isolation layer.

[0007] Optionally, the first channel portion is located on a first side of the active strip post, and the second channel portion is located on a second side of the active strip post; the plurality of storage units include: a plurality of first storage units and a plurality of second storage units; wherein, the first storage units are located on the first side and cover a portion of the sidewall of the first channel portion; the second storage units are located on the second side and cover a portion of the sidewall of the second channel portion.

[0008] Optionally, the first storage cell includes: a first charge storage section, the first charge storage section covering a portion of the sidewall of the first channel section; a first control gate structure, the first control gate structure extending along the first direction and covering the surface of the first charge storage section; and a first word line gate structure, the first word line gate structure extending along the first direction and adjacent to the first charge storage section along the second direction, the first word line gate structure covering a portion of the sidewall of the first channel section, for controlling the on / off state of the first channel section.

[0009] Optionally, the first charge storage unit includes a floating gate structure or an ONO structure.

[0010] Optionally, the second storage cell includes: a second charge storage section covering a portion of the sidewall of the second channel section; a second control gate structure extending along the first direction and covering the surface of the second charge storage section; and a second word line gate structure extending along the first direction and adjacent to the second charge storage section along the second direction, the second word line gate structure covering a portion of the sidewall of the second channel section for controlling the on / off state of the second channel section.

[0011] Optionally, the second charge storage unit includes a floating gate structure or an ONO structure.

[0012] Optionally, the material of the isolation pillar includes silicon oxide or silicon nitride.

[0013] Accordingly, the present invention also provides a method for forming a memory device, comprising: providing a substrate; forming a plurality of active strip pillars arranged in parallel along a first direction on the substrate, the active strip pillars extending along a second direction, the first direction being perpendicular to the second direction, the active strip pillars including a first region and a second region located on the first region, the first region and the second region having an isolation gap; forming an isolation pillar within the active strip pillars, the isolation pillars extending along the second direction to divide the second region into a first channel portion and a second channel portion arranged along the first direction, the isolation pillars extending into the first region to support the second region, the isolation gap exposing the isolation pillars; forming an isolation layer on the substrate, the isolation layer covering the first region of the active strip pillars and filling the isolation gap in the active strip pillars; forming a plurality of memory cells based on the second region, the memory cells being located on the isolation layer.

[0014] Optionally, the method for forming the active bar pillar includes: forming a sacrificial layer on the substrate; forming a channel layer on the sacrificial layer; performing patterned etching on the channel layer, the sacrificial layer, and the substrate to form an initial active bar pillar; removing the sacrificial layer so that the initial active bar pillar forms the active bar pillar; wherein the opening formed by removing the sacrificial layer is the isolation gap, the substrate forms the first region, and the channel layer forms the second region.

[0015] Optionally, the material of the sacrificial layer is different from the material of the channel layer.

[0016] Optionally, the sacrificial layer is made of silicon-germanium; the channel layer is made of silicon.

[0017] Optionally, the first channel portion is located on a first side of the active strip post, and the second channel portion is located on a second side of the active strip post; the plurality of storage units include: a plurality of first storage units and a plurality of second storage units; wherein, the first storage units are located on the first side and cover a portion of the sidewall of the first channel portion; the second storage units are located on the second side and cover a portion of the sidewall of the second channel portion.

[0018] Optionally, the first storage cell includes: a first charge storage section, the first charge storage section covering a portion of the sidewall of the first channel section; a first control gate structure, the first control gate structure extending along the first direction and covering the surface of the first charge storage section; and a first word line gate structure, the first word line gate structure extending along the first direction and adjacent to the first charge storage section along the second direction, the first word line gate structure covering a portion of the sidewall of the first channel section, for controlling the on / off state of the first channel section.

[0019] Optionally, the first charge storage unit includes a floating gate structure or an ONO structure.

[0020] Optionally, the second storage cell includes: a second charge storage section covering a portion of the sidewall of the second channel section; a second control gate structure extending along the first direction and covering the surface of the second charge storage section; and a second word line gate structure extending along the first direction and adjacent to the second charge storage section along the second direction, the second word line gate structure covering a portion of the sidewall of the second channel section for controlling the on / off state of the second channel section.

[0021] Optionally, the second charge storage unit includes a floating gate structure or an ONO structure.

[0022] Optionally, the material of the isolation pillar includes silicon oxide or silicon nitride.

[0023] Optionally, the method for forming the isolation layer includes: forming an isolation material film on the substrate, the isolation material film covering the active strip pillar; planarizing the isolation material film to form an initial isolation layer; and performing a back etching process on the initial isolation layer to form the isolation layer.

[0024] Optionally, after forming the isolation layer, the method further includes: performing ion implantation on the active strip to adjust the channel threshold voltage.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the storage device of the present invention, the isolation pillar located within the active strip pillar electrically isolates the first channel portion and the second channel portion, thereby cutting off the direct crosstalk path between different side channels and effectively preventing crosstalk between different side channels. Furthermore, an isolation gap exists between the first and second regions of the active strip pillar, and this gap exposes the isolation pillar. After the isolation layer fills the isolation gap, the isolation layer within the gap cuts off the indirect crosstalk path formed by electrons bypassing the isolation pillar from the first region. It also cuts off the connection between the first and second channel portions and the substrate, thereby avoiding substrate leakage and improving the reliability of the device's electrical performance.

[0027] In the method for forming a memory device according to the technical solution of the present invention, by forming the isolation pillar within the active strip pillar, the isolation pillar electrically isolates the first channel portion and the second channel portion formed therefrom, thereby cutting off the direct crosstalk path between different side channels and effectively preventing crosstalk generated between different side channels. Furthermore, the first and second regions of the active strip pillar have an isolation gap, and the isolation gap exposes the isolation pillar. After the isolation layer fills the isolation gap, the isolation layer filled within the isolation gap cuts off the indirect crosstalk path formed by electrons bypassing the isolation pillar from the first region. It also cuts off the connection between the first and second channel portions and the substrate, thereby avoiding substrate leakage and improving the reliability of the device's electrical performance. Attached Figure Description

[0028] Figure 1 A schematic diagram of the structure of a storage device;

[0029] Figures 2 to 16 This is a schematic diagram of the structure of each step in the method for forming a storage device according to an embodiment of the present invention. Detailed Implementation

[0030] As described in the background section, existing storage devices still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic diagram of a storage device.

[0032] Please refer to Figure 1A storage device includes: a substrate 100; an active strip pillar 101 located on the substrate 100, the active strip pillar 101 including opposing first sides 101a and second sides 101b, the active strip pillar 101 including a first region I and a second region II located on the first region I; an isolation pillar 102 located within the active strip pillar 101, the isolation pillar 102 dividing the second region II into a first channel portion 1011 and a second channel portion 1012, the first channel portion 1011 located on the first side 101a and the second channel portion 1012 located on the second side 101b; and an isolation layer 103 located on the substrate 100, the isolation layer 103 covering a portion of the active strip pillar 101. The isolation layer 103 has a sidewall, and the top surface of the isolation layer 103 is lower than the top surface of the active strip post 101; a first charge storage portion 104 is located on the isolation layer 103, the first charge storage portion 104 is located on the first side 101a and covers part of the sidewall of the first channel portion 1011; a second charge storage portion 105 is located on the isolation layer 103, the second charge storage portion 105 is located on the second side 101b and covers part of the sidewall of the second channel portion 1012; a control gate structure 106 is located on the isolation layer 103, the control gate structure 106 spans the active strip post 101, and the control gate structure 106 covers the first charge storage portion 104 and the second charge storage portion 105.

[0033] By forming the isolation post 102 within the active strip post 101, the isolation post 102 electrically isolates the first channel portion 1011 and the second channel portion 1012, thereby cutting off the crosstalk path between different side channels and effectively preventing crosstalk between different side channels.

[0034] However, since the isolation pillar 102 only divides the second zone II to cut off the direct crosstalk path between different side channels (such as... Figure 1 Indirect crosstalk path S1), but the first channel portion 1011 and the second channel portion 1012 formed are still connected to the first region I, and electrons can still bypass the isolation pillar 102 to form an indirect crosstalk path from the first region I (e.g., Figure 1 The first channel portion 1011 and the second channel portion 1012 are both connected to the substrate 100, so there will be leakage current in the substrate 100, which will affect the reliability of the device's electrical performance.

[0035] Based on this, the present invention provides a memory device and a method for forming the same. By forming the isolation pillar within the active strip pillar, the isolation pillar electrically isolates the first channel portion and the second channel portion, thereby cutting off the direct crosstalk path between different side channels and effectively preventing crosstalk between different side channels. Furthermore, the first and second regions of the active strip pillar have an isolation gap, and the isolation gap exposes the isolation pillar. After the isolation layer fills the isolation gap, the isolation layer within the isolation gap cuts off the indirect crosstalk path formed by electrons bypassing the isolation pillar from the first region. It also cuts off the connection between the first and second channel portions and the substrate, thereby avoiding substrate leakage and improving the reliability of the device's electrical performance.

[0036] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figures 2 to 16 This is a schematic diagram of the structure of each step in the method for forming a storage device according to an embodiment of the present invention.

[0038] Please refer to Figure 2 Substrate 200 is provided.

[0039] In this embodiment, the substrate 200 is made of silicon.

[0040] In other embodiments, the substrate material may also be silicon-germanium.

[0041] After providing the substrate 200, a plurality of active strip pillars arranged parallel to each other along a first direction are formed on the substrate 200. The active strip pillars extend along a second direction, which is perpendicular to the first direction. Each active strip pillar includes a first region and a second region located on the first region, with an isolation gap between the first and second regions. Isolation pillars are formed within the active strip pillars, extending along the second direction to divide the second region into a first channel portion and a second channel portion arranged along the first direction. The isolation pillars extend into the first region to support the second region, and the isolation gap exposes the isolation pillars. For a detailed formation process, please refer to [reference needed]. Figures 2 to 12 .

[0042] Please continue to refer to this. Figure 2 A sacrificial layer 201 is formed on the substrate 200; a channel layer 202 is formed on the sacrificial layer 201.

[0043] In this embodiment, the sacrificial layer 201 is used to reserve space for the isolation gap that is subsequently formed. After the sacrificial layer 201 is removed, the isolation gap can be formed. The channel layer 202 is used to form the first channel portion and the second channel portion.

[0044] In this embodiment, in order to minimize damage to the channel layer 202 when removing the sacrificial layer 201 and to ensure the channel performance of the first channel portion and the second channel portion, the sacrificial layer 201 and the channel layer 202 should be made of different materials. By using the etching process to select the etching ratio of different materials, it is possible to ensure that the etching damage to the channel layer 202 is reduced during the removal of the sacrificial layer 201.

[0045] In this embodiment, the sacrificial layer 201 is made of silicon-germanium and is formed by epitaxial growth; the channel layer 202 is made of silicon and is formed by epitaxial growth.

[0046] By using silicon-germanium for the sacrificial layer 201 and silicon for the channel layer 202, the materials are ensured to be different. This material selection strategy significantly reduces etching damage to the channel layer 202 during the subsequent removal of the sacrificial layer 201. Furthermore, the silicon-germanium sacrificial layer 201 not only provides the basis for the epitaxial growth of the channel layer 202 but also ensures that the re-epitaxied channel layer 202 is a single-crystal silicon structure. This characteristic helps to significantly improve the electron mobility of the first and second channel portions subsequently formed based on the channel layer 202, thereby optimizing the overall device performance.

[0047] In other embodiments, the sacrificial layer may also be made of silicon, and the channel layer may be made of silicon-germanium.

[0048] In this embodiment, after the trench layer 202 is formed, an oxide layer (not shown) is deposited on the surface of the trench layer 202 to protect the surface of the trench layer 202.

[0049] Please refer to Figure 3 A first mask layer 203 is formed on the channel layer 202, and the first mask layer 203 extends along the second direction.

[0050] In this embodiment, the first mask layer 203 is used to define the location where the isolation pillars are subsequently formed.

[0051] In this embodiment, the method for forming the first mask layer 203 includes: forming a first mask material layer (not shown) on the channel layer 202; and performing patterned etching on the first mask material layer to form the first mask layer 203.

[0052] Please refer to Figure 4 After the first mask layer 203 is formed, a fill layer 204 is formed on the channel layer 202, the fill layer 204 covering the sidewalls of the first mask layer 203 and exposing the top surface of the first mask layer 203.

[0053] In this embodiment, in order to reduce the etching damage to the filling layer 204 during the subsequent removal of the first mask layer 203, thereby improving the accuracy of the formation position of the isolation pillar, the filling layer 204 is made of a different material than the first mask layer 203.

[0054] In this embodiment, the filling layer 204 is made of polycrystalline silicon and is formed by chemical vapor deposition.

[0055] In this embodiment, the method for forming the filling layer 204 includes: forming a filling material layer on the channel layer 202, the filling material layer covering the first mask layer 203; and planarizing the filling material layer until the top surface of the first mask layer 203 is exposed, thereby forming the filling layer 204.

[0056] In this embodiment, the planarization process for the filler material layer is a chemical mechanical polishing process.

[0057] Please refer to Figure 5 The filler layer 204 is etched back so that the top surface of the filler layer 204 is lower than the top surface of the first mask layer 203; a capping layer 205 is formed on the filler layer 204, the capping layer 205 exposing the top surface of the first mask layer 203.

[0058] In this embodiment, the process of etching back the filling layer 204 adopts a dry etching process.

[0059] In this embodiment, the method for forming the cap layer 205 includes: forming a cap material layer (not shown) on the filler layer 204, the cap material layer covering the first mask layer 203; and planarizing the cap material layer until the top surface of the first mask layer 203 is exposed, thereby forming the cap layer 205.

[0060] In this embodiment, the cap layer 205 is made of silicon oxide, and the process for planarizing the cap material layer is chemical mechanical polishing.

[0061] Please refer to Figure 6 Remove the first mask layer 203 to form an etched opening 206.

[0062] In this embodiment, the etched opening 206 is used for subsequent etching of the trench layer 202.

[0063] In this embodiment, the process of removing the first mask layer 203 is a wet etching process.

[0064] Please continue to refer to this. Figure 6 After removing the first mask layer 203, an inner liner layer 207 is formed on the surface of the etched opening 206 and on the cap layer 205.

[0065] In this embodiment, the formed inner lining layer 207 is used to reserve space for the width dimension of the subsequently formed active strip column along the first direction.

[0066] In this embodiment, the inner liner 207 is formed using a self-aligned chemical vapor deposition process, and the material of the inner liner 207 is silicon nitride.

[0067] Please refer to Figure 7 After the inner liner 207 is formed, the channel layer 202 is etched based on the etched opening 206 to form an isolation opening 208 in the channel layer 202.

[0068] It should be noted that, in this embodiment, after etching the channel layer 202, the sacrificial layer 201 and the substrate 200 also need to be etched, so that the isolation opening 208 penetrates the sacrificial layer 201 and extends into the substrate 200. The purpose of the isolation opening 208 penetrating the sacrificial layer 201 is to ensure that the subsequently formed isolation gap can expose the isolation pillar, so that after the isolation layer fills the isolation gap, the isolation layer and the isolation pillar can connect, thereby completely isolating the first channel portion and the second channel portion, cutting off all paths through which electrons can flow. The isolation opening 208 extending into the substrate 200 ensures that the subsequently formed isolation pillar can be embedded in the first region, thereby providing protection for the isolation pillar to support the second region.

[0069] Please refer to Figure 8 In this embodiment, after the isolation opening 208 is formed, the isolation pillar 209 is formed in the isolation opening 208; the inner liner layer 207 is removed, and a second mask layer 210 is formed in the etched opening 206.

[0070] In other embodiments, after forming the isolation opening, the isolation pillar is formed within the isolation opening. Alternatively, the inner liner layer may be formed within the etched opening using the same material as the inner liner layer without removing it.

[0071] In this embodiment, the second mask layer 210 is used to define the position of the subsequently formed active strip pillar.

[0072] In this embodiment, the isolation column 209 is formed by oxidizing the sidewall exposed by the isolation opening 208 using an oxidation process.

[0073] In this embodiment, the material of the isolation pillar 209 is an insulating material, which can be silicon oxide, silicon nitride, or a Low-K dielectric material.

[0074] In this embodiment, the method for forming the second mask layer 210 includes: forming a second mask material layer (not shown) inside the etched opening 206 and on the cap layer 205; planarizing the second mask material layer until the top surface of the filling layer 204 is exposed, thereby forming the second mask layer 210.

[0075] In this embodiment, the material of the second mask layer 210 is silicon nitride.

[0076] In this embodiment, the material of the second mask material layer is formed using a high aspect ratio atomic layer deposition process.

[0077] It should be noted that if the depth and width of the isolation opening 208 are relatively large, the oxide formed directly by the oxidation process can fill the isolation opening 208 completely, and the deposited second mask material layer will not enter the isolation opening 208; if the depth and width of the isolation opening 208 are relatively small, the oxide formed directly by the oxidation process cannot fill the isolation opening 208 completely, and the deposited second mask material layer will enter the isolation opening 208 completely.

[0078] In this embodiment, the planarization process for the second mask material layer is a chemical mechanical polishing process, and the cap layer 205 is also removed during the planarization of the second mask material layer.

[0079] In this embodiment, in order to reduce etching damage to the second mask layer 210 and ensure the accuracy of pattern transfer during the subsequent removal of the filler layer 204, the materials of the second mask layer 210 and the filler layer 204 also need to be different.

[0080] Please refer to Figure 9After the second mask layer 210 is formed, the filler layer 204 is removed.

[0081] In this embodiment, the process of removing the filler layer 204 is a wet etching process.

[0082] Please refer to Figure 10 After removing the filler layer 204, the channel layer 202, the sacrificial layer 201 and the substrate 200 are etched using the second mask layer 210 as a mask to form the initial active strip pillar 211.

[0083] It should be noted that the sacrificial layer 201 still exists within the initial active strip column 211 formed at this time.

[0084] Please refer to Figure 11 and Figure 12 , Figure 12 This is a top view omitting the second mask layer 210, where the sacrificial layer 201 is removed so that the initial active strip pillar 211 forms the active strip pillar 212.

[0085] In this embodiment, the opening formed by removing the sacrificial layer 201 is the isolation gap 213, the substrate 200 forms the first region I, and the channel layer 202 forms the second region II.

[0086] At this point, the manufacturing process of the active strip column 212 is complete.

[0087] It should be noted that, Figures 2 to 11 The manufacturing process of a single active strip column 212 is shown only; the other active strip columns 212 are manufactured simultaneously with it.

[0088] Please continue to refer to this. Figure 11 and Figure 12 In this embodiment, Figure 12 The diagram shows a top view of two active strip columns 212, i.e., the two active strip columns 212 are arranged parallel to each other along a first direction X, and the active strip columns 212 extend along a second direction Y, the first direction X being perpendicular to the second direction Y. Each active strip column 212 includes a first region I and a second region II located on the first region I, with an isolation gap 213 between the first region I and the second region II. An isolation column 209 extends along the second direction Y to divide the second region II into a first channel portion 2121 and a second channel portion 2122 arranged along the first direction X. The isolation column 209 extends into the first region I to support the second region II, and the isolation gap 213 exposes the isolation column 209.

[0089] In this embodiment, the first channel portion 2121 is located on the first side 212a of the active strip post 212, and the second channel portion 2122 is located on the second side 212b of the active strip post 212.

[0090] Please refer to Figure 13 , Figure 13 and Figure 11 With the view orientation consistent, an isolation layer 216 is formed on the substrate 200, the isolation layer 216 covering the first region I of the active strip pillar 212 and filling the isolation gap 213 in the active strip pillar 212.

[0091] In this embodiment, the method for forming the isolation layer 216 includes: forming an isolation material film (not shown) on the substrate 200, the isolation material film covering the active strip pillar 212; performing planarization treatment on the isolation material film to form an initial isolation layer (not shown); and performing back etching treatment on the initial isolation layer to form the isolation layer 216.

[0092] In this embodiment, the material of the isolation layer 216 is silicon oxide.

[0093] In this embodiment, after forming the isolation layer 216, the method further includes: performing ion implantation on the active strip pillar 212 to adjust the channel threshold voltage.

[0094] In other embodiments, if the threshold voltage of the channel meets a preset value, ion implantation may not be necessary.

[0095] By forming the isolation post 209 within the active strip post 212, the isolation post 209 electrically isolates the formed first channel portion 2121 and the second channel portion 2122, thereby cutting off direct crosstalk paths between different side channels (such as...). Figure 13 The crosstalk path S1 in the active strip pillar 212 effectively prevents crosstalk between different side channels. Furthermore, the active strip pillar 212 has an isolation gap 213 between its first region I and second region II, and this isolation gap 213 exposes the isolation pillar 209. After the isolation layer 216 fills the isolation gap 213, the isolation layer 216 within the isolation gap 213 cuts off electrons from bypassing the isolation pillar 209 to form an indirect crosstalk path from the first region I (e.g., S1). Figure 13 In addition to the crosstalk path S2 in the middle, it can also cut off the connection between the first channel portion 2121 and the second channel portion 2122 and the substrate 200, thereby avoiding the problem of leakage current of the substrate 200 and improving the reliability of the electrical performance of the device.

[0096] After the isolation layer 216 is formed, a plurality of storage cells are formed based on the second region II, and the storage cells are located on the isolation layer 216. Please refer to [link / reference needed] for details. Figures 14 to 16 .

[0097] Please refer to Figures 14 to 16 , Figure 14 This is a top view omitting the second mask layer 210. Figure 15 yes Figure 14 Schematic diagram of the cross section along line AA. Figure 16 yes Figure 14 A cross-sectional diagram along line BB shows that the plurality of storage units include: a plurality of first storage units 214 and a plurality of second storage units 215.

[0098] In this embodiment, the first storage unit 214 is located on the first side 212a and covers part of the sidewall of the first channel portion 2121; the second storage unit 215 is located on the second side 212b and covers part of the sidewall of the second channel portion 2122.

[0099] In this embodiment, the first storage unit 214 includes: a first charge storage portion 2141, which covers a portion of the sidewall of the first channel portion 2121; a first control gate structure 2142, which extends along the first direction X and covers the surface of the first charge storage portion 2141; and a first word line gate structure 2143, which extends along the first direction X and is adjacent to the first charge storage portion 2141 along the second direction Y, covering a portion of the sidewall of the first channel portion 2121, for controlling the first channel portion 2121. The second storage unit 215 includes: a second charge storage section 2151, which covers a portion of the sidewall of the second channel section 2122; a second control gate structure 2152, which extends along the first direction X and covers the surface of the second charge storage section 2151; and a second word line gate structure 2153, which extends along the first direction X and is adjacent to the second charge storage section 2151 along the second direction Y, and covers a portion of the sidewall of the second channel section 2122, for controlling the on / off state of the second channel section 2122.

[0100] In this embodiment, the first charge storage unit 2141 and the second charge storage unit 2151 include a floating gate structure or an ONO structure (i.e., oxide-nitride-oxide). The floating gate structure consists of a floating gate layer and a tunneling oxide layer. The floating gate layer is a conductive layer completely surrounded by an insulating layer, typically made of polysilicon. The floating gate layer stores charge, and the charge state on it determines the logic state of the memory cell. The tunneling oxide layer is located between the floating gate layer and the channel portion, and is used to control the charge tunneling process. The write process of the floating gate structure injects charge into the floating gate layer through the tunneling oxide layer. The Fowler-Nordheim tunneling mechanism is typically used, where electrons tunnel from the channel portion through the oxide layer into the floating gate layer under a high electric field. The erase process removes charge from the floating gate layer by tunneling through the oxide layer. The erase process is the reverse of the write process and typically requires the application of a reverse voltage. The read process determines the logic state of the memory cell by detecting the effect of the charge on the floating gate layer on the channel current. The advantages of the floating gate structure are: excellent data retention capability: the floating gate layer can store a large amount of charge, and since it is completely surrounded by an insulating layer, charge leakage is minimal, resulting in a longer data retention time; strong resistance to read / write interference: the floating gate structure has a thicker tunneling layer, making it less susceptible to leakage current crosstalk during read / write operations on common word lines or bit lines. The floating gate structure is suitable for applications requiring high reliability and long data retention times, such as NOR Flash. The ONO structure consists of three layers: oxide, nitride, and oxide. The nitride layer is the key layer for charge storage; the charge can be trapped within the nitride layer, and the oxide layers on both sides isolate the nitride layer to prevent charge leakage. The write process in the ONO structure injects charge into the nitride layer by tunneling through the oxide layer. The charge is trapped in the nitride layer. The erase process removes the charge from the nitride layer by tunneling through the oxide layer. The erase process is similar to the write process but typically requires a higher voltage; the read process determines the logic state of the memory cell by detecting changes in channel voltage or current. The advantages of the ONO structure are: simple manufacturing process: the manufacturing process of the ONO structure is relatively simple and does not require complex floating gate fabrication processes; low power consumption: because the charge is stored in the trap level of the nitride layer, the tunneling layer is thinner, the operating voltage is lower, and the tunneling current is smaller, thus resulting in lower power consumption; good scalability: the ONO structure has good adaptability in size reduction and is suitable for high-density storage; the ONO structure is suitable for applications requiring low cost per bit and high-density storage, such as Nand Flash, and is also suitable for memory chips that require high integration and scalability.

[0101] Please continue to refer to this. Figures 14 to 16In this embodiment, the first control gate structure 2142 in a plurality of first storage cells 214 arranged along the first direction X and the second control gate structure 2152 in a plurality of second storage cells 215 adopt a common control gate structure, that is, one control gate structure is used to span the plurality of active strip pillars 212 arranged in parallel along the first direction X; between adjacent second channel portions 2122 and second channel portions 2122, the first word line gate structure 2143 and the second word line gate structure 2153 arranged along the first direction X adopt a common word line gate structure; along the second direction Y, adjacent first storage cells 2144 and second word line gate structures 2152 adopt a common word line gate structure. The first word line gate structure 2143 in 14, or the second word line gate structure 2153 in the adjacent second memory cell 215, are shared; along the first direction X and the second direction Y, four adjacent memory cells formed based on the active strip pillar 212 constitute one memory array cell 217, and the source and drain are shared in the memory array cell 217, which are formed within the active strip region; along the first direction X, adjacent memory array cells 217 share a source or drain (not shown); along the first direction X, several common word line gate structures are interleaved and electrically connected on two different metal lines (not shown).

[0102] Accordingly, embodiments of the present invention also provide a storage device, please refer to [the relevant documentation]. Figures 14 to 16 The system includes: a substrate 200; a plurality of active strip pillars 212 arranged parallel to each other along a first direction X on the substrate 200, the active strip pillars 212 extending along a second direction Y, the first direction X being perpendicular to the second direction Y, each active strip pillar 212 including a first region I and a second region II located on the first region I, with an isolation gap 213 between the first region I and the second region II; and isolation pillars 209 located within the active strip pillars 212, the isolation pillars 209 extending along the second direction Y to divide the second region II into... A first channel portion 2121 and a second channel portion 2122 are arranged along the first direction X. The isolation pillar 209 extends into the first region I to support the second region II. The isolation gap 213 exposes the isolation pillar 209. An isolation layer 216 is located on the substrate 200. The isolation layer 216 covers the first region I of the active strip pillar 212 and fills the isolation gap 213 in the active strip pillar 212. A plurality of memory cells are formed based on the second region II. The memory cells are located on the isolation layer 216.

[0103] The isolation post 209 located within the active strip post 212 electrically isolates the first channel portion 2121 and the second channel portion 2122, thereby cutting off direct crosstalk paths between different side channels (e.g., Figure 13 The crosstalk path S1 in the active strip pillar 212 effectively prevents crosstalk between different side channels. Furthermore, the active strip pillar 212 has an isolation gap 213 between its first region I and second region II, and this isolation gap 213 exposes the isolation pillar 209. After the isolation layer 216 fills the isolation gap 213, the isolation layer 216 within the isolation gap 213 cuts off electrons from bypassing the isolation pillar 209 to form an indirect crosstalk path from the first region I (e.g., S1). Figure 13 In addition to the crosstalk path S2 in the middle, it can also cut off the connection between the first channel portion 2121 and the second channel portion 2122 and the substrate 200, thereby avoiding the problem of leakage current of the substrate 200 and improving the reliability of the electrical performance of the device.

[0104] In this embodiment, the substrate 200 is made of silicon.

[0105] In other embodiments, the substrate material may also be silicon-germanium.

[0106] In this embodiment, the first channel portion 2121 is located on the first side 212a of the active strip post 212, and the second channel portion 2122 is located on the second side 212b of the active strip post 212; the plurality of storage units include: a plurality of first storage units 214 and a plurality of second storage units 215; wherein, the first storage units 214 are located on the first side 212a and cover part of the sidewall of the first channel portion 2121; the second storage units 215 are located on the second side 212b and cover part of the sidewall of the second channel portion 2122.

[0107] In this embodiment, the first storage unit 214 includes: a first charge storage portion 2141, which covers a portion of the sidewall of the first channel portion 2121; a first control gate structure 2142, which extends along the first direction X and covers the surface of the first charge storage portion 2141; and a first word line gate structure 2143, which extends along the first direction X and is adjacent to the first charge storage portion 2141 along the second direction Y, and covers a portion of the sidewall of the first channel portion 2121, for controlling the on / off state of the first channel portion 2121.

[0108] In this embodiment, the second storage unit 215 includes: a second charge storage portion 2151, which covers a portion of the sidewall of the second channel portion 2122; a second control gate structure 2152, which extends along the first direction X and covers the surface of the second charge storage portion 2151; and a second word line gate structure 2153, which extends along the first direction X and is adjacent to the second charge storage portion 2151 along the second direction Y, and covers a portion of the sidewall of the second channel portion 2122, for controlling the on / off state of the second channel portion 2122.

[0109] In this embodiment, the first charge storage unit 2141 and the second charge storage unit 2151 include a floating gate structure or an ONO structure (i.e., oxide-nitride-oxide). The floating gate structure consists of a floating gate layer and a tunneling oxide layer. The floating gate layer is a conductive layer completely surrounded by an insulating layer, typically made of polysilicon. The floating gate layer stores charge, and the charge state on it determines the logic state of the memory cell. The tunneling oxide layer is located between the floating gate layer and the channel portion, and is used to control the charge tunneling process. The write process of the floating gate structure injects charge into the floating gate layer through the tunneling oxide layer. The Fowler-Nordheim tunneling mechanism is typically used, where electrons tunnel from the channel portion through the oxide layer into the floating gate layer under a high electric field. The erase process removes charge from the floating gate layer by tunneling through the oxide layer. The erase process is the reverse of the write process and typically requires the application of a reverse voltage. The read process determines the logic state of the memory cell by detecting the effect of the charge on the floating gate layer on the channel current. The advantages of the floating gate structure are: excellent data retention capability: the floating gate layer can store a large amount of charge, and since it is completely surrounded by an insulating layer, charge leakage is minimal, resulting in a longer data retention time; strong resistance to read / write interference: the floating gate structure has a thicker tunneling layer, making it less susceptible to leakage current crosstalk during read / write operations on common word lines or bit lines. The floating gate structure is suitable for applications requiring high reliability and long data retention times, such as NOR Flash. The ONO structure consists of three layers: oxide, nitride, and oxide. The nitride layer is the key layer for charge storage; the charge can be trapped within the nitride layer, and the oxide layers on both sides isolate the nitride layer to prevent charge leakage. The write process in the ONO structure injects charge into the nitride layer by tunneling through the oxide layer. The charge is trapped in the nitride layer. The erase process removes the charge from the nitride layer by tunneling through the oxide layer. The erase process is similar to the write process but typically requires a higher voltage; the read process determines the logic state of the memory cell by detecting changes in channel voltage or current. The advantages of the ONO structure are: simple manufacturing process: the manufacturing process of the ONO structure is relatively simple and does not require complex floating gate fabrication processes; low power consumption: because the charge is stored in the trap level of the nitride layer, the tunneling layer is thinner, the operating voltage is lower, and the tunneling current is smaller, thus resulting in lower power consumption; good scalability: the ONO structure has good adaptability in size reduction and is suitable for high-density storage; the ONO structure is suitable for applications requiring low cost per bit and high-density storage, such as Nand Flash, and is also suitable for memory chips that require high integration and scalability.

[0110] In this embodiment, the material of the isolation pillar 209 is an insulating material, including silicon oxide, silicon nitride, or Low-K dielectric material.

[0111] Please continue to refer to this. Figures 14 to 16 In this embodiment, the first control gate structure 2142 in a plurality of first storage cells 214 arranged along the first direction X and the second control gate structure 2152 in a plurality of second storage cells 215 adopt a common control gate structure, that is, one control gate structure is used to span the plurality of active strip pillars 212 arranged in parallel along the first direction X; between adjacent second channel portions 2122 and second channel portions 2122, the first word line gate structure 2143 and the second word line gate structure 2153 arranged along the first direction X adopt a common word line gate structure; along the second direction Y, adjacent first storage cells 2144 and second word line gate structures 2152 adopt a common word line gate structure. The first word line gate structure 2143 in 14, or the second word line gate structure 2153 in the adjacent second memory cell 215, are shared; along the first direction X and the second direction Y, four adjacent memory cells formed based on the active strip pillar 212 constitute one memory array cell 217, and the source and drain are shared in one memory array cell 217, the source and drain being formed within the active strip region; along the first direction X, adjacent memory array cells 217 share a source or drain (not shown); along the first direction X, several common word line gate structures are interleaved and electrically connected on two different metal lines (not shown).

[0112] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A storage device, characterized in that, include: Substrate; A plurality of active strip pillars are arranged in parallel along a first direction on the substrate. The active strip pillars extend along a second direction, the first direction being perpendicular to the second direction. Each active strip pillar includes a first region and a second region located on the first region, with an isolation gap between the first region and the second region. An isolation column located within the active strip column extends along the second direction to divide the second region into a first channel portion and a second channel portion arranged along the first direction. The isolation column extends into the first region to support the second region, and the isolation gap exposes the isolation column. An isolation layer located on the substrate, the isolation layer covering the first region of the active strip pillar and filling the isolation gap in the active strip pillar; Based on the second area, a plurality of storage cells are formed, the storage cells being located on the isolation layer.

2. The storage device as claimed in claim 1, characterized in that, The first channel portion is located on the first side of the active strip column, and the second channel portion is located on the second side of the active strip column; the plurality of storage units include: a plurality of first storage units and a plurality of second storage units; wherein, the first storage units are located on the first side and cover a portion of the sidewall of the first channel portion; the second storage units are located on the second side and cover a portion of the sidewall of the second channel portion.

3. The storage device as claimed in claim 2, characterized in that, The first storage cell includes: a first charge storage section covering a portion of the sidewall of the first channel section; a first control gate structure extending along the first direction and covering the surface of the first charge storage section; and a first word line gate structure extending along the first direction and adjacent to the first charge storage section along the second direction, the first word line gate structure covering a portion of the sidewall of the first channel section for controlling the on / off state of the first channel section.

4. The storage device as claimed in claim 3, characterized in that, The first charge storage unit includes a floating gate structure or an ONO structure.

5. The storage device as claimed in claim 2, characterized in that, The second storage cell includes: a second charge storage section covering a portion of the sidewall of the second channel section; a second control gate structure extending along the first direction and covering the surface of the second charge storage section; and a second word line gate structure extending along the first direction and adjacent to the second charge storage section along the second direction, the second word line gate structure covering a portion of the sidewall of the second channel section for controlling the on / off state of the second channel section.

6. The storage device as claimed in claim 5, characterized in that, The second charge storage unit includes a floating gate structure or an ONO structure.

7. The storage device as claimed in claim 1, characterized in that, The materials of the isolation pillars include silicon oxide or silicon nitride.

8. A method for forming a storage device, characterized in that, include: Provide substrate; A plurality of active strip pillars are formed on the substrate and arranged in parallel along a first direction. The active strip pillars extend along a second direction, the first direction being perpendicular to the second direction. Each active strip pillar includes a first region and a second region located on the first region, with an isolation gap between the first region and the second region. An isolation column is formed within the active strip column, the isolation column extends along the second direction to divide the second region into a first channel portion and a second channel portion arranged along the first direction, the isolation column extends into the first region to support the second region, and the isolation gap exposes the isolation column; An isolation layer is formed on the substrate, the isolation layer covering the first region of the active strip pillar and filling the isolation gap in the active strip pillar; Several storage units are formed based on the second region, and the storage units are located on the isolation layer.

9. The method for forming the storage device as described in claim 8, characterized in that, The method for forming the active bar pillar includes: forming a sacrificial layer on the substrate; forming a channel layer on the sacrificial layer; performing patterned etching on the channel layer, the sacrificial layer, and the substrate to form an initial active bar pillar; removing the sacrificial layer so that the initial active bar pillar forms the active bar pillar; wherein, the opening formed by removing the sacrificial layer is the isolation gap, the substrate forms the first region, and the channel layer forms the second region.

10. The method for forming the storage device as claimed in claim 9, characterized in that, The material of the sacrificial layer is different from the material of the channel layer.

11. The method for forming the storage device as claimed in claim 10, characterized in that, The sacrificial layer is made of silicon-germanium; the channel layer is made of silicon.

12. The method for forming the storage device as described in claim 9, characterized in that, The first channel portion is located on the first side of the active strip column, and the second channel portion is located on the second side of the active strip column; the plurality of storage units include: a plurality of first storage units and a plurality of second storage units; wherein, the first storage units are located on the first side and cover a portion of the sidewall of the first channel portion; the second storage units are located on the second side and cover a portion of the sidewall of the second channel portion.

13. The method for forming the storage device as claimed in claim 12, characterized in that, The first storage cell includes: a first charge storage section covering a portion of the sidewall of the first channel section; a first control gate structure extending along the first direction and covering the surface of the first charge storage section; and a first word line gate structure extending along the first direction and adjacent to the first charge storage section along the second direction, the first word line gate structure covering a portion of the sidewall of the first channel section for controlling the on / off state of the first channel section.

14. The method for forming the storage device as claimed in claim 13, characterized in that, The first charge storage unit includes a floating gate structure or an ONO structure.

15. The method for forming the storage device as claimed in claim 12, characterized in that, The second storage cell includes: a second charge storage section covering a portion of the sidewall of the second channel section; a second control gate structure extending along the first direction and covering the surface of the second charge storage section; and a second word line gate structure extending along the first direction and adjacent to the second charge storage section along the second direction, the second word line gate structure covering a portion of the sidewall of the second channel section for controlling the on / off state of the second channel section.

16. The method for forming the storage device as claimed in claim 15, characterized in that, The second charge storage unit includes a floating gate structure or an ONO structure.

17. The method for forming the storage device as claimed in claim 8, characterized in that, The materials of the isolation pillars include silicon oxide or silicon nitride.

18. The method for forming the storage device as claimed in claim 8, characterized in that, The method for forming the isolation layer includes: forming an isolation material film on the substrate, the isolation material film covering the active strip pillar; planarizing the isolation material film to form an initial isolation layer; and performing a back etching process on the initial isolation layer to form the isolation layer.

19. The method for forming the storage device as claimed in claim 8, characterized in that, After forming the isolation layer, the method further includes: performing ion implantation on the active strip column to adjust the channel threshold voltage.

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