Semiconductor device with crystalline thin film ferroelectric layer and method of manufacturing same

Abstract

The invention relates to a semiconductor device with a crystalline thin film ferroelectric layer and a method of manufacturing the same. A semiconductor device includes: a first interconnect line extending in a first horizontal direction; a second interconnection line extending in a second horizontal direction, the first horizontal direction and the second horizontal direction intersecting each other; and a memory cell disposed between the first interconnection line and the second interconnection line. The memory cell includes: a lower electrode; a crystalline ferroelectric layer on the lower electrode; and an upper electrode on the crystalline ferroelectric layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0057662, filed on April 30, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device having a crystalline thin-film ferroelectric layer and a method for manufacturing a semiconductor device having a crystalline thin-film ferroelectric layer. Background Technology

[0004] Semiconductor devices with ferroelectric layers are under investigation. Ferroelectric layers exhibit low power consumption due to their low on-current characteristics. However, for cross-point structural cell sizes, the on-current is extremely low, making it difficult to achieve a high on / off current ratio for crystalline thin-film ferroelectric layers in semiconductor devices. Summary of the Invention

[0005] A semiconductor device includes: a first interconnect extending in a first horizontal direction; a second interconnect extending in a second horizontal direction, the first and second horizontal directions intersecting each other; and a memory cell disposed between the first and second interconnects. The memory cell includes: a lower electrode; a ferroelectric layer on the lower electrode; and an upper electrode on the ferroelectric layer.

[0006] A method for manufacturing a semiconductor device includes: forming a lower electrode material layer; forming a crystalline thick ferroelectric layer on the lower electrode material layer; thinning the crystalline thick ferroelectric layer by performing a first atomic layer etching process to form a preliminary crystalline thin film ferroelectric layer; forming an upper electrode material layer on the preliminary crystalline thin film ferroelectric layer; and patterning the upper electrode material layer, the preliminary crystalline thin film ferroelectric layer, and the lower electrode material layer by performing a patterning process to form a memory cell including a lower electrode, a crystalline thin film ferroelectric layer, and an upper electrode. Attached Figure Description

[0007] Figure 1A and Figure 1B These are circuit diagrams and perspective views schematically illustrating a cell array structure of a semiconductor device according to embodiments of the present disclosure.

[0008] Figure 2A It is a circuit diagram that schematically illustrates the cell array structure of a semiconductor device. Figure 2B It is a schematic longitudinal cross-sectional view of a unit cell of a semiconductor device.

[0009] Figures 3A to 3D This is a schematic longitudinal cross-sectional view of a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 4A to 4G This is a longitudinal cross-sectional view illustrating a method for forming a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figures 5A to 5G This is a longitudinal cross-sectional view illustrating a method for forming a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 6A and Figure 6B This is a longitudinal cross-sectional view illustrating a method for forming a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7A and Figure 7B This is a longitudinal cross-sectional view illustrating a method for forming a memory cell of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0014] Embodiments of this disclosure have been described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. The scope of this disclosure is not limited to the examples or embodiments described herein, as examples or embodiments of the concepts may be implemented in various forms.

[0015] Crosshairs throughout the figure indicate corresponding or similar areas between figures, rather than indicating the material associated with those areas.

[0016] When one element is labeled "connected" or "coupled" to another element, these elements can be directly connected or coupled, or connected or coupled through an intermediate element between the elements. When two elements are labeled "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0017] When one element is identified as being "above", "over", "below", or "under" another element, these elements can be in direct contact with each other, or an intermediate element can be placed between these elements.

[0018] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “underneath,” “above,” “over,” “side,” “upper part,” “topmost,” “lower part,” “bottommost,” “front,” “back,” “left,” “right,” “column,” “row,” and “horizontal,” as well as other terms that suggest relative spatial relationships or orientations, are used only for convenience of description or reference to the accompanying drawings and are not otherwise limiting. Within the scope of this disclosure, other spatial relationships or orientations not shown in the drawings or described in the specification are also possible.

[0019] Terms such as "first" and "second" are used to distinguish multiple components and do not imply the size, order, priority, number, or importance of the components. For example, in one example, the first component may be named the second component, while in another example, the second component may be named the first component.

[0020] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including a plurality of elements that perform the same or similar functions.

[0021] Embodiments of this disclosure provide a semiconductor device having a crystalline thin-film ferroelectric layer.

[0022] Embodiments of this disclosure provide a method for manufacturing a semiconductor device having a crystalline thin-film ferroelectric layer.

[0023] Figure 1A and Figure 1B These are schematic circuit diagrams and perspective views illustrating a cell array structure of a semiconductor device according to embodiments of the present disclosure.

[0024] refer to Figure 1A and Figure 1B The cell array structure CA1 of the semiconductor device may include a first interconnect 20, a second interconnect 90, and a memory cell MC. The first interconnect 20 may extend parallel to each other in a first horizontal direction X. In one embodiment, the first interconnect 20 may be a word line. The second interconnect 90 may extend parallel to each other in a second horizontal direction Y. In other embodiments, the second interconnect 90 may be a bit line. For example, the first interconnect 20 may be a bit line, while the second interconnect 90 may be a word line. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. From a plan view, the memory cells MC may be respectively disposed at the intersections of the first interconnect 20 and the second interconnect 90. Each memory cell MC may include a variable resistance element. For example, each memory cell MC may include a crystalline ferroelectric layer. Each memory cell MC may be a dual-electrode element. For example, the first electrode of the memory cell MC may be electrically connected to the first interconnect 20, and the second electrode of the memory cell MC may be electrically connected to the second interconnect 90.

[0025] Figure 2A It is a circuit diagram that schematically illustrates the cell array structure of a semiconductor device. Figure 2B It is a schematic longitudinal cross-sectional view of a unit cell of a semiconductor device.

[0026] refer to Figure 2A and Figure 2BThe cell array structure CA2 of the semiconductor device may include active lines 120, word lines 125, source lines 190, and unit cells UC. The active lines 120 may extend parallel to each other in a first horizontal direction X. The source lines 190 may extend parallel to each other in a second horizontal direction Y. The unit cells UC may be disposed at the intersections of the active lines 120 and the source lines 190. Each unit cell UC may include a select transistor ST and a memory cell MC. The drain electrode 111 of each select transistor ST may be electrically connected to the active line 120 via an active contact plug 115. The source electrode 112 of each select transistor ST may be electrically connected to the first electrode of each memory cell MC. The gate electrode of each select transistor ST may be electrically connected to each word line 125. For example, the gate electrode of each select transistor ST may be for each word line 125. The second electrode of each memory cell MC may be electrically connected to each source line 190. Each active contact plug 115 may include a conductor, such as doped polysilicon, metal, metal compound, metal silicide, or metal alloy.

[0027] Figures 3A to 3D This is a schematic longitudinal cross-sectional view of a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0028] refer to Figure 3A The memory cell MC1 of the semiconductor device may include a lower electrode 30, a crystalline thin-film ferroelectric layer 70, and an upper electrode 80.

[0029] Both the lower electrode 30 and the upper electrode 80 may include conductors. For example, the lower electrode 30 and the upper electrode 80 may each include at least one of a metal compound layer (e.g., titanium nitride), a metal layer (e.g., tungsten), a noble metal layer (e.g., platinum), or a transition metal layer (e.g., ruthenium). In one embodiment, the lower electrode 30 and the upper electrode 80 may include conductors that are different from each other to achieve an asymmetric electric field. For example, the lower electrode 30 may include a conductor with a work function greater than that of the upper electrode 80. Specifically, the lower electrode 30 may include a titanium nitride layer, and the upper electrode 80 may include a metal layer (e.g., tungsten). In one embodiment, the lower electrode 30 may include a noble metal layer (e.g., platinum) or a transition metal layer (e.g., ruthenium), while the upper electrode 80 may include a titanium nitride layer. When the lower electrode 30 and the upper electrode 80 include conductors with the same work function, current can be supplied in opposite directions, and the memory cell MC1 may malfunction. Therefore, for unidirectional current, the lower electrode 30 and the upper electrode 80 each include conductors with different work functions.

[0030] A crystalline thin-film ferroelectric layer 70 can be disposed between the lower electrode 30 and the upper electrode 80. The crystalline thin-film ferroelectric layer 70 may include a crystalline thin-film hafnium zirconium oxide (HZO) layer. For example, the crystalline thin-film ferroelectric layer 70 may have five atomic layers or less. The crystalline thin-film ferroelectric layer 70 may have a vertical thickness of about 2 nm or less.

[0031] Due to its irregular atomic bonding structure, the amorphous thin-film ferroelectric layer 70 can exhibit a narrower and longer current path than the crystalline thin-film ferroelectric layer 70. Therefore, the amorphous thin-film ferroelectric layer 70 can exhibit a relatively lower on-current characteristic than the crystalline thin-film ferroelectric layer 70. Conversely, the crystalline thin-film ferroelectric layer 70, due to its regular atomic bonding structure over a thin vertical thickness, can exhibit a shorter and wider current path than the amorphous thin-film ferroelectric layer. Therefore, the crystalline thin-film ferroelectric layer 70 can exhibit a higher on-current characteristic than the amorphous thin-film ferroelectric layer. For example, the crystalline thin-film ferroelectric layer 70 can exhibit on-current characteristics in the microampere (μA) range. Furthermore, the crystalline thin-film ferroelectric layer 70 can exhibit off-current characteristics in the nanoampere (μm) range. While the amorphous thin-film ferroelectric layer can exhibit different on / off current gain characteristics in the range of several to tens of times, the crystalline thin-film ferroelectric layer can exhibit different on / off current gain characteristics in the range of one thousand times or more. In other words, the memory cell MC1 with a crystalline thin-film ferroelectric layer 70 can exhibit low power consumption, high-speed operation and excellent data development characteristics.

[0032] refer to Figure 3B According to an embodiment of the present disclosure, the memory cell MC2 of a semiconductor device may include a lower electrode 30, a crystalline thin film interface insulating layer 60, a crystalline thin film ferroelectric layer 70, and an upper electrode 80. For example, with Figure 3A Compared to memory cell MC1, memory cell MC2 may further include a crystalline thin-film interface insulating layer 60 located between the lower electrode 30 and the crystalline thin-film ferroelectric layer 70. The crystalline thin-film interface insulating layer 60 may include at least one of a crystalline thin-film silicon oxide layer, a crystalline thin-film hafnium oxide layer, a crystalline thin-film zirconium oxide layer, a crystalline thin-film titanium oxide layer, and other crystalline thin-film metal oxide layers. The crystalline thin-film interface insulating layer 60 may have five atomic layers or less. The crystalline thin-film interface insulating layer 60 may have a vertical thickness of about 2 nm or less. The crystalline thin-film interface insulating layer 60 may have an asymmetric electric field applied to the crystalline thin-film ferroelectric layer 70. Due to the asymmetric electric field, current is provided in only one direction in memory cell MC2. Therefore, in one embodiment, due to the crystalline thin-film interface insulating layer 60, the lower electrode 30 and the upper electrode 80 may include the same material. Any element not described will be referred to... Figure 3A To understand. Although Figure 3A The lower electrode 30 and upper electrode 80 of the storage cell MC1 must have conductors with different work functions, but Figure 3BThe lower electrode 30 and upper electrode 80 of the storage cell MC2 may include conductors with the same work function. That is, in this embodiment, the lower electrode 30 and upper electrode 80 may include the same material.

[0033] refer to Figure 3C The memory cell MC3 of the semiconductor device may include a lower electrode 30, a select element layer 40, an intermediate electrode 50, a crystalline thin film ferroelectric layer 70, and an upper electrode 80.

[0034] Selective element layer 40 may include an insulating layer doped with at least one of arsenic (As) or germanium (Ge). The insulating layer of selective element layer 40 may include at least one of silicon oxide layer, silicon nitride layer, or silicon oxynitride layer. For example, selective element layer 40 may include at least one of arsenic-doped silicon oxide layer, arsenic-doped silicon nitride layer, arsenic-doped silicon oxynitride layer, germanium-doped silicon oxide layer, germanium-doped silicon nitride layer, germanium-doped silicon oxynitride layer, arsenic / germanium-doped silicon oxide layer, arsenic / germanium-doped silicon nitride layer, or arsenic / germanium-doped silicon oxynitride layer.

[0035] The intermediate electrode 50 may include a metal nitride layer (e.g., titanium nitride). In one embodiment, the intermediate electrode 50 may include at least one of a carbon layer, a carbon-containing metal layer, a carbon-containing metal compound layer, a carbon-containing metal alloy layer, or a carbon-containing metal silicide layer. Elements not described will be referred to... Figure 3A To understand this, since an asymmetric electric field is formed between the selected element layer 40 and the intermediate electrode 50, the lower electrode 30 and the upper electrode 80 can include the same material.

[0036] refer to Figure 3D According to an embodiment of the present disclosure, a semiconductor memory cell MC4 may include a lower electrode 30, a select element layer 40, an intermediate electrode 50, a crystalline thin film interface insulating layer 60, a crystalline thin film ferroelectric layer 70, and an upper electrode 80. For example, compared with a reference... Figure 3C Compared to the described memory cell MC3, memory cell MC4 may further include a crystalline thin film interface insulating layer 60 disposed between the intermediate electrode 50 and the crystalline thin film ferroelectric layer 70. Components not described will be referred to... Figures 3A to 3C Let's try to understand it.

[0037] refer to Figure 3C and Figure 3D When storage cells MC3 and MC4 include a selection element layer 40, it can be omitted from the unit cell. Figure 2B The selected transistor ST.

[0038] Figures 4A to 4G This is a longitudinal cross-sectional view illustrating a method for forming a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0039] refer to Figure 4A A method for forming a memory cell MC1 of a semiconductor device according to an embodiment of the present disclosure may include forming a lower electrode material layer 31 and forming a crystalline thick-film ferroelectric layer 71a on the lower electrode material layer 31. Forming the lower electrode material layer 31 may include performing a deposition process (e.g., chemical vapor deposition (CVD) or physical vapor deposition (PVD)) to form at least one of a titanium nitride layer, a noble metal layer, or a transition metal layer. For example, the noble metal layer may include a platinum (Pt) layer or a gold (Ag) layer. The transition metal layer may include a ruthenium (Ru) layer. Forming the crystalline thick-film ferroelectric layer 71a may include forming a crystalline thick-film hafnium zirconium oxide (HfZrO) layer by performing an atomic layer deposition (ALD) process. The crystalline thick-film ferroelectric layer 71a may have a vertical thickness sufficient to allow crystallization. It is well known that it is difficult to form a crystalline ferroelectric layer with a vertical thickness of less than 5 nm. Therefore, the crystalline thick-film ferroelectric layer 71a may have a vertical thickness of about 5 nm or greater. Since a single layer of the crystalline ferroelectric layer may be approximately 0.5 nm thick, the crystalline thick ferroelectric layer 71a can be formed by repeatedly performing atomic layer deposition processes approximately 10 or more times to create a stack of layers. That is, for example, the crystalline thick ferroelectric layer 71a may have 10 or more atomic layers. In one embodiment, the crystalline thick ferroelectric layer 71a can be formed by performing a deposition process (e.g., a chemical vapor deposition (CVD) process) and an annealing process.

[0040] refer to Figure 4B The method may further include forming a first modified ferroelectric layer 71b1 by partially modifying the upper portion of the crystalline thick-film ferroelectric layer 71a. For example, an atomic layer in the uppermost layer of the crystalline thick-film ferroelectric layer 71a may be modified and transformed into the first modified ferroelectric layer 71b1. The first modified ferroelectric layer 71b1 may have a vertical thickness of one atomic layer. Therefore, the first modified ferroelectric layer 71b1 may have a vertical thickness of about 0.5 nm. As a result, the crystalline thick-film ferroelectric layer 71a may be thinned to form a first thinned crystalline thick-film ferroelectric layer 71a1. Forming the first modified ferroelectric layer 71b1 may include performing a first modification process. The first modification process may include chemically modifying an atomic layer of the crystalline thick-film ferroelectric layer 71a using a modifying gas Gas A, which includes at least one of the halogen elements F, Cl, Br, or I. After performing the first modification process, a first pre-purge process may be performed. The first pre-purge process can be performed using at least one of an inert gas (e.g., nitrogen (N), helium (He), and argon (Ar)).

[0041] refer to Figure 4CThe method may further include removing the first modified ferroelectric layer 71b1. The first modified ferroelectric layer 71b1 can be removed by performing a first etching process using an etching gas (Gas B). The first thinned crystalline thick film ferroelectric layer 71a1 can be retained after the first etching process. After performing the first etching process, a first post-purging process can be performed. The first post-purging process can be performed using at least one of an inert gas (e.g., nitrogen (N), helium (He), and argon (Ar)).

[0042] refer to Figure 4D The method may further include forming a second modified ferroelectric layer 71b2 by partially modifying the upper portion of the first thinned crystalline thick-film ferroelectric layer 71a1. For example, one atomic layer in the uppermost layer of the first thinned crystalline thick-film ferroelectric layer 71a1 may be modified into the second modified ferroelectric layer 71b2. The second modified ferroelectric layer 71b2 may also have a vertical thickness of one atomic layer. For example, the second modified ferroelectric layer 71b2 may also have a vertical thickness of about 0.5 nm. Therefore, the first thinned crystalline thick-film ferroelectric layer 71a1 may be thinned to form the second thinned crystalline thick-film ferroelectric layer 71a2. Forming the second modified ferroelectric layer 71b2 may include performing a second modification process. The second modification process may include chemically modifying one atomic layer of the first thinned crystalline thick-film ferroelectric layer 71a1 using a modifying gas Gas A, which includes at least one of the halogen elements F, Cl, Br, or I. After performing the second modification process, a second pre-purge process may be performed.

[0043] refer to Figure 4E The method may further include removing the second modified ferroelectric layer 71b2. The second modified ferroelectric layer 71b2 can be removed by performing a second etching process using etching gas Gas B. The second thinned crystalline thick film ferroelectric layer 71a2 can be retained. After performing the second etching process, a second post-purging process can be performed.

[0044] refer to Figure 4F The method may also include repeatedly executing the reference Figures 4B to 4E The modified process, pre-purge process, etching process, and post-purge process described are used to form a preliminary crystalline thin film ferroelectric layer 71. The preliminary crystalline thin film ferroelectric layer 71 may have five atomic layers or less. For example, the preliminary crystalline thin film ferroelectric layer 71 may have a vertical thickness of about 2 nm or less.

[0045] refer to Figures 4B to 4F A preliminary crystalline thin-film ferroelectric layer 71 can be formed by performing an atomic layer etching process. For example, a modification process, a pre-purge process, an etching process, and a post-purge process can form a cycle of the atomic layer etching process. As described above, repeated cycles of the atomic layer etching process can be performed to form the preliminary crystalline thin-film ferroelectric layer 71.

[0046] refer to Figure 4G The method may further include forming an upper electrode material layer 81 on the pre-crystallized thin-film ferroelectric layer 71. The upper electrode material layer 81 can be formed by performing a deposition process (e.g., CVD or PVD). The upper electrode material layer 81 may include at least one of a titanium nitride layer, a noble metal layer, or a transition metal layer. The upper electrode material layer 81 may include a material layer different from the lower electrode material layer 31. For example, the work function of the upper electrode material layer 81 may be lower than that of the lower electrode material layer 31. In one embodiment, when the lower electrode material layer 31 includes a titanium nitride layer, the upper electrode material layer 81 may include a tungsten layer. In another embodiment, when the lower electrode material layer 31 includes a platinum layer, the upper electrode material layer 81 may include a titanium nitride layer.

[0047] Subsequently, refer to Figure 3A The method may further include forming a memory cell MC1 comprising a lower electrode 30, a crystalline thin film ferroelectric layer 70 and an upper electrode 80 by performing a patterning process to pattern an upper electrode material layer 81, a preliminary crystalline thin film ferroelectric layer 71 and a lower electrode material layer 31.

[0048] Figures 5A to 5G This is a longitudinal cross-sectional view illustrating a method for forming a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0049] refer to Figure 5A The method for forming the semiconductor memory cell MC2 may include forming a lower electrode material layer 31 and forming a crystalline thick-film interface insulating layer 61a on the lower electrode material layer 31. Forming the crystalline thick-film interface insulating layer 61a may include forming one of a crystalline thick-film silicon oxide (SiO2) layer, a crystalline thick-film hafnium oxide (HfO) layer, a crystalline thick-film zirconium oxide (ZrO) layer, or a crystalline thick-film titanium oxide (TiO2) layer by performing an atomic layer deposition (ALD) process. The crystalline thick-film interface insulating layer 61a may have a vertical thickness sufficient to allow crystallization. It is known to be difficult to form a crystalline interface insulating layer with a vertical thickness less than 5 nm. Therefore, the crystalline thick-film interface insulating layer 61a may have a vertical thickness of about 5 nm or greater. Since the thickness of one layer of the crystalline interface insulating layer is about 0.5 nm, the crystalline thick-film interface insulating layer 61a can be formed by repeatedly performing an atomic layer deposition process about 10 times or more to create a stack of layers. That is, for example, the crystalline thick-film interface insulating layer 61a may have at least 10 atomic layers. In one embodiment, the crystalline thick film interface insulating layer 61a can be formed by performing a deposition process (e.g., chemical vapor deposition (CVD) process) and an annealing process.

[0050] See Figure 5BThe method may further include forming a first modified interface insulating layer 61b1 by partially modifying the upper portion of the crystalline thick-film interface insulating layer 61a. For example, an atomic layer on the upper portion of the crystalline thick-film interface insulating layer 61a may be modified and transformed into the first modified interface insulating layer 61b1. The first modified interface insulating layer 61b1 may have a vertical thickness of one atomic layer. Therefore, the first modified interface insulating layer 61b1 may have a vertical thickness of about 0.5 nm. As a result, the crystalline thick-film interface insulating layer 61a may be thinned to form a first thinned crystalline thick-film interface insulating layer 61a1. Forming the first modified interface insulating layer 61b1 may include performing a first modification process. The first modification process may include chemically modifying an atomic layer of the crystalline thick-film interface insulating layer 61a using a modifying gas Gas A, which includes at least one of the halogen elements F, Cl, Br, and I. After performing the first modification process, a first pre-purge process may be performed. The first pre-purge process may be performed using at least one inert gas (e.g., nitrogen, helium, or argon).

[0051] refer to Figure 5C The method may further include removing the first modified interface insulating layer 61b1. The first modified interface insulating layer 61b1 can be removed by performing a first etching process using etching gas Gas B. The first thinned crystalline thick film interface insulating layer 61a1 can be retained after the first etching process. After performing the first etching process, a first post-purging process can be performed. The first post-purging process can be performed using at least one inert gas (e.g., nitrogen, helium, or argon).

[0052] See Figure 5D The method may further include forming a second modified interface insulating layer 61b2 by partially modifying the upper portion of the first thinned crystalline thick film interface insulating layer 61a1. For example, the uppermost atomic layer of the first thinned crystalline thick film interface insulating layer 61a1 may be modified into the second modified interface insulating layer 61b2. The second modified interface insulating layer 61b2 may also have a vertical thickness of one atomic layer. The second modified interface insulating layer 61b2 may also have a vertical thickness of about 0.5 nm. Therefore, the first thinned crystalline thick film interface insulating layer 61a1 may be thinned to form the second thinned crystalline thick film interface insulating layer 61a2. Forming the second modified interface insulating layer 61b2 may include performing a second modification process. The second modification process may include chemically modifying one atomic layer of the first thinned crystalline thick film interface insulating layer 61a1 using a modifying gas Gas A, which includes at least one of the halogen elements F, Cl, Br, and I. A second pre-purge process may be performed after the second modification process.

[0053] refer to Figure 5EThe method may further include removing the second modified interface insulating layer 61b2. The second modified interface insulating layer 61b2 can be removed by performing a second etching process using etching gas Gas B. The second thinned crystalline thick film interface insulating layer 61a2 can be retained. A second post-purging process can be performed after the second etching process.

[0054] refer to Figure 5F The method may also include repeatedly executing the reference Figures 5B to 5E The modified process, pre-purge process, etching process, and post-purge process described are used to form a preliminary crystalline thin film interface insulating layer 61. The preliminary crystalline thin film interface insulating layer 61 may have five or fewer atomic layers. For example, the preliminary crystalline thin film interface insulating layer 61 may have a vertical thickness of about 2 nm or less.

[0055] refer to Figures 5B to 5F The preliminary crystalline thin film interface insulating layer 61 can be formed by performing an atomic layer etching process. For example, a modification process, a pre-purge process, an etching process, and a post-purge process can form a cycle of an atomic layer etching process. As described above, repeated cycles of the atomic layer etching process can be performed to form the preliminary crystalline thin film interface insulating layer 61.

[0056] refer to Figure 5G The method may further include forming a preliminary crystalline thin film ferroelectric layer 71 and an upper electrode material layer 81 on the preliminary crystalline thin film interface insulating layer 61. The preliminary crystalline thin film ferroelectric layer 71 and the upper electrode material layer 81 can be formed by performing the above-mentioned reference. Figures 4A to 4G The process described is used to form it.

[0057] Subsequently, refer to Figure 3B The method may further include patterning the upper electrode material layer 81, the preliminary crystalline thin film ferroelectric layer 71, the preliminary crystalline thin film interface insulating layer 61 and the lower electrode material layer 31 by performing a patterning process to form a memory cell MC2 including the lower electrode 30, the crystalline thin film interface insulating layer 60, the crystalline thin film ferroelectric layer 70 and the upper electrode 80.

[0058] Figure 6A and Figure 6B This is a longitudinal cross-sectional view illustrating a method for forming a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0059] refer to Figure 6A The method of forming a semiconductor memory cell MC3 may include: forming a lower electrode material layer 31, forming a selection element material layer 41 on the lower electrode material layer 31, forming an intermediate electrode material layer 51 on the selection element material layer 41, and forming a crystalline thick ferroelectric layer 71a on the intermediate electrode material layer 51.

[0060] Selective element material layer 41 can be formed by performing deposition processes such as CVD and ion doping processes. Ion doping processes can include plasma doping processes or ion implantation processes. For example, forming selective element material layer 41 can include: forming a substrate insulating layer comprising at least one of silicon oxide or silicon nitride, and doping the substrate insulating layer with at least one of arsenic (As) or germanium (Ge).

[0061] The intermediate electrode material layer 51 may include a metal compound layer, such as a titanium nitride layer or a carbon layer.

[0062] The formation of the lower electrode material layer 31 and the crystalline thick ferroelectric layer 71a can be understood as described above (refer to the above reference). Figure 4A As stated above.

[0063] refer to Figure 6B The method may also include performing the above reference. Figures 4B to 4G The process described is used to form a preliminary crystalline thin film ferroelectric layer 71 and an upper electrode material layer 81.

[0064] Subsequently, refer to Figure 3C The method may further include patterning the upper electrode material layer 81, the preliminary crystalline thin film ferroelectric layer 71, the intermediate electrode material layer 51, the select element material layer 41 and the lower electrode material layer 31 by performing a patterning process to form a memory cell MC3 including a lower electrode 30, a select element layer 40, an intermediate electrode 50, a crystalline thin film ferroelectric layer 70 and an upper electrode 80.

[0065] Figure 7A and Figure 7B This is a longitudinal cross-sectional view illustrating a method for forming a memory cell of a semiconductor device according to an embodiment of the present disclosure.

[0066] refer to Figure 7A The method of forming a memory cell MC4 of a semiconductor device may include: forming a lower electrode material layer 31, forming a selection element material layer 41 on the lower electrode material layer 31, forming an intermediate electrode material layer 51 on the selection element material layer 41, and forming a crystalline thick film interface insulating layer 61a on the intermediate electrode material layer 51.

[0067] The selected element material layer 41 can be formed by performing a deposition process such as CVD and an ion doping process. As described above, the ion doping process can include a plasma doping process or an ion impedance process. For example, forming the selected element material layer 41 can include: forming a substrate insulating layer comprising at least one of silicon oxide or silicon nitride, and doping the substrate insulating layer with at least one of arsenic (As) or germanium (Ge).

[0068] The intermediate electrode material layer 51 may include a metal compound layer, such as a titanium nitride layer or a carbon layer.

[0069] The formation of the lower electrode material layer 31 and the crystalline thick film interface insulating layer 61a can be referenced as above. Figure 4A This can be understood from the above description.

[0070] refer to Figure 7B The method may also include performing the above reference. Figures 5B to 5G The process described is used to form a preliminary crystalline thin film interface insulating layer 61, a preliminary crystalline thin film ferroelectric layer 71, and an upper electrode material layer 81.

[0071] Subsequently, refer to Figure 3D The method may further include patterning the upper electrode material layer 81, the preliminary crystalline thin film ferroelectric layer 71, the preliminary crystalline thin film interface insulating layer 61, the intermediate electrode material layer 51, the select element material layer 41, and the lower electrode material layer 31 by performing a patterning process to form a memory cell MC4 having a lower electrode 30, a select element layer 40, an intermediate electrode 50, a crystalline thin film interface insulating layer 60, a crystalline thin film ferroelectric layer 70, and an upper electrode 80.

[0072] According to one embodiment of this disclosure, semiconductor devices comprising crystalline thin-film ferroelectric layers can exhibit high on-current characteristics and high on / off current ratios. Therefore, semiconductor devices according to embodiments of this disclosure can possess low power consumption, high-speed operation, and excellent data development characteristics.

[0073] The concepts have been disclosed in conjunction with the foregoing examples and embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concept of this disclosure. The embodiments disclosed in this specification should be considered from an illustrative rather than a restrictive perspective. Therefore, the scope of this disclosure is not limited to the foregoing description. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A semiconductor device, comprising: A first interconnect line extends in a first direction; A second interconnect line extends in a second direction, wherein the first direction and the second direction intersect each other; as well as A storage cell is disposed between the first interconnect and the second interconnect. The storage unit includes: Lower electrode; A crystalline ferroelectric layer is present on the lower electrode; and The upper electrode is located on the crystalline ferroelectric layer.

2. The semiconductor device according to claim 1, in, The crystalline ferroelectric layer includes a hafnium zirconium oxide layer.

3. The semiconductor device according to claim 1, wherein: The lower electrode has a first work function. The upper electrode has a second work function, and The first work function is greater than the second work function.

4. The semiconductor device according to claim 1, wherein: The lower electrode comprises titanium nitride, and The upper electrode comprises tungsten.

5. The semiconductor device according to claim 1, further comprising: A crystalline interface insulating layer is located between the lower electrode and the crystalline ferroelectric layer.

6. The semiconductor device according to claim 5, in, The crystalline interface insulating layer includes at least one of a crystalline silicon oxide layer, a crystalline hafnium oxide layer, and a crystalline zirconium oxide layer.

7. The semiconductor device according to claim 5, in, The work function of the lower electrode is the same as that of the upper electrode.

8. The semiconductor device according to claim 5, in, The lower electrode and the upper electrode are made of the same conductive material.

9. The semiconductor device according to claim 5, in, The insulating layer at the crystal interface has five atomic layers or less.

10. The semiconductor device according to claim 5, in, The thickness of the insulating layer at the crystal interface is equal to or less than 2 nm.

11. The semiconductor device according to claim 1, in, The crystalline ferroelectric layer has five atomic layers or less.

12. The semiconductor device according to claim 1, in, The thickness of the crystalline ferroelectric layer is equal to or less than 2 nm.

13. The semiconductor device according to claim 1, in, The storage unit further includes: Select an element layer located between the lower electrode and the crystalline ferroelectric layer; and An intermediate electrode is located between the selectable element layer and the crystalline ferroelectric layer.

14. The semiconductor device according to claim 1, further comprising: The selected transistor includes a drain electrode and a source electrode, the drain electrode being electrically connected to the first interconnect, and the source electrode being electrically connected to the memory cell.

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