Method for improving electric leakage of metal oxide semiconductor field effect transistor (MOSFET)

Abstract

The invention discloses a method for improving electric leakage of an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which relates to the technical field of semiconductors and comprises the following steps of: growing an oxide layer on an epitaxial layer on the surface of a substrate, carrying out photoetching, etching and ion implantation, and carrying out annealing treatment to form a voltage-resistant junction; wherein the annealing treatment comprises the following steps: putting a wafer into a furnace tube with the temperature of 730-770 DEG C, heating to 930-970 DEG C at first, heating to 1120-1170 DEG C again, cooling to 730-770 DEG C, and discharging from the furnace; according to the method, nitrogen and oxygen double atmospheres are introduced during annealing to form an oxidation film, and a special annealing temperature gradient is set, so that the center ID electric leakage of the MOSFET is effectively improved, the BV is improved, the reverse voltage stability is improved, the yield of a product is effectively improved, and the service life of the product is effectively prolonged.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for improving MOSFET leakage current. Background Technology

[0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a semiconductor power device. Due to its advantages such as simple drive circuit structure, fast switching speed, and good stability, it is widely used as a switching device and for amplifying electronic signals in electronic devices.

[0003] Among these, the reverse withstand voltage of a MOSFET is a fundamental characteristic, representing the voltage level of its operating environment. Withstand voltage and reverse leakage current are complementary parameters; consistent withstand voltage and reverse leakage current significantly impact the final product's usability. Many factors affect withstand voltage and reverse leakage current, the most directly related being the perfection and flawlessness of the device's reverse withstand junction. Current manufacturing processes often result in abnormalities in reverse withstand voltage and reverse leakage current in the wafer's central region, leading to lower reverse voltage, poor consistency, and higher leakage current. This negatively impacts product yield and the stability of the final product.

[0004] Therefore, a method for improving MOSFET leakage current is provided to solve this problem. Summary of the Invention

[0005] This invention aims to address the technical problems of low reverse voltage, poor consistency, and high leakage current in existing MOSFET products. The goal is to provide a method to improve MOSFET leakage current by introducing a nitrogen and oxygen dual atmosphere during annealing to form an oxide film and setting a special annealing temperature gradient. This effectively improves the leakage current at the center ID of the MOSFET and increases the BV. At the same time, the reverse voltage stability is improved, thereby effectively increasing the product yield and service life.

[0006] The present invention is achieved through the following technical solution.

[0007] The first objective of this invention is to provide a method for improving MOSFET leakage current, comprising the following steps: An oxide layer is grown on the epitaxial layer on the substrate surface, and photolithography, etching and ion implantation are performed, followed by annealing to form a breakdown junction; The annealing process includes: placing the wafer in a furnace tube at 730-770°C, heating it to 930-970°C in a nitrogen and oxygen atmosphere, then heating it to 1120-1170°C, and finally cooling it to 730-770°C before removing it from the furnace.

[0008] In the prior art, when wafers are annealed in pure nitrogen, the bare silicon or poly may be nitrided in pure nitrogen, resulting in nitrides, which can affect the parameters of the product. Furthermore, under certain conditions, at high temperatures, the dopant ions in heavily doped poly may overflow into the furnace atmosphere, affecting the unprotected PN junction surface (i.e., the open area of ​​bare silicon or the area with a very thin oxide layer), which in turn can lead to a larger leakage current during CP testing.

[0009] Through long-term process exploration, the inventors discovered that introducing oxygen into a nitrogen atmosphere during annealing can rapidly grow an oxide layer on the poly surface, encapsulating the doped ions inside the poly and ensuring that the doped ions do not overflow into the furnace tube. This protects the device structure from being affected by other ions and also increases the PN junction depth. The resulting device has better reverse withstand voltage and reverse leakage current, effectively improving the product yield and service life.

[0010] Furthermore, the present invention employs a temperature range of low (730-770℃) – medium (930-970℃) – high (1120-1170℃) – low (730-770℃) for annealing, which can effectively reduce warping or cracking of wafers caused by stress during the thermal process.

[0011] Furthermore, during the heating process, the nitrogen to oxygen flow rate ratio is (7-9):(6-9). During the cooling process, the nitrogen flow rate remains constant, while the oxygen flow rate is reduced to 1-2.5% of the heating flow rate. No oxygen is introduced during the unloading process. Throughout the annealing process, the oxygen flow rate decreases from a high initial flow rate to a low flow rate, and finally to zero upon unloading. This allows for the rapid growth of an oxide layer in the early stages of annealing, providing protection, while the subsequent reduction in oxygen levels prevents excessive oxidation.

[0012] Furthermore, the annealing process includes the following steps: The internal temperature of the furnace tube is set to 730-770℃, and the wafer is slowly fed into the furnace and kept at that temperature. The furnace tubes are heated from 730-770℃ to 930-970℃ and then kept at that temperature. The furnace tubes are heated from 930-970℃ to 1120-1170℃ and then kept at that temperature. The furnace tubes were cooled from 1120-1170℃ to 730-770℃; Wafers are being produced.

[0013] Furthermore, the wafer is slowly fed into the furnace and kept at a constant temperature, specifically including: The wafer feed rate is 8-14 mm / min, the nitrogen flow rate is 9-14 L / min, the oxygen flow rate is 9-12 L / min, and the duration is 20-25 min; After the wafers are placed in the furnace, the furnace tubes remain stationary to ensure that the temperature of the wafers inside the furnace tubes is uniform and stable. Keep the nitrogen and oxygen flow rates constant for 10-15 minutes.

[0014] Furthermore, the furnace tubes are heated from 730-770℃ to 930-970℃ and then kept at that temperature, specifically including: The furnace tube temperature is increased to 930-970℃ at a rate of 5-7℃ / min, with a nitrogen flow rate of 9-14L / min and an oxygen flow rate of 9-12L / min, for 50-60min. Keep the furnace tube stationary to ensure the wafer temperature inside the furnace tube is uniform and stable. Maintain constant nitrogen and oxygen flow rates for 10-20 minutes.

[0015] Furthermore, the furnace tubes are heated from 930-970℃ to 1120-1170℃ and then kept at that temperature, specifically including: The furnace tube is heated to 1120-1170℃ at a heating rate of 5-9℃ / min, with a nitrogen flow rate of 9-14L / min and an oxygen flow rate of 9-12L / min, for a duration of 40-50min. Keep the furnace tube stationary to ensure that the wafer temperature inside the furnace tube is uniform and stable. Maintain a constant nitrogen flow rate and reduce the oxygen flow rate to 150-180 mL / min for 10-20 minutes. After the temperature stabilizes, maintain it for another 50-70 minutes.

[0016] Furthermore, the furnace tube is cooled from 1120-1170℃ to 730-770℃, specifically including: a furnace tube cooling rate of 3-6℃ / min, a nitrogen flow rate of 9-14L / min, an oxygen flow rate of 150-180mL / min, for a duration of 133-160min.

[0017] Furthermore, the wafer unloading process specifically includes: slowly removing the wafer from the furnace tube, preparing it for unloading; the unloading rate is 15-25 mm / min, the nitrogen flow rate during the unloading process is 7-12 L / min, and it lasts for 20-35 min.

[0018] Furthermore, the annealing process also includes the following steps: Deposition medium layer; Heavy doping is performed to form good ohmic contacts; Frontal metal deposition; Deposition of passivation layer; Metal evaporates on the back.

[0019] A second objective of this invention is to provide a MOSFET device fabricated by the aforementioned method.

[0020] Compared with the prior art, the present invention has the following advantages and beneficial effects: 1. In the annealing process, oxygen is introduced into a nitrogen atmosphere, which enables the rapid growth of an oxide layer on the poly surface to encapsulate the doped ions inside the poly, ensuring that the doped ions do not overflow into the furnace tube, thus protecting the device structure from the influence of other ions. At the same time, it can also increase the PN junction depth, thereby improving the reverse withstand voltage and reverse leakage current of the final device, effectively improving the product yield and service life. 2. The present invention uses a temperature range of low temperature (730-770℃) - medium temperature (930-970℃) - high temperature (1120-1170℃) - low temperature (730-770℃) for annealing, which can effectively reduce the warping or cracking of wafers caused by stress during the thermal process. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of a MOSFET device prepared based on the method of the present invention; Figure 2 A variability graph of IDSS for 48 wafers produced using the process described in this example; Figure 3 A BVDSS variability graph for 48 wafers produced using the process described in this example; Figure 4 The figures show the MAPs after the CP test, with the left figure showing the MAP of Comparative Example 1 product after the CP test and the right figure showing the MAP of Example 1 product after the CP test. Figure 5 The figure shows the BV parameter MAP, where the left figure is the BV parameter MAP of Comparative Example 1 and the right figure is the BV parameter MAP of Example 1.

[0022] The attached diagram shows the markings and corresponding component names: 1-Backside metal, 2-Substrate, 3-Epipolar layer, 4-Oxide region, 5-Dielectric layer, 6-Frontside metal region, 7-Bottom junction, 8-Heavy doped P-type impurity region, 9-Poly region, 10-Channel region, 11-Gate oxide region. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0024] The following detailed description of an embodiment of a method for improving MOSFET leakage current according to the present invention is provided with appropriate reference to the accompanying drawings. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repeated descriptions may be omitted. This is to avoid making the following description unnecessarily lengthy and to facilitate understanding by those skilled in the art.

[0025] The "scope" disclosed in this invention is defined in the form of a lower limit and an upper limit. A given scope is defined by selecting a lower limit and an upper limit, which define the boundaries of the specific scope. The scope defined in this way can include or exclude end values, and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a scope.

[0026] Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions.

[0027] Unless otherwise specified, all technical features and optional technical features of this invention can be combined to form new technical solutions.

[0028] Unless otherwise specified, the terms "comprising" and "including" as used in this invention can be open-ended or closed-ended. For example, "comprising" and "including" can mean that other substances not listed may also be included, or that only the listed substances may be included.

[0029] Unless otherwise specified, all steps of the present invention may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the mention that the method may also include step (c) indicates that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.

[0030] The technical solution of the present invention will be further described in detail below with reference to the embodiments.

[0031] It should be noted that, unless otherwise specified, the experimental methods used in the embodiments are conventional methods. Unless otherwise specified, the materials, reagents, methods, and instruments used are all conventional materials, reagents, methods, and instruments in the art, and can be obtained commercially by those skilled in the art.

[0032] Example 1 A method for improving MOSFET leakage current, and devices fabricated based on this method, such as... Figure 1 As shown, it includes the following steps.

[0033] S1. Material preparation: Raw materials include wafers and gases such as nitrogen and oxygen; S11. The wafer is subjected to sacrificial oxidation and sacrificial oxygen etching in sequence to remove surface defects of epitaxial layer 3 (epitaxy layer 3 is set on the surface of substrate 2) to ensure product parameters and reliability. S12, obtained after the first oxidation. Figure 1 Oxidation region 4 (also known as gate oxide region 11) is obtained after the first poly deposition. Figure 1 In the Poly region 9, after the first photolithography and the first etching, a voltage-resistant ring and an open region of the voltage-resistant PN junction in the die are formed to allow for normal subsequent ion implantation, forming a voltage-resistant PN structure and a voltage-resistant ring; S13. Perform a second photolithography and implantation on the wafer sequentially.

[0034] S2, Post-injection annealing: Repairs the damage caused by injection in S1, forming a pressure-resistant PN structure and a pressure-resistant ring, thus obtaining... Figure 1 The withstand voltage junction 7 in the middle, this region is located Figure 1 Middle P+ position; S21, Furnace tube standby: Set the internal temperature of the furnace tube to 730-770℃; S22. Product feeding into the furnace: The product is slowly fed into the furnace tube at a rate of 8-14 mm / min, with a nitrogen supply of 9-14 L / min and an oxygen supply of 9-12 L / min, for a duration of 20-25 min. S23, Furnace tube stability: After the product enters the furnace, the furnace tube remains stationary to ensure that the wafer temperature inside the furnace tube is uniform and the furnace tube temperature is stable. Provide a large amount of nitrogen 9-14L / min and a large amount of oxygen 9-12L / min for 10-15min. S24. Furnace tube heating: The furnace tube is heated from 730-770℃ to 930-970℃ at a rate of 5-7℃ / min, with a nitrogen supply of 9-14L / min and an oxygen supply of 9-12L / min, for 50-60min. S25, Furnace tube stability: After the product enters the furnace, the furnace tube remains stationary to ensure that the wafer temperature inside the furnace tube is uniform and the furnace tube temperature is stable. Provide a large amount of nitrogen 9-14L / min and a large amount of oxygen 9-12L / min for 10-20 minutes. S26. Furnace tube heating: The furnace tube is heated from 930-970℃ to 1120-1170℃ at a rate of 5-9℃ / min, with a nitrogen supply of 9-14L / min and an oxygen supply of 9-12L / min, for 40-50min. S27. Furnace tube stability: After the product enters the furnace, the furnace tube remains stationary to ensure that the wafer temperature inside the furnace tube is uniform and the furnace tube temperature is stable. Provide a large amount of nitrogen at 9-14L / min and a small amount of oxygen at 150-180mL / min for 10-20min. S28. Annealing process: Anneal at 1120-1170℃ for 50-70 min; the annealing process provides 9-14 L / min of nitrogen and 150-180 mL / min of oxygen. S29. Furnace tube cooling: The temperature drops from 1120-1170℃ to the furnace tube outlet temperature of 730-770℃; the furnace tube cooling rate is 3-6℃ / min, providing 9-14L / min of nitrogen and 150-180mL / min of oxygen, lasting for 133-160min. S210, Product Unloading: Slowly remove the product from the furnace tube, preparing it for unloading. The product unloading rate is 15-25 mm / min, with a nitrogen supply of 7-12 L / min for 20-35 minutes.

[0035] S3. The wafer is sequentially subjected to a third photolithography, etching, a second implantation, oxidation, and dielectric layer deposition to protect the formed structure. S31. The third photolithography step mainly involves XN implantation blocking, which opens the region and forms a low-resistance ohmic contact after implantation; it also forms an effective conductive region, ensuring that current can flow into and out of the channel region efficiently, i.e. Figure 1 Channel area 10; S32. Next, an ILD dielectric layer is deposited. Its function is to physically isolate the conductive components of the device from the metal above, preventing short circuits, etc., thus obtaining... Figure 1 Medium layer 5 in the middle.

[0036] S4. The wafer is sequentially subjected to a fourth photolithography, etching, and two-step implantation to form a good ohmic contact. S41. The fourth photolithography and etching process physically opens a channel to prepare for subsequent implantation and metal filling, allowing the metal to make electrical connections with the electrodes below through this hole. S42. Heavy doping at the contact hole location can significantly reduce the ohmic contact resistance of this interface; thus obtaining... Figure 1 The P-type impurity heavily doped region 8 in the middle.

[0037] S5. The wafer is sequentially subjected to metal deposition, fifth photolithography, and metal etching to form the front contact area; S51. Metal deposition is a process that involves depositing a thin metal film on the surface of a wafer to create a conductive path and achieve electrical connections between devices. S52, the fifth photolithography and metal etching process selectively removes excess metal material to form the interconnect wires, electrodes, and pad structures required by the design, thus constructing the electrical connections for the device. Figure 1 The front metal area 6.

[0038] S6. Passivation layer deposition, sixth photolithography, and thinning are performed sequentially on the wafer to protect the entire device from the influence of the external environment. S61. Isolates the internal circuitry from external environmental physical (scratch and impact), chemical (moisture and ion isolation) and electrical damage (reduces leakage and short circuit risk, and resists electrostatic discharge), increasing product reliability. S62, the sixth photolithography step is a passivation layer that is not needed by dry etching, exposing the metal pads for the packaging plant to use for wire bonding.

[0039] S7. Perform back-side metal evaporation on the wafer sequentially; S71, Backside metal evaporation constructs low-resistance electrodes, heat dissipation channels, and mechanical support layers on the back of the product, i.e. Figure 1 Metal area 1 on the back side.

[0040] Comparative Example 1 The difference between this comparative example and Example 1 is that no oxygen is introduced during the annealing process.

[0041] The products prepared by the methods of Example 1 and Comparative Example 1 were tested in terms of appearance, PN junction, and electrical parameters (BVDSS IDSS).

[0042] 1. Appearance: The product obtained by the method in Example 1 of this invention has a uniform and bright surface color with no color difference.

[0043] 2. PN junction: The PN junction of the product slices of the present invention was observed in the source region and the terminal region, and the results were normal.

[0044] 3. Electrical parameters (1) Forty-eight wafers produced using the process described in the example were tested, and the variability diagrams of IDSS and BVDSS were obtained as follows: Figure 2 and Figure 3 As shown; from Figure 2 and Figure 3 It can be seen that the test repeatability is good.

[0045] (2) The reverse voltage and reverse leakage current of the products of Example 1 and Comparative Example 1 of the present invention were tested respectively, and the different processes were numbered as 1#~4#, 6#~23# and 25# respectively. Among them, products 11# and 13#~15# were processed by the process of Comparative Example 1, while products 1#~4#, 6#~10#, 12#, 16#~23# and 25# were processed by the process of Example 1 of the present invention. The test results are shown in Table 1.

[0046] Table 1. Reverse voltage and reverse leakage current test results of the products prepared in Example 1 and Comparative Example 1

[0047] As can be seen from the results in Table 1, the process of Example 1 ensured the consistency of BVDSS and improved the overall BV (reverse voltage). At the same time, the ID (reverse leakage current) leakage was significantly improved.

[0048] (3) MAP after CP test: such as Figure 4 As shown, the left figure shows the process of Comparative Example 1, where the center exhibits IDSS leakage current exceeding SPC failure; the right figure shows the process of Example 1, which performs well.

[0049] (4) BV parameter MAP: such as Figure 5 As shown, the left side is the BV parameter MAP of the product prepared by the process of Comparative Example 1, which shows that the center has a low BV and exceeds SPC failure. The right side is the BV parameter MAP of the product prepared by the process of Example 1 of the present invention, which shows good performance. In addition, from Figure 5 It can be seen that the reverse voltage BV at the center of the wafer obtained by the initial process is only about 50V; while the reverse voltage of the product obtained by the process of the present invention is about 73V. This shows that the method of the present invention can improve the leakage current ID at the center of the MOSFET, increase BV, and obtain a stable reverse voltage.

[0050] Finally, it should be noted that the above specific embodiments are only used to describe the purpose, technical solution, and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation of the present invention and is not intended to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to the foregoing specific embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions or improvements can be made to some or all of the technical features. These modifications, equivalent substitutions, and improvements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A method for improving MOSFET leakage current, characterized in that, Includes the following steps: An oxide layer is grown on the epitaxial layer on the substrate surface, and photolithography, etching and ion implantation are performed, followed by annealing to form a breakdown junction; The annealing process includes: placing the wafer in a furnace tube at 730-770°C, heating it to 930-970°C in a nitrogen and oxygen atmosphere, then heating it to 1120-1170°C, and finally cooling it to 730-770°C before removing it from the furnace.

2. The method for improving MOSFET leakage current according to claim 1, characterized in that, During the heating process, the nitrogen to oxygen flow ratio is (7-9):(6-9). During the cooling process, the nitrogen flow remains unchanged, while the oxygen flow is reduced to 1-2.5% of the heating flow. No oxygen is introduced during the unloading process.

3. The method for improving MOSFET leakage current according to claim 1, characterized in that, The annealing process includes the following steps: The internal temperature of the furnace tube is set to 730-770℃, and the wafer is slowly fed into the furnace and kept at that temperature. The furnace tubes are heated from 730-770℃ to 930-970℃ and then kept at that temperature. The furnace tubes are heated from 930-970℃ to 1120-1170℃ and then kept at that temperature. The furnace tubes were cooled from 1120-1170℃ to 730-770℃; Wafers are being produced.

4. The method for improving MOSFET leakage current according to claim 3, characterized in that, The wafer is slowly fed into the furnace and kept at a constant temperature, specifically including: The wafer feed rate is 8-14 mm / min, the nitrogen flow rate is 9-14 L / min, the oxygen flow rate is 9-12 L / min, and the duration is 20-25 min; After the wafers are placed in the furnace, the furnace tubes remain stationary to ensure that the temperature of the wafers inside the furnace tubes is uniform and stable. Keep the nitrogen and oxygen flow rates constant for 10-15 minutes.

5. The method for improving MOSFET leakage current according to claim 3, characterized in that, The furnace tubes are heated from 730-770℃ to 930-970℃ and then kept at that temperature, specifically including: The furnace tube temperature is increased to 930-970℃ at a rate of 5-7℃ / min, with a nitrogen flow rate of 9-14L / min and an oxygen flow rate of 9-12L / min, for 50-60min. Keep the furnace tube stationary to ensure the wafer temperature inside the furnace tube is uniform and stable. Maintain constant nitrogen and oxygen flow rates for 10-20 minutes.

6. The method for improving MOSFET leakage current according to claim 3, characterized in that, The furnace tubes are heated from 930-970℃ to 1120-1170℃ and then kept at that temperature, specifically including: The furnace tube is heated to 1120-1170℃ at a heating rate of 5-9℃ / min, with a nitrogen flow rate of 9-14L / min and an oxygen flow rate of 9-12L / min, for a duration of 40-50min. Keep the furnace tube stationary to ensure that the wafer temperature inside the furnace tube is uniform and stable. Maintain a constant nitrogen flow rate and reduce the oxygen flow rate to 150-180 mL / min for 10-20 minutes. After the temperature stabilizes, maintain it for another 50-70 minutes.

7. The method for improving MOSFET leakage current according to claim 3, characterized in that, The furnace tube temperature is reduced from 1120-1170℃ to 730-770℃, specifically including: a furnace tube cooling rate of 3-6℃ / min, a nitrogen flow rate of 9-14L / min, an oxygen flow rate of 150-180mL / min, and a duration of 133-160min.

8. The method for improving MOSFET leakage current according to claim 3, characterized in that, The wafer unloading process specifically includes: slowly removing the wafer from the furnace tube, preparing it for unloading; the unloading rate is 15-25 mm / min, the nitrogen flow rate during the unloading process is 7-12 L / min, and it lasts for 20-35 min.

9. The method for improving MOSFET leakage current according to claim 1, characterized in that, The annealing process also includes the following steps: Deposition medium layer; Heavy doping is performed to form good ohmic contacts; Frontal metal deposition; Deposition of passivation layer; Metal evaporates on the back.

10. A MOSFET device, characterized in that, Prepared by the method described in claim 9.

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