Gallium nitride semiconductor device and preparation method thereof

Abstract

The invention provides a gallium nitride semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The gallium nitride semiconductor device comprises a substrate, a buffer layer, a GaN channel layer and an AlGaN barrier layer which are sequentially laminated, the AlGaN barrier layer is provided with a composite AlGaN nano-column trapezoidal groove located below a grid electrode, and the composite AlGaN nano-column trapezoidal groove penetrates through the AlGaN barrier layer in a third direction perpendicular to the lamination direction and the channel length direction. A plurality of AlGaN nano-columns arranged along the lamination direction are arranged in the composite AlGaN nano-column trapezoidal groove, and areas among the AlGaN nano-columns are filled with insulating layers. According to the structure, a gate electric field accurately regulates and controls 2DEG in the GaN channel layer mainly through the AlGaN nanorod without an interface state, and meanwhile, leakage current is effectively blocked by the insulating layer. According to the invention, the problems of threshold drift and response delay caused by an interface state of a traditional insulated gate structure are fundamentally solved, and the stability and response speed of a device are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a gallium nitride semiconductor device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) semiconductor devices, especially AlGaN / GaN high electron mobility transistors (HEMTs), have become key components in high-frequency, high-power applications such as 5G communications, power electronics, electric vehicles, and RF amplifiers due to their high electron mobility, high breakdown field strength, and excellent thermal stability. Traditional GaN HEMTs typically employ a Schottky gate structure, but this structure suffers from significant gate leakage current issues. This not only increases the device's static power consumption but also limits its reliable operation at high gate voltages.

[0003] To address the gate leakage problem, current technologies generally employ the insertion of a dielectric insulating layer (such as...) between the gate metal and the AlGaN barrier layer. , The proposed scheme constructs a metal-insulator-semiconductor (MIS) structure. While this MIS-HEMT structure can reduce gate leakage current by several orders of magnitude, it introduces a new and more challenging problem: the heterogeneous interface formed between the insulating layer and the AlGaN semiconductor contains numerous interface state defects. These interface states act as charge traps, capturing and releasing electrons in the channel during device operation. This slow charge trapping / de-trapping process triggers a series of serious adverse effects. First, it causes the device's threshold voltage (Vth) to drift, making the device's switching characteristics unstable and severely affecting the circuit's reliability and long-term operational stability. Second, the charging and discharging response speed of the interface states is much slower than the device's switching speed, which leads to a significant delay in the gate's control of the two-dimensional electron gas (2DEG) in the channel, manifesting as a decrease in device response speed and deterioration in high-frequency performance, the so-called "current collapse" effect. Therefore, the existing technology is caught in a dilemma: measures to suppress leakage current sacrifice device stability and dynamic performance. Designing a GaN device structure that can effectively suppress gate leakage, maintain a high-quality interface, and avoid threshold drift and modulation delay has become a key technical challenge that urgently needs to be solved in this field. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a gallium nitride semiconductor device that can solve the technical problem that although inserting an insulating layer can reduce leakage current, it will introduce interface states, resulting in 2DEG control delay and threshold drift, which affects the device response speed and stability.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows: In a first aspect, the present invention provides a gallium nitride semiconductor device, comprising: A substrate, a buffer layer, a GaN channel layer, and an AlGaN barrier layer are stacked sequentially along the first direction; Gate; The source and drain electrodes disposed on the AlGaN barrier layer are distributed on both sides of the gate along the second direction; The composite AlGaN nanopillar trapezoidal groove is formed on the side of the AlGaN barrier layer facing the gate, and penetrates the AlGaN barrier layer in a third direction perpendicular to the first and second directions. An AlGaN nanopillar array is disposed within the trapezoidal groove of the composite AlGaN nanopillar array. Each AlGaN nanopillar in the AlGaN nanopillar array is arranged along a first direction, and its two ends are respectively connected to the bottom of the trapezoidal groove of the composite AlGaN nanopillar array and the gate. The non-AlGaN nanopillar regions within the trapezoidal groove of the composite AlGaN nanopillars are filled with an insulating layer. When the gate is powered on, a 2DEG is formed in the GaN channel layer as a conductive channel.

[0006] In a second aspect, the present invention provides a preparation method for preparing the gallium nitride semiconductor device described in the first aspect, comprising the following steps: S1: Pre-treat the substrate; S2: A buffer layer is grown on the substrate by metal-organic chemical vapor deposition; S3: Grow a GaN channel layer on the buffer layer; S4: Grow an AlGaN barrier layer on the GaN channel layer; S5: Define the pattern of the trapezoidal groove of the composite AlGaN nanopillar using electron beam lithography; S6: Based on the pattern of the composite AlGaN nanopillar trapezoidal groove, the composite AlGaN nanopillar trapezoidal groove is generated by ICP-RIE etching technology. S7: Grow several AlGaN nanopillars in the non-sidewall region of the trapezoidal groove of the composite AlGaN nanopillars to form an AlGaN nanopillar array; S8: Deposit an insulating layer in the non-AlGaN nanopillar region of the composite AlGaN nanopillar trapezoidal groove; S9: Combine photolithography alignment technology to grow the gate, source, and drain.

[0007] Compared with the prior art, the beneficial effects of the present invention are: (1) By setting a trapezoidal groove of composite AlGaN nanopillars below the gate and arranging an AlGaN nanopillar array that is homogeneous with the barrier layer in the groove, the electric field is mainly conducted to the channel through the AlGaN nanopillars, which greatly reduces the interface trap effect caused by the sandwich structure of gate-insulator-barrier layer in traditional MIS structure, avoids defects caused by material interface mismatch, improves structural integrity and stability, and can effectively enhance the polarization electric field, so that the device can achieve fine control of the electric field of the gate control region without relying on a large area of ​​insulating layer coverage.

[0008] (2) Although there is still an insulating layer in the trapezoidal groove of the composite AlGaN nanopillar, it only fills the non-nanopillar region, avoiding direct contact between the gate and the AlGaN barrier layer, effectively blocking leakage current, and reducing the introduction of interface states. This solves the problems of modulation hysteresis and threshold drift caused by traditional insulating layers, thus taking into account both leakage suppression and high-speed response characteristics.

[0009] (3) The groove adopts a trapezoidal structure. Its inclined sidewalls can effectively alleviate the electric field concentration effect at the edge of the groove, so that the electric field lines are more gently distributed, reducing the local electric field peaks, thereby significantly improving the withstand voltage and breakdown voltage of the device and enhancing the robustness of the device in power applications.

[0010] (4) Since the core AlGaN nanopillars are generated in situ on the AlGaN barrier layer through epitaxial growth technology, there is no lattice mismatch or thermal mismatch between the two, which ensures high crystal integrity and structural stability. Compared with the traditional process that requires additional deposition and etching of insulating layers, this preparation method has more advantages in atomic-level size and morphology control, which is conducive to improving the uniformity and yield of the device.

[0011] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of a gallium nitride semiconductor device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a gate structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a gallium nitride semiconductor device excluding three terminals provided in an embodiment of the present invention; Figure 4 This is a schematic flowchart of a gallium nitride semiconductor device fabrication method provided in an embodiment of the present invention.

[0014] In the figure: 1. Substrate; 2. Buffer layer; 3. GaN channel layer; 4. AlGaN barrier layer; 5. Source; 6. Gate; 7. Drain; 8. Trapezoidal groove of composite AlGaN nanopillar; 9. AlGaN nanopillar; 10. First inclined sidewall; 11. Second inclined sidewall. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0016] like Figure 1 The diagram illustrates a schematic of a gallium nitride (GaN) semiconductor device according to an embodiment of the present invention. The GaN semiconductor device achieves effective control of the two-dimensional electron gas (2DEG) density by setting a trapezoidal groove filled with an insulating layer in the AlGaN barrier layer 4, and arranging uniformly arranged AlGaN nanopillars 9 within the groove. This structure allows the electric field of the gate 6 to be precisely applied to the GaN channel layer 3 through the nanopillars, while the insulating layer blocks direct contact between the gate 6 and the barrier layer, effectively suppressing leakage current and avoiding the interface traps and electrical hysteresis problems introduced by traditional large-area insulating structures, thereby improving the stability and response speed of the device. Figure 1 annotations in Indicates the inclination angle of the first inclined sidewall 10, marked. This indicates the inclination angle of the second inclined sidewall 11.

[0017] like Figure 2 The diagram illustrates a gate structure according to an embodiment of the present invention. In this embodiment, an array of nanopillars is disposed within the groove of the AlGaN barrier layer 4 beneath the gate metal layer, with the tops of the nanopillars forming ohmic contacts with the gate metal layer. This design allows the gate electric field to act perpendicularly on the channel region through multiple nanopillar channels, facilitating uniform electric field distribution and fine-tuning of the two-dimensional electron gas (2DEG), thereby improving device performance and reliability. Figure 2 To simplify the drawing, nanopillars in the same column are depicted within the same black bar area. This means that the marked black area contains multiple nanopillars. Correspondingly, the number of black bar areas is also simplified; the actual number is... Figure 3The number of nanopillars is the same.

[0018] like Figure 3 The diagram illustrates a schematic of a gallium nitride semiconductor device without three terminals according to an embodiment of the present invention. The gallium nitride semiconductor device provided by the present invention has a regularly arranged array of nanopillars in the AlGaN barrier layer 4, located in the gate 6 region between the source 5 and the drain 7, and sidewalls with defined structures on both sides. The diagram highlights the spatial distribution of the nanopillars in the second and third directions, which is beneficial for enhancing the uniformity of the polarization electric field and the controllability of the two-dimensional electron gas (2DEG), providing a stable foundation for the subsequent formation of the three-terminal structure.

[0019] This invention provides a gallium nitride semiconductor device, comprising: A substrate 1, a buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, and three terminals are sequentially stacked in a first direction. The three terminals include a source 5, a gate 6, and a drain 7. A composite AlGaN nanopillar trapezoidal groove 8 is formed on the side facing the gate 6. The composite AlGaN nanopillar trapezoidal groove 8 extends through the AlGaN barrier layer 4 in a third direction perpendicular to the first and second directions. Multiple AlGaN nanopillars 9 arranged along the first direction are disposed in the non-sidewall region of the composite AlGaN nanopillar trapezoidal groove 8. The non-AlGaN nanopillar 9 region of the composite AlGaN nanopillar trapezoidal groove 8 is filled with an insulating layer. When the gate 6 is powered on, a 2DEG serving as a conductive channel is formed in the GaN channel layer 3.

[0020] The substrate, serving as the foundation of the entire device structure, is typically made of Si, SiC, or sapphire, providing mechanical support and determining the device's heat dissipation performance and cost. A buffer layer, located between the substrate 1 and the GaN channel layer 3, alleviates lattice mismatch and thermal expansion mismatch, suppresses defect conduction, and improves the quality of the GaN layer. The GaN channel layer provides the basis for the formation of 2DEG; due to GaN's high electron mobility, this layer plays a crucial role in efficient electron transport. The AlGaN barrier layer, due to its polarization effect, forms a two-dimensional electron gas (2DEG) with the GaN channel layer 3, providing a high carrier concentration. In the three-terminal array (source 5, gate 6, drain 7), source 5 and drain 7 are used for current injection and collection. Gate 6 is used to regulate the formation and transport of 2DEG in the channel and is the core structure for current control. A trapezoidal groove 8 of composite AlGaN nanopillars is formed in the AlGaN barrier layer 4 below the gate 6. This groove structure penetrates the barrier layer and its width is aligned with the gate 6 in the second direction. Its geometry facilitates control of the electric field distribution. AlGaN nanopillars 9 are arranged in the non-sidewall region within the groove. They are made of homogeneous AlGaN material and have no lattice mismatch with the barrier layer, which helps to enhance the polarization electric field, regulate the 2DEG density, and can be directly "carved" through epitaxial processes without adding additional manufacturing costs. The insulating layer fills only the gaps between the nanopillars to suppress leakage current, prevent direct conduction between the gate 6 and the barrier layer, and maintain good control over the 2DEG.

[0021] Specifically, by introducing a composite AlGaN nanopillar trapezoidal groove structure 8 into the AlGaN barrier layer 4, and setting a uniformly arranged AlGaN nanopillar array within the groove, the polarization electric field control capability of the gate 6 over the two-dimensional electron gas (2DEG) in the channel is effectively improved. The nanopillars and the barrier layer are made of the same material, avoiding the generation of heterogeneous interface defects and enhancing structural integrity and interface quality. Simultaneously, the nanopillar conduction path reduces the distance the electric field travels through the insulating layer, making control more direct and the response faster. Compared to traditional MIS structures, this structure only locally fills the insulating layer in the non-nanopillar regions, effectively suppressing gate 6 leakage and significantly reducing the formation of interface trap states, thus mitigating 2DEG density drift and threshold instability. Furthermore, this nanostructure can be grown in situ using epitaxial processes without complex post-processing, exhibiting higher manufacturing compatibility and process robustness, and overall improving the device's reliability, electrical performance, and scalability potential.

[0022] In this embodiment of the invention, by setting a trapezoidal groove 8 of composite AlGaN nanopillars below the gate 6 and arranging an AlGaN nanopillar array homogeneous with the barrier layer within the groove, defects caused by material interface mismatch are avoided, structural integrity and stability are improved, and the polarization electric field is effectively enhanced. This allows the device to achieve fine control of the electric field in the gate-controlled region without relying on a large-area insulating layer. Although an insulating layer still exists in the groove, it only fills the non-nanopillar region, avoiding direct contact between the gate 6 and the AlGaN barrier layer 4, effectively blocking leakage current, and reducing the introduction of interface states. This solves the control hysteresis and threshold drift problems caused by traditional insulating layers, thus balancing leakage suppression and high-speed response characteristics. At the same time, since the electric field is mainly conducted to the channel through the AlGaN nanopillars 9, the interface trap effect caused by the "gate-insulator-barrier layer" sandwich structure in traditional MIS structures is greatly reduced.

[0023] In one possible implementation, the opening width of the composite AlGaN nanopillar trapezoidal groove 8 in the second direction is consistent with the extension width of the gate 6 in the second direction.

[0024] It is understandable that by making the opening width of the trapezoidal groove 8 of the composite AlGaN nanopillar consistent with the extension width of the gate 6 in the second direction, the gate electric field can be ensured to completely cover the groove region, thereby achieving full control of the 2DEG region and improving the electrical control uniformity and performance stability of the device.

[0025] In one possible implementation, the composite AlGaN nanopillar trapezoidal groove 8 is provided with sidewalls on both sides in the second direction, wherein the sidewalls include a first sidewall and a second sidewall arranged in a relatively mirror-symmetrical manner, wherein the inclination angle of the first inclined sidewall 10 and the inclination angle of the second inclined sidewall 11 are related to the desired 2DEG density.

[0026] It should be noted that by setting mirror-symmetrical inclined sidewalls on both sides of the trapezoidal groove 8 of the composite AlGaN nanopillar, the electric field lines are reasonably distributed along the direction of the sidewalls, and their normal components are controlled, thereby affecting the formation and density of 2DEG and achieving precise control of the channel current carrying capacity.

[0027] In one possible implementation, the inclination angle of the first inclined sidewall 10 and the inclination angle of the second inclined sidewall 11 are calculated as follows: in, Indicates the inclination angle of the first inclined sidewall. Let represent the dip angle of the second inclined sidewall, arctan represent the arctangent function, and cot represent the cotangent function. This indicates the height of the trapezoidal groove in the first direction of the composite AlGaN nanopillar. Indicates the thickness of the AlGaN barrier layer. This indicates the maximum width of the trapezoidal groove in the second direction, i.e., the opening width. This represents the minimum width of the trapezoidal groove in the second direction of the composite AlGaN nanopillar. and These represent the dielectric constants of the insulating layer and AlGaN, respectively. Indicates the expected 2DEG density. This represents the lateral electric field distortion compensation term within the trapezoidal groove of the composite AlGaN nanopillar. Represents pi (π). This represents the correction factor.

[0028] The minimum width is the bottom width of the trapezoidal groove in the composite AlGaN nanopillar. Correction coefficient. It is the core parameter for controlling the transverse electric field compensation term ΔL, used to bridge the gap between the theoretical model and the actual structure. It is not a fixed constant, but depends on the adjustment amount of the device design goals and process parameters, and it is usually recommended to obtain it through simulation and experimental optimization.

[0029] It should be noted that the trapezoidal structure of the groove and the dielectric difference between the insulating layer and AlGaN lead to two problems. Problem 1: Electric field spikes: Localized high electric fields are generated at the groove edges due to dielectric abrupt changes, which may trigger breakdown. Problem 2: Uneven 2DEG distribution: Lateral electric field distortion affects the electron gas density, causing fluctuations in on-resistance. The lateral electric field distortion compensation term models this distortion and compensates for the electric field distribution by adjusting the tilt angle of the inclined sidewalls to avoid the above problems. Specifically, by introducing the tilt angles of the first and second inclined sidewalls, which are dynamically calculated based on the lateral electric field distortion compensation term, the problem of electric field concentration caused by the difference in dielectric constants between AlGaN and the insulating layer and the groove geometry can be effectively addressed. Specifically, reasonably increasing the tilt angle of the inclined sidewalls can change the electric field lines from vertical concentration to dispersion along the sidewall direction, reducing the normal electric field strength, thereby mitigating the breakdown risk caused by electric field spikes. Meanwhile, a more uniform electric field distribution helps to achieve stable control of the two-dimensional electron gas (2DEG) density, reduce fluctuations in on-resistance, and significantly improve the electrical stability and reliability of the device.

[0030] In one possible implementation, the height of each AlGaN nanopillar is consistent with the height of the composite AlGaN nanopillar trapezoidal groove in the first direction, that is, the height of the AlGaN nanopillar is equal to the groove depth of the composite AlGaN nanopillar trapezoidal groove, and the two ends of the AlGaN nanopillar are respectively in contact with the gate 6 and the bottom of the composite AlGaN nanopillar trapezoidal groove.

[0031] Understandably, by aligning the height of the AlGaN nanopillars with the height of the trapezoidal groove, ensuring the nanopillars are continuously connected throughout the groove, it helps to form a complete and stable polarization electric field channel, thereby improving the 2DEG control efficiency and the uniformity of the device electric field.

[0032] In one possible implementation, the formula for calculating the diameter of the AlGaN nanopillars is as follows: in, Indicates the diameter of AlGaN nanopillars. Indicates the length of the Debye shield. This represents the process correction factor.

[0033] Specifically, calculating the dielectric constant ratio introduced by the AlGaN nanopillar diameter can compensate for the dielectric difference between AlGaN and the insulating layer, enhancing the local polarization electric field to precisely control the 2DEG density. Utilizing the Debye shielding length to constrain the spatial attenuation range of the polarization charge can prevent electric field distortion caused by excessive size. Dynamically adapting etching errors and material defects through process correction factors ensures stable 2DEG concentration under processing deviations, achieving synergistic optimization of electric field control, structural reliability, and process robustness. The AlGaN nanopillar diameter is measured in nm. and The units are the unitless dielectric constant of the insulating layer and the dielectric constant of AlGaN, respectively. The unit of Debye shielding length is nanometer, the unit of two-dimensional electron gas density is , and the unit of process correction factor is .

[0034] Optionally, the Debye shielding length ranges from 5 to 10 nm. The process correction factor ranges from 0.6 to 0.8.

[0035] In one possible implementation, the spacing between the AlGaN nanopillars in the second direction is: in, Indicates the spacing between AlGaN nanopillars. Represents pi (π). The value represents the diameter of the AlGaN nanopillar (20±2 nm), and ln represents the natural logarithm function. This indicates the breakdown field strength of AlGaN. This represents the expected value of the average electric field intensity within the groove. This represents the adjustment coefficient.

[0036] μ is an adjustable parameter used to control the "density" of the AlGaN nanopillar spacing. It can be optimized based on factors such as target breakdown voltage, electric field uniformity, thermal management, charge coupling degree, and process precision. A typical recommended value is 1.0 to 2.0, but it can be fine-tuned based on simulation or experimental results. During the design process, μ can be adjusted within the target 2DEG density and electric field control range using TCAD simulation tools or finite element simulation to obtain the optimal structure.

[0037] The expected average electric field strength within the groove refers to the desired average spatial electric field strength within the trapezoidal groove region of the composite AlGaN nanopillars, particularly under the influence of the nanopillar array. It typically represents the ideal state that the designer hopes the overall electric field distribution in the groove region will neither be too concentrated (to prevent breakdown) nor lose its controllability (to maintain 2DEG stability) during device operation.

[0038] It should be noted that by calculating the spacing of the AlGaN nanopillars in the second direction, the electric field strength and structural arrangement can be synergistically optimized. Specifically, the formula comprehensively considers the difference in dielectric constant, the electric field breakdown limitation, and the uniformity of the array period. This allows for the maintenance of a uniform electric field distribution and the suppression of 2DEG density fluctuations, while effectively avoiding the breakdown risk caused by local electric field spikes. Furthermore, by using a reasonable spacing, it avoids carrier scattering caused by overly dense nanopillar arrangement. Thus, it balances the high mobility, low on-resistance, and high breakdown voltage of the device, improving the overall electrical performance and structural reliability.

[0039] Reference manual attached Figure 4 The diagram shows a flow chart of a gallium nitride semiconductor device fabrication method provided by an embodiment of the present invention.

[0040] S1: Pre-treatment of substrate 1 includes: ultrasonic cleaning with acetone, ethanol and deionized water for 10 minutes each, followed by immersion in hydrofluoric acid solution for 30 seconds to remove the surface oxide layer, and finally annealing at 800°C for 30 minutes in a hydrogen atmosphere. S2: Buffer layer 2 was grown on substrate 1 by metal-organic chemical vapor deposition. Buffer layer 2 was a 20 nm AlN layer. The growth pressure was 100 Torr, the V / III ratio was 2000, and the growth rate was 0.3 μm / h. S3: The temperature is adjusted to 1080℃, and GaN channel layer 3 is grown on buffer layer 2 using trimethylgallium and ammonia as precursors.

[0041] Optionally, the growth conditions for the GaN channel layer 3 include: Temperature setting: The growth temperature is set to 1080℃. Reaction gas: Trimethylgallium (TMGa) is used as the precursor, and ammonia (NH3) is used as the nitrogen source. The flow rate of TMGa should be set to a certain value, which can be adjusted according to experimental conditions, for example, 100 sccm (standard cubic centimeters per minute). Simultaneously, the ammonia flow rate is set to 1000 sccm. Growth pressure: A gas pressure of 100 Torr is selected. Growth time: The growth time can be set to 2-3 hours, adjusted according to the required GaN layer thickness. Growth method: The GaN channel layer 3 is grown on the buffer layer 2 using metal-organic chemical vapor deposition (MOCVD). To improve the crystal quality of the GaN layer, techniques such as periodic temperature changes or ammonia flow rate adjustment can be selected to reduce stress and dislocation formation.

[0042] S4: Set the temperature to 980℃ and grow an AlGaN barrier layer in the GaN channel layer 3.

[0043] Optionally, the growth conditions for the AlGaN barrier layer include: Temperature setting: The growth temperature is adjusted to 980℃. Reaction gas: Trimethylaluminum (TMAl) and trimethylgallium (TMGa) are used as precursors, and ammonia (NH3) is used as the nitrogen source. Controlling the flow rate ratio of TMGa and TMAl is crucial. Generally, the flow rate of TMAl is approximately 10%-20% of TMGa to form the AlGaN alloy layer, ensuring the required AlGaN composition (e.g., an Al molar fraction of 20%-30%). The ammonia flow rate is set to 1000 sccm to provide sufficient nitrogen source. Growth pressure: A gas pressure of 100 Torr is maintained to ensure a suitable reaction rate and layer quality. Growth time: The growth time can be set to 1-2 hours, adjusted according to the desired AlGaN barrier layer thickness. Growth method: The AlGaN barrier layer is grown on the GaN channel layer 3 using MOCVD technology.

[0044] S5: Define the trapezoidal groove pattern of composite AlGaN nanopillars using electron beam lithography.

[0045] S6: Based on the trapezoidal groove pattern of composite AlGaN nanopillars, the trapezoidal groove of composite AlGaN nanopillars is generated by ICP-RIE etching technology.

[0046] S7: Adjust the temperature to 950℃-1050℃ to grow individual AlGaN nanopillars in the non-sidewall region of the trapezoidal groove of the composite AlGaN nanopillar.

[0047] S8: Deposit an insulating layer (e.g., in the non-nanopillar region of the composite AlGaN nanopillar trapezoidal groove) or ).

[0048] S9: By combining photolithography alignment technology, three terminals are grown to obtain gallium nitride semiconductor devices.

[0049] In practical applications, high-quality material stacking is gradually achieved from substrate pretreatment to high-temperature epitaxial growth of buffer layer 2 and GaN channel layer 3, and then to the deposition of AlGaN barrier layer. Composite nanopillar trapezoidal groove structures are precisely constructed using electron beam lithography and ICP-RIE etching, with precise ICP-RIE etching gas ratios (such as...) ), RF power, bias voltage, etching rate, using A mixed gas was used with a radio frequency power of 300W, a bias voltage of 100V, and an etching rate of 50nm / min. AlGaN nanopillars were selectively grown in the non-sidewall region by temperature control, effectively enhancing the polarization electric field manipulation capability. Subsequently, a localized deposition of an insulating layer was employed to avoid the formation of large-area interface states. The insulating material was selected (e.g.,...). or Atomic layer deposition technology (ALD or PECVD), thickness range, growing 10nm via atomic layer deposition (ALD). Insulating layer, precursor is TMA and The deposition temperature is 250℃; gate control capability is retained while leakage current is suppressed, and finally a high-performance three-terminal structure is formed through photolithography and metal deposition processes. The overall process balances high crystal quality, structural controllability, and electrical performance, resulting in devices with high mobility, low on-resistance, and excellent breakdown voltage characteristics.

[0050] In one possible implementation, S3 specifically includes: S301: Set the temperature to 1080℃ and grow for the first preset time of 5±0.5 min with an initial ammonia flow rate of 2000±100 sccm.

[0051] S302: Set the temperature to 1050℃, adjust the ammonia flow rate to the preset initial ammonia flow rate, and grow for the second preset time of 3±0.3 min.

[0052] The preset ratio of initial ammonia flow rate refers to setting a preset ratio based on the initial ammonia flow rate in S301. The initial ammonia flow rate in S301 multiplied by this preset ratio is the preset ratio of initial ammonia flow rate.

[0053] Optionally, the preset ratio is 0.8.

[0054] S303: Temperature restored to 1080℃, ammonia flow rate restored to initial ammonia flow rate, growth time for the third preset duration 3±0.3 min.

[0055] In step S303, the initial ammonia flow rate refers to the initial ammonia flow rate set in step S301.

[0056] S304: Repeat steps S301 to S303 until GaN channel layer 3 is obtained.

[0057] It should be noted that this process achieves dynamic stress release and crystal quality optimization under different growth conditions by introducing periodic temperature and ammonia flow rate adjustments during the GaN channel layer 3 growth stage. Specifically, alternating high and low temperature growth can reduce dislocation density, avoid stress concentration, improve the crystal integrity and interface quality of the AlGaN barrier layer, and help to stably form a high-density and uniform 2DEG, thereby enhancing device performance and reliability.

[0058] In one possible implementation, the first preset duration, the second preset duration, and the third preset duration satisfy a periodic constraint.

[0059] It should be noted that by ensuring that the first, second, and third preset durations meet the periodic constraints, the growth process can be stabilized and the electric field can be uniformly controlled, which helps to reduce stress accumulation and interface defects, and improve device consistency and reliability.

[0060] The periodic constraints are specifically: in, This indicates the desired GaN channel layer thickness. , and These represent the first preset duration and the second preset duration, respectively. This indicates the total time spent growing at 1080℃. Indicates the number of cycles. This represents the expected growth rate at 1080℃. This represents the expected growth rate at 1050℃.

[0061] Optionally, the number of cycles can be set to 3.

[0062] Specifically, during the growth of the GaN channel layer, the periodic temperature-controlled growth process effectively reduces stress accumulation and optimizes the crystal structure of the GaN layer by controlling the growth time at different temperatures (1050℃ and 1080℃). Specifically, the quality and defect density of the GaN crystal are closely related to the growth rate and temperature. Excessively high growth rates or uneven temperatures can lead to more defects and trapped states within the crystal, thus affecting device performance. Periodic temperature control allows the GaN growth rate to fluctuate between 1050℃ and 1080℃. This temperature variation avoids excessively rapid material deposition under a single high-temperature condition, which can lead to interface inhomogeneities or defect accumulation. Simultaneously, by switching between 1050℃ and 1080℃, the growth of the GaN channel layer is regulated under different conditions, thereby reducing dislocations and other crystal defects caused by excessively rapid growth. Furthermore, periodic control effectively alleviates stress during the growth process. Because the crystal structure and thermal expansion coefficient of GaN material do not perfectly match those of the substrate material, temperature fluctuations help eliminate thermal stress generated by high-temperature growth and reduce stress concentration between crystal layers, which is also an important factor in the formation of trap states. Therefore, periodic growth processes can reduce defects caused by excessive material stress, thereby reducing the generation of trap states and improving the electrical performance of GaN layers and the stability of devices.

[0063] In summary, the periodic temperature-controlled growth process reduces the formation of material defects and optimizes the crystal structure of the GaN channel layer by controlling temperature and gas flow, thereby effectively reducing the formation of trapped states and improving the performance and reliability of the device.

[0064] It should be noted that those skilled in the art can set the first preset duration, the second preset duration, and the preset ratio according to actual needs, and this invention does not limit these settings. Specifically, by periodically adjusting the temperature and gas flow rate, not only can the stress accumulation that may occur during the GaN layer growth process be slowed down, but interface defects and non-ideal crystallization of the material can also be effectively reduced.

[0065] In this embodiment of the invention, by setting a trapezoidal groove of composite AlGaN nanopillars below the gate 6 and arranging an AlGaN nanopillar array homogeneous with the barrier layer within the groove, defects caused by material interface mismatch are avoided, structural integrity and stability are improved, and the polarization electric field is effectively enhanced. This allows the device to achieve fine control of the electric field in the gate-controlled region without relying on a large-area insulating layer. Although an insulating layer still exists in the groove, it only fills the non-nanopillar region, avoiding direct contact between the gate 6 and the AlGaN barrier layer, effectively blocking leakage current, and reducing the introduction of interface states. This solves the control hysteresis and threshold drift problems caused by traditional insulating layers, thus balancing leakage suppression and high-speed response characteristics. At the same time, since the electric field is mainly conducted to the channel through the AlGaN nanopillars, the interface trap effect caused by the "gate-insulator-barrier layer" sandwich structure in traditional MIS structures is greatly reduced.

[0066] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A gallium nitride semiconductor device, characterized in that, include: A substrate, a buffer layer, a GaN channel layer, and an AlGaN barrier layer are stacked sequentially along the first direction; Gate; The source and drain electrodes disposed on the AlGaN barrier layer are distributed on both sides of the gate along the second direction; The composite AlGaN nanopillar trapezoidal groove is formed on the side of the AlGaN barrier layer facing the gate, and penetrates the AlGaN barrier layer in a third direction perpendicular to the first and second directions. An AlGaN nanopillar array is disposed within the trapezoidal groove of the composite AlGaN nanopillar array. Each AlGaN nanopillar in the AlGaN nanopillar array is arranged along a first direction, and its two ends are respectively connected to the bottom of the trapezoidal groove of the composite AlGaN nanopillar array and the gate. The non-AlGaN nanopillar regions within the trapezoidal groove of the composite AlGaN nanopillars are filled with an insulating layer. When the gate is powered on, a 2DEG is formed in the GaN channel layer as a conductive channel.

2. The gallium nitride semiconductor device according to claim 1, characterized in that, The opening width of the trapezoidal groove of the composite AlGaN nanopillar in the second direction is consistent with the extension width of the gate in the second direction.

3. The gallium nitride semiconductor device according to claim 2, characterized in that, The composite AlGaN nanopillar trapezoidal groove includes a groove bottom and a first inclined sidewall and a second inclined sidewall that are relatively mirror-symmetrical in a second direction; wherein the inclination angle of the two inclined sidewalls is determined according to the desired 2DEG density.

4. The gallium nitride semiconductor device according to claim 3, characterized in that, The methods for determining the inclination angle of the two inclined sidewalls include: The inclination angle of the first inclined sidewall is related to the arctangent function, whose variables include the ratio of the dielectric constant of the insulating layer to the dielectric constant of AlGaN, the height of the composite AlGaN nanopillar trapezoidal groove in the first direction, and the difference between the maximum and minimum widths of the composite AlGaN nanopillar trapezoidal groove in the second direction. The minimum width of the composite AlGaN nanopillar trapezoidal groove in the second direction depends on the cotangent of the height of the composite AlGaN nanopillar trapezoidal groove in the first direction and the inclination angle of the first inclined sidewall; and the determination of the inclination angle of the first inclined sidewall also takes into account the transverse electric field distortion compensation term, which depends on the ratio of the dielectric constant of the insulating layer to the dielectric constant of AlGaN, the height of the composite AlGaN nanopillar trapezoidal groove, and the desired 2DEG density. The inclination angle of the second inclined sidewall is determined by the difference between pi and the inclination angle of the first inclined sidewall.

5. The gallium nitride semiconductor device according to claim 4, characterized in that, The height of the AlGaN nanopillar is consistent with the height of the trapezoidal groove of the composite AlGaN nanopillar in the first direction.

6. The gallium nitride semiconductor device according to claim 5, characterized in that, The diameter of the AlGaN nanopillars depends on the ratio of the dielectric constant of the insulating layer to the dielectric constant of AlGaN, the Debye shielding length, the desired 2DEG density, and the process correction factor.

7. The gallium nitride semiconductor device according to claim 6, characterized in that, The AlGaN nanopillar array is a square array arranged sequentially along the second and third directions; wherein, in the second direction, the spacing between two adjacent AlGaN nanopillars depends on the diameter of the AlGaN nanopillar, pi, adjustment coefficient, and the value of the natural logarithm function, the variables of which include the ratio of the dielectric constant of AlGaN to the dielectric constant of the insulating layer, the AlGaN breakdown field strength, and the expected value of the average electric field strength within the trapezoidal groove of the composite AlGaN nanopillar.

8. A method for fabricating a gallium nitride semiconductor device as described in any one of claims 1 to 7, characterized in that, Includes the following steps: S1: Pre-treat the substrate; S2: A buffer layer is grown on the substrate by metal-organic chemical vapor deposition; S3: Grow a GaN channel layer on the buffer layer; S4: Grow an AlGaN barrier layer on the GaN channel layer; S5: Define the pattern of the trapezoidal groove of the composite AlGaN nanopillar using electron beam lithography; S6: Based on the pattern of the composite AlGaN nanopillar trapezoidal groove, the composite AlGaN nanopillar trapezoidal groove is generated by ICP-RIE etching technology. S7: Grow several AlGaN nanopillars in the non-sidewall region of the trapezoidal groove of the composite AlGaN nanopillars to form an AlGaN nanopillar array; S8: Deposit an insulating layer in the non-AlGaN nanopillar region of the composite AlGaN nanopillar trapezoidal groove; S9: Combine photolithography alignment technology to grow the gate, source, and drain.

9. The method according to claim 8, characterized in that, The method for growing the GaN channel layer in step S3 specifically includes: S301: At the first temperature, grow for a first preset time at the initial ammonia flow rate; S302: At a second temperature lower than the first temperature, with an ammonia flow rate at a preset ratio lower than the initial ammonia flow rate, grow for a second preset duration; S303: Restore to the first temperature and the initial ammonia flow rate, and grow for the third preset time; S304: Repeat steps S301 to S303 until the GaN channel layer of the predetermined thickness is obtained.

10. The method according to claim 9, characterized in that, The first preset duration, the second preset duration, and the third preset duration satisfy the preset periodic constraints.

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