Method for reducing resistivity of photovoltaic silicon wafer and TOPCon battery
By depositing a phosphorus-doped amorphous silicon layer on the back of the silicon wafer after alkaline polishing and then annealing it to form a diffusion layer, the problem of high silicon wafer resistivity is solved, and the efficiency and yield of TOPCon cells are improved.
Patent Information
- Application Number
- CN202411165715.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2025-10-31
AI Technical Summary
In the fabrication of TOPCon cells, the high resistivity of silicon wafers leads to low cell efficiency and a low flyback factor (FF).
A phosphorus-doped amorphous silicon layer is deposited on the back side of the silicon wafer after alkaline polishing. Annealing is then performed to allow diffusion elements to diffuse into the back side of the silicon wafer to form a diffusion layer. The remaining phosphorus-doped amorphous silicon layer is then removed using an alkaline solution.
Reducing silicon wafer resistivity increases fly focal density (FF), thereby improving the conversion efficiency and yield of solar cells.
Smart Images
Figure CN120882142A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar photovoltaic technology, specifically to a method for reducing the resistivity of photovoltaic silicon wafers and a TOPCon cell. Background Technology
[0002] Photovoltaic silicon wafers are an indispensable substrate in cell development. Their quality directly determines the yield of downstream cells and their conversion efficiency.
[0003] The resistivity of photovoltaic silicon wafers is an important physical property. Generally speaking, lower resistivity helps improve cell conversion efficiency and yield, and reduces power generation costs. Currently, in the fabrication of TOPCon cells, a tunneling oxide layer is deposited directly on the alkaline-polished silicon wafer surface after alkaline polishing. Cell efficiency is affected by the resistivity of the silicon wafer; high silicon wafer resistivity results in a low fill factor (FF), leading to low cell efficiency. Summary of the Invention
[0004] The purpose of this invention is to overcome the defects of the prior art by providing a method for reducing the resistivity of photovoltaic silicon wafers and a TOPCon cell.
[0005] The present invention provides a method for reducing the resistivity of photovoltaic silicon wafers, comprising: depositing a phosphorus-doped amorphous silicon layer on the back side of a silicon wafer after alkaline polishing; annealing the silicon wafer with the phosphorus-doped amorphous silicon layer to allow the diffusion elements in the phosphorus-doped amorphous silicon layer to diffuse into the back side of the silicon wafer to form a diffusion layer; and removing the residual phosphorus-doped amorphous silicon layer on the back side of the silicon wafer by alkaline solution treatment.
[0006] In some implementations, the thickness of the silicon wafer after alkaline polishing is 70μm-150μm.
[0007] In some embodiments, depositing a phosphorus-doped amorphous silicon layer on the back side of an alkaline-polished silicon wafer includes depositing a phosphorus-doped amorphous silicon layer on the back side of an alkaline-polished silicon wafer using the PEVCD method.
[0008] In some embodiments, the steps include: inserting an alkaline-polished silicon wafer with its back side facing out into a graphite boat, introducing SiH4 and PH3, and depositing a phosphorus-doped amorphous silicon layer with a high phosphorus concentration on the back side of the alkaline-polished silicon wafer.
[0009] In some embodiments, during the deposition process, the SiH4 flow rate is controlled at 2700 sccm-3300 sccm, the PH3 flow rate at 2500 sccm-3100 sccm, the pressure at 2400 mbar-2900 mbar, the temperature at 420℃-460℃, the deposition time at 900 s-1100 s, and the plasma pulse duty cycle at (25:520)-(55:250).
[0010] In some embodiments, annealing a silicon wafer with a phosphorus-doped amorphous silicon layer includes inserting the silicon wafer with the phosphorus-doped amorphous silicon layer into a quartz boat for annealing under a protective gas atmosphere.
[0011] In some embodiments, the protective gas includes at least one of nitrogen and argon, the flow rate of the protective gas is 800 sccm-1200 sccm, the annealing temperature is 800℃-1200℃, the time is 5600s-6000s, and the pressure is 400mbar-800mbar.
[0012] In some embodiments, the diffusion element is phosphorus, and the phosphorus concentration in the diffusion layer is 1×10⁻⁶. 18 -5×10 20 / cm 3 .
[0013] In some embodiments, the alkaline solution is a NaOH solution, and the treatment temperature using the NaOH solution is 70℃-85℃, and the time is 50s-200s.
[0014] The present invention also provides a TOPCon battery, wherein the silicon wafer of the TOPCon battery is a low resistivity silicon wafer prepared by the above method.
[0015] The present invention has the following beneficial effects:
[0016] This invention provides a method for reducing the resistivity of photovoltaic silicon wafers and a TOPCon cell. The method for reducing the resistivity of photovoltaic silicon wafers includes: depositing a phosphorus-doped amorphous silicon layer on the back side of a silicon wafer after alkaline polishing; annealing the silicon wafer with the phosphorus-doped amorphous silicon layer to allow diffusion elements in the phosphorus-doped amorphous silicon layer to diffuse into the back side of the silicon wafer to form a diffusion layer; and removing the residual phosphorus-doped amorphous silicon layer on the back side of the silicon wafer using an alkaline solution. This method enables phosphorus doping of the back side of the silicon wafer, reducing the contact resistivity of the silicon wafer, increasing the flyback effect (FF), and thus improving the efficiency of the TOPCon cell fabricated using the aforementioned silicon wafer. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 The flowchart shows the method for reducing the resistivity of photovoltaic silicon wafers provided by this invention.
[0019] Figure numbers: 100-Alkali-polished silicon wafer, 200-Phosphorus-doped amorphous silicon layer, 300-Diffusion layer, 400-Residual phosphorus-doped amorphous silicon layer. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.
[0021] The following is a detailed description of a method for reducing the resistivity of photovoltaic silicon wafers and a TOPCon cell provided by embodiments of the present invention.
[0022] In a first aspect, embodiments of the present invention provide a method for reducing the resistivity of a TOPCon battery silicon wafer, comprising: depositing a phosphorus-doped amorphous silicon layer 200 on the back side of a silicon wafer 100 after alkaline polishing; annealing the silicon wafer with the phosphorus-doped amorphous silicon layer 200 to allow diffusion elements in the phosphorus-doped amorphous silicon layer 200 to diffuse into the back side of the silicon wafer to form a diffusion layer 300; and removing the residual phosphorus-doped amorphous silicon layer 400 on the back side of the silicon wafer by alkaline solution treatment.
[0023] This invention provides a method for reducing the resistivity of photovoltaic silicon wafers, see [link to relevant documentation]. Figure 1 This process includes: depositing a phosphorus-doped amorphous silicon layer 200 on the back side of an alkaline-polished silicon wafer 100, followed by annealing and removal of the residual phosphorus-doped amorphous silicon layer 400. Using this method, a diffusion layer 300 can be formed on the back side of the silicon wafer, reducing the contact resistivity and improving the flyback effect (FF). It is worth noting that, see again... Figure 1 It can be seen that: through annealing, the diffusion elements in the phosphorus-doped amorphous silicon layer 200 diffuse into the back of the silicon wafer to form a diffusion layer 300. Here, diffusion of diffusion elements refers to the diffusion of diffusion elements into the silicon wafer through the phosphorus-doped amorphous silicon layer 200, forming a diffusion layer 300 at a certain depth on the back of the silicon wafer.
[0024] In some alternative embodiments, the thickness of the alkaline-polished silicon wafer 100 is 70μm-150μm.
[0025] The method for reducing the resistivity of photovoltaic silicon wafers provided in this invention includes: depositing a phosphorus-doped amorphous silicon layer 200 on the back side of an alkaline-polished silicon wafer 100; and annealing the silicon wafer with the phosphorus-doped amorphous silicon layer 200 to allow the diffusion elements in the phosphorus-doped amorphous silicon layer 200 to diffuse into the back side of the silicon wafer to form a diffusion layer 300. In this method, the alkaline-polished silicon wafer 100 needs to have a suitable thickness to form a diffusion layer 300 of a certain thickness on the back side of the silicon wafer, thereby reducing the resistivity of the photovoltaic silicon wafer. The suitable thickness of the alkaline-polished silicon wafer is 70μm-150μm. The thickness of the diffusion layer 300 on the back side of the alkaline-polished silicon wafer 100, i.e., the maximum doping depth, is the silicon wafer thickness minus 2 times the PN junction depth. Controlling the above-mentioned doping layer thickness allows the diffusion layer 300 to form a good PN junction with the silicon wafer, improving the short-circuit current and open-circuit voltage of the prepared battery, thereby improving the battery's conversion efficiency.
[0026] Optionally, the thickness of the alkaline-polished silicon wafer 100 can be 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, and any other value between 70μm and 150μm.
[0027] In some alternative embodiments, depositing a phosphorus-doped amorphous silicon layer 200 on the back side of the alkaline-polished silicon wafer 100 includes: depositing the phosphorus-doped amorphous silicon layer 200 on the back side of the alkaline-polished silicon wafer 100 using the PEVCD method. The PEVCD method (plasma chemical vapor deposition) can deposit a uniform phosphorus-doped amorphous silicon layer 200 on the back side of the silicon wafer without damaging the wafer.
[0028] In some alternative embodiments, the steps include: inserting an alkaline-polished silicon wafer 100 with its back side facing out into a graphite boat, introducing SiH4 and PH3, and depositing a phosphorus-doped amorphous silicon layer 200 with a high phosphorus concentration on the back side of the alkaline-polished silicon wafer 100.
[0029] The method for reducing the resistivity of photovoltaic silicon wafers provided in this embodiment of the invention, which deposits a phosphorus-doped amorphous silicon layer 200 on the back side of an alkaline-polished silicon wafer 100, includes: inserting the alkaline-polished silicon wafer 100 with its back side facing out into a graphite boat of a PECVD equipment; evacuating the reaction chamber of the PECVD equipment; then introducing a certain amount of SiH4 and PH3; ionizing the SiH4 and PH3 in the PECVD equipment to obtain plasma; and depositing the plasma on the back side of the silicon wafer to form a phosphorus-doped amorphous silicon layer 200.
[0030] In some alternative embodiments, during the deposition process, the SiH4 flow rate is controlled at 2700 sccm-3300 sccm, the PH3 flow rate at 2500 sccm-3100 sccm, the pressure at 2400 mbar-2900 mbar, the temperature at 420℃-460℃, the deposition time at 900 s-1100 s, and the plasma pulse duty cycle at (25 / 520)-(55 / 250). By controlling appropriate SiH4 flow rate, PH3 flow rate, temperature, time, pressure, and plasma pulse duty cycle during the deposition of a phosphorus-doped amorphous silicon layer 200 on the back side of an alkaline-polished silicon wafer 100 using the PEVCD method, the thickness of the phosphorus-doped amorphous silicon layer 200 can be controlled, and the quality of the phosphorus-doped amorphous silicon layer 200 on the back side of the silicon wafer can be improved.
[0031] Optionally, the SiH4 flow rate can be any other value between 2700 sccm, 2800 sccm, 2900 sccm, 3000 sccm, 3100 sccm, 3200 sccm, 3300 sccm, and 2700 sccm-3300 sccm; the PH3 flow rate can be any other value between 2500 sccm, 2600 sccm, 2700 sccm, 2800 sccm, 2900 sccm, 3000 sccm, 3100 sccm, and 2500 sccm-3100 sccm; and the pressure can be 2400 mbar, 2500 mbar, 2600 mbar, or 2700 mbar. The plasma pulse duty cycle can be any other value between ar, 2800 mbar, 2900 mbar and 2400 mbar-2900 mbar, the temperature can be any other value between 420℃, 430℃, 440℃, 450℃, 460℃ and 420℃-460℃, the deposition time can be any other value between 900s, 950s, 1000s, 1050s, 1100s and 900s-1100s, and the plasma pulse duty cycle can be any other value between 25 / 520, 30 / 520, 35 / 520, 40 / 520, 45 / 520, 50 / 520, 55 / 520 and (25 / 520)-(55 / 250).
[0032] In some alternative embodiments, annealing the silicon wafer with the phosphorus-doped amorphous silicon layer 200 includes inserting the silicon wafer with the phosphorus-doped amorphous silicon layer 200 into a quartz boat for high-temperature annealing under a protective gas atmosphere.
[0033] The method for reducing the resistivity of photovoltaic silicon wafers provided in this invention includes annealing a silicon wafer with a phosphorus-doped amorphous silicon layer 200. This annealing process involves inserting the silicon wafer with the phosphorus-doped amorphous silicon layer 200 into a quartz boat for annealing. The annealing process allows the high concentration of phosphorus deposited in the phosphorus-doped amorphous silicon layer 200 on the back side of the silicon wafer to diffuse from the back side into the wafer, achieving phosphorus diffusion at a certain depth on the back side to form a diffusion layer 300. It is worth noting that high-temperature annealing promotes the diffusion of phosphorus from the phosphorus-doped amorphous silicon layer 200 into the back side of the silicon wafer. This is a solid-state diffusion process and will not form a diffusion layer 300 on the other surface or side of the silicon wafer. This achieves precise doping and diffusion, and eliminates the need for a subsequent cumbersome cleaning process of the diffusion layer 300, ensuring the integrity of the silicon wafer and the stability of the process.
[0034] In some optional embodiments, the protective gas includes at least one of nitrogen and argon, with a flow rate of 800 sccm-1200 sccm, an annealing temperature of 800℃-1200℃, a time of 5600s-6000s, and a pressure of 400mbar-800mbar. By controlling the appropriate protective gas flow rate, annealing temperature, time, and pressure during the annealing process to diffuse the diffusion elements within the phosphorus-doped amorphous silicon layer 200 into the back side of the silicon wafer to form the diffusion layer 300, the thickness of the diffusion layer 300 and the phosphorus concentration within the diffusion layer 300 on the back side of the silicon wafer can be controlled.
[0035] Optionally, the flow rate of the protective gas can be any other value between 800 sccm, 900 sccm, 1000 sccm, 1100 sccm, 1200 sccm and 800 sccm-1200 sccm; the annealing temperature can be any other value between 800℃, 900℃, 1000℃, 1100℃, 1200℃ and 800℃-1200℃; the annealing time can be any other value between 5600s, 5700s, 5800s, 5900s, 6000s and 5600s-6000s; and the pressure can be any other value between 400mbar, 500mbar, 600mbar, 700mbar, 800mbar and 400mbar-800mbar.
[0036] In some alternative embodiments, the diffusion element is phosphorus, and the phosphorus concentration within the diffusion layer 300 is 1×10⁻⁶. 18 -5×10 20 / cm 3 Forming a diffusion layer 300 on the back side of the silicon wafer and controlling an appropriate phosphorus concentration within the diffusion layer 300 helps to reduce the resistivity of the silicon wafer, reduce contact resistivity, and improve flyback effect (FF).
[0037] Optionally, the phosphorus concentration within the diffusion layer 300 can be 1×10⁻⁶. 18 2×10 18 5×10 18 1×10 19 2×10 19 5×10 19 1×10 20 2×10 20 5×10 20 and 1×10 18 -5×10 20 / cm 3 Any other value between.
[0038] In some optional embodiments, the alkaline solution is a NaOH solution, and the treatment temperature with NaOH solution is 70℃-85℃, and the treatment time is 50s-200s. Alkaline treatment can clean and remove the phosphorus-doped amorphous silicon layer 400 remaining after annealing on the back side of the silicon wafer, resulting in a silicon wafer with a diffusion layer 300 of a certain depth on the back side, thereby reducing the resistivity of the silicon wafer.
[0039] Optionally, the temperature for treatment with NaOH solution can be any other value between 70℃, 75℃, 80℃, 85℃ and 70℃-85℃, and the time can be any other value between 50s, 100s, 150s, 200s and 50s-200s.
[0040] The method for reducing the resistivity of photovoltaic silicon wafers provided in this embodiment of the invention can form a diffusion layer 300 on the back side of the silicon wafer. Tests show that, taking a silicon wafer 100 with a resistivity of 0.4-1.8 Ω·cm after alkaline polishing as an example, after processing the silicon wafer 100 with the method provided in this invention, the resistivity of silicon wafers with a resistivity of 0.4-1.1 Ω·cm can be reduced by 0.2 ± 0.05 Ω·cm; and the resistivity of silicon wafers with a resistivity of 1.1-1.8 Ω·cm can be reduced by 0.4 ± 0.1 Ω·cm. It can be seen that the method provided in this embodiment of the invention can effectively reduce the resistivity of the silicon wafer, improve the fairing (FF), and form a good ohmic contact with the subsequently fabricated electrodes, thereby improving the efficiency of the solar cell.
[0041] Secondly, embodiments of the present invention also provide a TOPCon cell, wherein the silicon wafer of the TOPCon cell is a low-resistivity silicon wafer prepared using the method described above. By employing the method for reducing the resistivity of photovoltaic silicon wafers provided by embodiments of the present invention, the resistivity of the silicon wafer can be reduced, the flyback effect (FF) can be increased, and thus the efficiency of the TOPCon cell made using the aforementioned silicon wafer can be improved.
[0042] The present invention will be further described below with reference to embodiments.
[0043] Example 1
[0044] A method for reducing the resistivity of photovoltaic silicon wafers, see [link to relevant documentation]. Figure 1 This includes the following steps:
[0045] (1) Depositing a phosphorus-doped amorphous silicon layer 200 on the back side of the alkaline-polished silicon wafer 100 using the PEVCD process: Insert the alkaline-polished silicon wafer 100 with the back side facing outward into a PE-poly graphite boat, and deposit a high-concentration phosphorus-doped amorphous silicon layer 200 on the back side of the silicon wafer. The process conditions are as follows: SiH4 flow rate is controlled at 2950 sccm; PH3 flow rate is controlled at 2800 sccm; pressure is controlled at 2650 mbar; temperature is controlled at 440℃; deposition time is controlled at 995 s; plasma pulse duty cycle is controlled at 40 / 520.
[0046] (2) Anneal the silicon wafer obtained in step (1) using an annealing process: insert the silicon wafer obtained in step (1) into a quartz boat for annealing. The process conditions are: N2 flow rate is controlled at 1000 sccm; temperature is 990℃; time is 5800s; pressure is 600mbar.
[0047] (3) Remove the phosphorus-doped amorphous silicon layer 400 remaining on the back of the silicon wafer obtained in step (2) using an alkaline solution: Place the silicon wafer obtained in step (2) into an alkaline solution to remove the phosphorus-doped amorphous silicon layer 400 remaining on the back of the silicon wafer. The process conditions are: NaOH concentration is controlled at 1%, temperature is 80℃, and time is 50s.
[0048] (4) Performance testing: After drying the silicon wafer obtained in step (3), perform normal alkaline polishing followed by TOPCON process. The testing process is as follows: PEpoly→annealing→RCA→ALD→coating→printing→testing.
[0049] Examples 2-10
[0050] The PEVCD process parameters and annealing process parameters in Examples 2-10 are shown in Table 1. The cleaning steps after the annealing process are the same as in Example 1.
[0051] Comparative Example 1
[0052] (1) Take silicon wafer 100 after alkaline polishing of TOPCON battery in the same process and path as in Examples 1-10.
[0053] (2) Performance testing: The silicon wafer obtained in step (1) can be subjected to normal alkaline polishing followed by TOPCON process. The testing process is as follows: PEpoly→annealing→RCA→ALD→coating→printing→testing.
[0054] Table 1 below shows the PEVCD process parameters and annealing process parameters for Examples 1-10 of the present invention.
[0055] Table 1
[0056]
[0057] Note: The silicon wafer performance tests obtained in the examples and comparative examples were conducted using the same solar cell testing machine and the same test formula. The solar cells were directly tested using the testing machine.
[0058] Table 2 below shows the performance test results of the silicon wafers obtained in the embodiments and comparative examples of the present invention.
[0059] Table 2
[0060]
[0061] As can be seen from Table 2 above, the method for reducing the resistivity of photovoltaic silicon wafers provided in the embodiments of the present invention can reduce the resistivity of silicon wafers, improve cell efficiency, cell yield and FF, and thus improve the efficiency of TOPCon cells made using the above-mentioned silicon wafers.
[0062] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for reducing the resistivity of photovoltaic silicon wafers, characterized in that, include: A phosphorus-doped amorphous silicon layer is deposited on the back side of the silicon wafer after alkaline polishing; The silicon wafer with the phosphorus-doped amorphous silicon layer is annealed to allow the diffusion elements in the phosphorus-doped amorphous silicon layer to diffuse into the back side of the silicon wafer to form a diffusion layer; and the residual phosphorus-doped amorphous silicon layer on the back side of the silicon wafer is removed by alkaline solution treatment.
2. The method according to claim 1, characterized in that, The thickness of the silicon wafer after alkaline polishing is 70μm-150μm.
3. The method according to claim 1, characterized in that, Depositing a phosphorus-doped amorphous silicon layer on the back side of an alkaline-polished silicon wafer includes: depositing a phosphorus-doped amorphous silicon layer on the back side of the alkaline-polished silicon wafer using the PEVCD method.
4. The method according to claim 3, characterized in that, Includes the following steps: The alkaline-polished silicon wafer is inserted into a graphite boat with its back side facing outwards, and SiH4 and PH3 are introduced to deposit a phosphorus-doped amorphous silicon layer with a high phosphorus concentration on the back side of the alkaline-polished silicon wafer.
5. The method according to claim 4, characterized in that, During the deposition process, the SiH4 flow rate was controlled at 2700 sccm-3300 sccm, the PH3 flow rate at 2500 sccm-3100 sccm, the pressure at 2400 mbar-2900 mbar, the temperature at 420℃-460℃, the deposition time at 900 s-1100 s, and the plasma pulse duty cycle at (25 / 520)-(55 / 250).
6. The method according to claim 1, characterized in that, Annealing a silicon wafer with the phosphorus-doped amorphous silicon layer includes inserting the silicon wafer with the phosphorus-doped amorphous silicon layer into a quartz boat for annealing under a protective gas atmosphere.
7. The method according to claim 6, characterized in that, The protective gas includes at least one of nitrogen and argon, the flow rate of the protective gas is 800 sccm-1200 sccm, the annealing temperature is 800℃-1200℃, the time is 5600s-6000s, and the pressure is 400mbar-800mbar.
8. The method according to claim 6, characterized in that, The diffusion element is phosphorus, and the phosphorus concentration in the diffusion layer is 1×10⁻⁶. 18 -5×10 20 / cm 3 .
9. The method according to claim 1, characterized in that, The alkaline solution is a NaOH solution, and the treatment temperature using the NaOH solution is 70℃-85℃, and the time is 50s-200s.
10. A TOPCon battery, characterized in that, The silicon wafer of the TOPCon battery is prepared by the method described in any one of claims 1-9.