Solar cell and photovoltaic module

Abstract

The invention provides a solar cell which comprises a silicon substrate and a plurality of collector grid lines formed on the surface of one side of the silicon substrate. The silicon substrate is doped with an antimony element, and when the grid line density of the collector grid lines with the same polarity on the unit length in the direction perpendicular to the collector grid lines is n / cm and the concentration of the antimony element in the silicon substrate is a atoms / cm < 3 >, n and a meet the following relation: n is greater than or equal to 35-klg a formula I, and k is less than or equal to 2. The invention further provides a photovoltaic module formed by the solar cell.

Description

[0001] This application is a divisional application of patent application number 202410461849.2, entitled "A Solar Cell and a Photovoltaic Module". Technical Field

[0002] This application relates to the field of photovoltaic technology, specifically to a solar cell and a photovoltaic module incorporating the solar cell. Background Technology

[0003] Currently, silicon solar cells typically use N-type or P-type doped silicon wafers as the substrate. P-type and N-type semiconductors are formed at different locations on the silicon wafer, and electrodes are then formed on the respective P-type and N-type semiconductor regions to form the cell. When light enters the silicon cell substrate, electron-hole pairs are generated. These ionized electron-hole pairs undergo carrier separation, causing electrons to accumulate near the N-type electrode and holes to accumulate near the P-type electrode. Connecting an external circuit to the electrodes allows for current output. In existing technologies, P-type or N-type substrates are commonly used as the semiconductor substrate for photovoltaics. P-type substrates are typically doped with boron or gallium, while N-type substrates are typically doped with phosphorus.

[0004] Due to their longer minority carrier diffusion length, N-type semiconductor substrates, when used in silicon solar cells, allow for the collection of more charge carriers compared to P-type substrates, resulting in higher efficiency. N-type substrates are typically doped with phosphorus. In the photovoltaic field, research has begun on using Sb-doped silicon wafers as silicon substrates to fabricate solar cells and photovoltaic modules. However, further optimization is needed to improve the efficiency of Sb-doped silicon substrate solar cells. Summary of the Invention

[0005] In view of the above problems, this application aims to improve the issues involved in the prior art. Through in-depth research, this application has confirmed the relationship between Sb concentration and grid line density, and has achieved improved transmission performance and cell efficiency of solar cells by combining and matching the Sb concentration and grid line number in the silicon substrate. This application provides the following solution:

[0006] 1. A solar cell comprising:

[0007] A silicon substrate, and several collector gate lines formed on one side surface of the silicon substrate;

[0008] The silicon substrate is doped with antimony.

[0009] The grid line density of the collector grid lines with the same polarity in the direction perpendicular to the collector grid lines is n lines / cm, and the concentration of antimony in the silicon substrate is a atoms / cm. 3 When n and a satisfy the following relationship:

[0010] Formula 1, n≥35-klg a

[0011] Where k is less than or equal to 2.

[0012] 2. The solar cell according to claim 1, wherein when the thickness of the silicon substrate of the cell is b μm, n satisfies the following relationship:

[0013]

[0014] Where c is a constant and takes the value of 50 μm.

[0015] 3. According to the solar cell described in item 1, n and a also satisfy the following relationship:

[0016] Formula 3: n≤35-lg a

[0017] 4. The solar cell according to any one of items 1 to 3, wherein the solar cell is a double-sided contact cell and k = 2.

[0018] 5. The solar cell according to any one of items 1 to 3, wherein the solar cell is a back contact cell and k = 1.9.

[0019] 6. The solar cell according to claim 5, wherein one side surface of the silicon substrate has an electron collecting region and a hole collecting region, and an isolation region located between the electron collecting region and the hole collecting region; when the depth of the isolation region is d μm, n satisfies the following relationship:

[0020]

[0021] 8. The solar cell according to item 6, wherein,

[0022] The depth of the isolation region is the numerical height difference between the bottom of the shallower region in the electron collection region and the bottom of the isolation region, and the bottom of the isolation region is the surface of the silicon substrate corresponding to the isolation region.

[0023] When the solar cell contains an interface passivation layer, the bottom of the electron collection region or hole collection region is the height of the interface passivation layer near the silicon substrate.

[0024] 8. The solar cell according to any one of items 1 to 7, wherein the range of a is 1E13 to 1E18.

[0025] 9. The solar cell according to any one of claims 1 to 8, wherein the width of each of the current collector grid lines is 10-200 μm.

[0026] 10. A photovoltaic module, characterized in that the photovoltaic module comprises a solar cell as described in any one of items 1 to 9.

[0027] Invention Effects

[0028] This application, based on the combination of cell structure, Sb element concentration in the silicon substrate, and the number of current collector grids, can satisfy Formula 1 above, thus effectively improving lateral transport performance. It achieves good cell efficiency (Eta) and open-circuit voltage, while also exhibiting excellent short-circuit current and fill factor, effectively improving cell efficiency. Attached Figure Description

[0029] Figure 1 A schematic diagram of a back-contact solar cell is shown.

[0030] Figure 2 The diagram shows the back electrode of the back-contact battery.

[0031] Figure 3 The diagram shows the back electrode of a double-contact battery.

[0032] Figure 4 This diagram illustrates a back-contact solar cell according to a specific embodiment of this application.

[0033] Figure 5 This diagram illustrates a back-contact solar cell according to a specific embodiment of this application.

[0034] Figure 6 This diagram illustrates a back-contact solar cell according to a specific embodiment of this application.

[0035] Figure 7 This diagram illustrates a double-sided contact solar cell according to a specific embodiment of this application.

[0036] Figure 8 The battery efficiency trend graph shown in Table 1 is displayed.

[0037] Figure 9 Table 2 shows the battery efficiency trend graph.

[0038] Figure 10 Table 3 shows the battery efficiency trend graph.

[0039] Figure 11 Table 4 shows the battery efficiency trend graph.

[0040] Figure 12 The diagram shows a fitted curve of antimony doping concentration and inflection point gate line density.

[0041] Symbol explanation:

[0042] 1: First electrode; 2: Passivation layer; 3: Semiconductor layer; 9: Interface passivation layer; 4: Silicon substrate; 5: Second electrode; 6: Isolation region; 7: Hole collection region; 8: Electron collection region. Detailed Implementation

[0043] The following embodiments of this application are only used to illustrate specific implementation methods of this application, and these embodiments should not be construed as limitations on this application. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of this application shall be considered equivalent substitutions and fall within the protection scope of this application.

[0044] Specific embodiments of this application will now be described in more detail. However, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0045] It should be noted that certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that different terms may be used to refer to the same component. This specification and claims do not distinguish components based on differences in terminology, but rather on differences in function. The terms "comprising" or "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." The following descriptions in the specification are preferred embodiments for carrying out this application; however, these descriptions are for the purpose of understanding the general principles of the specification and are not intended to limit the scope of this application. The scope of protection of this application shall be determined by the appended claims.

[0046] As used in this specification, "a" or "an" may mean one or more. As used in the claims, when used with the word "comprising," the word "a" or "an" may mean one or more.

[0047] The term “or” is used in the claims to mean “and / or” unless it is explicitly stated that it refers only to an alternative or that the alternatives are mutually exclusive, although this disclosure supports the definitions of referring only to an alternative and “and / or”. As used herein, “another” can mean at least a second or more.

[0048] In this application, there are no further limitations on the silicon substrate itself mentioned in the following description. It can be a silicon substrate obtained after machining and slicing following the pulling of silicon ingots (also referred to as a bare silicon wafer). In this application, it is also possible to peel off and recover a structure containing a silicon substrate and at least partially doped regions from the battery module, as long as it has a certain shape and can be sheet-like, that is, the size of one side is larger than the size of the side perpendicular to it, and it is flat or plate-like. There are no limitations on the size of the structure containing the silicon substrate body and at least partially doped regions. The silicon substrate or the structure containing the silicon substrate and at least partially doped regions can be of any size. The partial silicon substrate body or the structure containing the silicon substrate body and at least partially doped regions after peeling off other layers from the battery module can be recovered. In addition, those skilled in the art will understand that if at least partially doped regions are destroyed during peeling, as long as some doped regions still exist, it should also be understood that it corresponds to the solar cell mentioned in the battery of this application. For example, in one specific embodiment, the length of at least one side of the structure comprising a silicon substrate body and at least a partially doped region is greater than 156 mm. For example, it could be 158±2 mm, (160±2) mm, (165±2) mm, (170±2) mm, (175±2) mm, (180±2) mm, (185±2) mm, 190±2 mm, (195±2) mm, (200±2) mm, (205... ±2) mm, (210±2) mm, (215±2) mm, (220±2) mm, (225±2) mm, (230±2) mm, (235±2) mm, (240±2) mm, (245±2) mm, (250±2) mm, (255±2) mm, (260±2) mm, (265±2) mm, (270±2) mm, (275±2) mm, and any range between these values. For example, in one specific embodiment, the thickness of the silicon substrate or the structure containing the silicon substrate and at least partially doped regions of this application is at least 70 to 170 μm, for example, it can be 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, or 160 μm. In one specific approach, the size of the stripped portion containing the silicon substrate body and at least a portion of the doped region after the other layers are recovered and stripped can be smaller than the aforementioned size, as long as the parameters involved in this application, such as the doping concentration of the doping elements, can be detected for it.

[0049] In this application, the silicon substrate has antimony as a dopant. This dopant is usually present when the bare silicon wafer is prepared. Therefore, the doping concentration of the dopant in the silicon substrate is roughly uniform throughout the entire silicon substrate, that is, the average concentration is roughly the same.

[0050] In one specific embodiment of this application, the total antimony element concentration per unit volume in the silicon substrate of this application is a atoms / cm³. 3 Preferably, the range of a is 1E13 to 1E18.

[0051] Those skilled in the art will understand that the silicon substrate of this application can further include other doping elements to form doped regions with different functions. Different regions will be formed on the silicon substrate depending on the battery structure; for example, a hole collection region and an electron collection region can be formed on one side of the silicon substrate, or hole collection regions and electron collection regions can be formed on both sides of the silicon substrate respectively. Those skilled in the art can form hole collection regions and / or electron collection regions on the silicon substrate using methods they understand, and there are no limitations on the number or size of the hole collection regions and electron collection regions. Those skilled in the art can design according to the actual battery structure, size, and requirements.

[0052] In this application, the detection method for whether a certain element is present in the silicon substrate and doped region can be achieved by methods such as SIMS, SSMS, ICP-MS, GDMS, and ECV, with SIMS and SSMS methods being preferred for detecting metallic elements. In this application, solar cells are also referred to as cells.

[0053] In this application, the concentration of the dopant element (antimony) in the silicon substrate can be detected by any method known to those skilled in the art. Those skilled in the art can choose the appropriate method based on their needs, such as SIMS, SSMS, ICP-MS, GDMS, ECV, etc., with SIMS and SSMS being preferred. Those skilled in the art will understand that the concentration of the dopant element can refer to the concentration of the dopant element at any site on the surface, in the middle, or inside of the silicon substrate. It can also be the average concentration of the dopant element at multiple sites or the average concentration of the dopant element across the entire silicon substrate. Those skilled in the art can select any of the above-mentioned sites for detection based on the detection conditions and the instruments used, or they can detect multiple sites and calculate the average value of these sites as the concentration of the dopant element in the silicon substrate. In one specific embodiment, the concentration of the dopant element in the silicon substrate refers to the average value detected over the thickness of the silicon substrate. For example, the concentration of the dopant element in the silicon substrate can be detected in one thickness direction using SIMS or SSMS methods, and the average value in that thickness direction can be calculated. In this application, when referring to the concentration of antimony, it usually refers to the average concentration of antimony. However, antimony is usually doped relatively uniformly in the silicon substrate, and the average concentration can also be the concentration at any site.

[0054] In one specific embodiment of this application, antimony is doped into the silicon substrate as a Group 5 dopant instead of phosphorus. Those skilled in the art will understand that, depending on the source of the silicon substrate material, the silicon substrate itself may contain other elements, such as any one, two, or three of phosphorus, gallium, and germanium, but only antimony is actively doped as a Group 5 dopant instead of phosphorus. Typically, single-element doping in silicon substrates leads to lattice distortion, resulting in numerous defects in heavily doped regions. However, in one specific embodiment of this application, since the silicon substrate itself contains antimony, it can be further doped with Group 3 and Group 5 elements to form co-doping, which can overcome the lattice distortion caused by single-element doping and avoid numerous defects in heavily doped regions.

[0055] like Figure 1 This diagram illustrates a typical back-contact solar cell. Typically, a solar cell has a silicon substrate 4, a positive electrode (first electrode 1), and a negative electrode (second electrode 5). The positive electrode forms a contact with a P-type semiconductor, and the negative electrode forms a contact with an N-type semiconductor. Under illumination, an external circuit is connected to the electrodes, and the entire solar cell outputs current. Figure 1 In the diagram, the region on the left formed by P-type semiconductors is the hole collection region, and the region on the right formed by N-type semiconductors is the electron collection region.

[0056] Furthermore, such as Figure 1 An interface passivation layer 9 (also known as a tunneling layer) is disposed on the surface of the silicon substrate 4. The thickness of the interface passivation layer 9 is 0.1-5nm, for example, it can be 0.1nm, 0.5nm, 1nm, 2nm, 3nm, 4nm, 5nm, etc. The material of the interface passivation layer 9 can be a material commonly used by those skilled in the art. Depending on the specific type of battery, it can be selected from materials such as silicon oxide, aluminum oxide, silicon nitride, intrinsic amorphous silicon, etc.

[0057] Furthermore, a semiconductor layer 3 is disposed on the side of the interface passivation layer 9 away from the silicon substrate 4. The semiconductor layer 3 can be made of materials commonly used by those skilled in the art, and depending on the specific type of battery, can be selected from one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon. The semiconductor layer 3 can be a mixture or stack of various materials. Figure 1 In the battery structure shown, the hole collection region and the electron collection region can be isolated by the isolation region 6. Furthermore, a passivation layer 2 can be disposed on the semiconductor layer 3.

[0058] The silicon substrate 4 of this application may have some other doped regions, which can be formed by doping the semiconductor layer 3 into the silicon wafer through the interface passivation layer 9. Alternatively, they can be formed by direct doping.

[0059] In this application, in addition to antimony doping in the silicon substrate 4, other elements may be further doped, such as Group 3 elements or Group 5 elements. Group 3 elements include boron, aluminum, gallium, indium, and thallium, while Group 5 elements include nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0060] In one specific embodiment, a portion of the silicon substrate 4 is doped with phosphorus, and a portion is doped with boron. In another specific embodiment, the interface passivation layer refers to a layer that provides passivation while allowing dopant elements to pass through; for example, it could be a tunneling layer.

[0061] Figure 2 This diagram illustrates the back electrode pattern of an IBC (Interdigitated Back Contact) cell, specifically a two-dimensional electrode structure diagram of an interdigitated back contact cell. It shows interdigitated hole and electron collection regions arranged in a cross-shaped pattern on the back surface of a silicon substrate. Simultaneously, the positive and negative electrodes are also arranged in an interdigitated manner on the back surface of the cell, representing a back-junction back-contact solar cell. In this application, there are no limitations on the type of cell used in the IBC cell, as long as the first emitter (i.e., the electron collection region) and the second emitter (i.e., the hole collection region) are arranged in a cross-shaped pattern on the back surface.

[0062] In this application, the front side of the silicon substrate refers to the surface facing sunlight under normal battery operating conditions, while the back side refers to the surface of the silicon substrate on the other side opposite to the front side.

[0063] like Figure 2 As shown, several collector gate lines are formed on the back side of the silicon substrate. Figure 2 The image shows the center-to-center spacing d of the IBC fine grid lines of the same polarity. Figure 2 For example, the center spacing of the fine grid lines of the first electrode is d1, and the center spacing of the fine grid lines of the second electrode is d2, where d1 = d2 = d.

[0064] In this application, the grid line density of the same polarity current collector grid lines in the direction perpendicular to the current collector grid lines is n lines / cm. Those skilled in the art can determine the average number of current collector grid lines per centimeter through visual observation, for example, by counting. Alternatively, they can determine the total number of current collector grid lines on the entire silicon substrate by counting and then dividing by the length of the entire silicon substrate (in the direction perpendicular to the current collector grid lines) to determine the grid line density. For back-contact batteries, since current collector grid lines of different polarities are located on the same side, it is usually necessary to further divide by 2 to obtain the average number of current collector grid lines of the same polarity. Alternatively, the grid line density can also be obtained by the number of current collector grid lines of the same polarity and the battery length in the direction perpendicular to the current collector grid lines.

[0065] Figure 3This is a diagram of the back electrode of a double-sided contact battery. Figure 3 In the battery structure, the entire surface of one side of the silicon substrate is covered by electrodes of the same polarity, which include parallel or nearly parallel current collector grid lines, i.e., fine grid lines. Electrodes of opposite polarity are formed on the entire surface of the other side of the silicon substrate. Additionally, the electrodes may include, for example... Figure 3 The main gate lines shown are perpendicular to the fine gate lines. The center-to-center spacing of the fine gate lines of the same polarity is d, as shown... Figure 3 As shown.

[0066] Similar to the back contact electrode described above, those skilled in the art can calculate the number of electrodes by measuring the distance d between adjacent collector grid lines and dividing the total length of the battery in the direction perpendicular to the collector grid lines by the distance d. Those skilled in the art can also fully understand that the above calculation or measurement method for the number of electrodes is merely an example, and those skilled in the art can calculate it according to the actual situation.

[0067] In this application, when calculating the grid line density of the same polarity grid lines per unit length in the direction perpendicular to the grid lines, those skilled in the art also understand that this only applies to the area where the grid lines are disposed. If the grid lines are uniformly disposed on the silicon substrate, the entire silicon substrate can be used as the basis for calculating the grid lines. If they are only disposed in a local area of ​​the battery silicon substrate, that local area should be used as the total length of the area where the grid lines are disposed, and then the grid line density per unit length should be calculated.

[0068] Through in-depth research, the applicant of this application discovered that, in a specific embodiment of this application, a battery includes: a silicon substrate, and a plurality of current collector grid lines formed on one side surface of the silicon substrate; the silicon substrate is doped with antimony; and the grid line density of current collector grid lines of the same polarity per unit length in a direction perpendicular to the current collector grid lines is n lines / cm. The grid line density n and the concentration of antimony in the silicon substrate, a atoms / cm², are also considered. 3 The following relationship must be satisfied:

[0069] Formula 1: n≥35-klg a

[0070] In this application, the collector grid line is a grid line used to collect charge carriers, and is generally referred to as a fine grid line.

[0071] There are no restrictions on the form of the cell, and it can be applied to various types of solar cells, including aluminum back field cells (Al-BSF), passivated emitter and back contact cells (PERC), metal perforated wound cells (MWT), passivated emitter back localized diffusion cells (PERL), passivated emitter back fully diffused cells (PERT), emitter perforated wound cells (EWT), tunnel oxide passivated cells (TOPCon), interdigitated back contact cells (IBC), crystalline silicon heterojunction cells (HJT / HIT), and full back electrode back contact heterojunction cells (HBC).

[0072] In one specific embodiment, if it is a double-sided contact battery, the solution of this application is applicable to the design of the current collector grid lines of both the front and back electrodes, and can be designed according to the solution of this application. The data in the specific implementation takes the front grid line as an example.

[0073] In some specific ways, it can be a battery with at least a partial TOPCon structure, including TOPCon batteries, partial TOPCon batteries, back-contact hybrid batteries and TBC batteries, or it can be a crystalline silicon heterojunction battery (HJT / HIT) or a full back electrode back-contact heterojunction battery (HBC).

[0074] In one specific implementation, k is less than or equal to 2, for example, it can be 1.5, 1.6, 1.7, 1.8, 1.9, or 2.0.

[0075] In this application, there is no lower limit for k, but those skilled in the art will understand that k should be a positive number greater than 0.

[0076] For various types of batteries, effectively controlling the number of current collector grids to satisfy Formula 1 can effectively improve lateral transmission. This results in good battery efficiency (Eta) and open-circuit voltage, while also exhibiting excellent short-circuit current and fill factor, thus effectively improving the cell efficiency.

[0077] In one specific implementation, the number of collector grid lines n of the same polarity per unit length (i.e., grid line density n lines / cm) is further adjusted for different silicon substrate thicknesses in solar cells. When the silicon substrate thickness is b μm, the grid line density n and the concentration a of antimony in the silicon substrate satisfy the following relationship:

[0078]

[0079] In this equation, the constant c is 50 μm. Based on Equation 2, the thinner the silicon substrate, the greater the impact of the lateral transport resistance of charge carriers on the gate line design, and the more gate lines are required to improve battery performance. When the silicon substrate thickness b is 50-100 μm or 100-180 μm, different numerical ranges can be calculated based on Equation 2.

[0080] In a specific implementation, n satisfies the following relationship:

[0081] Formula 3: n≤35-lg a

[0082] Generally speaking, the more grid lines there are, the larger the contact area between the metal and the silicon semiconductor, making it easier for charge carriers in the silicon substrate to recombine. Therefore, grid line density is not always better the higher it is; there is an upper limit. Furthermore, since there is usually a higher carrier recombination rate at the electrodes (the recombination rate is measured by the reverse saturation current density), the higher the recombination rate, the more severe the recombination, and the worse the battery performance. Therefore, grid line density is not always better the higher it is; there is an upper limit. At the same time, the more grid lines there are, the more severe the light shading in the battery. Therefore, for n to simultaneously satisfy both Equation 1 and Equation 3, i.e., 35-klg a≤n≤35-lg a, the effect of lateral transport and the impact of light shading on battery efficiency can be effectively balanced, resulting in better battery efficiency.

[0083] In one specific embodiment, the grid line density in Formula 1, Formula 2 and Formula 3 of this application can be applied to the fine grid lines on the front and back sides of a double-sided contact battery, including the PN junction side and the high and low junction sides; it is also applicable to the back grid lines of a BC battery, including the fine grid lines on the back positive electrode and the fine grid lines on the back negative electrode.

[0084] In one specific implementation, for a double-sided contact battery, where the positive and negative electrodes are distributed on two different surfaces of the battery, k = 2 is preferred.

[0085] A bifacial contact battery refers to a battery in which charge carriers are collected on the same or different surfaces through doped regions on different surfaces. The positive and negative electrodes can be directly on opposite sides, or electrons and holes can be drawn out from opposite sides respectively, but ultimately the positive and negative electrodes are on the same side of the battery surface.

[0086] In one specific embodiment of this application, the double-sided contact battery can be a metal perforated wound (MWT) battery or an emitter perforated wound (EWT) battery.

[0087] In one specific embodiment of this application, the double-sided contact battery is a TOPCon battery. Figure 7This illustrates a typical structure of the double-sided contact solar cell involved in this application. A semiconductor layer 3 is disposed on the side of the interface passivation layer 9 away from the silicon substrate 4. Further, a passivation layer 2 may be disposed on the semiconductor layer 3. Further, the solar cell has a silicon substrate 4, a first electrode 1, and a second electrode 5. Figure 7 In the middle, the upper part is a hole collection region formed by P-type semiconductors, and the lower part is an electron collection region formed by N-type semiconductors.

[0088] In one specific embodiment, for a back-contact battery, when the positive and negative terminals are disposed on one surface of the battery, k = 1.9. The inventors of this application, through extensive experimentation, discovered that a value of 1.9 for k is more accurate for back-contact batteries.

[0089] In one specific embodiment of this application, the back contact battery is a back contact hybrid battery.

[0090] In one specific embodiment of this application, the back contact battery is a TBC battery.

[0091] In one specific embodiment of this application, the back-contact battery is a full-back electrode back-contact heterojunction battery.

[0092] In one specific implementation, for the case of a back-contact battery, there is typically an electron collection region and a hole collection region on one side of the battery, along with an isolation region between the electron collection region and the hole collection region; when the depth of the isolation region between the battery's electron collection region and hole collection region is dμm, the n satisfies the following relationship:

[0093]

[0094] The depth of the isolation region is the numerical height difference between the bottom of the shallower region in the electron collection region and the bottom of the isolation region, which corresponds to the average depth of the bottom of the isolation region. In other words, it is the vertical depth from the interface between the tunneling layer of the hole collection region or the electron collection region and the substrate (i.e., the silicon substrate surface) to the deepest part of the isolation region. If the hole collection region and the electron collection region have different heights, the vertical depth from the higher region to the deepest part of the isolation region is selected.

[0095] The aforementioned isolation region refers to an electrically insulating region (or gap region) introduced between the hole collection region and the electron collection region, thereby avoiding direct lateral contact between the two regions. Those skilled in the art will readily understand that the height difference d refers to the vertical height difference between the bottom of the shallower region of the electron collection region and the average depth of the bottom of the isolation region, or, when the solar cell contains an interface passivation layer, the bottom of the electron collection region or hole collection region is the height of the interface passivation layer closest to the silicon substrate.

[0096] In one specific embodiment, the structural diagram of the back contact battery is as follows: Figure 4 As shown, the hole collection region 7 and the electron collection region 8 are separated by the isolation region 6. The hole collection region 7 is the higher region between the two regions, therefore the aforementioned height difference d is as follows: Figure 4 As shown, this refers to the difference between the bottom of the hole collection area 7 and the bottom of the isolation area 6.

[0097] In one specific embodiment, the hole collection region, electron collection region, and isolation region of the solar cell involved in this application are at the same height, that is, at the same depth, so there is no height difference.

[0098] In one specific embodiment, this application provides a structure for a solar cell, the structure of which is as follows: Figure 5 As shown, the hole collection region and the electron collection region have the same depth, and the numerical height difference between the bottom of any region in the hole collection region and the bottom of the isolation region is d.

[0099] This application provides a schematic diagram of the structure of a solar cell, such as... Figure 6 As shown, the hole collection region and the electron collection region have the same depth, and the numerical height difference between the bottom of any region in the hole collection region and the bottom of the isolation region is d.

[0100] For a back-contact battery with a numerical height difference d, if the above formula four (k = 1.9) is satisfied, such a setting can effectively balance the effects of lateral and longitudinal transmission and the impact of shading on battery efficiency.

[0101] In one specific embodiment, the concentration 'a' of the antimony element is in the range of 1E13 to 1E18 atom / cm³. 3 .

[0102] For example, the concentration 'a' of the antimony element can be 1E13 atom / cm³. 3 1E14 atom / cm 3 1E15atom / cm 3 1E16 atom / cm 3 1E17 atom / cm 3 1E18 atom / cm 3 For example, it could be 2E13 atom / cm. 3 3E13 atom / cm 3 4E13 atom / cm 3 5E13 atom / cm3 ,6E13atom / cm 3 ,7E13 atoms / cm 3 ,8E13 atoms / cm 3 、9E13atom / cm 3 ,1E14 atoms / cm 3 、4E+14atom / cm 3 、4.1E+14atom / cm 3 、4.2E+14atom / cm 3 、4.3E+14atom / cm 3 、4.4E+14atom / cm 3 、4.5E+14atom / cm 3 、4.6E+14atom / cm 3 、4.7E+14atom / cm 3 、4.8E+14atom / cm 3 、4.9E+14atom / cm 3 、5E+14atom / cm 3 、5.1E+14atom / cm 3 、5.2E+14atom / cm 3 、5.3E+14atom / cm 3 、5.4E+14atom / cm 3 、5.5E+14atom / cm 3 、5.6E+14atom / cm 3 、5.7E+14atom / cm 3 、5.8E+14atom / cm 3 、5.9E+14atom / cm 3 、6E+14atom / cm 3 、6.1E+14atom / cm 3 、6.2E+14atom / cm 3 、6.3E+14atom / cm 3 、6.4E+14atom / cm 3 、6.5E+14atom / cm 3 、6.6E+14atom / cm 3 、6.7E+14atom / cm 3 、6.8E+14atom / cm 3 、6.9E+14atom / cm 3 、7E+14atom / cm 3、7.1E+14atom / cm 3 、7.2E+14atom / cm 3 、7.3E+14atom / cm 3 、7.4E+14atom / cm 3 、7.5E+14atom / cm 3 、7.6E+14atom / cm 3 、7.7E+14atom / cm 3 、7.8E+14atom / cm 3 、7.9E+14atom / cm 3 、8E+14atom / cm 3 、8.1E+14atom / cm 3 、8.2E+14atom / cm 3 、8.3E+14atom / cm 3 、8.4E+14atom / cm 3 、8.5E+14atom / cm 3 、8.6E+14atom / cm 3 、8.7E+14atom / cm 3 、8.8E+14atom / cm 3 、8.9E+14atom / cm 3 、9E+14atom / cm 3 、9.1E+14atom / cm 3 、9.2E+14atom / cm 3 、9.3E+14atom / cm 3 、9.4E+14atom / cm 3 、9.5E+14atom / cm 3 、9.6E+14atom / cm 3 、9.7E+14atom / cm 3 、9.8E+14atom / cm 3 、9.9E+14atom / cm 3 、1E+15atom / cm 3 、1.1E+15atom / cm 3 、1.2E+15atom / cm 3 、1.3E+15atom / cm 3 、1.4E+15atom / cm 3 、1.5E+15atom / cm 3 、1.6E+15atom / cm 3、1.7E+15atom / cm 3 、1.8E+15atom / cm 3 、1.9E+15atom / cm 3 、2E+15atom / cm 3 、2.1E+15atom / cm 3 、2.2E+15atom / cm 3 、2.3E+15atom / cm 3 、2.4E+15atom / cm 3 、2.5E+15atom / cm 3 、2.6E+15atom / cm 3 、2.7E+15atom / cm 3 、2.8E+15atom / cm 3 、2.9E+15atom / cm 3 、3E+15atom / cm 3 、3.1E+15atom / cm 3 、3.2E+15atom / cm 3 、3.3E+15atom / cm 3 、3.4E+15atom / cm 3 、3.5E+15atom / cm 3 、3.6E+15atom / cm 3 、3.7E+15atom / cm 3 、3.8E+15atom / cm 3 、3.9E+15atom / cm 3 、4E+15atom / cm 3 、4.1E+15atom / cm 3 、4.2E+15atom / cm 3 、4.3E+15atom / cm 3 、4.4E+15atom / cm 3 、4.5E+15atom / cm 3 、4.6E+15atom / cm 3 、4.7E+15atom / cm 3 、4.8E+15atom / cm 3 、4.9E+15atom / cm 3 、5E+15atom / cm 3 、5.1E+15atom / cm 3 、5.2E+15atom / cm 3、5.3E+15atom / cm 3 、5.4E+15atom / cm 3 、5.5E+15atom / cm 3 、5.6E+15atom / cm 3 、5.7E+15atom / cm 3 、5.8E+15atom / cm 3 、5.9E+15atom / cm 3 、6E+15atom / cm 3 、6.1E+15atom / cm 3 、6.2E+15atom / cm 3 、6.3E+15atom / cm 3 、6.4E+15atom / cm 3 、6.5E+15atom / cm 3 、6.6E+15atom / cm 3 、6.7E+15atom / cm 3 、6.8E+15atom / cm 3 、6.9E+15atom / cm 3 、7E+15atom / cm 3 、7.1E+15atom / cm 3 、7.2E+15atom / cm 3 、7.3E+15atom / cm 3 、7.4E+15atom / cm 3 、7.5E+15atom / cm 3 、7.6E+15atom / cm 3 、7.7E+15atom / cm 3 、7.8E+15atom / cm 3 、7.9E+15atom / cm 3 、8E+15atom / cm 3 、8.1E+15atom / cm 3 、8.2E+15atom / cm 3 、8.3E+15atom / cm 3 、8.4E+15atom / cm 3 、8.5E+15atom / cm 3 、8.6E+15atom / cm 3 、8.7E+15atom / cm 3 、8.8E+15atom / cm 3、8.9E+15atom / cm 3 、9E+15atom / cm 3 、9.1E+15atom / cm 3 、9.2E+15atom / cm 3 、9.3E+15atom / cm 3 、9.4E+15atom / cm 3 、9.5E+15atom / cm 3 、9.6E+15atom / cm 3 、9.7E+15atom / cm 3 、9.8E+15atom / cm 3 、9.9E+15atom / cm 3 、1E+16atom / cm 3 、1.1E+16atom / cm 3 、1.2E+16atom / cm 3 、1.3E+16atom / cm 3 、1.4E+16atom / cm 3 、1.5E+16atom / cm 3 、1.6E+16atom / cm 3 、1.7E+16atom / cm 3 、1.8E+16atom / cm 3 、1.9E+16atom / cm 3 、2E+16atom / cm 3 、3E+16atom / cm 3 、4E+16atom / cm 3 、5E+16atom / cm 3 、6E+16atom / cm 3 、7E+16atom / cm 3 、8E+16atom / cm 3 、9E+16atom / cm 3 、1E+17atom / cm 3 、2E+17atom / cm 3 、3E+17atom / cm 3 、4E+17atom / cm 3 、5E+17atom / cm 3 、6E+17atom / cm 3 、7E+17atom / cm 3 、8E+17atom / cm 39E+17atom / cm 3 And any range between these values.

[0103] This application dops Sb into a silicon substrate. Due to the low concentration of doping, there are fewer defects, which can improve the charge mobility of the silicon substrate and reduce the resistivity of the silicon substrate. Secondly, the Sb element at this concentration can reduce the differentiation of the silicon band edge energy level caused by doping, and the Sb element doping ionization rate is relatively high.

[0104] Examples and Comparative Examples

[0105] I. Obtaining the initial formula

[0106] First, a silicon substrate was prepared using conventional methods in the art. Then, by adjusting the Sb dopant concentration, the antimony concentration was determined to be 8.00E+16cm⁻¹. -3 1.00E+16cm -3 2.40E+15cm -3 9.00E+14cm -3 4.50E+14cm -3 3.00E+14cm -3 2.20E+14cm -3 4.40E+13cm -3 The silicon substrate was used. The concentration of antimony in the silicon substrate was determined using conventional methods in the art.

[0107] The silicon substrate was used to fabricate a battery, and different grid line densities were set. The battery performance was then tested.

[0108] For silicon substrates with the same antimony concentration, the distribution of cell efficiency under different grid line densities is shown in the graph, i.e., the trend of cell performance (based on conversion efficiency Eta) under the same silicon substrate with different grid line densities. Figures 8-11 As shown, it was found that within a certain range, the electrical performance tends to decrease as the gate line density decreases. Furthermore, below a specific gate line density, the electrical performance degrades very rapidly. This specific gate line density is denoted as the inflection point gate line density; then, data fitting was performed based on different antimony concentrations and the corresponding inflection point gate line density n, and the results are as follows. Figure 12 As shown.

[0109] like Figure 12 As shown, the horizontal axis represents the antimony doping concentration 'a' in the silicon substrate, in cm⁻¹. -3The vertical axis represents the grid line density n, in units of lines / cm. It can be seen that the fitted curve formula is y = 35 - 2lgx, that is, n = 35 - 2lga. When n and a satisfy the formula 35 - 2lg a, that is, n ≥ 35 - 2lg a, the efficiency of the solar cell increases significantly. If n < 35 - 2lga, the efficiency of the solar cell decreases significantly.

[0110] It can be seen that when the grid line density n of the actual battery is greater than this lower critical value (35-2lg a), the electrical performance level is significantly higher. When the n of the actual battery is greater than this lower critical value, the electrical performance level is relatively lower.

[0111] II. Verification of Solar Cell Performance

[0112] Preparation Example

[0113] First, a silicon substrate was prepared using conventional methods in the art. Then, by adjusting the Sb dopant concentration, the antimony concentration was determined to be 8.00E+16cm⁻¹. -3 1.00E+16cm -3 2.40E+15cm -3 9.00E+14cm -3 4.50E+14cm -3 3.00E+14cm -3 2.20E+14cm -3 4.40E+13cm -3 The silicon substrate was used. The concentration of antimony in the silicon substrate was determined using conventional methods in the art.

[0114] Example 1 is for a double-sided contact battery

[0115] Preparation of batteries 1-1 to 1-10

[0116] The following preparations were made using antimony-doped silicon substrates obtained from the preparation examples: Figure 7 The double-sided contact battery structure shown is a TOPCon solar cell, wherein Examples 1-1 and 1-6 use an antimony concentration of 8.00E+16cm⁻¹. -3 The silicon substrate used in Examples 1-2 and 1-7 had an antimony concentration of 1.00E+16cm⁻¹. -3 The silicon substrate used in Examples 1-3 and 1-8 had an antimony concentration of 9.00E+14 cm⁻¹. -3 The silicon substrate used in Examples 1-4 and 1-9 had an antimony concentration of 8.00E+14cm⁻¹. -3 The silicon substrate, and the antimony element concentration used in Examples 1-5 and 1-10 was 4.00E+14cm. -3The silicon substrates in Examples 1-1 to 1-5 have a thickness of 150 μm; the silicon substrates in Examples 1-6 to 1-10 have a thickness of 100 μm.

[0117] The solar cells prepared in Examples 1-1 to 1-10 were tested using an IV tester, specifically a photovoltaic performance testing device manufactured by Halm Corporation. When preparing the test samples, 100 experimental cells were prepared for each group, and the final number of finished cells ranged from 30 to 100. The median efficiency of each group was used to obtain the Isc, Uoc, FF and Eta performance, and the results are shown in Table 1 and Table 2, respectively.

[0118] Table 1 Results of bifacial contact cells with a thickness of 150 μm

[0119]

[0120]

[0121] Table 2 Results of bifacial contact cells with a thickness of 100 μm

[0122]

[0123]

[0124] Based on the results of Example 1, it can be seen that in the case of a double-sided contact cell, i.e., the positive and negative electrodes of the cell are distributed on two different sides of the cell, when the relationship between the grid line density n and the antimony doping concentration a does not conform to Formula 1, the performance of Isc, Uoc, FF, and Eta of the solar cell is poor; as the grid line density increases, when the relationship between the grid line density n and the antimony doping concentration a satisfies Formula 1, the performance of Isc, Uoc, FF, and Eta of the solar cell is better; when the relationship between the grid line density n and the antimony doping concentration a satisfies Formula 2, the performance of Isc, Uoc, FF, and Eta of the solar cell is even better.

[0125] Based on the data in Table 1, trend graphs of Eta performance data were plotted according to the increasing order of grid line density in this embodiment at different concentrations, as shown below. Figure 8 Based on the data in Table 2, trend graphs of Eta performance were plotted according to the increasing order of grid line density in this embodiment at different concentrations, as shown below. Figure 9 It should be noted that, Figure 8 and Figure 9 The horizontal axis in the figure only represents the sequence number of the gate line density data in this embodiment and has no actual physical meaning.

[0126] from Figure 8 and Figure 9 In the figure, the data to the left of the vertical dotted line do not satisfy Formula 1, which shows that the battery performance degrades faster when Formula 1 is not satisfied.

[0127] Example 2 is for back contact batteries

[0128] Preparation of batteries 2-1 to 2-10

[0129] Back contact battery structures were fabricated using antimony-doped silicon substrates obtained in the preparation examples, as shown in the examples. Figure 1 As shown, the gate structure is as follows Figure 2 As shown. Examples 2-1 and 2-6 used an antimony concentration of 8.00E+16cm. -3 The silicon substrate used in Examples 2-2 and 2-7 had an antimony concentration of 1.00E+16cm⁻¹. -3 The silicon substrate used in Examples 2-3 and 2-8 had an antimony concentration of 9.00E+14cm⁻¹. -3 The silicon substrate used in Examples 2-4 and 2-9 had an antimony concentration of 8.00E+14cm⁻¹. -3 The silicon substrate used in Examples 2-5 and 2-10 had an antimony concentration of 4.00E+14cm⁻¹. -3 The silicon substrates were designed based on different silicon substrate thicknesses and different back contact cell isolation depths.

[0130] For the solar cells prepared in Examples 2-1 to 2-15, the Isc, Uoc, FF and Eta performance were tested using the same method as in Example 1. The results are shown in Tables 3 and 4, respectively.

[0131] Table 3 Results of back contact batteries with a thickness of 150 μm

[0132]

[0133]

[0134] Table 4 Results of back contact batteries with a thickness of 100 μm

[0135]

[0136]

[0137]

[0138] Based on the results in Tables 3 and 4, it can be seen that in the case of back-contact batteries, i.e., when both the positive and negative electrodes of the battery are on one side of the battery, the performance of Isc, Uoc, FF and Eta of the solar cell is good when n≥35-1.9lga. However, when this formula is not met, the performance of Isc, Uoc, FF and Eta is poor.

[0139] Furthermore, when n conforms to Formula 2, the solar cell exhibits better performance in Isc, Uoc, FF, and Eta. The inventors speculate that this is because charge carriers not only need to pass through the thickness direction of the silicon substrate, but also typically need to move laterally between the positive and negative electrodes on the back side. During lateral transport, the path traveled is longer, so more grid lines per unit length are needed to counteract this effect.

[0140] When n conforms to Formula 4, the performance of solar cells Isc, Uoc, FF and Eta can be further improved.

[0141] Based on the data in Table 3, trend graphs of Eta performance were plotted according to the increasing order of grid line density in this embodiment at different concentrations, as shown below. Figure 10 Based on the data in Table 4, trend graphs of Eta performance were plotted according to the increasing order of grid line density in this embodiment at different concentrations, as shown below. Figure 11 It should be noted that, Figure 10 and Figure 11 The horizontal axis in the figure only represents the sequence number of the gate line density data in this embodiment and has no actual physical meaning.

[0142] exist Figure 10 and Figure 11 In the figure, the data to the left of the vertical dotted line do not satisfy Formula 1, making it even clearer that battery performance degrades faster when Formula 1 is not satisfied.

[0143] Although the embodiments of this application have been described above in conjunction with the specific embodiments described, this application is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, and not restrictive. Those skilled in the art can make many other forms based on the teachings of this specification and without departing from the scope of protection of the claims of this application, and these are all within the scope of protection of this application.

Claims

1. A solar cell comprising: A silicon substrate, and several collector gate lines formed on one side surface of the silicon substrate; The silicon substrate is doped with antimony. The grid line density of the collector grid lines with the same polarity in the direction perpendicular to the collector grid lines is n lines / cm, and the concentration of antimony in the silicon substrate is a atoms / cm. 3 When n and a satisfy the following relationship: Formula 1, n≥35-klg a Where k is less than or equal to 2.

2. The solar cell according to claim 1, wherein, When the thickness of the silicon substrate of the battery is b μm, n satisfies the following relationship: Where c is a constant and takes the value of 50 μm.

3. The solar cell according to claim 1, wherein, n and a also satisfy the following relationship: Formula 3: n≤35-lg a 4. The solar cell according to any one of claims 1 to 3, wherein, The solar cell is a double-sided contact cell, k=2.

5. The solar cell according to any one of claims 1 to 3, wherein, The solar cell is a back-contact cell with k = 1.

9.

6. The solar cell according to claim 5, wherein, One side surface of the silicon substrate has an electron collecting region and a hole collecting region, as well as an isolation region located between the electron collecting region and the hole collecting region; when the depth of the isolation region is dμm, n satisfies the following relationship:

7. The solar cell according to claim 6, wherein, The depth of the isolation region is the numerical height difference between the bottom of the shallower region in the electron collection region and the bottom of the isolation region, and the bottom of the isolation region is the surface of the silicon substrate corresponding to the isolation region. When the solar cell contains an interface passivation layer, the bottom of the electron collection region or hole collection region is the height of the interface passivation layer near the silicon substrate.

8. The solar cell according to any one of claims 1 to 7, wherein, The range of 'a' is 1E13 to 1E18.

9. The solar cell according to any one of claims 1 to 8, wherein, The width of each of the aforementioned collector grid lines is 10-200 μm.

10. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell according to any one of claims 1 to 9.

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