Preparation method of micro light-emitting diode

Abstract

The invention discloses a preparation method of a miniature light emitting diode. The preparation method comprises the following steps: providing an LED epitaxial wafer; the LED epitaxial wafer comprises a GaN semiconductor layer, a quantum well layer and a p-GaN layer, wherein the GaN semiconductor layer, the quantum well layer and the p-GaN layer are arranged in a stacked mode. Annealing treatment is carried out on the N surface of the GaN semiconductor layer, so that GaN on the surface of the GaN semiconductor layer is converted into GaO, and a GaN-GaO semiconductor layer is obtained; etching the N surface of the GaN-GaO semiconductor layer to obtain a multi-surface micro cone mirror pattern layer; the etching method is wet etching, and the wet etching comprises the following steps: placing the GaN-GaO semiconductor layer in a corrosive liquid at a temperature of 80-120 DEG C, and heating for 10-30 min to obtain closely arranged six-sided micro-cone mirrors on the N surface of the GaN-GaO semiconductor layer, and six surfaces of each six-sided micro-cone mirror are {10 <-1 >-1} crystal surfaces. According to the method provided by the invention, the multi-surface micro cone mirror pattern layer with a special structure is arranged on the N surface of the semiconductor layer, so that the surface light extraction efficiency and the surface light extraction ratio can be increased.

Description

[0001] This application is a divisional application of the invention patent application filed on April 11, 2025, with application number 2025104530359 and invention title "Micro Light Emitting Diode with High Surface Light Extraction Efficiency and Preparation Method Thereof". Technical Field

[0002] This invention relates to the field of micro light-emitting diode technology, and specifically to a method for fabricating a micro light-emitting diode with high surface light extraction efficiency. Background Technology

[0003] In recent years, micro light-emitting diodes (Micro-LEDs) have shown great promise in fields such as display, communication, and medicine due to their advantages such as higher luminous efficiency, higher brightness, and ultra-high resolution. Currently, most GaN-based Micro-LEDs on the market are heteroepitaxial, meaning they use sapphire as the substrate. Homoepitaxial Micro-LED chips are also under active exploration and have made relevant progress. Sapphire substrates are less expensive, while homoepitaxial substrates have lower dislocation density (2-3 orders of magnitude lower) and extremely low stress compared to sapphire substrates.

[0004] However, the quantum efficiency of Micro-LEDs remains low, and improving the light extraction efficiency (LEE) is a pressing issue. For traditional large-size LEDs, the small surface area to volume ratio results in a small proportion of light emitted from the sidewalls. However, as the size decreases, the surface area to volume ratio increases, leading to a gradual increase in the sidewall light extraction proportion of Micro-LEDs. Micro-LEDs used in micro-displays generally require dimensions below 10μm. For 10μm Micro-LEDs, sidewall light extraction accounts for more than half of the total light output, and the surface light extraction efficiency (LSE) and surface light extraction proportion (S) significantly limit their performance. In practical applications, the large sidewall light extraction and low top light extraction cause severe inter-pixel crosstalk, reducing resolution and contrast. Furthermore, the packaging process can obstruct sidewall light extraction. Therefore, improving the light extraction efficiency essentially requires improving the surface light extraction efficiency.

[0005] However, current methods for improving light extraction (LSE) are costly and highly dependent on process precision and technology. While they are effective for large-size LEDs, their effectiveness is limited for Micro-LEDs, and there is a lack of optimization schemes specifically for LSE. Examples include patterned substrates, surface plasmon polaritons, and photonic crystal micro / nano structures. Among these, patterned substrates have complex fabrication processes, high costs, and stringent etching requirements; photonic crystal fabrication processes are extremely complex and require high precision; and surface plasmon polaritons are highly susceptible to environmental influences, potentially affecting device stability and reliability, and their fabrication is complex and costly.

[0006] Traditional large-size LEDs only need to focus on the overall LEE, but Micro-LEDs are different. Given the current problems of low LSE and low surface light emission ratio in Micro-LEDs, there is an urgent need for a relatively simple and feasible method to improve LSE and S for Micro-LEDs. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a method for preparing a micro light-emitting diode with high surface light extraction efficiency, which can effectively improve the surface light extraction efficiency of the micro light-emitting diode.

[0008] In a first aspect, the present invention provides a method for fabricating a micro light-emitting diode with high surface light extraction efficiency, comprising the following steps:

[0009] An LED epitaxial wafer is provided; wherein the LED epitaxial wafer includes a GaN semiconductor layer, a quantum well layer and a p-GaN layer stacked together;

[0010] The N-side of the GaN semiconductor layer is annealed to convert GaN on the surface of the GaN semiconductor layer into GaO, thus obtaining a GaN-GaO semiconductor layer.

[0011] The N-side of the GaN-GaO semiconductor layer is etched to obtain a multifaceted microcone mirror pattern layer.

[0012] The multifaceted microcone pattern layer comprises a plurality of regularly arranged multifaceted microcones, with the bottom edges of adjacent multifaceted microcones fitting together, i.e., closely arranged adjacent multifaceted microcones; the bottom-to-height ratio of the multifaceted microcones is (1-2.5):1. Preferably, the bottom-to-height ratio of the multifaceted microcones is 1:1, 4:3, 5:3, or 5:2; more preferably, the bottom-to-height ratio of the multifaceted microcones is 4:3.

[0013] According to some preferred embodiments of the present invention, the GaN semiconductor layer includes an n-GaN layer, and a multifaceted microcone pattern layer is disposed on the n-GaN layer; or, the GaN semiconductor layer includes a u-GaN layer and an n-GaN layer, and a multifaceted microcone pattern layer is disposed on the u-GaN layer.

[0014] According to some preferred embodiments of the present invention, the multifaceted microcone is a three-sided, six-sided, or twelve-sided microcone. When the multifaceted microcone is a three-sided or six-sided microcone, the bottom edges of the multifaceted microcone are completely fitted together without gaps; when the multifaceted microcone is a twelve-sided microcone, the bottom edges of some of the multifaceted microcone are completely fitted together without gaps, although the bottoms of multiple twelve-sided microcones are closely arranged, there is a triangular gap in the middle of every three closely arranged twelve-sided microcones.

[0015] According to some preferred embodiments of the present invention, the bottom surface dimension of the multifaceted microcone is 100-1000 nm, preferably 200-1000 nm. When the multifaceted microcone is a three-sided microcone, the height of the bottom triangle is 100-1000 nm; when the multifaceted microcone is a six-sided or twelve-sided microcone, the distance between the bottom facets and edges is 100-1000 nm. The six-sided microcone pattern has a better effect on enhancing surface light extraction. However, not all pattern layer dimensions have a positive effect on light extraction. When the bottom surface dimension is less than 100 nm, the effect is not obvious, and may even be detrimental to the surface light extraction of the micro-LED.

[0016] According to some preferred embodiments of the present invention, the etching method is wet etching, and the steps of the wet etching are as follows:

[0017] Under a temperature of 80-120℃, the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-40 minutes to obtain closely packed six-sided microcone mirrors on the N-side of the GaN-GaO semiconductor layer. Each of the six sides of the six-sided microcone mirror is a {10-11} crystal plane.

[0018] The corrosive liquid is a mixture of ammonia, H2O2 and H2O, with a volume ratio of ammonia:H2O2:H2O = 1:0.5-1.5:4-6.

[0019] According to some preferred embodiments of the present invention, the etching method is wet etching, and the steps of the wet etching are as follows:

[0020] Under a temperature of 80-120℃, the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-30 minutes to obtain closely packed six-sided microcone mirrors on the N-side of the GaN-GaO semiconductor layer. Each of the six sides of the six-sided microcone mirror is a {10-1-1} crystal plane.

[0021] The corrosive solution is a mixture of KOH solution and water, with a volume ratio of KOH solution:H2O = 1:4-6.

[0022] According to some preferred embodiments of the present invention, the etching method is wet etching, and the steps of the wet etching are as follows:

[0023] Under a temperature of 80-120℃, the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-40 minutes to obtain a closely packed dodecahedral microcone mirror on the N-side of the GaN-GaO semiconductor layer. Six of the twelve microcone mirrors are {20-2-3} crystal planes, and the remaining six are {22-4-5} crystal planes, with the two types of mirrors alternating.

[0024] The corrosive liquid is an H3PO4 solution, or a mixture of H3PO4 solution and water.

[0025] According to some preferred embodiments of the present invention, the annealing process conditions include: a temperature of 400-600°C, an oxygen atmosphere, and a treatment time of 5-20 min; and / or,

[0026] The steps also include pretreatment prior to annealing:

[0027] The GaN semiconductor layer is cleaned;

[0028] The N-side of the GaN semiconductor layer is dried using nitrogen gas at room temperature for 3-30 minutes; or the GaN semiconductor layer is dried using a nitrogen oven, wherein the drying process conditions include a drying time of 3-15 minutes and a drying temperature of 40-80°C.

[0029] According to some preferred embodiments of the present invention, the fabrication of the LED epitaxial wafer includes:

[0030] A substrate structure is provided, and an n-GaN layer, a stress relief layer, the quantum well layer, an electron blocking layer, and the p-GaN layer are sequentially fabricated on the substrate structure to obtain a first epitaxial wafer;

[0031] The first epitaxial wafer is processed to obtain the LED epitaxial wafer;

[0032] Before the step of etching the N-side of the GaN semiconductor layer, the following steps are included:

[0033] Photoresist is coated onto the surface of the LED epitaxial wafer and then baked.

[0034] After the step of etching the N-side of the GaN semiconductor layer, the following steps are included:

[0035] The photoresist is removed to obtain the micro light-emitting diode.

[0036] According to some preferred embodiments of the present invention, the process of obtaining the LED epitaxial wafer by processing the first epitaxial wafer includes:

[0037] The first epitaxial wafer is cleaned;

[0038] A transparent conductive layer is fabricated on the p-GaN layer to obtain a second epitaxial wafer; wherein, the second epitaxial wafer includes the substrate structure, the n-GaN layer, the stress relief layer, the quantum well layer, the electron blocking layer, the p-GaN layer and the transparent conductive layer stacked together;

[0039] Etching begins from the transparent conductive layer until the n-GaN layer is exposed, resulting in multiple mesa structures;

[0040] A passivation layer is deposited on the sidewalls of the platform structure, the upper surface of the platform structure, and between two adjacent platforms.

[0041] The passivation layer is etched to form an n-electrode window, and an n-electrode is fabricated within the n-electrode window to form a first LED epitaxial structure; wherein the n-electrode is in contact with the n-GaN layer;

[0042] The first LED epitaxial structure is annealed to obtain the second LED epitaxial structure.

[0043] The passivation layer in the second LED epitaxial structure is etched to form a p-electrode window, and a p-electrode is fabricated within the p-electrode window to obtain a third LED epitaxial structure; wherein the p-electrode is in contact with the transparent conductive layer;

[0044] The third LED epitaxial structure is bonded to the driving substrate to obtain the fourth LED epitaxial structure;

[0045] The fourth LED epitaxial structure is thinned or peeled off to obtain the LED epitaxial wafer.

[0046] According to some preferred embodiments of the present invention, the substrate structure includes a heterogeneous substrate and a u-GaN layer stacked together, and the step of thinning or peeling off the fourth LED epitaxial structure to obtain the LED epitaxial wafer includes: peeling off the heterogeneous substrate to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the u-GaN layer; or, peeling off the heterogeneous substrate and the u-GaN layer to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the n-GaN layer;

[0047] Alternatively, the substrate structure is a u-GaN layer, and the thinning or peeling of the fourth LED epitaxial structure to obtain the LED epitaxial wafer includes:

[0048] The u-GaN layer is thinned to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the thinned u-GaN layer; or, the u-GaN layer and the n-GaN layer are thinned to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the thinned n-GaN layer.

[0049] In some embodiments of the present invention, the method for fabricating a micro light-emitting diode with high surface light extraction efficiency specifically includes the following steps:

[0050] S1. Preparation of LED epitaxial wafers

[0051] The fabrication of the LED epitaxial wafer includes:

[0052] S11. Provide a substrate structure, and sequentially prepare an n-GaN layer, a stress relief layer, a quantum well layer, an electron blocking layer, and a p-GaN layer on the substrate structure by metal-organic chemical vapor deposition to obtain a first epitaxial wafer.

[0053] S12. The first epitaxial wafer is processed to obtain the LED epitaxial wafer.

[0054] Specifically, it includes:

[0055] S121. Clean the first epitaxial wafer.

[0056] S122. A transparent conductive layer, such as ITO, is prepared on the p-GaN layer to obtain a second epitaxial wafer; wherein the second epitaxial wafer includes the substrate structure, the n-GaN layer, the stress relief layer, the quantum well layer, the electron blocking layer, the p-GaN layer, and the transparent conductive layer stacked together.

[0057] S123. Etch from the transparent conductive layer until the n-GaN layer is exposed to obtain multiple mesa structures.

[0058] S124. A passivation layer is deposited on the sidewall of the platform structure, the upper surface of the platform structure, and between two adjacent platforms.

[0059] S125. The passivation layer is etched to form an n-electrode window, and an n-electrode is fabricated within the n-electrode window to form a first LED epitaxial structure; wherein the n-electrode is in contact with the n-GaN layer.

[0060] S126. Anneal the first LED epitaxial structure to obtain the second LED epitaxial structure.

[0061] S127. The passivation layer in the second LED epitaxial structure is etched to form a p-electrode window, and a p-electrode is fabricated in the p-electrode window to obtain a third LED epitaxial structure; wherein the p-electrode is in contact with the transparent conductive layer.

[0062] S128. The third LED epitaxial structure is bonded to the driving substrate to obtain the fourth LED epitaxial structure.

[0063] S129. Thinning or peeling the fourth LED epitaxial structure to obtain the LED epitaxial wafer.

[0064] Preferably, the above steps further include the step of depositing a sidewall metal reflective layer after depositing the passivation layer. The sidewall metal reflective layer can reflect the light emitted from the original sidewall back, allowing more light to be emitted from the surface, which can better improve the surface light emission efficiency of the micro light-emitting diode.

[0065] In some embodiments, the substrate structure includes a heterogeneous substrate (such as sapphire) and a u-GaN layer stacked together. The step of thinning or peeling off the fourth LED epitaxial structure to obtain the LED epitaxial wafer includes: peeling off the heterogeneous substrate to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the u-GaN layer; or, peeling off the heterogeneous substrate and the u-GaN layer to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the n-GaN layer.

[0066] In other embodiments, the substrate structure is a u-GaN layer, and the thinning or stripping of the fourth LED epitaxial structure to obtain the LED epitaxial wafer includes: thinning the u-GaN layer to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is a thinned homogeneous substrate; or, thinning the u-GaN layer and the n-GaN layer to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is a thinned n-GaN layer.

[0067] S2. Anneal the N-side of the GaN semiconductor layer to convert GaN on the surface of the GaN semiconductor layer into GaO, thereby obtaining a GaN-GaO semiconductor layer.

[0068] S3. Etch the N-side of the GaN-GaO semiconductor layer to obtain a multifaceted microcone mirror pattern layer;

[0069] By etching a multifaceted microcone pattern layer with a special structure onto the N-side of a GaN-GaO semiconductor layer, the surface light extraction efficiency and surface light emission ratio of a micro-LED can be increased. The multifaceted microcone pattern layer comprises multiple regularly arranged multifaceted microcones, with the bottom edges of adjacent multifaceted microcones closely fitted together; the base-to-height ratio of the multifaceted microcones is (1-2.5):1, and the multifaceted microcones are three-sided, six-sided, or twelve-sided; the bottom surface size of the multifaceted microcones is 100-1000 nm. When the multifaceted microcones are three-sided or six-sided, the bottom edges of the multifaceted microcones are completely fitted without gaps; when the multifaceted microcones are twelve-sided, some of the bottom edges of the multifaceted microcones are completely fitted without gaps.

[0070] Preferably, the etching method is selected from wet etching, photolithography and dry etching, and laser direct writing lithography.

[0071] Specifically, when the etching method is wet etching, it includes the following steps:

[0072] S31, Cleaning

[0073] The GaN semiconductor layer of the micro LED was sequentially ultrasonically cleaned in acetone, alcohol, and deionized water for 3-20 minutes to remove surface organic contaminants. The purpose of cleaning was to allow the N-side of the GaN semiconductor layer to better contact the etching solution.

[0074] S32, Remove surface liquid residue

[0075] The N-side of the GaN semiconductor layer is dried using a nitrogen gun at room temperature for 3-30 minutes; or, the GaN semiconductor layer is dried using an N2 oven for 3-15 minutes at a temperature of 40-80°C.

[0076] S33, Annealing

[0077] Rapid annealing of the N-side of the GaN semiconductor layer transforms the GaN compound on the surface into a more easily etchable GaO compound, forming a GaN-GaO semiconductor layer and enhancing the etching effect of the solution. The annealing process conditions include: a temperature of 400-600℃, an oxygen atmosphere, and a processing time of 5-20 minutes.

[0078] S34, Wet corrosion

[0079] The wet etching process for the N-side of the GaN-GaO semiconductor layer is as follows:

[0080] Under a temperature of 80-120℃, the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-40 minutes to obtain closely packed six-sided microcone mirrors on the N-side of the GaN-GaO semiconductor layer. Each of the six sides of the six-sided microcone mirror is a {10-11} crystal plane.

[0081] The corrosive solution is a mixture of ammonia, H2O2, and H2O, with a volume ratio of ammonia:H2O2:H2O = 1:0.5-1.5:4-6; preferably, the volume ratio of the substances in the corrosive solution is ammonia:H2O2:H2O = 1:1:5. The ammonia solution is a 20%-30% (by mass) aqueous solution, and the H2O2 solution has a concentration of 25-35%.

[0082] Alternatively, at a temperature of 80-120℃, the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-30 minutes to obtain closely packed six-sided microcone mirrors on the N-side of the GaN-GaO semiconductor layer, wherein each of the six faces of the six-sided microcone mirrors is a {10-1-1} crystal plane.

[0083] The corrosive solution is a mixture of KOH solution and water, with a volume ratio of KOH solution:H2O = 1:4-6; preferably, the volume ratio of substances in the corrosive solution is KOH solution:H2O = 1:5, wherein the KOH solution is a solution with a concentration of 0.01-0.02 mol / L.

[0084] Alternatively, at a temperature of 80-120℃, the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-40 minutes to obtain a closely packed dodecahedral microcone mirror on the N-side of the GaN-GaO semiconductor layer. Six of the twelve microcone mirrors are {20-2-3} crystal planes, and the remaining six are {22-4-5} crystal planes, with the two types alternating.

[0085] The corrosive solution is an H3PO4 solution, or a mixture of H3PO4 solution and water, with a volume ratio of H3PO4 solution to H2O of 1:16-128. Preferably, the volume ratio of each substance in the corrosive solution is H3PO4 solution to H2O of 1:16, 1:32, 1:64 or 1:128, wherein the H3PO4 solution is a solution with a concentration of 0.1-0.3 mol / L.

[0086] S4. Remove the photoresist to obtain the micro light-emitting diode.

[0087] Secondly, the present invention also provides a micro light-emitting diode prepared by the preparation method described above.

[0088] The present invention provides a method for fabricating a micro light-emitting diode with high surface light extraction efficiency. This method involves annealing the N-side of a GaN semiconductor layer to convert GaN on the surface of the GaN semiconductor layer into GaO, resulting in a GaN-GaO semiconductor layer. Then, the N-side of the GaN-GaO semiconductor layer is etched to obtain a multifaceted microcone pattern layer. The multifaceted microcone pattern layer comprises multiple regularly arranged multifaceted microcones, with the bottom edges of adjacent multifaceted microcones adhering to each other. The bottom-to-height ratio of the multifaceted microcones is (1-2.5):1. Annealing the GaN semiconductor layer transforms the GaN on its surface into GaO, and the GaO surface facilitates subsequent etching to form the desired multifaceted microcone pattern layer. Furthermore, the densely packed multifaceted microcone pattern layer on the N-side of the GaN-GaO semiconductor layer increases the surface light extraction efficiency and surface light emission ratio of the micro-LED. In addition, setting the bottom-to-height ratio of the multifaceted microcones to (1-2.5):1 further improves surface light emission efficiency and facilitates the fabrication of micro-LEDs. Attached Figure Description

[0089] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0090] Figure 1 This is a schematic diagram of the fabrication method of the micro light-emitting diode provided by the present invention;

[0091] Figure 2 This is a schematic diagram of the structure of the miniature light-emitting diode provided by the present invention;

[0092] Figure 3 This is another structural schematic diagram of the miniature light-emitting diode provided by the present invention;

[0093] Figure 4 This is a top view schematic diagram of the six-sided microcone mirror patterned layer provided by the present invention;

[0094] Figure 5 This is a schematic diagram of the three-dimensional structure of the six-sided microcone mirror patterned layer provided by the present invention;

[0095] Figure 6 The image shows the LSE results for the six-sided microconical mirror structure on the surface of a 10μm micro-LED with different bottom-to-height ratios.

[0096] Figure 7The image shows the LSE results for a 10μm micro LED corresponding to three-sided, six-sided, and twelve-sided microcone mirror structures, with a bottom-to-height ratio of 4:3.

[0097] Figure 8 The images show the LSE and S-images of a six-sided microcone pattern layer with different microcone base dimensions T for a 10μm micro LED.

[0098] Figure 9 The photoluminescence (PL) spectra of a homogeneous 10μm micro LED before and after wet etching are shown.

[0099] The reference numerals in the attached figures include: 10 for the n-GaN layer; 11 for the passivation layer; 12 for the main structure; 13 for the driving substrate; 14 for the n-electrode; 15 for the solder; 16 for the solder joint; 17 for the multifaceted microcone pattern layer; 18 for the sidewall metal reflective layer; and 19 for the p-electrode. Detailed Implementation

[0100] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0101] Existing technologies, such as patent CN201010617750.5, describe a method for fabricating patterned GaN substrates. This method primarily involves preparing micro / nano patterns on the GaN surface of a GaN single-crystal or composite substrate, which can then be used as a growth substrate to fabricate high-performance GaN-based LEDs. However, when used in LEDs, the need to grow n-GaN again on top of the substrate leads to an unclear interface between the substrate and the epitaxial layer, hindering the reduction of total internal reflection and the enhancement of light extraction. Furthermore, the structure described in this patent does not provide adequate enhancement for Micro-LEDs. When used in flip-chip applications, the substrate needs to be peeled off, and the GaN patterned substrate cannot be effectively separated from the GaN-based material of the LED epitaxial layer, resulting in poor preservation of the patterned layer.

[0102] For example, patent CN202010600418.1 uses the micro-nano structure surface of AlN as the light extraction optimization layer, and the AlN surface after annealing is N-polar. Epitaxial layer growth and light extraction structure are performed on the first and second surfaces of the substrate, respectively. However, since the substrate layer is very thick and has not been thinned, the heat dissipation effect is poor, and the light will undergo large total internal reflection between the epitaxial layer material and the substrate material. In addition, due to the absorption of the substrate, the light extraction structure on the first surface cannot achieve a good effect of enhancing light extraction.

[0103] For example, patent CN201710024540.7 describes a method for preparing nanoscale patterned substrates using polymer microspheres. This method can prepare micron- and nanoscale PSS sapphire substrates to improve the light extraction efficiency of GaN-based LEDs. However, in the actual fabrication of flip-chip Micro-LED devices, a thicker substrate can affect light extraction, requiring substrate peeling and thinning. In this case, the use of PSS sapphire substrates is limited, and the fabrication process is relatively complex.

[0104] Based on this, the present invention provides a method for fabricating a micro light-emitting diode based on a multi-faceted microcone mirror, which can increase the surface light extraction efficiency and the surface light emission ratio, and is described in detail below.

[0105] like Figure 1 As shown, Figure 1 This is a schematic flowchart of the fabrication method of the micro light-emitting diode provided by the present invention. The fabrication method of the micro light-emitting diode with high surface light extraction efficiency of the present invention specifically includes the following steps:

[0106] S1. Preparation of LED epitaxial wafers

[0107] The fabrication of LED epitaxial wafers includes:

[0108] S11. Provide a substrate structure, and sequentially prepare an n-GaN layer, a stress relief layer, a quantum well layer, an electron blocking layer, and a p-GaN layer on the substrate structure by metal-organic chemical vapor deposition (MOCVD) to obtain a first epitaxial wafer.

[0109] S12. Process the first epitaxial wafer to obtain the LED epitaxial wafer.

[0110] Specifically, it includes:

[0111] S121. Clean the first epitaxial wafer.

[0112] S122. A transparent conductive layer, such as ITO, is prepared on the p-GaN layer to obtain a second epitaxial wafer; wherein the second epitaxial wafer includes a substrate structure, an n-GaN layer, a stress relief layer, a quantum well layer, an electron blocking layer, a p-GaN layer, and a transparent conductive layer stacked together.

[0113] S123. Etch from the transparent conductive layer until the n-GaN layer is exposed to obtain multiple mesa structures.

[0114] S124. A passivation layer of SiO2 material is deposited on the sidewalls of the mesa structure, the upper surface of the mesa structure, and between two adjacent mesa structures using plasma enhanced chemical vapor deposition (PECVD), with a deposition thickness of 50-300 nm.

[0115] S125. The passivation layer is etched using BOE etching solution to form an n-electrode window, and an n-electrode of Ti / Al / Ti / Au material is prepared in the n-electrode window by electron beam evaporation to form the first LED epitaxial structure; wherein the n-electrode is in contact with the n-GaN layer.

[0116] S126. Anneal the first LED epitaxial structure to obtain the second LED epitaxial structure.

[0117] S127. The passivation layer in the second LED epitaxial structure is etched to form a p-electrode window, and a p-electrode is prepared in the p-electrode window to obtain the third LED epitaxial structure; wherein the p-electrode is in contact with the transparent conductive layer.

[0118] S128. The third LED epitaxial structure is bonded to the driving substrate to obtain the fourth LED epitaxial structure.

[0119] S129. Thinning or peeling off the fourth LED epitaxial structure to obtain an LED epitaxial wafer.

[0120] Preferably, the above steps further include the step of depositing a sidewall metal reflective layer after depositing the passivation layer. The material of the sidewall metal reflective layer can be a metal material such as Au, Al or Ag. The sidewall metal reflective layer is disposed outside the stress relief layer, quantum well layer, electron blocking layer and p-GaN layer side passivation layer. The sidewall metal reflective layer is used to reflect the light from the sidewall back. It works in conjunction with the multifaceted microcone pattern layer to allow more light to be emitted from the surface, thereby better improving the surface light emission efficiency and surface light emission ratio of the micro light-emitting diode.

[0121] In some embodiments, the substrate structure includes a heterogeneous substrate (such as sapphire) and a u-GaN layer stacked together. Thinning or peeling the fourth LED epitaxial structure to obtain an LED epitaxial wafer includes: peeling off the heterogeneous substrate to obtain an LED epitaxial wafer, wherein the GaN semiconductor layer is a u-GaN layer; or peeling off the heterogeneous substrate and the u-GaN layer to obtain an LED epitaxial wafer, wherein the GaN semiconductor layer is an n-GaN layer.

[0122] In other embodiments, the substrate structure is a u-GaN layer. Thinning or peeling the fourth LED epitaxial structure to obtain an LED epitaxial wafer includes: thinning the u-GaN layer to obtain an LED epitaxial wafer, wherein the GaN semiconductor layer is a thinned homogeneous substrate; or, thinning the u-GaN layer and the n-GaN layer to obtain an LED epitaxial wafer, wherein the GaN semiconductor layer is a thinned n-GaN layer.

[0123] The substrate structure includes a u-GaN layer, and the first epitaxial wafer includes a stacked substrate structure, an n-GaN layer, a stress relief layer, a quantum well layer, an electron blocking layer, and a p-GaN layer. For heterogeneous growth, laser lift-off of the sapphire substrate is required; for homogeneous growth, the u-GaN layer needs to be thinned. After substrate processing, if the u-GaN layer remains on the LED epitaxial wafer, a dense multifaceted microcone pattern layer is subsequently etched onto the u-GaN layer; if the u-GaN layer is completely removed, a dense multifaceted microcone pattern layer is subsequently etched onto the n-GaN layer. The final LED epitaxial wafer sequentially includes a GaN semiconductor layer, a stress relief layer, a quantum well layer, an electron blocking layer, and a p-GaN layer, where the GaN semiconductor layer is either a thinned u-GaN layer or an n-GaN layer.

[0124] S2. Anneal the N-side of the GaN semiconductor layer to convert GaN on the surface of the GaN semiconductor layer into GaO, thus obtaining a GaN-GaO semiconductor layer.

[0125] S3. Etch the N-side of the GaN-GaO semiconductor layer to obtain a multi-faceted microcone pattern layer.

[0126] Photoresist is coated onto the N-side of a GaN-GaO semiconductor layer and baked, followed by etching to obtain a multifaceted microcone pattern layer.

[0127] By etching a multifaceted microcone pattern layer with a special structure onto the N-side of a GaN-GaO semiconductor layer, the surface light extraction efficiency and the surface light emission ratio can be increased.

[0128] Furthermore, the multifaceted microcone pattern layer comprises a plurality of regularly arranged multifaceted microcones, with the bottom edges of adjacent multifaceted microcones adhering to each other, i.e., closely arranged; the base-to-height ratio of the multifaceted microcones is (1-2.5):1. Preferably, the base-to-height ratio of the multifaceted microcones is 1:1, 4:3, 5:3, or 5:2; more preferably, the base-to-height ratio of the multifaceted microcones is 4:3. Figure 6 As shown, the surface light extraction efficiency first increases and then decreases as the bottom-to-height ratio increases. Within this range, the bottom-to-height ratio can achieve better surface light extraction efficiency and is more conducive to the preparation of actual products. Too large or too small a bottom-to-height ratio will increase the difficulty of the preparation process.

[0129] Furthermore, the multifaceted microcone can be a three-sided, six-sided, or twelve-sided microcone. When the multifaceted microcone is a three-sided or six-sided microcone, the bottom edges of the multifaceted microcone are completely fitted together without gaps. When the multifaceted microcone is a twelve-sided microcone, some of the bottom edges of the multifaceted microcone are completely fitted together without gaps. Although the bottoms of multiple twelve-sided microcones are closely arranged, there will be a triangular gap in the middle of every three twelve-sided microcones that are closely arranged.

[0130] Furthermore, the bottom surface dimension of the multifaceted microcone is 100-1000 nm, preferably 200-1000 nm. When the multifaceted microcone is a three-sided microcone, the height of the bottom triangle is 100-1000 nm; when the multifaceted microcone is a six-sided or twelve-sided microcone, the distance between the bottom surface and the edge is 100-1000 nm.

[0131] Preferably, the etching method is selected from wet etching, photolithography and dry etching, and laser direct writing lithography.

[0132] Specifically, when the etching method is wet etching, it includes the following steps:

[0133] S31, Cleaning

[0134] The GaN semiconductor layer was ultrasonically cleaned sequentially in acetone, alcohol, and deionized water for 3-20 minutes to remove surface organic contaminants. The purpose of cleaning was to allow the N-side of the GaN semiconductor layer to better contact the etching solution.

[0135] S32, Remove surface liquid residue

[0136] At room temperature, use a nitrogen gun to dry the N-side of the GaN semiconductor layer with N2 for 3-30 minutes; or use an N2 oven to dry the GaN semiconductor layer for 3-15 minutes at a temperature of 40-80℃.

[0137] S33, Annealing

[0138] Rapid annealing of the N-side of the GaN semiconductor layer transforms the GaN compound on the surface into a more easily etchable GaO compound, forming a GaN-GaO semiconductor layer and enhancing the etching effect of the solution. The annealing process conditions include: a temperature of 400-600℃, an oxygen atmosphere, and a processing time of 5-20 minutes.

[0139] S34, Wet corrosion

[0140] In one embodiment, a wet etching process is performed on the N-side of the GaN-GaO semiconductor layer, as follows:

[0141] Under conditions of 80-120℃ (e.g., 80℃, 85℃, 90℃, 95℃, 100℃, 105℃, 110℃, 115℃ or 120℃), the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-40 min (e.g., 10 min, 15 min, 20 min, 25 min, 30 min, 35 min or 40 min) to obtain closely packed six-sided microcone mirrors on the N-side of the GaN-GaO semiconductor layer, where each of the six faces of the six-sided microcone mirror is a {10-11} crystal plane.

[0142] Further, the corrosive solution is a mixture of ammonia, H2O2, and H2O, with a volume ratio of ammonia:H2O2:H2O = 1:(0.5-1.5):(4-6), for example: 1:0.5:4, 1:1:4, 1:1.5:4, 1:0.5:5, 1:1:5, 1:1.5:5, 1:0.5:6, 1:1:6, or 1:1.5:6; preferably, the volume ratio of substances in the corrosive solution is ammonia:H2O2:H2O = 1:1:5, wherein the ammonia is a 25% by mass aqueous solution, and the concentration of the H2O2 solution is 30%.

[0143] In another embodiment, the N-side of the GaN-GaO semiconductor layer is subjected to a wet etching process, as follows:

[0144] Under conditions of 80-120℃ (e.g., 80℃, 85℃, 90℃, 95℃, 100℃, 105℃, 110℃, 115℃ or 120℃), the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-30 min (e.g., 10 min, 13 min, 15 min, 17 min, 20 min, 23 min, 25 min, 27 min or 30 min) to obtain closely packed six-sided microcone mirrors on the N-side of the GaN-GaO semiconductor layer, where each of the six faces of the six-sided microcone mirror is a {10-1-1} crystal plane.

[0145] Further, the corrosive solution is a mixture of KOH solution and water, with a volume ratio of KOH solution:H2O = 1:4-6, for example: 1:4, 1:4.2, 1:4.4, 1:4.6, 1:4.8, 1:5, 1:5.2, 1:5.4, 1:5.6, 1:5.8, or 1:6; preferably, the volume ratio of substances in the corrosive solution is KOH solution:H2O = 1:5. The KOH solution is a 0.01 mol / L solution.

[0146] In other embodiments, the N-side of the GaN-GaO semiconductor layer is subjected to a wet etching process, as detailed below:

[0147] Under conditions of 80-120℃ (e.g., 80℃, 85℃, 90℃, 95℃, 100℃, 105℃, 110℃, 115℃ or 120℃), the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-40 min (e.g., 10 min, 15 min, 20 min, 25 min, 30 min, 35 min or 40 min) to obtain closely packed dodecahedral microcones on the N-side of the GaN-GaO semiconductor layer. Six faces of each dodecahedral microcone are {20-2-3} crystal planes, and the remaining six faces are {22-4-5} crystal planes, and the two are alternately distributed.

[0148] Further, the corrosive solution is an H3PO4 solution. Alternatively, the corrosive solution is a mixture of H3PO4 solution and water, with a volume ratio of H3PO4 solution:H2O = 1:(16-128), for example: 1:16, 1:26, 1:32, 1:36, 1:46, 1:56, 1:64, 1:66, 1:76, 1:86, 1:96, 1:106, 1:116, 1:122, or 1:128; preferably, the volume ratio of substances in the corrosive solution is H3PO4 solution:H2O = 1:16, 1:32, 1:64, or 1:128, wherein the H3PO4 solution is a 0.2 mol / L solution.

[0149] After etching, organic cleaning is performed to remove the photoresist, resulting in a miniature light-emitting diode with a multifaceted microcone mirror pattern layer. The size of the miniature light-emitting diode includes, but is not limited to, 10 μm, and can range from 100 μm to infinitely small.

[0150] The micro-light-emitting diode (LED) fabricated by the above method sequentially comprises a multifaceted microcone pattern layer, an epitaxial layer, electrodes, and a driving substrate, effectively improving the surface light extraction efficiency and surface light emission ratio of the micro-LED. The epitaxial layer sequentially comprises a GaN-GaO semiconductor layer (n-GaN layer or a stacked u-GaN layer and n-GaN layer), a stress relief layer, a quantum well layer, an electron blocking layer, and a p-GaN layer. The multifaceted microcone pattern layer is disposed on the GaN-GaO semiconductor layer. The p-GaN layer has a p-electrode extending towards the driving substrate, and the semiconductor layer has an n-electrode extending towards the driving substrate. The driving substrate has solder joints corresponding to the p-electrode and n-electrode, which are bonded to the solder joints by solder. A passivation layer is present on the bottom surface of the GaN-GaO semiconductor layer and on the sides of the stress relief layer, quantum well layer, electron blocking layer, and p-GaN layer.

[0151] The above etching steps require control of the solution ratio, water bath temperature, and time based on the desired multifaceted microcone mirror pattern layer structure. When other methods such as dry etching are used, the corresponding shape is prepared by bombarding the GaN surface with Cl2 or other gases, and the etching gas ratio, flow rate, and time are adjusted as needed for control.

[0152] Example 1

[0153] In this embodiment, the etching method for the micro LED is wet etching, which includes the following steps:

[0154] S31, Cleaning

[0155] The GaN semiconductor layer was sequentially ultrasonically cleaned in acetone, alcohol, and deionized water for 20 minutes to remove surface organic contaminants. The purpose of cleaning was to allow the N-side of the GaN semiconductor layer to better contact the etching solution.

[0156] S32, Remove surface liquid residue

[0157] The N-side of the GaN semiconductor layer was dried using a nitrogen gun at room temperature for 30 minutes.

[0158] S33, Annealing

[0159] Rapid annealing of the N-side of the GaN semiconductor layer transforms the GaN compound on the surface into a more easily etchable GaO compound, forming a GaN-GaO semiconductor layer and enhancing the etching effect of the solution. The annealing process conditions include: a temperature of 500℃, an oxygen atmosphere, and a processing time of 20 minutes.

[0160] S34, Wet corrosion

[0161] At 100℃, a GaN-GaO semiconductor layer was placed in an etching solution and heated for 30 minutes to obtain closely packed hexagonal microcones on the N-face of the GaN-GaO semiconductor layer. All six faces of each hexagonal microcone belong to the same crystal plane family {10-11}S crystal planes. The bottom edges of the multiple hexagonal microcones were completely bonded together without gaps.

[0162] The corrosive solution is a mixture of ammonia, H2O2, and H2O, with a volume ratio of ammonia:H2O2:H2O = 1:1:5. The ammonia solution is a 25% (by mass) aqueous solution, and the H2O2 solution has a concentration of 30%.

[0163] Example 2

[0164] The wet etching method in this embodiment differs from that in Embodiment 1 in that steps S32 and S34 are different.

[0165] In this embodiment, step S32 uses an N2 oven to dry the entire sheet for 10 minutes at a temperature of 60°C.

[0166] In this embodiment, the wet etching step S34 is specifically as follows:

[0167] At 100℃, a GaN-GaO semiconductor layer was placed in an etching solution and heated for 30 minutes to obtain closely packed hexagonal microcones on the N-face of the GaN-GaO semiconductor layer. Each hexagonal microcone has six {10-1-1} crystal faces. The bottom edges of the multiple hexagonal microcones are completely bonded together without gaps.

[0168] The corrosive solution is a mixture of KOH solution and water, with a volume ratio of KOH solution to H2O of 1:5, where the KOH solution has a concentration of 0.01 mol / L.

[0169] Example 3

[0170] The wet etching method in this embodiment differs from that in Embodiment 1 in step S34. The specific steps of the wet etching method in step S34 of this embodiment are as follows:

[0171] At 100℃, a GaN-GaO semiconductor layer was placed in an etching solution and heated for 30 minutes to obtain closely packed dodecahedral microcone mirrors on the N-face of the GaN-GaO semiconductor layer. Six faces of each dodecahedral microcone mirror are {20-2-3} crystal planes, and the remaining six faces are {22-4-5} crystal planes, with the two types alternating. The bottoms of the multiple dodecahedral microcone mirrors are closely packed together, with some bottom edges completely adhered without gaps.

[0172] The corrosive solution is a mixture of H3PO4 solution and water, with a volume ratio of H3PO4 solution to H2O of 1:16, wherein the H3PO4 solution has a concentration of 0.2 mol / L.

[0173] Example 4

[0174] like Figure 1-2 As shown, the fabrication method of the miniature light-emitting diode in this embodiment specifically includes the following steps:

[0175] S1. Preparation of LED epitaxial wafers

[0176] The substrate structure is a u-GaN layer, and the fabrication of the LED epitaxial wafer includes:

[0177] S11. A first epitaxial wafer is grown on the substrate structure using a metal-organic chemical vapor deposition method. The first epitaxial wafer comprises, from bottom to top: a u-GaN layer, an n-GaN layer, a stress relief layer, a quantum well layer, an electron blocking layer, and a p-GaN layer.

[0178] S12. The first epitaxial wafer is processed to obtain an LED epitaxial wafer, i.e., the first epitaxial wafer is used to fabricate a Micro-LED flip chip. This process includes, in sequence, LED epitaxial wafer cleaning, ITO thin film deposition, mesa etching, passivation layer 11 deposition, n-electrode 14 fabrication, rapid annealing (high-temperature annealing to form ohmic contacts), p-electrode 19 fabrication, thermo-bonding with the driving substrate 13, and substrate structure processing. Details are as follows:

[0179] S121. Clean the first epitaxial wafer.

[0180] S122. A transparent conductive layer, such as ITO, is prepared on the p-GaN layer to obtain a second epitaxial wafer; wherein the second epitaxial wafer includes a substrate structure, an n-GaN layer 10, a stress relief layer, a quantum well layer, an electron blocking layer, a p-GaN layer, and a transparent conductive layer stacked together.

[0181] S123. Etch from the transparent conductive layer until the n-GaN layer 10 is exposed to obtain multiple mesa structures.

[0182] S124. A passivation layer 11 with SiO2 material is deposited on the sidewalls of the mesa structure, the upper surface of the mesa structure, and between two adjacent mesa structures using PEC VD, with a deposition thickness of 200 nm.

[0183] S125. The passivation layer 11 is etched using BOE etching solution to form an n-electrode 14 window, and an n-electrode 14 of Ti / Al / Ti / Au material is prepared in the n-electrode 14 window by electron beam evaporation to form the first LED epitaxial structure; wherein, the n-electrode 14 is in contact with the n-GaN layer 10.

[0184] S126. Anneal the first LED epitaxial structure to obtain the second LED epitaxial structure.

[0185] S127. The passivation layer 11 in the second LED epitaxial structure is etched to form a p-electrode window, and a p-electrode 19 is prepared in the p-electrode window to obtain the third LED epitaxial structure; wherein the p-electrode 19 is in contact with the transparent conductive layer.

[0186] S128. The third LED epitaxial structure is bonded to the driving substrate 13 to obtain the fourth LED epitaxial structure.

[0187] S129. Thin the u-GaN layer of the fourth LED epitaxial structure to obtain the LED epitaxial wafer.

[0188] S2. Anneal the N-side of the GaN semiconductor layer to convert GaN on the surface of the GaN semiconductor layer into GaO, thus obtaining a GaN-GaO semiconductor layer.

[0189] S3. Photoresist is coated onto the N-side of the GaN-GaO semiconductor layer and etched to obtain a multi-faceted microcone pattern layer 17.

[0190] After etching, organic cleaning is performed to remove the photoresist, resulting in a miniature light-emitting diode with a multifaceted microcone mirror pattern layer 17.

[0191] Understandably, the semiconductor layer on top of the chip is etched according to the etching steps in the above embodiments to obtain a dense multifaceted microcone pattern layer 17, that is, multiple multifaceted microcones are closely arranged, which will not be described in detail here.

[0192] like Figure 2 As shown, the micro light-emitting diode prepared by the above method includes a multifaceted microcone mirror pattern layer 17, an epitaxial layer, an electrode, and a driving substrate 13 in sequence, which can effectively improve the surface light extraction efficiency of the micro light-emitting diode.

[0193] Further, the epitaxial layer sequentially includes an n-GaN layer 10 and a main structure 12 (including a stacked stress relief layer, a quantum well layer, an electron blocking layer, and a p-GaN layer). A multifaceted microcone pattern layer 17 is disposed on the u-GaN layer. The p-GaN layer has a p electrode 19 extending toward the driving substrate 13. The semiconductor layer has an n electrode 14 extending toward the driving substrate 13. The driving substrate 13 has solder joints 16 corresponding to the p electrode 19 and the n electrode 14. The p electrode 19 and the n electrode 14 are bonded to the corresponding solder joints 16 by solder 15. The bottom surface of the u-GaN layer and the sides of the n-GaN layer 10, the stress relief layer, the quantum well layer, the electron blocking layer, and the p-GaN layer have passivation layers 11.

[0194] Example 5

[0195] like Figure 3 As shown, the fabrication method of the micro-LED in this embodiment differs from that in embodiment 4 in that, in this embodiment, between the deposition of the passivation layer 11 (step S124) and the fabrication of the n-electrode 14 (step S125), there is an additional step of depositing a metal reflective layer on the sidewall of the Micro-LED to form a sidewall metal reflective layer 18 on the outside of the passivation layer 11 on the sidewalls of the stress relief layer, quantum well layer, electron blocking layer and p-GaN layer. The other steps are basically the same as in embodiment 4 and will not be described again here.

[0196] The sidewall metal reflective layer 18 is made of Au. The sidewall metal reflective layer 18 can reflect the light emitted from the original sidewall back, allowing more light to be emitted from the surface, which can better improve the surface light emission efficiency of the micro light-emitting diode.

[0197] Tests and Results

[0198] According to the aforementioned Example 1, after wet chemical etching, the N-side of the GaN-GaO semiconductor layer will exhibit the following characteristics: Figure 4-5 The dense hexagonal microcone pattern layer shown is where T is the distance between the bottom face and the edge of the hexagonal microcone, and H is the height of the hexagonal microcone. Different sizes of structures can be achieved by adjusting the solution ratio, water bath temperature, and time.

[0199] (1) Base-to-height ratio

[0200] Figure 6 LSE plots of a six-sided microconical mirror structure for a 10μm miniature light-emitting diode at different bottom:height ratios. Figure 6 The results show that the LSE with the addition of the hexagonal microcone structure is more than twice that of the LSE without the surface microcone structure (6.5%). When the bottom:height = 4:3, the best LSE result of 15.5% can be achieved, which is 2.38 times that of the LSE without the surface microcone structure.

[0201] (2) Microcone structures with different numbers of facets

[0202] According to the aforementioned Examples 1 to 3, microcone structures with different numbers of facets are formed on the semiconductor layer. Figure 7 The LSE, which is a GaN-GaO semiconductor layer of a 10μm micro-light-emitting diode, has three-sided, six-sided, and twelve-sided micro-cone mirror structures corresponding to the N-side of the micro-cone mirror. The bottom-to-height ratio of the multi-sided micro-cone mirror is 4:3. Figure 7 The results show that the three-sided / six-sided / twelve-sided microconical mirror structures have different enhancement effects on LSE, among which the six-sided pyramidal mirror structure can achieve the best enhancement effect.

[0203] (3) Base dimensions of the microcone

[0204] Taking a six-sided microcone mirror structure as an example, Figure 8 The graph shows the surface light extraction efficiency (LSE) and surface light extraction ratio (S) of a six-sided microcone patterned layer for a 10μm micro LED with different microcone base dimensions T (100-1200nm). Figure 8 The results show that the 100nm structure has no positive effect on LSE, while the LSE increases with the increase of the micro-nano structure in the 200-600nm range. The 600-800nm ​​structure remains relatively stable with slight fluctuations. The 1000nm structure achieves the best LSE and S effect, at which S can reach 47%, which is 2.14 times that of the structure without microcone mirror (S=22%), showing a significant improvement.

[0205] (4) Photoluminescence spectrum

[0206] Figure 9 The micro-area photoluminescence spectrum of a homogeneous 10μm micro-LED before and after wet etching is shown. The horizontal axis represents wavelength, and the vertical axis represents luminous intensity. To reduce error, multiple tests were conducted, and the average value of the luminous intensity was taken. Figure 9 This indicates that the luminous intensity of the micro LED with the six-sided microcone mirror structure is significantly improved, reaching 146.08% of that without the six-sided microcone mirror structure. The optimization effect is quite obvious, and the overall spectral width is widened, but the full width at half maximum (FWHM) remains unchanged.

[0207] The concepts and goals of surface light extraction efficiency and overall light extraction efficiency differ significantly. The method for fabricating a micro-LED with high surface light extraction efficiency according to this invention improves the surface light extraction efficiency and surface light extraction ratio of flip-chip Micro-LED devices through a densely packed micro / nano-structured multifaceted microcone mirror pattern layer. This method is applicable to micron-scale Micro-LEDs and is not limited by substrate type; all LED epitaxial wafer structures are suitable, including but not limited to homogeneous (GaN) and heterogeneous (sapphire, Si, etc.) substrates. Homogeneous substrates undergo thinning, while heterogeneous substrates undergo stripping. Furthermore, in the above embodiments, the multifaceted microcone mirror pattern layer is formed after etching on the semiconductor. In other embodiments, dielectric films such as ZnO, SiO2, and Al2O3 can be formed on the semiconductor layer through methods such as evaporation and deposition, and then the multifaceted microcone mirror pattern layer is formed on the dielectric film using the aforementioned etching method.

[0208] The method for fabricating a micro-light-emitting diode (LED) of the present invention can be used to improve the surface light extraction efficiency and surface light emission ratio of micro-LEDs, thus solving the problem of low surface light extraction efficiency of Micro-LEDs. By utilizing a layer of densely packed multifaceted microcone mirror patterns on the top of the micro-LED, the surface light extraction efficiency of the micro-LED can be improved, and the effect of different structures and sizes of multifaceted microcone mirror patterns on improving the surface light extraction efficiency and surface light emission ratio varies.

[0209] The above embodiments are only for illustrating the technical concept and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

[0210] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

Claims

1. A method for fabricating a miniature light-emitting diode, characterized in that, The preparation method includes the following steps: An LED epitaxial wafer is provided; wherein the LED epitaxial wafer includes a GaN semiconductor layer, a quantum well layer and a p-GaN layer stacked together; The N-side of the GaN semiconductor layer is annealed to convert GaN on the surface of the GaN semiconductor layer into GaO, thus obtaining a GaN-GaO semiconductor layer. The N-side of the GaN-GaO semiconductor layer is etched to obtain a multifaceted microcone mirror pattern layer. The etching method is wet etching, and the steps of the wet etching are as follows: Under a temperature of 80-120℃, the GaN-GaO semiconductor layer is placed in an etching solution and heated for 10-30 minutes to obtain closely arranged six-sided microcone mirrors on the N-side of the GaN-GaO semiconductor layer. Each of the six sides of the six-sided microcone mirror is a {10-1-1} crystal plane.

2. The preparation method according to claim 1, characterized in that, The corrosive solution is a mixture of KOH solution and water, with a volume ratio of KOH solution:H2O = 1:4-6.

3. The preparation method according to claim 1, characterized in that, The multifaceted microcone pattern layer includes multiple multifaceted microcones arranged in a regular pattern, with the bottom edges of adjacent multifaceted microcones fitting together.

4. The preparation method according to claim 1, characterized in that, The bottom-to-height ratio of the multifaceted microcone is (1-2.5):1; the bottom dimension of the multifaceted microcone is 100-1000nm.

5. The preparation method according to claim 1, characterized in that, The GaN semiconductor layer includes an n-GaN layer, and the multifaceted microcone pattern layer is disposed on the n-GaN layer; or, the GaN semiconductor layer includes a u-GaN layer and an n-GaN layer, and the multifaceted microcone pattern layer is disposed on the u-GaN layer.

6. The preparation method according to claim 1, characterized in that, The annealing process conditions include: a temperature of 400-600℃, an oxygen atmosphere, or a treatment time of 5-20 minutes; and / or, The steps also include pretreatment prior to annealing: The GaN semiconductor layer is cleaned; The N-side of the GaN semiconductor layer is dried using nitrogen gas at room temperature for 3-30 minutes; or the GaN semiconductor layer is dried using a nitrogen oven, wherein the drying process conditions include a drying time of 3-15 minutes or a drying temperature of 40-80°C.

7. The preparation method according to claim 1, characterized in that, The fabrication of the LED epitaxial wafer includes: A substrate structure is provided, and an n-GaN layer, a stress relief layer, the quantum well layer, an electron blocking layer, and the p-GaN layer are sequentially fabricated on the substrate structure to obtain a first epitaxial wafer; The first epitaxial wafer is processed to obtain the LED epitaxial wafer; Before the step of etching the N-side of the GaN semiconductor layer, the following steps are included: Photoresist is coated onto the surface of the LED epitaxial wafer and then baked. After the step of etching the N-side of the GaN semiconductor layer, the following steps are included: The photoresist is removed to obtain the micro light-emitting diode.

8. The preparation method according to claim 7, characterized in that, The process of processing the first epitaxial wafer to obtain the LED epitaxial wafer includes: The first epitaxial wafer is cleaned; A transparent conductive layer is fabricated on the p-GaN layer to obtain a second epitaxial wafer; wherein, the second epitaxial wafer includes the substrate structure, the n-GaN layer, the stress relief layer, the quantum well layer, the electron blocking layer, the p-GaN layer and the transparent conductive layer stacked together; Etching begins from the transparent conductive layer until the n-GaN layer is exposed, resulting in multiple mesa structures; A passivation layer is deposited on the sidewalls of the platform structure, the upper surface of the platform structure, and between two adjacent platforms. The passivation layer is etched to form an n-electrode window, and an n-electrode is fabricated within the n-electrode window to form a first LED epitaxial structure; wherein the n-electrode is in contact with the n-GaN layer; The first LED epitaxial structure is annealed to obtain the second LED epitaxial structure. The passivation layer in the second LED epitaxial structure is etched to form a p-electrode window, and a p-electrode is fabricated within the p-electrode window to obtain a third LED epitaxial structure; wherein the p-electrode is in contact with the transparent conductive layer; The third LED epitaxial structure is bonded to the driving substrate to obtain the fourth LED epitaxial structure; The fourth LED epitaxial structure is thinned or peeled off to obtain the LED epitaxial wafer.

9. The preparation method according to claim 8, characterized in that, The step of processing the first epitaxial wafer to obtain the LED epitaxial wafer also includes the step of depositing a sidewall metal reflective layer after depositing the passivation layer. The sidewall metal reflective layer is disposed outside the stress relief layer, quantum well layer, electron blocking layer and p-GaN layer side passivation layer, and is used to reflect the light emitted from the original sidewall back, so that more light can be emitted from the surface.

10. The preparation method according to claim 8, characterized in that, The substrate structure includes a heterogeneous substrate and a u-GaN layer stacked together. Thinning or peeling the fourth LED epitaxial structure to obtain the LED epitaxial wafer includes: peeling off the heterogeneous substrate to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the u-GaN layer; or, peeling off the heterogeneous substrate and the u-GaN layer to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the n-GaN layer. Alternatively, the substrate structure is a u-GaN layer, and the process of thinning or peeling off the fourth LED epitaxial structure to obtain the LED epitaxial wafer includes: thinning the u-GaN layer to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the thinned u-GaN layer; or, thinning the u-GaN layer and the n-GaN layer to obtain the LED epitaxial wafer, wherein the GaN semiconductor layer is the thinned n-GaN layer.

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