Storing contiguous display content in each DRAM for idle static screen savings

Abstract

An apparatus and method for efficiently managing power consumption among a plurality of replicated function blocks of an integrated circuit. An integrated circuit includes a plurality of replica memories using independent power domains. Data of a given type is stored in the plurality of memories in an interleaved manner. When the control circuit detects an idle state, a command is sent to the plurality of memories specifying that the given type of data is stored in the memories connected to the plurality of functional blocks in a contiguous manner. The control circuit then transitions all of the memories other than one of the memories to a sleep state. The memories alternate among themselves with a single memory in an active state and services the requests based on the data of the given type for which the requests are directed.

Description

Background Technology

[0001] Description of related technologies

[0002] Both planar transistors (devices) and non-planar transistors are manufactured for use in integrated circuits within semiconductor chips. There are various options for integrating multiple types of integrated circuits into a system-on-a-package (SoC). Some examples are system-on-chip (SOC), multi-chip module (MCM), and system-in-package (SiP). Mobile devices, desktop systems, and servers use these packages. Regardless of the choice of system package, in several applications, the power consumption of modern integrated circuits has become an increasingly important design issue with each generation of semiconductor chips.

[0003] As power consumption increases, more expensive cooling systems, such as larger fans and heatsinks, are used to remove excess heat and prevent integrated circuit failure. However, cooling systems increase system costs. Power dissipation constraints of integrated circuits are not only a problem for portable computers and mobile communication devices, but also for high-performance desktop and server computers. Power management circuitry assigns operating parameters to different sections of the integrated circuit. These operating parameters include at least the operating supply voltage and the operating clock frequency.

[0004] While a partition may not have any computational tasks to perform during specific periods when the application is running, the power management circuitry cannot assign a sleep state to the partition due to occasional maintenance tasks for it. Modern integrated circuits include multiple replicated function blocks within a partition to increase throughput. Each function block includes one or more sub-blocks for data processing, one or more levels of caches, and an interface for communicating with local memory. In one example, when the integrated circuit is executing a video graphics application, a partition comprising multiple function blocks responsible for rendering video frame data has no additional computational tasks to perform when not updating the image presented on the display device. The image remains unchanged during application pauses, during user input wait times, or other situations where the application is still running but image updates are not required. However, the power management circuitry cannot assign sleep states to multiple function blocks due to periodic refresh operations that request data retrieval from multiple function blocks and send it to the display device.

[0005] In view of the above, there is a need for methods and mechanisms to effectively manage the power consumption of multiple replicated functional blocks of an integrated circuit. Attached Figure Description

[0006] Figure 1 It is a general block diagram of an integrated circuit that manages power consumption in a copy memory.

[0007] Figure 2 It is a general block diagram of an integrated circuit that manages power consumption in a copy memory.

[0008] Figure 3 It is a general block diagram of an integrated circuit that manages power consumption in a copy memory.

[0009] Figure 4 It is a general block diagram of an integrated circuit that manages power consumption in a copy memory.

[0010] Figure 5 It is a general block diagram of an integrated circuit that manages power consumption in a copy memory.

[0011] Figure 6 It is a general block diagram of a power manager that manages power consumption in the replicated memory of an integrated circuit.

[0012] Figure 7 This is a diagram summarizing a method for effectively managing power consumption in the replicated memory of an integrated circuit.

[0013] Figure 8 This is a diagram summarizing a method for effectively managing power consumption in the replicated memory of an integrated circuit.

[0014] While the invention may have various modifications and alternatives, specific embodiments are shown by way of example in the accompanying drawings and are described in detail herein. However, it should be understood that the drawings and the detailed description thereof are not intended to limit the invention to the specific forms disclosed, but rather, the invention covers all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims. Detailed Implementation

[0015] In the following description, numerous specific details are set forth to provide a thorough understanding of the invention. However, those skilled in the art will recognize that the invention can be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the invention. Furthermore, it should be understood that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are enlarged relative to other elements.

[0016] Apparatus and methods for effectively managing power consumption in multiple replicated memories of an integrated circuit are anticipated. In various embodiments, the integrated circuit includes multiple replicated memories using independent power domains. The multiple memories store data of a given type in an interleaved manner. In one embodiment, the given type of data is video frame data in a frame buffer that has already been rendered by multiple functional blocks of the integrated circuit. A system idle state indicates a static screen of a display device connected to a display controller, and the only memory access being performed is a memory access for refreshing content displayed on the display device. When the control circuit detects a system idle state, the control circuit sends commands to the multiple memories specifying that the given type of data be stored sequentially in these memories connected to the multiple functional blocks. Subsequently, the control circuit puts one or more memories into a sleep state. In one embodiment, the control circuit puts all memories except one of these memories into a sleep state.

[0017] In one implementation, a sleep state is a component idle state with the lowest available voltage value among one or more component idle states. The corresponding memory in the sleep state has reduced power consumption, but retains sufficient configuration information (or context information) to return to the active state without restarting the operating system. In another implementation, a sleep state is a component idle state with a voltage value lower than the voltage value provided by the active state but higher than the lowest available voltage value among one or more component idle states. In some implementations, in the sleep state, the control circuitry additionally shuts off the power reference level to the corresponding memory interface used by the memory. For example, the control circuitry sends a control signal to the power switch to disconnect the power reference level used by the corresponding memory interface from the physical voltage plane. The function block uses the currently active memory and the request being targeted to process a request for data of a given type.

[0018] Turn now Figure 1This diagram illustrates a general block diagram of an integrated circuit 100 that manages power consumption across multiple memories. In the illustrated embodiment, the integrated circuit 100 includes a system-on-chip (SoC) 110, which includes multiple memory interfaces 112, 122, 132, and 142 connected to multiple memories 114, 124, 134, and 144. Furthermore, in some embodiments, the SoC 110 includes a cache 150; however, in other embodiments, no cache is provided. In various embodiments, each of the memories 114, 124, 134, and 144 is a type of DRAM among various types of dynamic random access memory (DRAM). Although not shown for ease of illustration, the SoC 110 includes one or more functional blocks and sub-blocks that provide various functionalities and generate memory access requests for contents stored in the memories 114, 124, 134, and 144. As used herein, a "functional block" is also referred to as an "intellectual property block" (or IP block). One or more function blocks in a function block can also generate requests for another function block and can serve requests from another function block.

[0019] One or more functional blocks are fabricated on a larger semiconductor die, such as a system-on-a-chip (SoC) 110. Examples of functional blocks are central processing units (CPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), multimedia engines, and processing units with highly parallel microarchitectures, such as graphics processing units (GPUs) and digital signal processors (DSPs). It is also possible and anticipated that the SoC 110 may include one or more functional blocks from a variety of other types. Due to the limited on-die area of ​​the SoC 110, the size of the cache 150 of the SoC 110 is limited, whether the SoC includes a single functional block or multiple functional blocks. Therefore, in one specific implementation, the integrated circuit 100 includes a microprocessor with a cache (such as cache 150) of finite size, and circuitry that executes firmware instructions, including instructions for algorithms managing power consumption within multiple memories 114, 124, 134, and 144.

[0020] Various computing devices utilize integrated circuit 100. Examples of these computing devices include desktop computers, laptop computers, server computers, tablet computers, smartphones, gaming devices, smartwatches, and so on. The following description describes the power management of multiple replicated memories 114, 124, 134, and 144 connected to SoC 110; however, the following description also applies to the power management of multiple replicated memory chiplets placed in a multi-chip module (MCM). In the case of using an MCM, one or more memory chiplets are connected to independent power rails and therefore have access to independent power domains. Similarly, in the case of integrated circuit 100, one or more of the memories 114, 124, 134, and 144 are connected to independent power rails and therefore have access to independent power domains.

[0021] Each of the multiple power domains includes at least operating parameters such as operating supply voltage and operating clock frequency. Each of the power domains also includes control signals for enabling and disabling connections to the clock generation circuitry and power reference. In various embodiments, each of the memories 114, 124, 134, and 144 utilizes an independent power rail and can be configured as an independent power domain. The functional blocks and sub-blocks of SoC 110 and the memories 114, 124, 134, and 144 utilize transistors. Additionally, as used herein, "transistor" is also referred to as a "semiconductor device" or "device." In addition to n-type metal-oxide-semiconductor (NMOS) FETs (or nFETs), transistors also include p-type metal-oxide-semiconductor (PMOS) field-effect transistors (or pFETs). In some embodiments, the devices (or transistors) in integrated circuit 100 are planar devices.

[0022] In other embodiments, the devices (or transistors) in integrated circuit 100 are non-planar devices. Examples of non-planar transistors include tri-gate transistors, fin field-effect transistors (FETs), and gate-all-around (GAA) transistors. In some embodiments, integrated circuit 100 includes one or more three-dimensional integrated circuits (3D ICs). A 3D IC includes two or more layers of active electronic components integrated vertically and / or horizontally into a single circuit. In one embodiment, interposer-based integration is used, thereby placing the 3D IC next to a central processing unit (CPU) that includes one or more general-purpose processor cores. Alternatively, the 3D IC is stacked directly on top of another IC.

[0023] As shown in the figure, each of the memories 114, 124, 134, and 144 stores a copy of one or more portions of data of a given type. Each of the memories 114, 124, 134, and 144 is a type of DRAM among various types of Dynamic Random Access Memory (DRAM). In one embodiment, the data of the given type is video frame data stored in a frame buffer implemented by memories 114, 124, 134, and 144. The portions of the data of the given type are shown as numbered boxes, where they are identified using numbers. In some embodiments, each portion of the data is a consecutive portion compared to a previous portion of a larger dataset (such as a video frame buffer), where the previous portion has a number that identifies it that is one less than the number identifying the current portion. For example, portion "2" is the next consecutive portion after portion "1". In one embodiment, each portion has the same size, such as the size of a page in DRAM or other sizes. In other embodiments, one or more portions have different sizes.

[0024] In the illustrated implementation, memory 114 stores copies of portions "1", "2", "3", and "4". Memory 124 stores copies of portions "5", "6", "7", and "8". Memory 134 stores copies of portions "9" through "12", and memory 144 stores copies of portions "13" through "16". In the implementation of SoC 110 utilizing cache 150, cache 150 is capable of storing copies of data stored in memories 114, 124, 134, and 144. However, the size of cache 150 is smaller than the size of a combination of portions of any of memories 114, 124, 134, and 144. For example, cache 150 cannot store portions "1" through "4" simultaneously. Similarly, cache 150 cannot store portions "5" through "8". The planar layout of SoC 110 cannot provide sufficient on-die area to provide a larger size for cache 150.

[0025] In one implementation, SoC 110 handles video graphics workloads, such as rendering video frame data (not shown) for a display device. The given type of data is video frame data that has been rendered and then stored in frame buffers in memories 114, 124, 134, and 144. This given type of data is sent from memories 114, 124, 134, and 144 and transmitted via SoC 110 to a display controller, and then to a display device. In some implementations, memories 114, 124, 134, and 144 store the given type of data contiguously, as shown in the illustrated implementation. Although storing data contiguously includes more access latency, this memory arrangement reduces the latency of the integrated circuit 100 transitioning to an idle state. Typically, data is stored in interleaved memories 114, 124, 134, and 144 to hide the overhead latency (penalty) of the memory devices used to implement memories 114, 124, 134, and 144. For example, opening a page in DRAM, storing the target page in the line buffer, accessing the line buffer, and closing the page each involve measurable latency or penalty. When new data of a given type is retrieved from the DMA engine or other units and sent to memories 114, 124, 134, and 144, the new data of that given type is now stored contiguously in memories 114, 124, 134, and 144, rather than interleaved.

[0026] In one embodiment, control circuitry 160 is part of power management circuitry (not shown), such as a power manager. Control circuitry 160 determines an idle state or assigns an idle state to integrated circuit 100, or receives an indication of an idle state. For example, a video graphics application ceases updating frame data to be viewed on a display device. The video graphics application may be paused or waiting for further user input, and during the waiting period, the scene or image on the display device is not updated. Therefore, although the video graphics application has not ceased execution, the video processing subsystem of the computing system utilizing memories 114, 124, 134, and 144 enters an idle state.

[0027] Due to the static allocation of data of a given type stored in a contiguous manner as shown in the figure, control circuitry 160 transitions one or more of memories 114, 124, 134, and 144 to a sleep state. In one embodiment, the sleep state is the minimum power consumption state without powering off. When memories 114, 124, 134, and 144 utilize DRAM, they are volatile memories. In some embodiments, the sleep state is a component idle state with the lowest available voltage value among one or more component idle states. The memories in 114, 124, 134, and 144 have reduced power consumption, but the memory still retains sufficient configuration information (or context information) to return to an active state without restarting the operating system.

[0028] In another implementation, a sleep state is a component idle state where the voltage value is lower than that provided by the active state but higher than the lowest available voltage value of any of the component idle states. In one implementation, in the sleep state, control circuitry 160 (or power manager or other circuitry) additionally shuts off the power reference level to one or more corresponding memory interfaces of memory interfaces 112, 122, 132, and 142. For example, control circuitry 160 (or power manager or other circuitry) sends a control signal to a power switch to disconnect the power reference level used by one or more corresponding memory interfaces of memory interfaces 112, 122, 132, and 142 from the physical voltage plane. The sleep state and one or more active states may be associated with one or more power performance states (P-states) indicating the corresponding power domain managed by the power management circuitry. The sleep state and one or more active states may be associated with one or more states of the Advanced Configuration and Power Interface (ACPI) standard. States of another standard are also possible and anticipated. Instead of putting memory 114 to sleep, control circuit 160 keeps memory 114 in one of a plurality of active states. In one embodiment, control circuit 160 puts each of memories 124, 134, and 144 to sleep.

[0029] During the idle state of the video subsystem, memory 114, which stores data of a given type (parts "1" to "4"), processes any generated requests for that given type of data. For example, even though no request is made to render new frame data, the display device of the computing system still performs a refresh operation. In this case, the data of the given type (parts "1" to "4") is a subset of the entire rendering data (parts "1" to "16") of the last frame to be processed before transitioning to the idle state that indicates the static screen of the display device.

[0030] To perform a refresh operation, the display device requests data of a given type (parts "1" through "16") from memories 114, 124, 134, and 144. After accessing parts "1" through "4" from memory 114, control circuitry 160 transitions memory 124 from a sleep state to an active state and transitions memory 114 from an active state to a sleep state. Thus, one memory is active while the remaining memories are sleep. Similarly, after accessing parts "5" through "8" from memory 124, control circuitry 160 transitions memory 134 from a sleep state to an active state and transitions memory 124 from an active state to a sleep state.

[0031] Furthermore, after accessing portions "9" to "12" of memory 134, control circuit 160 transitions memory 144 from a sleep state to an active state, and transitions memory 134 from an active state to a sleep state. Continuing, after accessing portions "13" to "16" of memory 144, control circuit 160 transitions memory 114 from a sleep state to an active state, and transitions memory 144 from an active state to a sleep state. These steps are repeated during video refresh operations. Therefore, a single memory is active, while the remaining memories are in a sleep state. While still supporting refresh operations, integrated circuit 100 reduces power consumption by keeping a single memory in memories 114, 124, 134, and 144 active while keeping the remaining memories in memories 114, 124, 134, and 144 in a sleep state.

[0032] refer to Figure 2This diagram illustrates a general block diagram of an integrated circuit 200 that manages power consumption in the copy memory. The circuits and signals described previously are numbered identically. Here, each of the memories 114, 124, 134, and 144 stores corresponding copies of portions "1" to "16" in a sequential manner as previously described. Control circuit 160 determines when integrated circuit 200 exits an idle state. For example, the end of a video graphics workload indicates the idle state of the static screen of the display device and resumes rendering video frame data for the display device. Control circuit 160 assigns an active state to each of the memories 114, 124, 134, and 144 such that no memory in memories 114, 124, 134, and 144 remains in a sleep state. Furthermore, control circuit 160 ensures that no memory interface in memory interfaces 112, 122, 132, and 142 remains closed or disconnected from the corresponding power supply reference level. Instead, each memory interface in memory interfaces 112, 122, 132, and 142 is turned on and is active. When new data of a given type is retrieved from the DMA engine or other units and sent to integrated circuit 200, the new data of that type continues to be stored sequentially in memories 114, 124, 134, and 144. This reduces the latency of transitioning back to an idle state.

[0033] Turn now Figure 3 This diagram shows a general block diagram of an integrated circuit 300 that manages power consumption in a copy memory. The circuits and signal numbers described previously are the same. Here, each of the memories 114, 124, 134, and 144 stores corresponding copies of portions "1" through "16" in an interleaved manner. For example, a first portion (portion "1") of data of a given type is stored in the first memory (memory 114), and a second portion (portion "2") that is different from the first portion (portion "1") of data of the given type is stored in the second memory (memory 124). A third portion (portion "3") that is different from the first and second portions of data of the given type is stored in the third memory (memory 134), and so on. When the last memory (memory 144) of the plurality of memories has a portion (portion "4") of data of a given type stored therein, the next portion (portion "5") of data of the given type is stored in the first memory (memory 114). Data storage of data of a given type continues in this manner.

[0034] Memory arrays 114, 124, 134, and 144 store portions "1" through "16" in an interleaved manner to hide the overhead latency (penalty) of the memory devices used to implement the memories 114, 124, 134, and 144. For example, each of opening a page in DRAM, storing the target page in a line buffer, accessing the line buffer, and closing the page includes measurable latency or penalty. Control circuitry 160 determines an idle state or assigns an idle state to integrated circuit 300, or receives an indication of an idle state. For example, a video graphics application no longer updates frame data to be viewed on a display device. Control circuitry 160 changes the data storage arrangement from interleaved storage to sequential storage. Control circuitry 160 sends a command or indication of this change to one or more of the direct memory access (DMA) engine or circuit and memory interfaces 112, 122, 132, and 142.

[0035] In one embodiment, the next frame, including portions "17" through "32", is the last frame rendered before integrated circuit 300 enters an idle state. Due to a change initiated by control circuitry 160, memory interfaces 112, 122, 132, and 142 store these portions sequentially in memories 114, 124, 134, and 144. For example, memory 114 stores portions "17" through "20", memory 124 stores portions "21" through "24", and so on. In one embodiment, control circuitry 160 transitions each of memories 124, 134, and 144 to a sleep state while keeping memory 114 active. Additionally, control circuitry 160 de-energizes memory interfaces 122, 132, and 142, or disables their corresponding power supply reference levels. Memory interface 112 remains connected to its corresponding power supply reference level and remains operational in the active state along with memory 114.

[0036] To perform a refresh operation, the display device requests data of a given type (parts "17" through "32") from memories 114, 124, 134, and 144. After accessing parts "17" through "20" from memory 114 to send these parts to the display device, control circuitry 160 transitions memory 124 from a sleep state to an active state and memory 114 from an active state to a sleep state. Additionally, control circuitry 160 energizes memory interface 122 and de-energizes memory interface 112. For example, control circuitry 160 reconnects the corresponding power supply reference level to memory interface 122 and disconnects the corresponding power supply reference level from memory interface 112. Thus, in some implementations, a single memory is active while the remaining memories are in a sleep state. Similarly, after accessing parts "21" through "24" from memory 124, control circuitry 160 transitions memory 134 from a sleep state to an active state and memory 124 from an active state to a sleep state. Additionally, control circuit 160 energizes memory interface 132 and de-energizes memory interface 122. These steps continue as the display device refreshes.

[0037] In another specific implementation, the video frame including portions "1" through "16" is the last frame rendered before integrated circuit 300 enters an idle state. In this case, memory interfaces 112, 122, 132, and 142 transfer data between memories 114, 124, 134, and 144 to store portions "1" through "16" in a sequential manner. Subsequently, control circuit 160 transitions each of memories 124, 134, and 144 to a sleep state while keeping memory 114 active. Additionally, control circuit 160 de-energizes memory interfaces 122, 132, and 142, or disables their corresponding power supply reference levels. Memory interface 112 remains connected to its corresponding power supply reference level and remains operational in the active state along with memory 114. Subsequently, integrated circuit 300 performs the refresh operation steps as described above.

[0038] refer to Figure 4This diagram illustrates a general block diagram of an integrated circuit 400 that manages power consumption in the copy memory. The circuits and signals described previously are numbered identically. Here, each of the memories 114, 124, 134, and 144 stores corresponding copies of portions "17" to "32" in a sequential manner as previously described. Control circuit 160 determines when integrated circuit 400 exits an idle state. For example, the end of a video graphics workload indicates the idle state of the static screen of the display device and resumes rendering video frame data for the display device. Control circuit 160 assigns an active state to each of the memories 114, 124, 134, and 144 such that no memory in memories 114, 124, 134, and 144 remains in a sleep state. Furthermore, control circuit 160 ensures that no memory interface in memory interfaces 112, 122, 132, and 142 remains closed or disconnected from the corresponding power supply reference level. Instead, each memory interface in memory interfaces 112, 122, 132, and 142 is turned on and is active. When new data of a given type is retrieved from the DMA engine or other units and sent to integrated circuit 400, the new data of that given type continues to be stored in memory 114, 124, 134, and 144 in an interleaved manner. This reduces the latency of accesses in non-idle states.

[0039] refer to Figure 5 A general block diagram of a device 500 for managing power consumption in a replicated memory of an integrated circuit is shown. In the illustrated embodiment, device 500 includes a SoC 510 and memories 530A-530B. SoC 510 includes a memory controller 520, memory interfaces 522A and 526A for transferring data to local memory 530A via communication channels 524A and 528A, and memory interfaces 522B and 526B for transferring data to local memory 530B via communication channels 524B and 528B. SoC 510 also includes a power manager 540, a display controller 550, direct memory access (DMA) circuitry 560 (or DMA engine 560), and a network interface 570.

[0040] In various implementations, the SoC 510 also includes one or more functional blocks (not shown) for processing various types of tasks. Examples of functional blocks are a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a multimedia engine, and processing units with highly parallel microarchitectures, such as a graphics processing unit (GPU) and a digital signal processor (DSP). In some implementations, one or more of these functional blocks render video frame data that is later sent to the display controller 550. For ease of illustration, other components of the device 500 are not shown. For example, an off-chip memory controller, one or more input / output (I / O) interface units, an interrupt controller, one or more phase-locked loops (PLLs) or other clock generation circuitry, and various other functional blocks are not shown, although the device 500 may use these components. In various implementations, the device 500 is used in desktop computers, portable computers, mobile devices, servers, peripheral devices, etc.

[0041] Although only two memories 530A-530B are shown, it is possible and anticipated that device 500 may use other numbers of memories, and this number is based on design requirements. In one embodiment, optional cache 522 is the last level cache in the cache memory subsystem hierarchy. However, the size of cache 522 is also limited due to the limited on-die area of ​​SoC 510. Memory controller 520 uses local memory controllers 522A and 526A to transfer data with local memory 530A via communication channels 524A and 528A. Local memory 530A includes memory devices 532A and 534A. In some embodiments, each of memory devices 532A and 534A is one type of SDRAM among various types of Synchronous Dynamic Random Access Memory (SDRAM) specifically designed for applications requiring high memory data bandwidth and high memory data rates. In other embodiments, each of memory devices 532A and 534A is another type of DRAM.

[0042] In various implementations, each of the communication channels 524A and 528A is a point-to-point (P2P) communication channel. A P2P communication channel is a dedicated communication channel between a single source and a single destination. Therefore, a P2P communication channel transmits data only between a single source and a single destination. Address information, command information, response data, payload data, header information, and other types of information are transmitted over metallic traces or wires accessible only by a single source and a single destination. In one implementation, local memory controllers 522A and 526A support one of several types of Graphics Double Data Rate (GDDR) communication protocols.

[0043] It should be noted that although communication channels 524A and 528A use the term "communication channel," each of communication channels 524A and 528A is capable of transmitting data across multiple memory channels supported by the corresponding memory device. For example, a single memory channel of a particular memory device may include 60 or more individual signals, of which 32 signals are dedicated to response data or payload data. The memory controller or interface of the memory device may support multiple memory channels. Each of these memory channels is included within either communication channel 524A or 528A.

[0044] Components of SoC 510 communicate with each other via one or more of a communication bus, point-to-point channel, communication structure, or other structures for transmitting data and commands. Network interface 570 supports communication protocols for communicating with one of several types of networks. DMA circuitry 560 supports memory mapping and communication protocols for communicating with one of several types of system memory. Display controller 550 receives rendered video frame data from memories 530A-530B and prepares the data for rendering an image on the corresponding display device. Power manager 540 assigns a corresponding power domain to each of the memory devices 532A-532B and 534A-534B. Each power domain includes at least operating parameters, such as at least an operating supply voltage and an operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to clock generation circuitry and power references.

[0045] In some implementations, the hardware of power manager 540, such as circuitry, determines when a task of the workload enters an idle state. In other implementations, power manager 540 receives an indication of an idle state. An idle state may indicate a static screen connected to display controller 550. For example, a video graphics application may no longer update frame data to be viewed on the display device. The video graphics application may be paused or waiting for further user input, and during the waiting period, the scene or image on the display device is not updated. Therefore, although the video graphics application has not stopped executing, the video processing subsystem of the computing system enters an idle state. Power manager 540 sends operating parameters and data storage commands 542 to one or more of DMA circuitry 560 and memory controller 520. For example, power manager 540 includes ( Figures 1 to 4 The functionality of the control circuit 160 of the integrated circuit 100-400. In another specific embodiment, the functionality is included in other circuits besides the power manager 540.

[0046] Turn now Figure 6This illustrates a general block diagram of a power manager 600 that manages power consumption in a replicated memory of an integrated circuit. In various specific embodiments, the power manager 600 includes ( Figures 1 to 4 The integrated circuit 100-400 includes the functionality of the control circuit 160. As shown, the power manager 600 includes a table 610 and control circuitry 630. Control circuitry 630 includes multiple components 632-636 for generating operating parameters and data storage commands 640 to update the power domains of multiple memories. Table 610 includes multiple table entries (or entries), each storing information in multiple fields such as at least fields 612-618. Table 610 is implemented using one of the following: trigger circuitry, random access memory (RAM), content-addressable memory (CAM), etc. Although specific information is shown stored in fields 612-618 in a specific sequential order, in other implementations, different orders are used, and different amounts and types of information are stored. As shown, field 612 stores status information, such as at least valid bits. Field 614 stores an identifier specifying one of the multiple memories (such as DRAM).

[0047] Field 616 stores a value indicating whether the corresponding memory (such as DRAM used as local memory) stores a given type of data in a sequential or interleaved manner. Field 618 stores a value indicating the latest P-state or current value of the power domain of the corresponding memory. Control circuitry 630 receives usage measurements and indications 624, which represent the activation level of the memory and power consumption measurements or parameters used to determine the latest power consumption value of the memory. Power performance status (P-state) selector 632 selects the next operating parameter for the memory and the corresponding memory interface. Data storage layout allocator 634 (or allocator 634) includes circuitry for determining whether the memory stores a given type of data in a sequential or interleaved manner.

[0048] In some implementations, the given type of data is video frame data. Based on one or more of the following: the expected size of the video frame data, the expected performance degradation when accessing data from memory sequentially, any Quality of Service (QoS) values ​​associated with the video graphics application, and values ​​stored in Table 610, allocator 634 determines whether the cache and memory store the given type of data sequentially or in an interleaved manner. One or more components of power manager 600 use values ​​stored in configuration and status register (CSR) 636. CSR 636 stores examples of the values ​​described above used by allocator 634. In some implementations, one or more components of power manager 600 and corresponding functionality are set in another external circuit (rather than within power manager 600 here).

[0049] refer to Figure 7 A general block diagram of a method 700 for effectively managing power consumption in a replicated memory of an integrated circuit is shown. For illustrative purposes, the specific implementation (and) is shown in chronological order. Figure 8 The steps in the diagram are shown. However, in other specific implementations, some steps occur in a different order than those shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are not present.

[0050] The hardware, such as circuitry, of the multiple memories in the integrated circuit uses assigned operating parameters to handle workload tasks (box 702). In various embodiments, the multiple memories include memory devices, such as one type of DRAM from multiple types. In various embodiments, a power manager assigns a corresponding power domain to each of the multiple memories in the integrated circuit. Each power domain includes at least operating parameters, such as at least an operating supply voltage and an operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to clock generation circuitry and a power reference. In one embodiment, the integrated circuit handles video graphics workload tasks, such as rendering video frame data for a display device. Data of a given type is already rendered video frame data in a frame buffer. This data of that given type is sent from the multiple memories to the display device.

[0051] Multiple memories store data of a given type in an interleaved manner (box 704). In some embodiments, a power manager or other control circuitry determines when the workload task causes the integrated circuit to transition to an idle state. In other embodiments, the power manager or other control circuitry receives an indication of the idle state. The idle state may indicate a static screen on a display device. For example, a video graphics application may no longer update frame data to be viewed on the display device. The video graphics application may be paused or waiting for further user input, and during the waiting time, the scene or image on the display device is not updated. Therefore, although the video graphics application has not stopped executing, the video processing subsystem of the computing system, which includes multiple memories, enters an idle state.

[0052] If the control circuit determines that a transition to an idle state has not yet occurred (the "No" branch of condition branch 706), the control flow of method 700 returns to block 702, where the integrated circuit uses the assigned operating parameters to handle the workload task. However, if the control circuit determines that a transition to an idle state has occurred (the "Yes" branch of condition branch 706), the control circuit sends commands to multiple memories to transfer data of a given type between these memories until data of the given type is stored in these memories in a contiguous manner (block 708). In another embodiment, the control circuit sends commands to multiple memories to store new data in a contiguous manner.

[0053] The control circuit sends a command or instruction to the memory specifying operating parameters for maintaining the active state of a given memory among the plurality of memories (box 710). The control circuit transitions each memory among the plurality of memories except the given memory to a sleep state (box 712). Additionally, in some embodiments, the control circuit de-energizes the memory interface corresponding to each memory among the plurality of memories except the given memory. For example, in one embodiment, the control circuit removes the corresponding power supply reference level for each memory among the plurality of memories except the given memory. During the idle state, the memory uses the given memory to process a request for data of a given type (box 714). The control circuit rotates among the plurality of memories to keep a single memory active and serves the request based on the given type of data requested (box 716). In one embodiment, the control circuit energizes only the single memory interface associated with the single memory that is active. The other memory interfaces are de-energized.

[0054] Turn now Figure 8This diagram illustrates a general block diagram of a method 800 for effectively managing power consumption in a replicated memory of an integrated circuit. A control circuit sends a command or instruction to the memory specifying that data of a given type be stored sequentially in multiple memories (box 802). The control circuit determines that a transition to an idle state has occurred (box 804). The control circuit sends a command or instruction to the memory specifying operating parameters for maintaining the active state of a given memory among the multiple memories (box 808). The control circuit transitions each memory among the multiple memories except the given memory to a sleep state (box 810). Additionally, in some embodiments, the control circuit de-energizes the memory interface corresponding to each memory among the multiple memories except the given memory. For example, in one embodiment, the control circuit removes the corresponding power supply reference level for each memory among the multiple memories except the given memory. During the idle state, the memory uses the given memory to process a request for data of a given type (box 812). The control circuit rotates among the multiple memories to keep a single memory active and serves the request based on the given type of data requested (box 814). In one implementation, the control circuit powers on only the single memory interface associated with the single active memory. Other memory interfaces are de-energized.

[0055] It should be noted that one or more of the above-described embodiments include software. In such embodiments, program instructions for implementing the method and / or mechanism are transmitted or stored on a computer-readable medium. Many types of media configured to store program instructions are available and include hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROMs (PROMs), random access memory (RAMs), and various other forms of volatile or non-volatile storage devices. Generally, computer-accessible storage media include any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include storage media such as magnetic or optical media, such as magnetic disks (fixed or removable), magnetic tape, CD-ROMs or DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-ray discs. Storage media also include volatile or non-volatile storage media, such as RAM (e.g., Synchronous Dynamic RAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM, Low Power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), Static RAM (SRAM), etc.), ROM accessible via a peripheral device interface (such as a Universal Serial Bus (USB) interface), flash memory, and non-volatile memory (e.g., flash memory). Storage media include microelectromechanical systems (MEMS), and storage media accessible via communication media such as networks and / or wireless links.

[0056] Additionally, in various specific implementations, program instructions include behavioral-level or register-transfer-level (RTL) descriptions of hardware functionality in high-level programming languages ​​(such as C) or design languages ​​(HDLs) (such as Verilog, VHDL, or database formats (such as GDS II streaming format (GDSII)). In some cases, the description is read by a synthesis tool that synthesizes the description to produce a netlist comprising a list of gates from a synthesis library. The netlist includes gate sets, which also represent the functionality of the hardware comprising the system. The netlist is then placed and strung to produce a dataset describing the geometry to be applied to a mask. The mask is then used in various semiconductor manufacturing steps to produce semiconductor circuits or circuits corresponding to the system. Alternatively, computer-accessible instructions on a storage medium are, as desired, netlists (with or without synthesis libraries) or datasets. Furthermore, the instructions are used by, for example... and Mentor The purpose of this type of supplier's hardware-based type simulator is to perform simulation.

[0057] Although the specific embodiments described above have been described in considerable detail, many variations and modifications will become apparent to those skilled in the art once the foregoing disclosure is fully understood. The following claims are intended to be interpreted as covering all such variations and modifications.

Claims

1. An integrated circuit, the integrated circuit comprising: Control circuit; In response to the idle state of the integrated circuit, the control circuit is configured to: The operation parameters of the active state are assigned to the first memory among multiple memories that stores data of a given type for one or more requests; The operation parameters for the sleep state are assigned to one or more of the plurality of memories other than the first memory; as well as During the idle state, requests are served by accessing the first memory.

2. The integrated circuit of claim 1, wherein, further in response to the idle state, the control circuit is further configured to send an indication configured to cause data of the given type to be stored in the plurality of memories in a continuous manner.

3. The integrated circuit of claim 2, wherein the control circuit is further configured to send the indication in response to the end of the idle state.

4. The integrated circuit according to claim 1, wherein the control circuit is further configured as follows: Prior to the idle state, an instruction configured to store data of the given type in an interleaved manner is sent to the plurality of memories; and In further response to the idle state, an instruction is sent to the plurality of memories to be configured to transfer data of the given type between the plurality of memories so that the data of the given type is stored in the plurality of memories in a continuous manner.

5. The integrated circuit of claim 4, wherein in response to the end of the idle state, the control circuit is further configured to send an instruction to the plurality of memories configured to transfer data of the given type between the plurality of memories so that the data of the given type is stored in the plurality of memories in an interleaved manner.

6. The integrated circuit of claim 1, wherein the data of the given type is video frame data stored in a frame buffer.

7. The integrated circuit according to claim 1, wherein the idle state corresponds to a display device.

8. A method, the method comprising: The task is processed by an integrated circuit that includes multiple memories; In response to the idle state of the integrated circuit: The control circuit assigns the operating parameters of the active state to the first memory among multiple memories, which stores one or more data of a given type targeted by a request; The control circuit assigns the operation parameters of the sleep state to one or more of the plurality of memories other than the first memory. as well as The first memory serves the request during the idle state.

9. The method according to claim 8, further comprising: In further response to the idle state, the control circuitry sends an instruction configured to store the given type of data in the plurality of memories in a continuous manner.

10. The method according to claim 9, further comprising: In response to the end of the idle state, the control circuit sends the indication.

11. The method according to claim 8, further comprising: Prior to the idle state, the control circuit sends an instruction to the plurality of memories configured to store data of the given type in the plurality of memories in an interleaved manner. as well as In further response to the idle state, the control circuit sends an instruction to the plurality of memories configured to transfer data of the given type between the plurality of memories so that the data of the given type is stored in the plurality of memories in a continuous manner.

12. The method according to claim 11, further comprising: In response to the end of the idle state, the control circuit sends an instruction to the plurality of memories configured to transfer data of the given type between the plurality of memories so that the data of the given type is stored in the plurality of memories in an interleaved manner.

13. The method of claim 8, wherein the data of the given type is video frame data stored in a frame buffer.

14. The method of claim 8, wherein the idle state corresponds to the display device.

15. A computing system, the computing system comprising: A memory configured to store instructions for one or more tasks and source data to be processed by the one or more tasks; An integrated circuit configured to execute the instructions using the source data, wherein the integrated circuit includes: Control circuit; In response to the idle state of the integrated circuit, the control circuit is configured to: The operation parameters of the active state are assigned to the first memory among multiple memories that stores data of a given type for one or more requests; Assigning the operation parameters of the sleep state to one or more of the plurality of memories other than the first memory; and During the idle state, requests are served by accessing the first memory.

16. The computing system of claim 15, wherein, further in response to the idle state, the control circuitry is further configured to send an instruction configured to cause data of the given type to be stored in the plurality of memories in a continuous manner.

17. The computing system of claim 16, wherein the control circuitry is further configured to send the instruction in response to the end of the idle state.

18. The computing system of claim 15, wherein the control circuit is further configured to: Prior to the idle state, an instruction configured to store data of the given type in an interleaved manner is sent to the plurality of memories; and In further response to the idle state, an instruction is sent to the plurality of memories to be configured to transfer data of the given type between the plurality of memories so that the data of the given type is stored in the plurality of memories in a continuous manner.

19. The computing system of claim 18, wherein in response to the end of the idle state, the control circuitry is further configured to send an instruction to the plurality of memories configured to transfer data of the given type between the plurality of memories so that the data of the given type is stored in the plurality of memories in an interleaved manner.

20. The computing system of claim 15, wherein the data of the given type is video frame data stored in a frame buffer.

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