Substrate with glass core and glass build-up layer

Abstract

Substrates having a glass core and a glass build-up layer and methods of forming the same are described herein. In one example, a substrate includes a glass core, glass layers above and below the glass core, conductive traces in the glass core and at least some of the glass layers, and conductive contacts on a surface of the substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 194,550, filed on March 31, 2023, entitled “SUBSTRATES WITH A GLASSCORE AND GLASS BUILDUP LAYERS”, the entire contents of which are incorporated herein by reference. Background Technology

[0003] The need to miniaturize the form factor of computing devices and increase integration density to achieve high performance in computing devices has driven the development of complex packaging methods in the semiconductor industry. Reducing electrical input / output (I / O) interconnects is one of the biggest drivers of performance improvement. However, for microbump-based interconnects, reducing the bump pitch beyond 10 micrometers (μm) has reached a technological bottleneck. Therefore, other interconnect technologies with greater scalability are emerging, such as hybrid bonding, a combination of dielectric bonding and direct copper-copper bonding. Hybrid bonding is used for silicon-to-silicon bonding, such as bonding multiple silicon dies, wafers, etc. However, interconnects between silicon dies and packaging substrates are still primarily implemented using microbumps. Attached Figure Description

[0004] Figure 1 A glass packaging substrate for a silicon die used in hybrid bonding is shown.

[0005] Figure 2A -J illustrates the process flow for forming a glass packaging substrate for silicon dies used in hybrid bonding.

[0006] Figure 3 An embedded die package in a glass substrate is shown.

[0007] Figure 4A -I illustrates the process flow for forming embedded die packages in a glass substrate.

[0008] Figure 5 An embedded die package in a glass substrate using through-silicon vias is shown.

[0009] Figure 6A -I illustrates the process flow for forming embedded die packages in glass substrates using through-silicon vias.

[0010] Figure 7A -C illustrates various embodiments of a glass substrate and package with microbumps.

[0011] Figure 8 A flowchart is shown for forming an integrated circuit (IC) package on a substrate having a glass core and a glass stack.

[0012] Figure 9 It can be a top view of wafers and dies that can be included in microelectronic components.

[0013] Figure 10 It can be a cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly.

[0014] Figure 11 It is a cross-sectional side view of an integrated circuit device assembly that may include microelectronic components.

[0015] Figure 12 It can be a block diagram of an example electrical device that may include microelectronic components. Detailed Implementation

[0016] Competition in the field of high-performance computing has intensified over the past decade. The need to miniaturize the form factor of computing devices and increase integration to achieve high performance in computing devices has helped drive the development of complex packaging methods in the semiconductor industry.

[0017] Shrinking electrical input / output (I / O) interconnects is one of the biggest drivers of performance improvement. However, for microbump-based interconnects, reducing bump pitch beyond 10 micrometers (μm) has reached a technological bottleneck. Therefore, other interconnect technologies are emerging. For example, direct copper-copper bonding (e.g., solderless) is a promising alternative to microbumps to drive bump pitches below 10 μm. Another promising alternative is hybrid bonding, a combination of dielectric bonding and copper-copper bonding.

[0018] Current hybrid bonding technologies are limited to silicon-to-silicon bonding, such as wafer-to-wafer, die-to-wafer, die-to-die / die stack, etc. However, the packaging substrate is typically made of materials other than silicon. Therefore, the interconnect between silicon dies and (non-silicon) packaging substrates is still primarily implemented using microbumps.

[0019] Encapsulation substrates are typically made of organic materials or a combination of glass and organic materials. For example, organic substrates typically include an organic core with multiple organic stacked layers, and glass substrates typically include a glass core with multiple organic stacked layers. For both types of substrates, the organic stacked layers are typically formed from organic films (e.g., Ajinomoto laminate (ABF) and polyimide (PI)). However, organic materials have a high coefficient of thermal expansion (CTE), which causes them to expand significantly at high temperatures. Therefore, these substrates are not suitable for hybrid bonding because the organic materials in these substrates will expand, which can stress the encapsulation and potentially lead to defects.

[0020] Therefore, this disclosure proposes embodiments of all-glass (or primarily glass) substrates suitable for both microbump bonding and hybrid die-to-substrate bonding (e.g., copper-copper / dielectric bonding). Current glass-based substrates use only glass in the substrate core, while organic materials (e.g., ABF, PI) are used to form the stacked layers, making them unsuitable candidates for hybrid bonding. However, the glass substrates of this disclosure include both a glass core and glass stacked layers, thus fully utilizing the electrical and mechanical benefits of glass.

[0021] These glass substrates can be formed by starting with a glass core and replacing conventional organic stacking layers with glass layers, for example by forming a silicon oxide layer on the glass core using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other similar techniques.

[0022] Processes typically used only on glass cores (e.g., forming through-glass vias (TGVs) using laser-based etching techniques (e.g., laser-induced selective etching (LISE)) and conductive seeding and plating (e.g., using copper-plated titanium / copper seeding)) can also be used on glass stacks to form electrical interconnects.

[0023] The back end of the substrate may have microbumps for conventional die attachment using thermo-press bonding and mass reflow, or alternatively, it may have recessed Cu bumps within a glass (e.g., silicon oxide) layer for direct hybrid bonding with the silicon chip.

[0024] These glass substrates offer a variety of advantages. For example, organic stacked layers are replaced by glass layers that can closely match the glass core. This provides greater flexibility in substrate design, which was previously limited by manufacturing capabilities.

[0025] Compared to conventional glass-based substrates that utilize glass only in the core, this all-glass substrate more effectively utilizes the mechanical and electrical benefits of glass. For example, the resulting glass substrate exhibits better electrical and mechanical properties, such as lower dielectric loss, higher bandwidth, lower CTE, and lower warpage.

[0026] Furthermore, this all-glass design can be used for both microbump bonding and hybrid bonding. In particular, this design enables hybrid bonding between the die and substrate to achieve lower latency and higher bandwidth communication. For example, the mechanical properties of the glass layers can be fine-tuned to match the mechanical properties of the silicon used for hybrid bonding. Direct copper-copper bonding between a monolithic die or die stack and the substrate provides significant performance benefits. Moreover, this all-glass substrate can be fabricated and hybrid-bonded with silicon chips at the panel or wafer level.

[0027] Figure 1A glass packaging substrate 100 for hybrid bonding of silicon dies is shown. In some embodiments, such as integrated circuit packaging, the glass substrate 100 may be used in one or more integrated circuit dies to be hybrid bonded to the glass substrate 100.

[0028] The glass substrate 100 includes a glass core 102 with glass stacks 104 above and below the core. In various embodiments, the glass core 102 can be a glass substrate made of any suitable glass (e.g., amorphous) material, including but not limited to silicon oxide (SiOx) (e.g., silicon dioxide (SiO2), also known as silica), fused silica, alkaline glass, non-alkaline glass, borosilicate glass, float borosilicate glass (e.g.,...). ), alkaline borosilicate glass, quartz and / or any other type of glass.

[0029] Therefore, in various embodiments, the glass core 102 may be made of a material including elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium and / or zinc), calcium carbonate (CaCO3) and sodium carbonate (Na2CO3).

[0030] Glass stack 104 can be a dielectric layer made of any suitable glass material, including but not limited to silicon oxide (SiO2). x (For example, silicon dioxide (SiO2) is also known as silica, fused silica), spin-coated glass (e.g., glass materials with dopants (e.g., boron, phosphorus, titanium and / or zinc) such as silicon dioxide (SiO2)), etc. Therefore, in some embodiments, the glass stack 104 may be made of a material comprising elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3). Furthermore, in some embodiments, the properties of the glass layer 104 (e.g., CTE) may be tuned to match the properties of the silicon used for hybrid bonding with the silicon die.

[0031] The packaging substrate 100 also includes conductive traces 106 patterned in the glass core 102 and the glass stack 104, including vias in the glass core 102 and the glass stack 104 and horizontal traces in the glass stack 104. In some embodiments, the conductive traces may be made of metal 106 (e.g., copper and / or titanium).

[0032] Conductive trace 106 electrically couples a recessed pad 108 at the top of the package substrate 100 to a bump 110 at the bottom of the substrate. The recessed pad 108 and bump 110 are conductive contacts for electrically coupling other components to the package substrate 100. The recessed pad 108 may be a copper pad slightly recessed below the dielectric glass layer 104, and the bump 110 may be a solder ball, a bump, or a microbump. The package substrate 100 also includes a solder resist layer 109 at the bottom of the substrate where the bump 110 is located.

[0033] In some embodiments, for example, one or more integrated circuit dies (not shown) may be coupled to the top side of the package substrate 100 and hybrid-bonded to the recessed pads 108 (e.g., via a combination of dielectric and copper-copper bonding). Furthermore, the package substrate 100 may be coupled to a circuit board (e.g., a motherboard, mainboard, etc.) or another integrated circuit package (not shown) via bumps 110 at the bottom of the package substrate 100.

[0034] Figure 2A -J shows the method used for forming Figure 1 The process flow shown is for the glass packaging substrate 100. Specifically, the process flow can be used for panel-level or wafer-level fabrication of glass substrates with hybrid bonded silicon dies (e.g., substrate-to-die hybrid bonding). However, this process flow is merely one example method for fabricating such a substrate.

[0035] exist Figure 2A In this process, an amorphous glass panel (or wafer) of appropriate thickness serves as the substrate core 102. In some embodiments, the glass panel may have a thickness ranging from 100 micrometers (μm) to 1000 μm or 1 millimeter (mm). Depending on process requirements, various glass compositions can be used, including but not limited to, alkaline glass, non-alkaline glass, borosilicate glass, float borosilicate glass (e.g., Alkaline borosilicate glass and / or quartz, and other examples.

[0036] exist Figure 2B In this process, a through-hole 103 is formed in the glass core 102. In some embodiments, the through-hole 103 is formed using a laser-based technique (e.g., laser-induced selective etching (LISE)). LISE is a two-step process in which the glass is locally modified using ultrafast laser pulses, and the modified portion is etched away using a wet chemical etching technique (e.g., an etching bath with hydrofluoric acid (HF), potassium hydroxide (KOH), or sodium hydroxide (NaOH)). The laser-damped region has a much faster etching rate than the undamped region, which makes it possible to form a through-hole 103 with a high aspect ratio.

[0037] exist Figure 2CIn this process, metal seeding and plating are performed to form conductive paths 106 that pass through and are above / below the core 102. For example, titanium and copper can be deposited on the surfaces of the core 102 and the via 103 to form a seed layer, and copper can be deposited on the seed layer to form a through-glass via (TGV) 106 in the core 102 (e.g., by filling the via 103) and to form conductive layers 106 above and below the core 102. Polishing techniques can be used to planarize the surface of the conductive layers on the core 102 (e.g., grinding, chemical mechanical planarization (CMP)).

[0038] exist Figure 2D In this process, the conductive layers on the top and bottom of the core 102 are patterned into conductive traces 106 by etching away unwanted metal. In some embodiments, conventional photolithography processes can be used to etch away unwanted metal, such as dry film resist (DFR) lamination, photolithography exposure, photoresist development, and copper etching.

[0039] exist Figure 2E In this process, a glass deposit 104 is formed above and below the core 102. For example, instead of laminating an organic deposit (e.g., using an ABF film) on the core, a glass layer 104 of appropriate thickness (e.g., 10-50 μm) is formed above and below the core 102 by depositing a suitable material for forming glass.

[0040] In some embodiments, the glass layer 104 may be a silicon oxide layer formed by depositing an oxide of silicon (SiOx) (e.g., silicon dioxide (SiO2) (also known as silica)) onto the core 102 using chemical vapor deposition (CVD) or physical vapor deposition (PVD), which solidifies into glass. Different dopants and concentrations can be carefully selected to modify the silicon oxide forming agent and modifier to obtain the desired electrical and mechanical properties in the resulting glass layer 104.

[0041] The surface of glass layer 104 can then be planarized using polishing techniques (e.g., grinding, chemical mechanical planarization (CMP)).

[0042] exist Figure 2F In this process, a through-hole 105 is formed in the glass layer 104. For example, instead of using laser drilling to form a conventional through-hole in an organic laminate (e.g., ABF), the through-hole 105 is formed in the glass laminate 104. As a result, it can be used with... Figure 2B The same LISE process is used to form the through-hole 105 in the glass layer 104, which means that the same tool set can be used.

[0043] exist Figure 2GIn this process, a second set of via / conductive layers 106 is formed on the glass layer 104 above and below the core 102 using metallization and surface planarization techniques similar to the first set of via / conductive layers in Figure 2.

[0044] Similarly, in Figure 2H In China, use and Figure 2D The same etching technique is used to pattern the conductive layer 106 at the top and bottom as conductive traces 106.

[0045] In Figure 21, repeat Figure 2E Step -H forms another set of glass stacked layers 104 and conductive stacked layers 106 on the top and bottom surfaces. These steps can be repeated until the appropriate number of glass / conductive stacked layers for a particular substrate have been formed.

[0046] exist Figure 2J In this process, another glass layer 104 is formed on the bottom surface and planarized (e.g., flush with the layer of trace 106), a solder resist layer 109 is formed on the glass layer 104, and bumps or microbumps 110 are formed on the trace 106 to create a second-level interconnect.

[0047] Another glass layer 104 (slightly raised relative to the layer of trace 106) is formed on the top surface and then planarized (e.g., using CMP) to form an extremely flat dielectric glass surface 104, wherein copper pads 108 are slightly recessed below surface 104 (e.g., 5 nm–20 nm). The recessed copper pads 108 form a first-level interconnect for co-bonding with one or more silicon dies (not shown). In some embodiments, co-bonding can be performed at the panel level between the panel of the glass substrate 100 and the silicon die. As described above, the properties of the dielectric glass layer 104 (e.g., CTE) can be fine-tuned by adding silicon forming agents, substitutes, and / or modifiers to match the properties of silicon. As a result, the glass substrate 100 can be co-bonded to the silicon die without causing stress or damage to the substrate 100.

[0048] In the illustrated example, the process flow is described at a high level. For simplicity, some steps have been omitted, and / or some steps may differ from those described herein without departing from the scope of the described embodiments. For simplicity, only a limited number of glass / conductive stacked layers 104, 106 are shown in substrate 100. In practical embodiments, the number of stacked layers can reach 20 or more. Furthermore, the number of stacked layers above and below the core does not necessarily have to be the same.

[0049] Compared to substrates with a glass core and organic stacked layers, the all-glass (or primarily glass) substrates described herein offer numerous advantages. For example, the described embodiments support hybrid bonding between the glass substrate and the silicon die, enabling higher interconnect density and shorter interconnect distances between the substrate and the die compared to microbump interconnects. Furthermore, these glass substrates also offer various mechanical / structural benefits (e.g., lower warpage) because the materials used for the glass stacked layers can be very similar to those used for the glass core, which increases yield. The described embodiments also require fewer tools for fabrication, resulting in significant cost savings.

[0050] Figure 3 An embedded die package 300 in a glass substrate 301 is shown. The embedded die package 300 is an integrated circuit package having a silicon die 312 embedded in the glass substrate 301.

[0051] In the illustrated embodiment, the glass substrate 301 includes a glass core 302, which can be a glass substrate made of any suitable glass (e.g., amorphous) material, including but not limited to silicon oxide (SiOx) (e.g., silicon dioxide (SiO2), also known as silica), fused silica, alkaline glass, non-alkaline glass, borosilicate glass, float borosilicate glass (e.g., Alkaline borosilicate glass, quartz, and / or any other type of glass. Therefore, in various embodiments, the glass core 302 can be made of a material comprising elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0052] In addition, the glass core 302 includes a plurality of cavities 307 having embedded silicon dies 312, the embedded silicon dies 312 being attached to the bottom of the respective cavities 307 using die attachment films (DAF) 311.

[0053] The glass substrate 301 also includes glass stack layers 304 above and below the glass core 302. The glass stack layer 304 can be a dielectric layer made of any suitable glass material, including but not limited to silicon oxides (SiOx) (e.g., fused silica, silicon dioxide (SiO2), also known as silica), spin-coated glass (e.g., glass materials such as silica (SiO2) with dopants (e.g., boron, phosphorus, titanium, and / or zinc)), etc. Therefore, in some embodiments, the glass stack layer 304 can be made of a material including elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3). Furthermore, in some embodiments, the properties of the glass layer 304 (e.g., CTE) can be tuned to match the properties of silicon (e.g., for hybrid bonding with a silicon chip).

[0054] The substrate 301 also includes conductive traces 306 patterned in the glass core 302 and the glass stack 304, including vias in the glass core 302 and the glass layer 304, as well as horizontal traces in the glass layer 304. In some embodiments, the conductive traces 306 may be made of a metal (e.g., copper and / or titanium).

[0055] Conductive traces 306 electrically couple embedded die 312, a recessed pad 308 at the top of substrate 301, and a bump 310 at the bottom of substrate 301. The recessed pad 308 and bump 310 are conductive contacts for electrically coupling other components to substrate 301. The recessed pad 308 may be a copper pad slightly recessed below the dielectric glass layer 304, and the bump 310 may be a solder ball, a bump, or a microbump. Substrate 301 also includes a solder resist layer 309 at the bottom of the substrate where the bump 310 is located.

[0056] In some embodiments, for example, one or more additional silicon dies (not shown) may be hybrid-bonded to recessed pads 308 on the top side of substrate 301 (e.g., via a combination of dielectric and copper-copper bonding). Furthermore, substrate 301 may be coupled to a circuit board (e.g., motherboard, mainboard, etc.) or another integrated circuit package (not shown) via bumps 310 at the bottom of substrate 301.

[0057] For simplicity, only the embedded die 312 is shown on the top side of the core 302. However, in other embodiments, passive components (e.g., trace 306) and active silicon dies 312 may be embedded on both sides of the core 302, or embedded in the glass stack 304 (e.g., using an embedded multi-die interconnect / bridge), or embedded in both the core 302 and the glass stack 304.

[0058] Figure 4A -I shows the method used for formation Figure 3 The process flow shown is for embedding active dies and passive components (e.g., traces / bridges / interconnects) within a glass substrate. However, this process flow is merely one example method for manufacturing such a package.

[0059] exist Figure 4A In this process, a glass panel (or wafer) of appropriate thickness is used as the substrate core 302 (e.g., similar to...). Figure 2A ).

[0060] exist Figure 4B In the core 302, a cavity 307 for the silicon die is formed (e.g., using the LISE process).

[0061] exist Figure 4C In this process, a die attachment film (DAF) 311 with precise alignment and tilt control is used to mount a silicon die 312 to the bottom of the cavity 307. The die 312 includes pads 314 on its top surface for interconnection with other components.

[0062] exist Figure 4D In this process, silicon oxide deposition is used to form a glass layer 304 to fill the gap above the die 312, and the glass layer 304 is planarized (e.g., using grinding and / or CMP).

[0063] exist Figure 4E In the process, a through-hole 303 is formed in the glass core 302, and a through-hole 305 is formed in the glass layer 304 to the pad 314 on the silicon die 312 (e.g., using LISE process).

[0064] exist Figure 4F In this process, metal seeding and plating are performed to form conductive paths 306 that pass through the core 302 to the silicon die 312 and are above and below the core 302 (e.g., on the glass layer 304). For example, a through-glass via (TGV) 306 is formed in the core 302 by filling a via 303 with metal, a via 306 is formed in the glass layer 304 by filling a via 305 with metal, and a conductive layer 306 is formed above / below the core 302 by depositing metal below the core 302 and above the core 302 on the glass layer 304.

[0065] Figure 4G , 4H The remaining steps in 41 are similar to those in 41. Figure 2H Figure 21 and Figure 2J The steps in the process.

[0066] Figure 5An embedded die package 500 in a glass substrate using through-silicon vias (TSVs) is shown. For example, the embedded die package 500 is an integrated circuit package in a glass substrate 501 having an embedded silicon die 512 having through-silicon vias (TSVs) 513.

[0067] In the illustrated embodiment, the glass substrate 501 includes a glass core 502, which can be a glass substrate made of any suitable glass (e.g., amorphous) material, including but not limited to silicon oxide (SiOx) (e.g., silicon dioxide (SiO2), also known as silica), fused silica, alkaline glass, non-alkaline glass, borosilicate glass, float borosilicate glass (e.g., Alkaline borosilicate glass, quartz, and / or any other type of glass. Therefore, in various embodiments, the glass core 302 can be made of a material comprising elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0068] Furthermore, the glass core 502 includes a plurality of cavities 507 having embedded silicon dies 512, the embedded silicon dies 512 being attached to the bottom of the respective cavity 507 using die attachment films (DAF) 511. The embedded silicon dies 512 include through-silicon vias (TSVs) 513 to electrically couple the dies 512 to conductive traces 506 above and below the dies 512 in the substrate 501.

[0069] The glass substrate 501 also includes glass stack layers 504 above and below the glass core 502. The glass stack layer 504 can be a dielectric layer made of any suitable glass material, including but not limited to silicon oxides (SiOx) (e.g., fused silica, silicon dioxide (SiO2), also known as silica), spin-coated glass (e.g., glass materials such as silica (SiO2) with dopants (e.g., boron, phosphorus, titanium, and / or zinc)), etc. Therefore, in some embodiments, the glass stack layer 504 can be made of a material including elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3). Furthermore, in some embodiments, the properties of the glass layer 504 (e.g., CTE) can be tuned to match the properties of silicon (e.g., for hybrid bonding with a silicon chip).

[0070] The substrate 501 also includes conductive traces 506 patterned in the glass core 502 and the glass stack 504, including vias in the glass core 502 and the glass layer 504, as well as horizontal traces in the glass layer 504. In some embodiments, the conductive traces 506 may be made of a metal (e.g., copper and / or titanium).

[0071] Conductive traces 506 electrically couple embedded die 512, recessed pads 508 at the top of substrate 501, and bumps 510 at the bottom of substrate 501. Recessed pads 508 and bumps 510 are conductive contacts for electrically coupling other components to substrate 501. Recessed pads 508 may be copper pads slightly recessed below dielectric glass layer 504, and bumps 510 may be solder balls, bumps, or microbumps. Substrate 501 also includes a solder resist layer 509 at the bottom of substrate where bumps 510 are located.

[0072] In some embodiments, for example, one or more additional silicon dies (not shown) may be hybrid-bonded to recessed pads 508 on the top side of substrate 501 (e.g., via a combination of dielectric and copper-copper bonding). Furthermore, substrate 501 may be coupled to a circuit board (e.g., motherboard, mainboard, etc.) or another integrated circuit package (not shown) via bumps 510 at the bottom of substrate 501.

[0073] For simplicity, only the embedded die 512 is shown on the top side of the core 502. However, in other embodiments, passive components (e.g., trace 506) and active silicon dies 512 may be embedded on both sides of the core 502, or embedded in the glass stack 504 (e.g., using an embedded multi-die interconnect / bridge), or embedded in both the core 502 and the glass stack 504.

[0074] Figure 6A -I shows the method used for formation Figure 5 The process flow for the 500 embedded die package is described below. This process flow is merely an example method for manufacturing such a package.

[0075] Figure 6A The process flow for the embedded die package 500 shown in -I is similar to... Figure 4A The process flow for the embedded die package 300 shown in -I is the same as described below.

[0076] exist Figure 6C In the cavity 507, the die 512 includes through-silicon vias (TSVs) 513 connected to pads 514 on the top and bottom of the die 512.

[0077] exist Figure 6EIn this process, through-holes 505 are formed in the glass core 502 to die pads 514 on the bottom of the embedded die 512 (e.g., in addition to through-holes 505 in the glass layer 504 to die pads 514 on the top of the die 512 and through-holes 503 in the glass core 502). Furthermore, die attachment film 511 on the bottom die pads 514 is removed (e.g., using a laser) to establish an electrical connection between the bottom die pads 514 and subsequently formed vias.

[0078] Figure 7A -C illustrates various embodiments of a glass substrate and a package with microbumps. In particular, Figure 7A , 7B 7C and 7C respectively depict Figure 1 , 3 In embodiment 5, the first-level interconnects on the top surface are formed by microbumps instead of recessed pads for hybrid bonding. In this way, one or more silicon dies (or other integrated circuit packages / components) can be attached to the top surface via microbumps.

[0079] For example, Figure 7A A glass encapsulation substrate 100' with microbumps 108' on its top surface is shown. Figure 7B A glass-embedded die package 300' with microbumps 308' on its top surface is shown, and Figure 7C A glass embedded die package 500' is shown, having a through-silicon via 513 in an embedded die 512 and microbumps 508' on the top surface.

[0080] Figure 7A , 7B The embodiments in 7C can be used respectively with Figure 2A The fabrication process follows a similar flow to that described in -J, 4A-I, and 6A-I. However, in the final stage of this process, solder resist and bumps are added to both sides of the glass substrate, rather than just the bottom. Conventional bumping techniques can be used to form bumps for first-level interconnects (on top) and second-level interconnects (on bottom). In this way, conventional bump / microbump bonding is used on an all-glass substrate (rather than an organic substrate or a glass-core-only substrate) to fully utilize the electrical and mechanical benefits of glass.

[0081] Throughout the embodiments shown and described in this disclosure (e.g., substrates / packages 100, 100', 300, 300', 500, 500'), other types of conductive contacts may be used in place of or supplement to the conductive contacts shown, including but not limited to metal pads (e.g., recessed or non-recessed copper pads), metal bumps / microbumps (e.g., C4 / C4 copper bumps), solder balls / bumps and solder paste, and other examples.

[0082] Furthermore, in various embodiments, the glass substrate described herein can be an "all-glass" substrate or a "primarily glass" substrate, meaning that the core is made of glass and all or some of the dielectric stacks are made of glass. In some embodiments, for example, the glass core may be made of solid glass (and patterned with various integrated circuit features) instead of glass cloth or fabric. Additionally, in some embodiments, all dielectric stacks may be glass layers, while in other embodiments, a combination of glass stacks and non-glass stacks may be present, wherein the non-glass stacks are made of other dielectric materials (e.g., organic materials (e.g., ABF, solder resist)). Furthermore, the glass core and / or glass / dielectric stacks can be patterned with various features, including but not limited to vias / traces, conductive contacts (e.g., pads, bumps), recesses, cavities, embedded silicon dies, etc.

[0083] Furthermore, the described glass substrate can be used as a substrate in any type of electronic device, including integrated circuit packaging, circuit boards (e.g., printed circuit boards), etc.

[0084] Figure 8 A flowchart 800 for forming an integrated circuit (IC) package on a substrate having a glass core and glass stack is shown. As will be understood from this disclosure, flowchart 800 is merely an example method for achieving an IC package on a substrate having a glass core and glass stack.

[0085] The steps of flowchart 800 can be performed using any suitable semiconductor manufacturing technology. For example, patterning and removal (e.g., interconnect patterning, via opening formation, and shaping) can be performed using any suitable technology (e.g., photolithography-based patterning / masking and / or etching). Furthermore, film deposition (e.g., deposited layers, portions of filled layers (e.g., removed portions), and filled via openings can be performed using any suitable deposition technology (including, for example, electroless deposition, chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and / or physical vapor deposition (PVD)).

[0086] The flowchart begins at box 802, which is the glass panel (or wafer) receiving the core used as a substrate for an IC package. The glass core can be formed from any type of glass. In some embodiments, the glass core can be made of a material including elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0087] The flowchart then proceeds to block 804 to form traces within and above / below the glass core. For example, a through-hole may be formed in the glass core and filled with a conductive material (e.g., a metal) to form a through-glass via passing through the core. Additionally, conductive layers may be formed above and below the core and etched into a suitable conductive trace pattern. In some embodiments, the conductive material used to form the traces may include metals such as copper, titanium, tin, silver, gold, nickel, aluminum, tungsten, and / or alloys thereof.

[0088] The flowchart then proceeds to block 806 to form glass layers above and below the glass core. Furthermore, in some embodiments, the properties of the glass layers (e.g., CTE) can be adjusted to match the properties of the glass core and / or silicon (e.g., for hybrid bonding with a silicon die).

[0089] In some embodiments, for example, the glass layer may be a dielectric layer made of any suitable glass material, including but not limited to silicon oxides (SiOx) (e.g., fused silica, silicon dioxide (SiO2), also known as silica), spin-coated glass (e.g., glass materials such as silica (SiO2) with dopants (e.g., boron, phosphorus, titanium, and / or zinc)), etc. Therefore, in some embodiments, the glass stack 504 may be made of a material comprising elements such as silicon, oxygen, boron, phosphorus, titanium, zinc, aluminum, magnesium, calcium, sodium, carbon, alkaline earth metals, and / or any combination of these elements, including but not limited to silicon dioxide (SiO2) (e.g., with or without dopants such as boron, phosphorus, titanium, and / or zinc), calcium carbonate (CaCO3), and sodium carbonate (Na2CO3).

[0090] The flowchart then proceeds to frame 808 to form traces, including vias and horizontal traces, in the glass layers above and below the core.

[0091] Boxes 806 and 808 can be repeated multiple times as needed to form an appropriate number of glass stacks patterned with conductive traces above and below the core.

[0092] The flowchart then proceeds to block 810 to form conductive contacts (e.g., on the top and / or bottom glass layers and coupled to traces) on one or more surfaces of the substrate, such as metal pads (e.g., recessed or non-recessed copper pads), metal bumps / microbumps (e.g., C4 / C4 copper bumps), solder balls / bumps and solder paste, and other examples.

[0093] In some embodiments, for example, recessed pads (e.g., for hybrid bonding) or microbumps may be formed on the top surface of the glass substrate for first-level interconnects to one or more integrated circuit dies. Additionally, bumps may be formed on the bottom surface of the glass substrate for second-level interconnects to a circuit board (e.g., motherboard, mainboard, etc.) or another integrated circuit package.

[0094] In this way, the completed packaging substrate includes a glass core, glass stacks above and below the glass core, conductive traces patterned in the glass core and glass stacks, and conductive contacts on the surface of the substrate for first and / or second-level interconnects.

[0095] The flowchart then proceeds to block 812 to attach one or more integrated circuit (IC) dies to the substrate. In some embodiments, for example, one or more dies may be attached to the top of a glass substrate, such as by bonding the die to recessed copper pads on the substrate surface, or by attaching the die to microbumps on the substrate surface, and other examples. Alternatively, in some embodiments, one or more cavities may be formed in a glass core and / or glass layer during an earlier stage of processing, and one or more silicon dies may be embedded in the cavities and interconnected with conductive traces patterned in the glass stack.

[0096] An integrated circuit die may include any suitable type of circuit system, including but not limited to processing circuit systems, communication circuit systems, and / or memory / storage circuit systems. In some embodiments, for example, an integrated circuit die may include a central processing unit (CPU), a graphics processing unit (GPU), a vision processing unit (VPU), a microprocessor, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an input / output (I / O) controller, a network interface controller (NIC), a memory and / or a solid-state storage device, and other examples.

[0097] The completed IC package can then be attached to or included as part of a circuit board, another integrated circuit substrate, or package or electronic device (e.g., electronic device 1200).

[0098] In some embodiments, such as, among other examples, an IC package may be included in an electronic device such as a cellular phone, wearable device, computer, server, camera, video playback device, video game console, display device, vehicle control unit, or electrical appliance.

[0099] At this point, the flowchart can be completed. However, in some embodiments, the flowchart may restart and / or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart at block 802 to form another integrated circuit package with the same or similar design.

[0100] Example integrated circuit embodiment

[0101] Figure 9This is a top view of the wafer 900 and die 902 that may be included in any of the embodiments disclosed herein. The wafer 900 may be made of semiconductor material and may include one or more dies 902 having integrated circuit structures formed on the surface of the wafer 900. Each die 902 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After the semiconductor product is manufactured, the wafer 900 may undergo a singlet process in which the dies 902 are separated from each other to provide discrete “chips” of the integrated circuit product. The die 902 may be any die disclosed herein. The die 902 may include one or more transistors (e.g., discussed below). Figure 10 The wafer 900 or die 902 may include some transistors in transistor 1040, supporting circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, the wafer 900 or die 902 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridged RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 902. For example, a memory array formed by multiple memory devices may be formed in conjunction with a processor unit (e.g., Figure 12 The processor unit 1202 or other logically identical die 902 is configured to store information in a memory device or execute instructions stored in a memory array. Various microelectronic components in the microelectronic components disclosed herein can be manufactured using die-to-wafer assembly technology, wherein some of these dies are attached to a wafer 900 that includes other dies in the die, and the wafer 900 is subsequently unified.

[0102] Figure 10 This is a cross-sectional side view of an integrated circuit device 1000 that may be included in any embodiment disclosed herein (e.g., in any die). One or more of the integrated circuit devices 1000 may be included in one or more dies 902 ( Figure 9 The integrated circuit device 1000 can be formed on the die substrate 1002 (e.g., Figure 9 On a 900-inch wafer, and can be included in a die (e.g., Figure 9The die substrate 1002 can be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1002 can include, for example, a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, the die substrate 1002 can be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV can also be used to form the die substrate 1002. Although several examples of materials that can form the die substrate 1002 are described herein, any material that can be used as the basis for the integrated circuit device 1000 can be used. The die substrate 1002 can be a single-element die (e.g., Figure 9 902 die) or wafer (e.g., Figure 9 A portion of the 900 wafer.

[0103] The integrated circuit device 1000 may include one or more device layers 1004 disposed on a die substrate 1002. Device layer 1004 may include features of one or more transistors 1040 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. Transistor 1040 may include, for example, one or more source and / or drain (S / D) regions 1020, a gate 1022 for controlling current flow between S / D regions 1020, and one or more S / D contacts 1024 for routing electrical signals to / from S / D regions 1020. Transistor 1040 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. Transistor 1040 is not limited to... Figure 10 The types and configurations shown are not limited to those described above, but can include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations thereof. Non-planar transistors can include FinFET transistors, such as dual-gate or tri-gate transistors, as well as gate-all-around transistors or all-around-gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.

[0104] return Figure 10 The transistor 1040 may include a gate 1022 formed of at least two layers—a gate dielectric and a gate electrode. The gate dielectric may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0105] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using high-k materials, the gate dielectric may undergo an annealing process to improve its quality.

[0106] The gate electrode may be formed on the gate dielectric and may include at least one p-type or n-type work function metal, depending on whether the transistor 1040 is a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, the gate electrode may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a fill metal layer. For other purposes, additional metal layers, such as barrier layers, may be included.

[0107] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0108] In some embodiments, when viewed in cross-section along the source-channel-drain direction as a cross-section of the transistor 1040, the gate electrode may be composed of a U-shaped structure, the U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1002 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1002. In other embodiments, at least one of the metal layers forming the gate electrode may be merely a planar layer substantially parallel to the top surface of the die substrate 1002 and does not include the sidewall portions substantially perpendicular to the top surface of the die substrate 1002. In other embodiments, the gate electrode may be composed of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0109] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to clamp the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0110] The S / D region 1020 can be formed within the die substrate 1002 adjacent to the gate 1022 of each transistor 1040. For example, the S / D region 1020 can be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic can be implanted into the die substrate 1002 to form the S / D region 1020. An annealing process to activate the dopant and further diffuse it into the die substrate 1002 can be performed after the ion implantation process. In the latter process, the die substrate 1002 can be etched first to form a recess at the location of the S / D region 1020. An epitaxial deposition process can then be performed to fill the recess with the material used to fabricate the S / D region 1020. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide can be used to fabricate the S / D region 1020. In some embodiments, the epitaxially deposited silicon alloy can be in-situ doped with dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or group III-V materials or alloys, may be used to form the S / D region 1020. In other embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 1020.

[0111] Electrical signals such as power and / or input / output (I / O) signals can be transmitted through one or more interconnect layers disposed on device layer 1004 (in Figure 10 The interconnect layers (shown as interconnect layers 1006-1010) are routed to and / or from devices in device layer 1004 (e.g., transistor 1040). For example, conductive components of device layer 1004 (e.g., gate 1022 and S / D contact 1024) may be electrically coupled to interconnect structures 1028 of interconnect layers 1006-1010. One or more interconnect layers 1006-1010 may form a metallized stack (also referred to as an "ILD stack") 1019 of integrated circuit device 1000.

[0112] Interconnect structure 1028 can be arranged within interconnect layers 1006-1010 to route electrical signals according to various designs; in particular, this arrangement is not limited to... Figure 10 The specific configuration of the interconnect structure 1028 shown. Although in Figure 10 A specific number of interconnect layers 1006-1010 are shown, but embodiments of this disclosure include integrated circuit devices having more or fewer interconnect layers than shown.

[0113] In some embodiments, the interconnect structure 1028 may include lines 1028a and / or vias 1028b filled with a conductive material such as a metal. Line 1028a may be arranged to route electrical signals in a direction substantially parallel to a plane on which the die substrate 1002 on which the device layer 1004 is formed. For example, line 1028a may be in the direction of entering and exiting a page and / or from... Figure 10 The via 1028b routes electrical signals in the direction through which the view passes the page. The via 1028b can be arranged to route electrical signals in a direction substantially perpendicular to the plane of the die substrate 1002 on which the device layer 1004 is formed. In some embodiments, the via 1028b can electrically couple lines 1028a of different interconnect layers 1006-1010 together.

[0114] Interconnect layers 1006-1010 may include dielectric material 1026 disposed between interconnect structures 1028, such as Figure 10 As shown. In some embodiments, the dielectric material 1026 disposed between interconnect structures 1028 in different interconnect layers 1006-1010 may have different compositions; in other embodiments, the composition of the dielectric material 1026 between different interconnect layers 1006-1010 may be the same. Device layer 1004 may also include dielectric material 1026 disposed between transistor 1040 and the bottom layer of metallization stack. The dielectric material 1026 included in device layer 1004 may have a different composition than the dielectric material 1026 included in interconnect layers 1006-1010; in other embodiments, the composition of the dielectric material 1026 in device layer 1004 may be the same as the dielectric material 1026 included in any of the interconnect layers 1006.

[0115] A first interconnect layer 1006 (referred to as metal 1 or "M1") may be formed directly on device layer 1004. In some embodiments, the first interconnect layer 1006 may include a line 1028a and / or a via 1028b, as shown. The line 1028a of the first interconnect layer 1006 may be coupled to a contact (e.g., S / D contact 1024) of device layer 1004. The via 1028b of the first interconnect layer 1006 may be coupled to the line 1028a of the second interconnect layer 1008.

[0116] The second interconnect layer 1008 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1006. In some embodiments, the second interconnect layer 1008 may include a via 1028b to couple the line 1028 of the second interconnect layer 1008 to the line 1028a of the third interconnect layer 1010. Although for clarity, the line 1028a and the via 1028b are structurally depicted as lines within the respective interconnect layers, in some embodiments, the line 1028a and the via 1028b may be structurally and / or materially continuous (e.g., simultaneously filled during a dual damascene process).

[0117] Based on similar techniques and configurations described in conjunction with the second interconnect layer 1008 or the first interconnect layer 1006, a third interconnect layer 1010 (referred to as metal 3 or "M3") (and additional interconnect layers as needed) can be continuously formed on the second interconnect layer 1008. In some embodiments, the "higher" (i.e., more distant from device layer 1004) interconnect layers in the metallization stack 1019 of the integrated circuit device 1000 can be thicker than the lower interconnect layers in the metallization stack 1019, wherein lines 1028a and vias 1028b in the higher interconnect layers are thicker than lines 1028a and vias 1028b in the lower interconnect layers.

[0118] The integrated circuit device 1000 may include a solder resist material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on an interconnect layer 1006. Figure 10 In this embodiment, conductive contact 1036 is shown in the form of a bonding pad. Conductive contact 1036 may be electrically coupled to interconnect structure 1028 and configured to route electrical signals from transistor 1040 to external devices. For example, solder bonds may be formed on one or more conductive contacts 1036 to mechanically and electrically couple an integrated circuit die including integrated circuit device 1000 to another component (e.g., a printed circuit board). Integrated circuit device 1000 may include additional or alternative structures for routing electrical signals from interconnect layers 1006-1010; for example, conductive contact 1036 may include other similar features (e.g., posts) for routing electrical signals to external components. Conductive contact 1036 may be used as any conductive contact described throughout this disclosure.

[0119] In some embodiments where the integrated circuit device 1000 is a double-sided die, the integrated circuit device 1000 may include another metallization stack (not shown) on the opposite side of the device layer 1004. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 1006-1010 to provide a conductive path (e.g., including wires and vias) between the device layer 1004 and additional conductive contacts (not shown) on the side of the integrated circuit device 1000 opposite to the conductive contact 1036. These additional conductive contacts may be used as any conductive contact described herein.

[0120] In other embodiments where the integrated circuit device 1000 is a double-sided die, the integrated circuit device 1000 may include one or more through-silicon vias (TSVs) through the die substrate 1002; these TSVs may contact the device layer 1004 and may provide a conductive path between the device layer 1004 and additional conductive contacts (not shown) on the side of the integrated circuit device 1000 opposite to the conductive contact 1036. These additional conductive contacts may serve as any conductive contact described herein. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the opposite side of the integrated circuit device 1000 from the conductive contact 1036 to the transistor 1040 and any other components integrated into the die 1000, and the metallized stack 1019 may be used to route I / O signals from the conductive contact 1036 to the transistor 1040 and any other components integrated into the die 1000.

[0121] Multiple integrated circuit devices 1000 can be stacked with one or more TSVs in various stacked devices, thereby providing connectivity between one device and any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide connectivity between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connectivity between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

[0122] Figure 11This can be a cross-sectional side view of an integrated circuit device assembly 1100 that may include any embodiment disclosed herein. For example, any suitable component of the integrated circuit device assembly 1100 may include one or more of the glass substrate / packages 100, 300, 500 disclosed herein. In some embodiments, the integrated circuit device assembly 1100 may be a microelectronic assembly. The integrated circuit device assembly 1100 includes multiple components disposed on a circuit board 1102 (which may be a motherboard, system board, motherboard, etc.). The integrated circuit device assembly 1100 includes components disposed on a first surface 1140 and an opposing second surface 1142 of the circuit board 1102; typically, components may be disposed on one or both of surfaces 1140 and 1142. Any integrated circuit component discussed below with reference to the integrated circuit device assembly 1100 may take the form of any suitable embodiment of the microelectronic assembly 100 disclosed herein.

[0123] In some embodiments, circuit board 1102 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers separated from each other by dielectric material layers and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1102 (optionally combined with other metal layers). In other embodiments, circuit board 1102 may be a non-PCB substrate. Figure 11 The integrated circuit device assembly 1100 shown includes an on-intermediate package structure 1136 coupled to a first side 1140 of a circuit board 1102 via a coupling member 1116. The coupling member 1116 electrically and mechanically couples the on-intermediate package structure 1136 to the circuit board 1102 and may include solder balls (such as...). Figure 11 The coupling element 1116 may be used as a coupling element shown or described herein for any substrate assembly or substrate assembly component, as appropriate. This includes pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a disk grid array (LGA),) male and female portions of sockets, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structure.

[0124] The on-intermediate package structure 1136 may include an integrated circuit component 1120 coupled to the intermediate layer 1104 via a coupling member 1118. The coupling member 1118 may take any suitable form for the application, such as the form discussed above with reference to coupling member 1116. Although in Figure 11A single integrated circuit component 1120 is shown, but multiple integrated circuit components can be coupled to the interposer 1104; in fact, additional interposers can be coupled to the interposer 1104. The interposer 1104 can provide an intermediary substrate for bridging the circuit board 1102 and the integrated circuit component 1120.

[0125] Integrated circuit component 1120 may be a packaged or unpackaged integrated circuit product, comprising one or more integrated circuit dies (e.g., Figure 9 902 core, Figure 10 The packaged integrated circuit component 1120 includes an integrated circuit device 1000 and / or one or more other suitable components. The packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit die and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 1120, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1104. The integrated circuit component 1120 may include one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, the integrated circuit component 1120 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0126] In embodiments where integrated circuit component 1120 includes multiple integrated circuit dies, they may be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0127] In addition to including one or more processor units, the integrated circuit component 1120 may also include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These individual integrated circuit dies may be referred to as “chiplets.” In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (e.g., Embedded multi-die interconnect bridges (EMIBs) or combinations thereof are provided.

[0128] Typically, interposer 1104 can extend connections to wider spacing or reroute connections to different connections. For example, interposer 1104 can couple integrated circuit component 1120 to a set of ball grid array (BGA) conductive contacts of coupling component 1116 to couple to circuit board 1102. Figure 11 In the illustrated embodiment, integrated circuit component 1120 and circuit board 1102 are attached to opposite sides of interposer 1104; in other embodiments, integrated circuit component 1120 and circuit board 1102 may be attached to the same side of interposer 1104. In some embodiments, three or more components may be interconnected via interposer 1104.

[0129] In some embodiments, the interposer 1104 may be formed as a PCB comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1104 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the interposer 1104 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates (e.g., silicon, germanium, and other Group III-V and Group IV materials). The interposer 1104 may include metal interconnects 1108 and vias 1110, including but not limited to through-hole vias 1110-1 (which extend from a first side 1150 of the interposer 1104 to a second side 1154 of the interposer 1104), blind vias 1110-2 (which extend from a first side 1150 or a second side 1154 of the interposer 1104 to an inner metal layer), and buried vias 1110-3 (which connect to the inner metal layer).

[0130] In some embodiments, the interposer 1104 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer can connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, the interposer 1104 including the silicon interposer may further include one or more wiring layers to route connections on the first side of the interposer 1104 to an opposite second side of the interposer 1104.

[0131] Intermediate layer 1104 may also include embedded devices 1114, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on intermediate layer 1104. The on-intermediate package structure 1136 may take the form of any on-intermediate package structure known in the art. In embodiments where the intermediate layer is not a printed circuit board.

[0132] The integrated circuit device assembly 1100 may include an integrated circuit component 1124 coupled to a first surface 1140 of the circuit board 1102 via a coupling member 1122. The coupling member 1122 may take the form of any of the embodiments discussed above with reference to the coupling member 1116, and the integrated circuit component 1124 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1120.

[0133] Figure 11 The integrated circuit device assembly 1100 shown includes a stacked package structure 1134 coupled to a second side 1142 of a circuit board 1102 via a coupling member 1128. The stacked package structure 1134 may include integrated circuit components 1126 and 1132 coupled together via a coupling member 1130, such that integrated circuit component 1126 is disposed between the circuit board 1102 and integrated circuit component 1132. Coupling members 1128 and 1130 may take the form of any embodiment of coupling member 1116 discussed above, and integrated circuit components 1126 and 1132 may take the form of any embodiment of integrated circuit component 1120 discussed above. The stacked package structure 1134 can be configured according to any stacked package structure known in the art.

[0134] Figure 12 This may be a block diagram of an example electrical device 1200 that may include one or more embodiments disclosed herein. For example, any suitable component of the electrical device 1200 may include one or more of the glass substrate / package 100, 100', 300, 300', 500, 500', integrated circuit device assembly 1100, integrated circuit component 1120, integrated circuit device 1000, or integrated circuit die 902 disclosed herein. Multiple components in... Figure 12The components are shown as included in electrical device 1200, but any one or more of these components may be omitted or copied, as applicable to the application. In some embodiments, some or all of the components included in electrical device 1200 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-a-chip (SoC) die.

[0135] Additionally, in various embodiments, electrical equipment 1200 may not include... Figure 12 The electrical device 1200 may include one or more components as shown, but may include interface circuitry systems for coupling to one or more components. For example, the electrical device 1200 may not include display device 1206, but may include display device interface circuitry systems (e.g., connectors and drive circuitry systems) to which display device 1206 may be coupled. In another set of examples, the electrical device 1200 may not include audio input device 1224 or audio output device 1208, but may include audio input or output device interface circuitry systems (e.g., connectors and support circuitry systems) to which audio input device 1224 or audio output device 1208 may be coupled.

[0136] Electrical device 1200 may include one or more processor units 1202 (e.g., one or more processor cells). As used herein, the terms "processor unit," "processing unit," or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processor unit 1202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Thus, a processor unit may be referred to as an XPU (or xPU).

[0137] Electrical device 1200 may include memory 1204, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard disk drive. In some embodiments, memory 1204 may include memory located on the same integrated circuit die as processor unit 1202. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last-level cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0138] In some embodiments, electrical device 1200 may include one or more processor units 1202 that are heterogeneous or asymmetric to another processor unit 1202 in electrical device 1200. There can be various differences between the processing units 1202 in the system in terms of a range of value indicators, including architecture, microarchitecture, thermal, and power consumption characteristics. These differences can effectively manifest themselves as asymmetry and heterogeneity between the processor units 1202 in electrical device 1200.

[0139] In some embodiments, electrical device 1200 may include communication component 1212 (e.g., one or more communication components). For example, communication component 1212 may manage wireless communication for data transmission to and from electrical device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid medium. The term "wireless" does not imply that the associated devices do not include any wires, although in some embodiments they may not include any wires.

[0140] Communication component 1212 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any modifications, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym for Global Microwave Access Interoperability, which is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. Communication component 1212 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication component 1212 may operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication component 1212 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, communication component 1212 may operate according to other wireless protocols. Electrical device 1200 may include antenna 1222 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0141] In some embodiments, communication component 1212 can manage wired communication, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, communication component 1212 may include multiple communication components. For example, a first communication component 1212 may be dedicated to short-range wireless communication, such as Wi-Fi or Bluetooth, and a second communication component 1212 may be dedicated to long-range wireless communication, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1212 may be dedicated to wireless communication, and the second communication component 1212 may be dedicated to wired communication.

[0142] Electrical device 1200 may include a battery / power circuit system 1214. The battery / power circuit system 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of electrical device 1200 to an energy source (e.g., AC line power) separate from electrical device 1200.

[0143] Electrical device 1200 may include display device 1206 (or a corresponding interface circuit system, as described above). Display device 1206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as head-up displays, computer monitors, projectors, touch screen displays, liquid crystal displays (LCDs), light-emitting diode displays, or flat panel displays.

[0144] Electrical device 1200 may include audio output device 1208 (or a corresponding interface circuit system, as described above). Audio output device 1208 may include any embedded or wired or wirelessly connected external device that generates audible indicators, such as a speaker, headphones, or earphones.

[0145] Electrical device 1200 may include audio input device 1224 (or a corresponding interface circuitry system, as described above). Audio input device 1224 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output). Electrical device 1200 may include Global Navigation Satellite System (GNSS) device 1218 (or a corresponding interface circuitry system, as described above), such as a Global Positioning System (GPS) device. GNSS device 1218 may communicate with satellite-based systems and may determine the geographical location of electrical device 1200 based on information received from one or more GNSS satellites, as is known in the art.

[0146] Electrical equipment 1200 may include other output devices 1210 (or corresponding interface circuitry systems, as described above). Examples of other output devices 1210 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0147] Electrical device 1200 may include other input devices 1220 (or corresponding interface circuitry systems, as described above). Examples of other input devices 1220 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., single-lens or stereo cameras), trackballs, touchpads, keyboards, cursor control devices such as mice, styluses, touchscreens, proximity sensors, microphones, barcode readers, quick-response (QR) code readers, electrocardiogram (ECG) sensors, PPG (photoplethysmography) sensors, skin conductance sensors, any other sensors, or radio frequency identification (RFID) readers.

[0148] Electrical device 1200 can have any desired form factor, such as handheld or mobile electrical devices (e.g., cellular phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, 2-in-1 convertible computers, portable all-in-one computers, netbook computers, ultrabook computers, personal digital assistants (PDAs), ultra-mobile personal computers, portable game consoles, etc.), desktop electrical devices, servers, rack-level computing solutions (e.g., blade, tray, or rack-mount computing systems), workstations or other networked computing components, printers, scanners, display devices (e.g., monitors, televisions), set-top boxes, entertainment control units, video game consoles, video playback devices, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems as part of a vehicle, smart home appliance, consumer electronics product or equipment, or manufacturing equipment). In some embodiments, electrical device 1200 can be any other electronic device that processes data. In some embodiments, electrical device 1200 can include multiple discrete physical components. The given electrical device 1200 can be represented as a range of devices in various embodiments, and in some embodiments, electrical device 1200 can be referred to as a computing device or computing system.

[0149] Example Implementation

[0150] The following provides illustrative examples of techniques described throughout this disclosure. Embodiments of these techniques may include any one or more and any combination of the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the foregoing figures may be configured to perform one or more operations, techniques, processes, and / or methods as set forth in the examples below.

[0151] Example 1 includes a substrate comprising: a glass core; a plurality of glass layers on the glass core, some of which are above the glass core and some of which are below the glass core; a plurality of conductive traces in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the substrate.

[0152] Example 2 includes a substrate according to Example 1, wherein the conductive traces include: a plurality of vias, wherein the vias are in a glass core and at least some glass layers; and a plurality of horizontal traces, wherein the horizontal traces are in at least some glass layers.

[0153] Example 3 includes a substrate according to any one of Examples 1-2, wherein at least some conductive contacts are used for electrical coupling to a circuit board or integrated circuit package.

[0154] Example 4 includes a substrate according to any one of Examples 1-3, wherein at least some conductive contacts are used for electrical coupling to an integrated circuit die.

[0155] Example 5 includes a substrate according to Example 4, wherein the conductive contacts for electrical coupling to an integrated circuit die include: a plurality of microbumps; or a plurality of pads.

[0156] Example 6 includes a substrate according to Example 5, wherein the pads are recessed relative to the glass layer.

[0157] Example 7 includes a substrate according to any one of Examples 1-6, wherein the glass core has a thickness ranging from about 100 micrometers to about 1000 micrometers.

[0158] Example 8 includes a substrate according to any one of Examples 1-7, wherein at least some of the glass layers have a thickness ranging from about 10 micrometers to about 50 micrometers.

[0159] Example 9 includes a substrate according to any one of Examples 1-8, wherein at least some of the glass layers comprise silicon and oxygen.

[0160] Example 10 includes a substrate according to any one of Examples 1-9, wherein the conductive traces include at least one of copper or titanium.

[0161] Example 11 includes an integrated circuit package comprising: an integrated circuit die; and a package substrate electrically coupled to the integrated circuit die, wherein the package substrate comprises: a glass core; a plurality of glass layers on the glass core, some of which are above the glass core and some of which are below the glass core; a plurality of conductive traces in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the package substrate.

[0162] Example 12 includes an integrated circuit package according to Example 11, wherein at least some conductive contacts are used for electrical coupling to a circuit board or another integrated circuit package.

[0163] Example 13 includes an integrated circuit package according to any one of Examples 11 to 12, wherein at least some conductive contacts are electrically coupled to the integrated circuit die.

[0164] Example 14 includes an integrated circuit package according to any one of Examples 11 to 12, wherein the integrated circuit die is embedded in a cavity of the package substrate.

[0165] Example 15 includes an integrated circuit package according to any one of Examples 11 to 14, wherein the integrated circuit die includes a processing circuit system, a communication circuit system, or a memory circuit system.

[0166] Example 16 includes an electronic device comprising: a circuit board; and an integrated circuit package electrically coupled to the circuit board, wherein the integrated circuit package includes: one or more integrated circuit dies; and a package substrate electrically coupled to the one or more integrated circuit dies, wherein the package substrate includes: a glass core; a plurality of glass layers on the glass core, some of which are above the glass core and some of which are below the glass core; a plurality of conductive traces, wherein the conductive traces are in the glass core and at least some of the glass layers; and a plurality of conductive contacts on one or more surfaces of the package substrate.

[0167] Example 17 includes an electronic device according to Example 16, wherein the electronic device is a cellular phone, a wearable device, a computer, a server, a camera, a video playback device, a video game console, a display device, a vehicle control unit, or an electrical appliance.

[0168] Example 18 includes a method comprising: receiving a glass core; forming a plurality of glass layers on the glass core, wherein some of the glass layers are formed above the glass core and some of the glass layers are formed below the glass core; forming a plurality of conductive traces in the glass core and at least some of the glass layers; and forming a plurality of conductive contacts on one or more surfaces of the glass layers.

[0169] Example 19 includes the method according to Example 18, further comprising: attaching an integrated circuit die to at least some conductive contacts.

[0170] Example 20 includes the method according to Example 18, further comprising: forming a cavity in a glass core and / or at least some glass layers; and embedding an integrated circuit die in the cavity.

[0171] While the concepts of this disclosure are susceptible to various modifications and alternatives, specific embodiments thereof have been illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the concepts of this disclosure are not intended to be limited to the specific forms disclosed, but rather are intended to cover all modifications, equivalents, and alternatives consistent with this disclosure and the appended claims.

[0172] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Instead, in some embodiments, such features may be arranged in a different manner and / or order than those shown in the illustrative drawings. Furthermore, the inclusion of a structural or methodological feature in a particular drawing does not imply that such a feature is required in all embodiments, and in some embodiments, such a feature may be omitted or may be combined with other features. Moreover, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0173] Furthermore, for ease of understanding, the illustrations and / or descriptions of various embodiments may be simplified or approximated, and therefore may not necessarily reflect the level of precision and variation that may exist in actual embodiments. For example, while some figures generally indicate straight lines, right angles, and smooth surfaces, actual implementations of the disclosed embodiments may not achieve perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth due to practical limitations of the manufacturing process. Similarly, for ease of understanding, the illustrations and / or descriptions of how components are arranged may be simplified or approximated, and may vary within a certain range of error in actual embodiments (e.g., due to manufacturing processes, etc.).

[0174] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates different instances of similar objects mentioned and is not intended to imply that the objects described must be in a given sequence in time, space, rank, or any other way.

[0175] The terms “substantially,” “close to,” “approximately,” “near,” and “about” generally refer to within + / -10% of the target value (unless otherwise specified). Similarly, terms describing spatial relationships (e.g., “perpendicular,” “orthogonal,” or “coplanar”) may refer to substantially within the described spatial relationship (e.g., within + / -10 degrees of orthogonality).

[0176] Certain terms may also be used for reference only in the foregoing description and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” “below,” “bottom,” and “top” refer to directions of reference in the accompanying drawings. Terms such as “front,” “back,” “rear,” and “side” describe the orientation and / or position of portions of a component within a consistent but arbitrary frame of reference, as becomes clear from the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0177] As used herein, the terms “above,” “between,” “adjacent,” “to,” and “above” can refer to the relative position of a layer or component with respect to other layers or components. For example, a layer that is “above,” “adjacent to,” or bonded “to” another layer may be in direct contact with the other layer or may have one or more intermediate layers. A layer that is “between” two layers may be in direct contact with both layers or may have one or more intermediate layers.

[0178] The meanings of “one,” “an,” and “the” include multiple references. The meanings of “in…” include “in…” and “on…”.

[0179] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0180] The term "package" typically refers to a self-contained carrier of one or more dies, wherein the dies are attached to a package substrate and can be encapsulated for protection, with integrated or wire-bonded interconnects between the dies and leads, pins, or bumps located on an external portion of the package substrate. A package can contain a single die or multiple dies to provide a specific function. Packages are typically mounted on printed circuit boards to interconnect with other packaged integrated circuits and discrete components, forming a larger circuit.

[0181] The term "core" typically refers to an integrated circuit package built on a board, card, or wafer, where the substrate comprises a non-flexible, rigid material. Typically, a small printed circuit board serves as the core, on which integrated circuit devices and discrete passive components can be soldered. The core often has vias extending from one side to the other, allowing circuitry on one side of the core to be directly coupled to circuitry on the opposite side. The core can also serve as a platform for building conductor and dielectric material layers.

[0182] The term "coreless" typically refers to an integrated circuit package substrate that lacks a core. The absence of a core allows for higher-density package architectures because through-holes have relatively large dimensions and spacing compared to high-density interconnects.

[0183] When used herein, the term "pad side" generally refers to the side of an integrated circuit package substrate closest to the plane to which it is attached to a printed circuit board, motherboard, or other package. This contrasts with the term "die side," which is the side of an integrated circuit package substrate to which one or more dies are attached.

[0184] The term "dielectric" generally refers to any number of non-conductive materials that constitute the structure of the package substrate. For the purposes of this disclosure, dielectric materials may be incorporated into the integrated circuit package as layers of a laminate or as resin molded onto an integrated circuit die mounted on a substrate.

[0185] The term "metallization" generally refers to a metal layer formed on and through the dielectric material of a packaging substrate. The metal layer is typically patterned to form metallic structures such as traces and bonding pads. Metallization of the packaging substrate can be confined to a single layer or multiple layers separated by dielectric layers.

[0186] The term "bonding pad" generally refers to the metallized structure that terminates integrated traces and vias in integrated circuit packages and dies. The term "pad" is sometimes used interchangeably with "bonding pad" and has the same meaning.

[0187] The term "solder bump" generally refers to a layer of solder formed on bonding pads. Solder layers typically have a circular shape, hence the term "solder bump".

[0188] The term "substrate" generally refers to a planar platform comprising dielectric and / or metallized structures. A substrate can mechanically support and electrically couple one or more IC dies onto a single platform, wherein one or more IC dies are encapsulated by a moldable dielectric material. The substrate may include solder bumps (or other conductive contacts) as bonding interconnects on one or both sides. One side of the substrate (often referred to as the "die side") may include solder bumps for chip or die bonding. The opposite side of the substrate (often referred to as the "pad side") may include solder bumps for bonding the package to a printed circuit board.

[0189] The term "component" generally refers to grouping parts into individual functional units. Components can be separate and mechanically assembled into functional units, and some components can be removable. In another instance, components can be permanently bonded together. In some instances, components are integrated together.

[0190] The term “coupled” or “connected” refers to a direct or indirect connection, such as a direct electrical, mechanical, magnetic, or fluid connection between things connected or indirectly through one or more passive or active intermediate devices.

[0191] The terms "circuit" or "module" can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.

Claims

1. A substrate, comprising: Glass core; A plurality of glass layers on the glass core, wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core; Multiple conductive traces, wherein the conductive traces are in at least some of the glass layers in the glass core and the glass layers; and Multiple conductive contacts on one or more surfaces of the substrate.

2. The substrate according to claim 1, wherein, The conductive trace includes: Multiple vias, wherein the vias are located in at least some of the glass layers in the glass core and the glass layers; and Multiple horizontal traces, wherein the horizontal traces are in at least some of the glass layers.

3. The substrate according to any one of claims 1-2, wherein, At least some of the conductive contacts are used for electrical coupling to a circuit board or integrated circuit package.

4. The substrate according to any one of claims 1-3, wherein, At least some of the conductive contacts are used for electrical coupling to the integrated circuit die.

5. The substrate according to claim 4, wherein, The conductive contacts for electrical coupling to the integrated circuit die include: Multiple microbumps; or Multiple solder pads.

6. The substrate according to claim 5, wherein, The pads are recessed relative to the glass layer.

7. The substrate according to any one of claims 1-6, wherein, The glass core has a thickness ranging from about 100 micrometers to about 1000 micrometers.

8. The substrate according to any one of claims 1-7, wherein, At least some of the glass layers have a thickness ranging from about 10 micrometers to about 50 micrometers.

9. The substrate according to any one of claims 1-8, wherein, At least some of the glass layers comprise silicon and oxygen.

10. The substrate according to any one of claims 1-9, wherein, The conductive traces include at least one of copper or titanium.

11. An apparatus comprising: Integrated circuit die; as well as A packaging substrate electrically coupled to the integrated circuit die, wherein the packaging substrate comprises: Glass core; A plurality of glass layers on the glass core, wherein some of the glass layers are above the glass core and some of the glass layers are below the glass core; Multiple conductive traces, wherein the conductive traces are in at least some of the glass layers in the glass core and the glass layers; and Multiple conductive contacts on one or more surfaces of the packaging substrate.

12. The device according to claim 11, wherein, At least some of the conductive contacts are electrically coupled to the integrated circuit die, wherein the conductive contacts electrically coupled to the integrated circuit die include microbumps or pads.

13. The device according to claim 12, wherein, The pads are recessed relative to the glass layer.

14. The device according to any one of claims 11-13, wherein, The integrated circuit die is embedded in the cavity of the packaging substrate.

15. The device according to any one of claims 11-14, wherein, The glass core has a thickness ranging from about 100 micrometers to about 1000 micrometers.

16. The device according to any one of claims 11-15, wherein, At least some of the glass layers have a thickness ranging from about 10 micrometers to about 50 micrometers.

17. The device according to any one of claims 11-16, wherein, At least some of the glass layers comprise silicon and oxygen.

18. The device according to any one of claims 11-17, wherein, The conductive traces include at least one of copper or titanium.

19. The device according to any one of claims 11-18, wherein, The integrated circuit die includes a processing circuit system, a communication circuit system, or a memory circuit system.

20. The device according to any one of claims 11-19, further comprising an integrated circuit package, wherein, The integrated circuit package includes the integrated circuit die and the packaging substrate.

21. The device of claim 20, further comprising a circuit board, wherein the integrated circuit package is electrically coupled to the circuit board.

22. The device according to claim 21, wherein, The device is a cellular phone, wearable device, computer, server, camera, video playback device, video game console, display device, vehicle control unit, or electrical appliance.

23. A method comprising: Receive glass core; Multiple glass layers are formed on the glass core, wherein some of the glass layers are formed above the glass core and some of the glass layers are formed below the glass core; A plurality of conductive traces are formed in at least some of the glass layers in the glass core and the glass layers; and Multiple conductive contacts are formed on one or more surfaces of the glass layer.

24. The method of claim 23, further comprising: The integrated circuit die is attached to at least some of the conductive contacts.

25. The method of claim 23, further comprising: A cavity is formed in at least some of the glass layers in the glass core and / or the glass layers; as well as The integrated circuit die is embedded in the cavity.

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