Chip testing method and system of general test machine based on artificial intelligence model

Abstract

The present application relates to the technical field of chip testing, and specifically provides a chip testing method and system of a universal testing machine based on an artificial intelligence model. The method comprises: generating a test plan corresponding to a specification file according to the specification file of a chip to be tested, through a trained specification understanding model; inputting the test plan and a parameter digital twin model of the universal testing machine into a trained parameter conversion model, outputting a corresponding test circuit and test program from the parameter conversion model, the test circuit comprising an editable circuit in the universal testing machine; outputting a programming program of the test circuit in accordance with the test program, using a trained firmware programming model; and deploying the programming program and the test program on the universal testing machine to test the chip to be tested. The method solves the problem of low efficiency of the universal testing machine in the related art, which needs to rely on manual development of test programs for testing.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing method and system based on an artificial intelligence model-based universal testing machine. Background Technology

[0002] The chip market is rapidly evolving. Developing a dedicated chip testing machine for each chip is impractical given current industry technology; the development cycle cannot keep up with the chip iteration cycle, and the overall cost is not competitive. Therefore, dedicated chip testing machines are rarely seen on the market. The mainstream chip testing industry provides general-purpose chip testing machines.

[0003] General-purpose chip testers need to balance performance, stability, flexibility, and economy, resulting in complex structures. This not only makes the testers themselves difficult to develop but also makes them challenging for users to learn and use, leading to poor usability. However, the rapid iteration of chip technology demands both fast development of chip testing projects to shorten chip time-to-market and continuous technological upgrades of the testers themselves.

[0004] The development of chip testing projects relies heavily on experienced test engineers, a talent that is scarce. Technological iterations of test equipment can, to some extent, depend on programmable firmware upgrades. However, firmware development still requires manual work and necessitates advanced FPGA programming skills. This talent-technology contradiction represents a bottleneck in the field. The market urgently needs a technological approach that is simple in structure yet flexible and cost-effective.

[0005] For general-purpose test machines in related technologies, testing requires manual development of test programs, which is inefficient, and no effective solution has yet been proposed. Summary of the Invention

[0006] The present invention provides a chip testing method and system for a general-purpose test machine based on an artificial intelligence model, which at least solves the problem that general-purpose test machines in related technologies require manual development of test programs, resulting in low efficiency.

[0007] According to one aspect of the present invention, a chip testing method based on an artificial intelligence model and a general-purpose test machine is provided, comprising: generating a test plan corresponding to the specification document of the chip under test using a trained specification understanding model; inputting the test plan and a parameter digital twin model of the general-purpose test machine into a trained parameter conversion model, wherein the parameter conversion model outputs a corresponding test circuit and a test program, wherein the test circuit includes an editable circuit in the general-purpose test machine; outputting a programming program for the test circuit conforming to the test program using a trained firmware programming model based on the editable circuit and the test program; and deploying the programming program and the test program on the general-purpose test machine to test the chip under test.

[0008] As an optional approach, based on the specification document of the chip under test, a test plan corresponding to the specification document is generated using a trained specification understanding model. This includes: extracting data from the specification document using the specification understanding model to obtain multimodal data, wherein the specification understanding model is a multimodal model, and the multimodal data includes multiple data types, including at least one of the following: text, chart, and structured data; extracting test items and test parameters required for testing the chip under test based on the multimodal data; searching for matching test plan engineering templates from a test plan template library based on the test items and test parameters; and generating a corresponding test plan based on the test items, test parameters, and the corresponding test plan engineering template.

[0009] As an optional approach, before extracting data from the specification file using the multimodal model of the specification understanding model to obtain multimodal data, the method further includes: performing a first-stage pre-training of the specification understanding model using a professional dataset in the chip field; performing a second-stage pre-training of the specification understanding model completed in the first stage using historical test cases; and after outputting a programming program that conforms to the test program for the test circuit using the trained firmware programming model based on the editable circuit and the test program, the method further includes: obtaining corresponding test cases, and dynamically adjusting and training the specification understanding model using the specification file.

[0010] As an optional approach, the test plan and the fully parameterized digital twin model of the general-purpose test machine are input into a trained parameter conversion model, and the parameter conversion model outputs the corresponding test circuit and test program. This includes: inputting the test plan into the parameter conversion model, wherein the parameter conversion model is trained based on the fully parameterized digital twin model of the general-purpose test machine and historical test cases; and outputting the test circuit and test program of the test plan based on the fully parameterized digital twin model from the conversion model.

[0011] As an optional approach, before inputting the test plan into the parameter conversion model, the method further includes: obtaining the full test parameters of the general-purpose test machine, generating a fully parameterized digital twin model through multi-level modeling and model synthesis, wherein the full test parameters include hardware parameters, circuit parameters, and action parameters; based on the fully parameterized digital twin model, selecting historical test cases and test code from the historical test data of the general-purpose test machine, training the parameter conversion model to obtain the parameter conversion model; after outputting a programming program that conforms to the test program for the test circuit using the trained firmware programming model according to the editable circuit and the test program, the method further includes: obtaining the corresponding test cases and dynamically adjusting and training the parameter conversion model with the test code.

[0012] As an optional approach, before outputting a programming program that conforms to the test program using a trained firmware programming model based on the editable circuit and the test program, the method further includes: inputting the test program and the editable circuit into the firmware programming model, wherein the firmware programming model is trained based on programming knowledge data of the control chip of the editable circuit; selecting a firmware programming submodule based on the editable circuit from the firmware programming submodule library of the control chip by the conversion model, wherein the firmware programming submodule library includes multiple firmware programming submodules, which are used to implement different sub-functions; and generating the programming program by combining the firmware programming submodules and verifying resource conflicts.

[0013] As an optional approach, before inputting the test program and the editable circuit into the firmware programming model, the method further includes: performing a first-stage pre-training of the firmware programming model using the programming knowledge data of the control chip of the editable circuit; performing a second-stage pre-training of the firmware programming model using the test program and the firmware programming submodule library of the control chip; and after outputting a programming program that conforms to the test program for the test circuit using the trained firmware programming model based on the editable circuit and the test program, the method further includes: obtaining the corresponding programming program and updating the firmware programming submodule library; and dynamically adjusting and training the firmware programming model using the test program and the updated firmware programming submodule library.

[0014] As an optional approach, the programming program and the test program are deployed on the general-purpose test machine to test the chip under test, including: controlling the general-purpose test machine to load the programming program into the control chip of the editable circuit; when the chip under test is connected, responding to the start test command, automatically running the test program, and controlling the general-purpose test machine to test the chip under test according to the corresponding test plan; acquiring test data, generating a test report, and sending it to the display interface for display.

[0015] According to another aspect of the present invention, a chip testing system based on an artificial intelligence model and a general-purpose test machine is provided, comprising: a general-purpose test machine; a control device for controlling the general-purpose test machine; the general-purpose test machine includes a test circuit, the test circuit including an editable circuit; the control device includes a specification understanding model, a parameter conversion model, and a firmware programming model, the specification understanding model being connected to the parameter conversion model, and the parameter conversion model being connected to the firmware programming model; the specification understanding model is used to generate a test plan corresponding to the specification file of the chip under test; the parameter conversion model is used to output a corresponding test circuit and a test program based on the test plan and a parameter digital twin model of the general-purpose test machine; the firmware programming model is used to output a programming program for the test circuit conforming to the test program based on the editable circuit and the test program; the control device is further used to deploy the programming program and the test program on the general-purpose test machine to test the chip under test.

[0016] According to another aspect of the present invention, an electronic device is also provided, comprising: a processor, and a memory storing a program, characterized in that the program includes instructions that, when executed by the processor, cause the processor to perform the method described in any one of the preceding descriptions.

[0017] According to another aspect of the invention, a non-transitory machine-readable medium storing computer instructions is also provided, characterized in that the computer instructions are used to cause the computer to perform any of the methods described above.

[0018] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program / instructions, characterized in that, when the computer program / instructions are executed by a processor, they implement the method described in any one of the above.

[0019] The chip testing method for a general-purpose test machine based on an artificial intelligence model provided by this invention utilizes a three-level vertical artificial intelligence model, including a specification understanding model, a parameter conversion model, and a firmware programming model, to automatically understand the specification file of the chip under test and generate corresponding test programs based on the actual situation of the general-purpose test machine. This allows for customized testing of the chip under test. Compared with manual development and programming, this method not only greatly improves efficiency but also reduces costs, thereby solving the problem of low efficiency in related technologies where general-purpose test machines rely on manual development of test programs.

[0020] In addition, firmware programming can be performed on editable circuits, allowing general-purpose testers to edit the editable circuits more effectively based on the testing requirements of the chip under test. This maximizes the efficiency and utilization of the hardware, improving testing efficiency and accuracy, making the use of general-purpose testers more flexible, and avoiding the need for specialized technicians to perform firmware programming, which is not only costly but also has a longer development cycle. Attached Figure Description

[0021] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a chip testing method for a general-purpose test machine based on an artificial intelligence model, according to an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the improved test machine architecture according to an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram illustrating the improved testing process of an embodiment of the present invention.

[0025] Figure 4This is a schematic diagram of a chip testing system based on an artificial intelligence model, which is an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of the structure of the electronic device created by this invention. Detailed Implementation

[0027] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0028] To address the issue of inefficient general-purpose test machines in related technologies, which rely on manually developed test programs, this invention provides a chip testing method based on an artificial intelligence model and a general-purpose test machine. Figure 1 As shown, the method includes the following steps:

[0029] S101, based on the specification file of the chip under test, generates a test plan corresponding to the specification file through a trained specification understanding model;

[0030] S102, input the test plan and the parameter digital twin model of the general test machine into the trained parameter conversion model, and the parameter conversion model outputs the corresponding test circuit and test program, wherein the test circuit includes the editable circuit in the general test machine;

[0031] S103, based on the editable circuit and the test program, uses the trained firmware programming model to output a programming program that conforms to the test program for the test circuit;

[0032] S104 deploys programming and testing programs on a general-purpose test machine to test the chip under test.

[0033] The execution entity for the above steps can be the control device of a general-purpose test machine. Utilizing a three-tiered vertical artificial intelligence model—including a specification understanding model, a parameter conversion model, and a firmware programming model—it automatically understands the specification file of the chip under test and generates corresponding test programs based on the actual conditions of the general-purpose test machine. This allows for customized testing of the chip under test. Compared to manual development and programming, this significantly improves efficiency and reduces costs, thus solving the problem of low efficiency in related technologies where general-purpose test machines rely on manually developed test programs.

[0034] In addition, firmware programming can be performed on editable circuits, allowing general-purpose testers to edit the editable circuits more effectively based on the testing requirements of the chip under test. This maximizes the efficiency and utilization of the hardware, improving testing efficiency and accuracy, making the use of general-purpose testers more flexible, and avoiding the need for specialized technicians to perform firmware programming, which is not only costly but also has a longer development cycle.

[0035] In one embodiment, S101, based on the specification file of the chip under test, a test plan corresponding to the specification file is generated through a trained specification understanding model. Specifically, this includes receiving the input specification file, which contains information such as the electrical characteristics, pin definitions, and timing requirements of the chip; parsing the text and chart content through multimodal processing, wherein multimodal processing refers to converting text data into vector representation and fusing it with image data; and extracting key features using a pre-trained Transformer structure.

[0036] Automatically match test parameters to the selected template to generate a standard format test plan. This test plan includes a list of test items, parameter thresholds, and execution order. Matching is completed by filling in placeholders in the template to ensure that the output is in a structured matrix form.

[0037] Specifically, this generation process can be applied to different chip specifications, such as processor chips or memory chips. In the case of processor chips, the specification document may emphasize clock frequency and power consumption testing. The model will prioritize searching for high-frequency test templates and matching specific frequency values, such as 2.5GHz, as parameter thresholds, thereby forming a test plan that includes functional verification and performance evaluation.

[0038] For example, in one possible implementation, the read / write latency parameters, such as 10ns, are parsed from the memory chip's specification file. Relevant nodes for latency testing are retrieved through a knowledge graph, a latency scan template is selected, and a test plan is generated that includes a scan range from 5ns to 15ns. This ensures that the test covers potential defects, improves the comprehensiveness of the plan, and reduces manual analysis time by more than 50%.

[0039] In one embodiment, step S102 involves inputting the test plan and the parameter digital twin model of the general-purpose test machine into the trained parameter conversion model, and the parameter conversion model outputting the corresponding test circuit and test program, wherein the test circuit includes the editable circuit in the general-purpose test machine.

[0040] Specifically, this involves taking the test plan generated by S101 as input and combining it with a parametric digital twin model. This digital twin model is a virtual copy of a general-purpose test machine, including numerical simulations of hardware parameters such as clock speed and interface configuration. The test plan is then converted into a parametric circuit description using a parameter transformation model. This model uses reinforcement learning to optimize the transformation, with a reward function considering coverage (e.g., 95%) and time (e.g., less than 1ms). An editable circuit form is generated by iteratively adjusting the circuit parameters.

[0041] A corresponding test program is generated, which is an executable code sequence used to drive the parameterized circuit to perform test items. Simulation verification is performed using a digital twin model to check whether the simulated circuit behavior matches expectations, such as whether the voltage output is within the planned threshold.

[0042] In one embodiment, step S103, based on the editable circuit and the test program, uses a trained firmware programming model to output a programming program that ensures the test circuit conforms to the test program. Specifically, this includes extracting the logic unit configuration and timing requirements from the editable circuit. The logic unit configuration refers to the specific arrangement of gate circuits, registers, and interconnect resources used to implement the test function in the circuit, and the timing requirements refer to the maximum allowable value of signal propagation delay. This information is obtained by parsing the circuit description file.

[0043] Based on the extracted information, the firmware programming model is invoked for reinforcement learning iteration. The FPGA (Field-Programmable Gate Array) resource utilization rate is the state, the sub-module combination is the action, and the reward function considers timing convergence and power consumption balance. The iteration is repeated multiple times until an optimized circuit mapping scheme is generated.

[0044] The firmware-specific submodule library is retrieved, and suitable submodules for the test program are selected and combined. This library contains predefined hardware description language modules such as clock managers and signal generators. The selection process involves matching parameters in the test program, such as frequency and voltage thresholds. The combined modules form a complete programmable logic implementation. Hardware description language code is then generated and compiled into a binary firmware file.

[0045] For example, in one possible implementation, for a clock test scenario of a processor chip, the editable circuit includes a parameterized clock divider circuit. The test program specifies a division ratio of 4. The firmware programming model extracts the timing requirements of the circuit, such as a maximum delay of 5ns. Then, through reinforcement learning, iterative optimization of resource allocation is performed, and the combination of divider sub-modules in the library is selected. After generating HDL (Hardware Description Language) code, the firmware is compiled, which improves test efficiency by more than 30% because the timing path is optimized and reconfiguration time is reduced.

[0046] In one embodiment, the firmware programming model is trained based on a historical dataset, including a set of hardware description languages ​​for unit test functional modules and a set of corresponding constraint files. The pre-training phase learns the syntax of a general hardware description language, and the reinforcement phase optimizes for the dedicated modules of the chip test machine. Fine-tuning focuses on ensuring the correctness of the code functions. The resulting program can double the performance of the FPGA by reducing redundant logic.

[0047] For example, in one possible implementation, for read and write tests of memory chips, the editable circuit is defined as a parameterized bus interface, the test program includes read and write sequences, a bus arbitrator submodule retrieved from the model library, and firmware is generated after combination. Compared with general firmware, dedicated firmware simplifies interface design and reduces power consumption by 20% because AI optimizes resource allocation and avoids unnecessary buffers.

[0048] In one embodiment, after the programming program is output, IAP dynamic deployment is supported. IAP refers to application programming, which means loading firmware onto the FPGA at system runtime to achieve rapid customization, thus ensuring that the test circuit meets the test program requirements in real time.

[0049] For example, in one possible implementation, for analog signal testing of a sensor chip, the input circuit is a parametric ADC (Analog-to-Digital Converter), the program specifies a sampling rate of 100kHz, and the model is deployed via IAP after firmware generation. This improves test coverage by 40% because dynamic loading allows for real-time adjustment of circuit configuration based on different parameters, shortening the chip time-to-market.

[0050] Step S104 above deploys the programming and testing programs on a general-purpose testing machine for testing the chip under test. Specifically, the compatibility of the programming and testing programs can be confirmed first by checking file format and version matching to ensure that the programming and testing programs can be effectively loaded into the programmable control circuit of the general-purpose testing machine.

[0051] IAP technology is used to dynamically load programming programs onto the FPGA components of the test machine, enabling instant firmware updates without interrupting the test machine's operation. Test programs are deployed into the test machine's execution environment, and test parameters such as voltage thresholds and clock frequencies are set to match the specifications of the chip under test (DUT). Finally, the test sequence is initiated, input signals are applied to the DUT, and the output response is acquired and recorded to verify the chip's functionality.

[0052] In one embodiment, the process of deploying the programming program and the test program can be applied to the test scenario of a processor chip. For example, for a processor chip with a clock frequency of 1 GHz, the programming program is an AI-generated FPGA firmware that includes an optimized parameterized circuit for simulating a specific test environment. The test program includes serialized test instructions such as function verification and power consumption measurement.

[0053] First, the firmware is loaded into the test machine through the IAP mechanism, and the loading time is controlled within 10 seconds to ensure a quick response. Then, the test program is run to input signals to the chip for 1000 consecutive cycles, and it is monitored whether the output meets the threshold range defined in the specification. For example, the voltage output is stable at 3.3V ± 0.1V. This method significantly shortens the test preparation time and is beneficial to accelerating the chip iteration cycle.

[0054] For example, in another possible implementation, for the test of a memory chip, the programming program generates exclusive firmware to support high-bandwidth data transmission, and the test program focuses on the detection of read / write error rates. After deploying the programming program and the test program, the test machine performs a random access test on the chip, and the result with an error rate data lower than 0.001% is regarded as passing, thereby improving the test efficiency and reducing human errors.

[0055] In one embodiment, the specific process of dynamically loading using the IAP technology includes first backing up the current firmware, then transmitting a new firmware data packet, and activating it after verifying the integrity through a checksum. This loading mechanism allows the test machine to switch the firmware without restarting. For example, when testing different batches of chips, it can quickly adapt to specification changes, and the beneficial effect is to improve the flexibility and economy of the test system.

[0056] For example, considering the application of a sensor chip, after the programming program is deployed, the test program runs the environmental monitoring temperature parameter in the range from -40°C to 85°C, performs a durability test, and records that the average response time is 50 ms. This deployment method ensures the reliability and adaptability of the test. [[ID=**14]]

[0057] In one embodiment, the specific execution of starting the test sequence involves batch-processing chip samples. For example, input signals are applied to 10 chip samples simultaneously, and the pass rate is calculated after collecting data. If the pass rate exceeds 95%, it is regarded as batch qualified. This method reduces manual intervention through an automated sequence and is beneficial to cost control in mass production testing.

[0058] As an optional embodiment, based on the specification document of the chip under test, a test plan corresponding to the specification document is generated using a trained specification understanding model. This includes: extracting data from the specification document using the specification understanding model to obtain multimodal data, wherein the specification understanding model is a multimodal model, and the multimodal data includes multiple types of data, including at least one of the following: text type, chart type, and structured type; extracting the test items and test parameters required for testing the chip under test based on the multimodal data; searching for matching test plan engineering templates from a test plan template library based on the test items and test parameters; and generating a corresponding test plan based on the test items, test parameters, and corresponding test plan engineering templates.

[0059] In one embodiment, the specification understanding model receives an input specification document, which may contain a chip datasheet in PDF format, including text descriptions, performance charts, and parameter tables. The model utilizes a multimodal model to parse text-based data, chart-based data, and structured data.

[0060] For example, this multimodal extraction ensures the comprehensiveness of the data. For instance, when processing the specification document of a digital signal processor chip, the core frequency of 1.2GHz is first extracted from the text, then the peak power corresponding to the power consumption curve of 5W is parsed from the chart, and finally the number of pins of 144 is obtained from the structured table, thus forming a complete multimodal dataset. This is beneficial for the accurate extraction of subsequent steps, avoids the omission of single-modal processing, and improves the reliability of test plan generation.

[0061] In one embodiment, the above-described multimodal data is used to extract the test items and parameters required for testing the chip under test. Specifically, the multimodal data is input into an extraction module, which uses natural language processing technology to identify key test requirements. For example, in the case of an analog chip, the test items extracted from the multimodal data include noise testing and gain testing, with parameters of a noise floor of -90dB and a gain range of 20-40dB. This extraction process ensures the correspondence between test items and parameters, which is beneficial for improving test coverage.

[0062] The above process involves searching for matching test plan templates from a test plan template library based on the test items and test parameters. A similarity calculation method, such as cosine similarity, is used to compare the extracted test items and parameters with entries in the template library. The template with the highest matching degree is selected; for example, a standard ATE template is chosen for functional test items. This search mechanism quickly locates templates, which helps shorten the generation cycle. Based on the test items, test parameters, and the corresponding test plan template, a corresponding test plan is then generated.

[0063] As an optional embodiment, before extracting data from the specification file using the multimodal model of the specification understanding model to obtain multimodal data, the method further includes: performing a first-stage pre-training of the specification understanding model using a professional dataset in the chip field; performing a second-stage pre-training of the specification understanding model completed in the first stage using historical test cases; and after outputting a programming program that conforms to the test program for the test circuit based on the editable circuit and test program using the trained firmware programming model, the method further includes: obtaining corresponding test cases and dynamically adjusting the specification understanding model using the specification file. The first-stage pre-training of the specification understanding model is performed using a professional dataset in the chip field.

[0064] In one embodiment, the specialized dataset includes a chip-specific dataset containing electronic engineering corpora and specialized vocabulary. Initial parameter adjustments are made to the specification understanding model to ensure that the model initially grasps the basic structure and terminological relationships of chip specifications. Through historical test cases, chip specification documents are used to perform a second stage of pre-training on the specification understanding model completed in the first stage.

[0065] Specifically, historical test cases are broken down into test item sequences and parameter labels, which are then input into the model for parameter matching training. Based on key parameters in the chip specification file, such as voltage range and clock frequency, the model's retrieval logic for test templates is strengthened.

[0066] In one possible implementation, this second-stage pre-training can also handle multimodal inputs, such as specification documents combining text and charts. The model learns to extract patterns from historical cases, improving the parsing efficiency of complex chip documents and helping to shorten the overall test plan generation time. The model dynamically adjusts and trains the specification understanding model by acquiring corresponding test cases and specification documents.

[0067] In one embodiment, actual test logs are collected as test cases from test execution after the output programming program. The collected test cases are paired with the original specification file, and parameter deviation values, such as the difference between test coverage and the expected plan, are calculated. Model weights are adjusted based on the deviation values ​​to achieve dynamic fine-tuning, for example, reducing the extraction bias for low-frequency parameters. Dynamically adjusted training uses these test cases and the specification file to update the model, making it more focused on the accurate extraction of time-series correlated data during subsequent multimodal data extraction, thereby improving the reliability of firmware generation.

[0068] The aforementioned dynamic adjustment of model weights through test cases can also incorporate reinforcement learning mechanisms. The reward function considers test success rates, continuously optimizing the model's adaptability to new chip specifications. This facilitates data closure and improves long-term system performance. For sensor chip testing, dynamically adjusting training to handle historical biased cases ensures the model gradually reduces parameter matching errors, resulting in lower testing costs.

[0069] As an optional embodiment, the test plan and the fully parameterized digital twin model of the general-purpose test machine are input into a trained parameter conversion model, and the parameter conversion model outputs the corresponding test circuit and test program. This includes: inputting the test plan into the parameter conversion model, wherein the parameter conversion model is trained based on the fully parameterized digital twin model of the general-purpose test machine and historical test cases; and outputting the test plan, the test circuit, and the test program based on the fully parameterized digital twin model.

[0070] The test plan is input into the parameter conversion model, which is trained based on a fully parameterized digital twin model of a general-purpose test machine and historical test cases. The generated test plan is obtained, containing standard format outputs of chip test items and test parameters, such as a standardized test requirement matrix obtained from the specification understanding model. The test plan, along with the fully parameterized digital twin model of the general-purpose test machine, is used as input data to the trained parameter conversion model. The fully parameterized digital twin model is a virtual copy of the test machine's hardware structure, including a simulated representation of all configurable parameters such as clock frequency, signal paths, and resource allocation.

[0071] Digital twin models are used to perform joint simulation of circuits and programs, predict test results, and automatically optimize the code structure to improve efficiency if violations are found.

[0072] The output of the final test circuit and test program serves as input for subsequent firmware synthesis steps, ensuring that the entire process, from test plan to circuit program conversion, forms a closed loop, supporting rapid customization of chip adaptive testing.

[0073] In one embodiment, the above output process can significantly improve testing efficiency, for example by generating 3-5 candidate circuit schemes for selection, each scheme considering different resource allocations such as logic unit occupancy rates from 50% to 80%, and finally selecting the scheme with the highest coverage, thereby reducing the later debugging time.

[0074] The above parameter conversion model can use a reinforcement learning model. The comprehensive coverage of the reward function is above 95%, the testing time is less than 1 hour, and the cost is lower than the preset value. These factors support each other and form an efficient conversion chain.

[0075] The aforementioned co-simulation avoids actual hardware errors, such as analog circuits running programs in a digital twin, detecting potential problems like signal interference, optimizing and outputting reliable results, and supporting the stability of adaptive testing.

[0076] As an optional embodiment, before inputting the test plan into the parameter conversion model, the method further includes: obtaining the full test parameters of a general-purpose test machine, generating a fully parameterized digital twin model through multi-level modeling and model synthesis, wherein the full test parameters include hardware parameters, circuit parameters, and action parameters; based on the fully parameterized digital twin model, selecting historical test cases and test codes from the historical test data of the general-purpose test machine, training the parameter conversion model to obtain the parameter conversion model; after outputting the programming program that conforms to the test program for the test circuit using the trained firmware programming model according to the editable circuit and test program, the method further includes: obtaining the corresponding test cases and test codes to dynamically adjust and train the parameter conversion model.

[0077] In one embodiment, the full set of test parameters for a general-purpose test machine is acquired. A fully parameterized digital twin model is generated through multi-level modeling and model synthesis. These full test parameters include hardware parameters, circuit parameters, and action parameters. Specifically, this involves collecting the hardware parameters of the general-purpose test machine, such as test channel types and the number of channels for each type, channel numbers, the hardware function set for each type, processor frequency, memory capacity, and interface type. The values ​​of these parameters are obtained through a combination of manual configuration and autonomous scanning and identification by the test machine, forming an initial parameter set.

[0078] Circuit parameters are extracted, including signal timing, AC / DC parameters such as resolution and accuracy, time response, bandwidth, voltage and current thresholds, and impedance characteristics. These parameter values ​​are obtained by combining calibration data from the test machine with a large amount of real-world test case data. Simulation software is used to model circuit behavior, quantifying these parameters into vector representations. Action parameters are defined, such as the expected signal waveform for the test sequence execution, and the behavioral characteristics of signal interactions, including timing features and data transmission rates. The action flow is analyzed based on historical logs to form a parameter matrix. Through multi-level modeling, a low-level hardware layer model is first constructed, followed by a circuit layer model, and finally, an action layer model is synthesized. A model synthesis algorithm is used to fuse these layers into a fully parameterized digital twin model. Model synthesis involves parameter vector weighted averaging and constraint optimization to ensure that the model accurately reflects the behavior of the test machine.

[0079] For example, in a chip voltage testing scenario, hardware parameters such as processor frequency are set to 2GHz, circuit parameters include a voltage threshold of 1.2V, and action parameters include a test sequence execution time of 10ms. By generating a digital twin model through multi-level modeling, the impact of voltage fluctuations on the test can be simulated, improving the simulation accuracy of the model and thus increasing the conversion accuracy by more than 30% in subsequent training.

[0080] In one possible implementation, based on a fully parameterized digital twin model, historical test cases and test code are selected from historical test data of a general-purpose test machine to train the parameter conversion model, thus obtaining the parameter conversion model. Specifically, test cases with high parameter matching degree with the digital twin model, such as cases with similar hardware configurations, are screened from the historical database, and the corresponding test code is extracted for supervised learning training of the parameter conversion model.

[0081] In one embodiment, corresponding test cases and test code are obtained to dynamically adjust and train the parameter transformation model. Specifically, this includes collecting execution logs of the current test circuit and program, extracting key performance indicators such as coverage and execution time, selecting historical test cases similar to the current test, and comparing the differences in the test code. The gradient descent algorithm is used to dynamically adjust the model weights, and the parameter transformation model is fine-tuned based on new data to ensure the model adapts to the new chip specifications.

[0082] For example, in high-speed data transmission chip testing, after obtaining the corresponding cases, dynamically adjusting the training can reduce the conversion error rate by 20%. By continuously optimizing the model's ability to process circuit parameters through feedback, a significant improvement in testing efficiency can be achieved.

[0083] As an optional embodiment, before outputting a programming program that conforms to the test program using a trained firmware programming model based on the editable circuit and the test program, the method further includes: inputting the test program and the editable circuit into the firmware programming model, wherein the firmware programming model is trained based on the programming knowledge data of the control chip of the editable circuit; selecting a firmware programming submodule based on the editable circuit from the firmware programming submodule library of the control chip by the conversion model, wherein the firmware programming submodule library includes multiple firmware programming submodules, which are used to implement different sub-functions; and generating a programming program by combining the firmware programming submodules and verifying resource conflicts.

[0084] In one embodiment, a test program and an editable circuit are input into a firmware programming model, which is trained based on programming knowledge data of the control chip of the editable circuit. Specifically, the firmware programming model is trained using pre-collected programming knowledge data, including the hardware description language code set of the control chip, timing constraint files, and functional verification test cases. The training process is divided into a general syntax learning phase and a dedicated module reinforcement phase to ensure that the model can understand the logical structure of the input test program.

[0085] Based on the input test program, the firmware programming model parses the test items and parameters in the program, such as extracting the chip pin configuration and timing requirements, as the basis for subsequent selection.

[0086] In one embodiment, a conversion model selects a firmware programming submodule for the test program from a firmware programming submodule library of editable circuits. This library includes multiple firmware programming submodules, each implementing different sub-functions. Specifically, the conversion model first analyzes the sub-functional requirements of the test program, such as signal generation, data acquisition, and error detection. Then, it searches the submodule library for matching items. The submodule library contains predefined modules such as a clock divider module for timing control, a data buffer module for storing intermediate results, and a protocol conversion module for adapting to different interfaces. The selection process uses similarity calculations to ensure that the matching degree between the submodule and the test program requirements is higher than a preset threshold, such as 0.85, thereby achieving automatic selection.

[0087] In one embodiment, a programming program is generated by combining firmware programming submodules and verifying resource conflicts. Specifically, selected submodules are logically combined, for example, by connecting them into a complete circuit using a hardware description language. Then, resource conflict verification is performed. The verification process checks the occupancy of the FPGA's logic cells, memory blocks, and I / O pins. If conflicts exist, the module layout is adjusted, and finally, a conflict-free programming program, such as a bitstream file, is generated.

[0088] For example, in processor chip performance testing, the combined sub-modules implement multi-threaded data injection, and the programming program generated after verifying resource conflicts can optimize FPGA utilization to 95%, significantly improving test accuracy and speed, and helping to shorten the chip iteration cycle.

[0089] In one possible implementation, for analog signal testing of sensor chips, the data acquisition and filtering submodules are combined. After verifying that there are no memory block conflicts, the program supports real-time data processing. This can reduce the test error rate by 20% and enhance the system's adaptability.

[0090] As an optional embodiment, before inputting the test program and editable circuit into the firmware programming model, the method further includes: performing a first-stage pre-training of the firmware programming model using programming knowledge data of the control chip of the editable circuit; performing a second-stage pre-training of the firmware programming model using the test program and the firmware programming sub-module library of the control chip; after outputting a programming program that conforms to the test program for the test circuit using the trained firmware programming model based on the editable circuit and the test program, the method further includes: obtaining the corresponding programming program and updating the firmware programming sub-module library; and dynamically adjusting and training the firmware programming model using the test program and the updated firmware programming sub-module library.

[0091] The firmware programming model undergoes a first-stage pre-training process using programming knowledge data from the control chip of the programmable circuit. In one embodiment, programming knowledge data from the control chip is first collected. This data includes basic syntax rules of the hardware description language and general constraints of the FPGA architecture, such as timing requirements and resource allocation principles. This data is then input into the firmware programming model for pre-training. By learning this foundational knowledge, the firmware programming model builds initial programming capabilities, ensuring efficient handling of complex tasks in subsequent stages.

[0092] Specifically, programming knowledge data is organized into a structured dataset, including code examples and architecture documentation. Gradient descent algorithms are used to adjust model parameters, enabling the model to grasp programming fundamentals. For example, in chip testing scenarios, this pre-training allows the firmware programming model to quickly understand the FPGA's logic unit configuration, thus laying the foundation for generating test firmware and improving overall efficiency.

[0093] The firmware programming model undergoes a second stage of pre-training using a test program and the firmware programming submodule library of the control chip. In one embodiment, enhanced pre-training is performed by combining the specific instruction sequence of the test program with predefined modules in the firmware programming submodule library, such as clock management and signal processing modules. The firmware programming model learns how to map the test program to combinations of submodules, optimizing parameters through multiple iterations.

[0094] Key parameters, such as test timing and data flow, are extracted from the test program. Submodule libraries are retrieved to match corresponding components, and the assembly process is simulated to train the firmware programming model. For example, this pre-training enables the firmware programming model to automatically select the most suitable submodule when generating firmware, reducing manual intervention and improving the flexibility of adaptive chip testing.

[0095] After outputting a programming program that conforms to the test program based on the editable circuit and test program, using a trained firmware programming model, the corresponding programming program is obtained, and the firmware programming submodule library is updated. In one embodiment, after outputting the programming program, its structure and performance indicators, such as resource utilization and execution speed, are analyzed, and this information is then incorporated into the update of the firmware programming submodule library. For example, if the programming program introduces new signal routing optimizations, this is added as a new submodule to add to or modify an existing module, ensuring the continuous enrichment of the firmware programming submodule library.

[0096] As an optional embodiment, the programming program and test program are deployed on a general-purpose test machine to test the chip under test, including: controlling the general-purpose test machine to load the programming program into the control chip of the editable circuit; when the chip under test is connected, responding to the start test command, automatically running the test program, controlling the general-purpose test machine to test the chip under test according to the corresponding test plan; acquiring test data, generating a test report, and sending it to the display interface for display.

[0097] The general-purpose test machine loads the programming program into the control chip of the programmable circuit. During the writing process, the test machine's built-in verification unit automatically verifies the integrity of each data block. If an error is detected, the data block is retransmitted, thus ensuring the reliability of the loading. After loading is complete, the control chip restarts and applies the new firmware, reconfiguring the test circuit. This method allows the test machine to quickly adapt to the testing requirements of different chips. For example, when processing high-frequency signal chips, the loaded firmware optimizes timing paths to reduce latency.

[0098] Once the chip under test is connected, it responds to the start test command, automatically runs the test program, and controls the general test machine to test the chip under test according to the corresponding test plan.

[0099] In one embodiment, the process begins by detecting the physical connections of the chip under test (DUT). Once the connections are established, the system verifies the connection stability through pin scanning. Next, in response to a user-triggered or automatically triggered start test command (which may originate from the user interface), the system immediately loads and executes a test program generated by a parametric transformation model, containing specific test sequences such as voltage tests and functional verifications.

[0100] The general-purpose test machine controls signal generation and data acquisition according to the test plan. For example, for memory chips, the test plan may include read-write cycle tests, and the system automatically adjusts parameters to match the chip specifications. The entire testing process is driven by the loaded firmware to ensure high testing efficiency. For example, in multi-core processor chip testing, the firmware processes the load tests of multiple cores in parallel, reducing the total test time.

[0101] The system acquires test data, generates a test report, and sends it to a display interface for presentation. In one embodiment, test data is extracted from the acquisition buffer of a general-purpose test machine. This data includes voltage values, current readings, functional response timings, and pass / fail results. The system then summarizes and processes the data to generate a report organized in a standard format, containing pass / fail indicators and detailed logs. The report is then sent to the display interface via an internal bus for real-time visualization, such as presenting test coverage as a chart on the user interface, facilitating engineers' rapid evaluation of chip performance.

[0102] It should be noted that this embodiment also provides an optional implementation method, which will be described in detail below.

[0103] This invention proposes an AI-based adaptive chip testing system, characterized by the application of a "three-level vertical large model application architecture" to understand test specifications, automatically generate test code, and automatically generate firmware programs.

[0104] Specification Understanding Model: Based on a multimodal model, input the chip's specification sheet (datasheet / design document), complete the analysis of chip test items and test parameters, search the test template library, automatically select applicable test templates, automatically match test parameters, apply standardized test solution engineering templates, and output a test plan in a standard format.

[0105] Parameter conversion model: Based on the digital twin of the fully parameterized test machine model, the test plan is converted into a parameterized circuit that the test machine can implement and test code that the parameterized circuit can execute, and simulation verification is performed using the digital twin of the test machine model.

[0106] Firmware programming model: Combining reinforcement learning model with FPGA architecture knowledge, the firmware-specific sub-module library of the test machine is retrieved, and suitable firmware sub-modules are selected and combined to build the parameterized circuit into the programmable logic implementation of the FPGA. This generates a dedicated test machine firmware adapted to the chip under test. The firmware is then deployed on the programmable control circuit of the test system through IAP, enabling rapid customization of the chip test system.

[0107] Technical benefits include enabling AI-driven rapid FPGA programming: AI automatically generates test machine firmware, reducing the skill requirements for test machine firmware development engineers; AI empowerment enables the rapid development of customized test machine firmware for each chip under test project; furthermore, it enables the rapid development of customized test machine firmware for each chip project's test plan; and it achieves the performance and ease of use of a dedicated test machine on a general-purpose test machine hardware architecture.

[0108] Improvements to the test machine architecture: such as Figure 2 As shown, customized dedicated test machine firmware can optimize hardware performance and execution efficiency; customized dedicated test machine firmware can simplify the design of test machine software system; and test records from massive cases form high-value data, which is used to recursively train large AI models, forming a closed loop of learning data for the chip adaptive testing system.

[0109] Improved test development process: Test machine firmware is generated directly based on test objectives, allowing users to break free from traditional test program development processes and reduce reliance on manpower and debugging costs; Test machine model digital twins are used to predict test results through AI system-level simulation; Test machine software is simplified into an AI dialogue user interface that can understand the chip data submitted by users and analyze the completeness of the content.

[0110] Specifically, the model training method, specification understanding model training: Dataset: Technical terminology (basic knowledge such as technical vocabulary); historical test cases (validated test schemes, labeled with key parameters); chip specification documents (labeled with key parameters). Pre-training: First stage: Domain-adaptive training (training with electronic engineering corpus). Second stage: Test knowledge reinforcement (continuing training using the test base dataset). Fine-tuning: Accuracy of key parameter extraction.

[0111] Parameter transformation model training: Dataset: Digital twin of a fully parameterized test machine model; historical test cases (test code). Pre-training: Phase 1: Learning basic syntax and structure. Phase 2: Learning test pattern generation logic. Fine-tuning: Improving the accuracy of converting test instructions to parameterized circuit test code.

[0112] Firmware programming model training: Dataset: Hardware description language set for unit test functional modules; accompanying test cases and constraint files. Pre-training: Phase 1: General hardware description language training. Phase 2: Reinforcement training of firmware-specific modules on the chip test machine. Fine-tuning: Focus on optimizing the correctness of code functionality.

[0113] like Figure 3 As shown, the system workflow is as follows: 1. Specification understanding: Input the chip specification document; the system automatically parses the document and outputs a standard format test plan (including chip test items and test parameters) for chip testing requirements.

[0114] 2. Parametric test circuit and program generation: Import the digital model of the test machine specifications and parameters, and import the confirmed chip test plan; the system automatically outputs dedicated parametric test circuits and corresponding dedicated test program code that can be used for digital simulation verification according to the test item.

[0115] 3. Firmware synthesis: Input parameterized test circuit model; dedicated test program code; the system automatically generates hardware description language and automatically compiles it into binary files for application to FPGA chips.

[0116] 4. Field Application: In the chip testing phase, the corresponding firmware is invoked according to the testing requirements, and the FPGA firmware is dynamically deployed through IAP technology to complete the corresponding test tasks.

[0117] Specification understanding model: Supports multi-format document input; integrates a test knowledge graph containing big data entities; retrieves test template library, automatically selects applicable test templates, and automatically matches test parameters; outputs a standardized test requirement matrix (test project + test plan).

[0118] Parameter Transformation Model: Based on a digital twin of a fully parameterized test machine model, the test plan is transformed into a parameterized circuit implementable by the test machine and test code executable by the parameterized circuit. Simulation verification is then performed using the digital twin of the test machine model. The test plan is optimized through reinforcement learning, with the reward function comprehensively considering coverage, time, and cost; 3-5 candidate solutions are generated for designers to choose from.

[0119] Firmware programming model: Directly generates optimized bitstreams or synthesizable HDL code; supports mainstream FPGA platforms; the generated dedicated firmware can double the performance of FPGA implementations compared to general-purpose firmware.

[0120] IAP dynamic firmware loading mechanism: Each test plan in the chip test project corresponds to an independent firmware image.

[0121] Adaptive testing includes: adaptively parsing chip documentation through a specification understanding model to generate test requirements; using a solution generation model to develop optimized test plans; generating dedicated test firmware through a firmware synthesis model; and dynamically loading the firmware to execute tests.

[0122] Firmware generation steps: Analyze FPGA architecture characteristics and optimize resource allocation; search the test machine firmware-specific submodule library, independently select suitable firmware submodules for combination and construction, and build a complete firmware implementation. Consider timing convergence constraints and automatically adjust placement and routing; output a verified bitstream file.

[0123] It can also collect test log data and extract high-value data; continuously optimize model parameters through deep learning; and update the model version monthly to improve accuracy.

[0124] This embodiment discloses an AI-based adaptive chip testing system and method, which achieves fully automated generation from chip specifications to test machine firmware through a three-dimensional vertical large-scale model architecture. The system includes a specification understanding model, a parameter conversion model, and a firmware programming model. Combined with a fully parameterized digital twin system, it makes it possible to develop dedicated test machine firmware for each chip under test, shortening the development cycle of chip testing projects by more than 50%, significantly improving the performance and operating efficiency of test machine hardware resources, and reducing testing costs by 40-60%. The invention's specially designed IAP dynamic firmware loading mechanism supports highly efficient reconfiguration, with each chip testing project or chip testing plan corresponding to exclusive firmware, solving the problems of high complexity and low efficiency of general-purpose firmware in traditional testing systems.

[0125] like Figure 4 As shown, an embodiment of the present invention also provides a chip testing system based on an artificial intelligence model-driven universal test machine, comprising: a universal test machine 41, and a control device 42 for controlling the universal test machine; the universal test machine 41 includes a test circuit 411, which includes an editable circuit 412; the control device 42 includes a specification understanding model 421, a parameter conversion model 422, and a firmware programming model 423, wherein the specification understanding model 421 is connected to the parameter conversion model 422, and the parameter conversion model 422 is connected to the firmware programming model 423; the specification understanding model 421 is used to generate a test plan corresponding to the specification file of the chip under test; the parameter conversion model 422 is used to output a corresponding test circuit and test program based on the test plan and the parameter digital twin model of the universal test machine; the firmware programming model 423 is used to output a programming program that conforms to the test program based on the editable circuit and the test program; the control device 42 is also used to deploy the programming program and the test program on the universal test machine to test the chip under test.

[0126] The system utilizes a three-tiered vertical artificial intelligence model, including a specification understanding model, a parameter conversion model, and a firmware programming model, to automatically understand the specification documents of the chip under test and generate corresponding test programs based on the actual situation of the general test machine. This allows for customized testing of the chip under test. Compared to manual development and programming, this not only greatly improves efficiency but also reduces costs. It also solves the problem of low efficiency in related technologies where general test machines rely on manual development of test programs.

[0127] In addition, firmware programming can be performed on editable circuits, allowing general-purpose testers to edit the editable circuits more effectively based on the testing requirements of the chip under test. This maximizes the efficiency and utilization of the hardware, improving testing efficiency and accuracy, making the use of general-purpose testers more flexible, and avoiding the need for specialized technicians to perform firmware programming, which is not only costly but also has a longer development cycle.

[0128] Embodiments of the present invention also provide a non-transitory machine-readable medium storing computer instructions, characterized in that the computer instructions are used to cause a computer to perform the method according to any one of the foregoing claims.

[0129] An embodiment of the present invention also provides a computer program product, including a computer program / instructions, characterized in that, when the computer program / instructions are executed by a processor, they implement the method described above.

[0130] An embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform the method of the embodiment of the present invention.

[0131] refer to Figure 5 The present invention will now describe a structural block diagram of an electronic device that can serve as an embodiment of the present invention, serving as an example of a hardware device applicable to various aspects of the present invention. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0132] like Figure 5 As shown, the electronic device includes a computing unit 501, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. The RAM 503 may also store various programs and data required for the operation of the electronic device. The computing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0133] Multiple components in the electronic device are connected to I / O interface 505, including: input unit 506, output unit 507, storage unit 508, and communication unit 509. Input unit 506 can be any type of device capable of inputting information into the electronic device. Input unit 506 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of the electronic device. Output unit 507 can be any type of device capable of presenting information and may include, but is not limited to, a display, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 508 may include, but is not limited to, disks and optical discs. Communication unit 509 allows the electronic device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, and / or wireless communication transceivers, such as Bluetooth devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0134] The computing unit 501 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, CPUs, graphics processing units (GPUs), various special-purpose artificial intelligence (AI) computing units, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the various methods and processes described above. For example, in some embodiments, the method embodiments of the present invention can be implemented as computer programs tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed on an electronic device via ROM 502 and / or communication unit 509. In some embodiments, the computing unit 501 can be configured to perform the methods described above by any other suitable means (e.g., by means of firmware).

[0135] Computer programs for implementing the methods of embodiments of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0136] In the context of embodiments of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable signal medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, or infrared systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0137] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0138] The steps described in the method embodiments provided by the present invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0139] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0140] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A chip testing method using a general-purpose test machine based on an artificial intelligence model, characterized in that, include: Based on the specifications of the chip under test, a test plan corresponding to the specifications is generated using a trained specifications understanding model. The test plan and the parameter digital twin model of the general test machine are input into the trained parameter conversion model, and the parameter conversion model outputs the corresponding test circuit and test program, wherein the test circuit includes the editable circuit in the general test machine; Based on the editable circuit and the test program, using the trained firmware programming model, a programming program that conforms to the test program is output for the test circuit; The programming program and the testing program are deployed on the general-purpose testing machine to test the chip under test; Before generating a test plan corresponding to the specification document based on the specification document of the chip under test using a trained specification understanding model, the method further includes: performing a first-stage pre-training of the specification understanding model using a professional dataset in the chip field; performing a second-stage pre-training of the specification understanding model completed in the first stage using historical test cases; and after outputting a programming program that conforms to the test program for the test circuit using a trained firmware programming model based on the editable circuit and the test program, the method further includes: acquiring corresponding test cases and dynamically adjusting and training the specification understanding model using the specification document. Before inputting the test plan and the parameter digital twin model of the general-purpose test machine into the trained parameter conversion model, and before the parameter conversion model outputs the corresponding test circuit and test program, the method further includes: obtaining the full test parameters of the general-purpose test machine, generating a fully parameterized digital twin model through multi-level modeling and model synthesis, wherein the full test parameters include hardware parameters, circuit parameters, and action parameters; based on the fully parameterized digital twin model, selecting historical test cases and test code from the historical test data of the general-purpose test machine, and training the parameter conversion model to obtain the parameter conversion model; after outputting the test circuit conforming to the test program using the trained firmware programming model according to the editable circuit and the test program, the method further includes: obtaining the corresponding test cases and the test code to dynamically adjust and train the parameter conversion model; Before outputting a programming program that conforms to the test program using the trained firmware programming model based on the editable circuit and the test program, the method further includes: performing a first-stage pre-training of the firmware programming model using the programming knowledge data of the control chip of the editable circuit; performing a second-stage pre-training of the firmware programming model using the test program and the firmware programming submodule library of the control chip; after outputting a programming program that conforms to the test program using the trained firmware programming model based on the editable circuit and the test program, the method further includes: obtaining the corresponding programming program and updating the firmware programming submodule library; and dynamically adjusting and training the firmware programming model using the test program and the updated firmware programming submodule library.

2. The method according to claim 1, characterized in that, Based on the specifications of the chip under test, a test plan corresponding to the specifications is generated using a trained specifications understanding model, including: The specification understanding model is used to extract data from the specification file to obtain multimodal data. The specification understanding model is a multimodal model, and the multimodal data includes multiple types of data, including at least one of the following: text type, chart type, and structured type. Based on the multimodal data, the test items and test parameters required for testing the chip under test are extracted; Based on the test items and test parameters, search for a matching test plan project template from the test plan template library; Based on the test items, test parameters, and corresponding test scheme project templates, generate the corresponding test plan.

3. The method according to claim 1, characterized in that, The test plan and the fully parameterized digital twin model of the general-purpose test machine are input into the trained parameter conversion model, which then outputs the corresponding test circuit and test program, including: The test plan is input into the parameter conversion model, wherein the parameter conversion model is trained based on the fully parameterized digital twin model of the general test machine and historical test cases; The conversion model outputs the test plan, which includes test circuits and test procedures based on the fully parameterized digital twin model.

4. The method according to claim 1, characterized in that, Based on the editable circuit and the test program, before outputting a programming program that conforms to the test program using the trained firmware programming model, the method further includes: The test program and the editable circuit are input into the firmware programming model, wherein the firmware programming model is trained based on the programming knowledge data of the control chip of the editable circuit; The conversion model selects the firmware programming submodule based on the editable circuit from the firmware programming submodule library of the control chip. The firmware programming submodule library includes multiple firmware programming submodules, which are used to implement different sub-functions. The programming program is generated by combining the firmware programming submodules and verifying resource conflicts.

5. The method according to claim 1, characterized in that, Deploying the programming program and the testing program on the general-purpose testing machine to test the chip under test includes: The general-purpose test machine is controlled to load the programming program into the control chip of the editable circuit; Once the chip under test is connected, the test program is automatically run in response to the start test command, and the general-purpose test machine is controlled to test the chip under test according to the corresponding test plan. Acquire test data, generate test reports, and send them to the display interface for display.

6. A chip testing system based on a universal test machine using an artificial intelligence model, characterized in that, include: A general-purpose testing machine, and a control device for controlling the general-purpose testing machine; The general-purpose test machine includes a test circuit, and the test circuit includes an editable circuit. The control device includes a specification understanding model, a parameter conversion model, and a firmware programming model. The specification understanding model is connected to the parameter conversion model, and the parameter conversion model is connected to the firmware programming model. The specification understanding model is used to generate a test plan corresponding to the specification file of the chip under test. The parameter conversion model is used to output the corresponding test circuit and test program based on the test plan and the parameter digital twin model of the general test machine; The firmware programming model is used to output a programming program that conforms to the test program based on the editable circuit and the test program; The control device is also used to deploy the programming program and the test program on the general-purpose test machine to test the chip under test; The training method for the specification understanding model includes: performing a first-stage pre-training of the specification understanding model using a professional dataset in the chip field; performing a second-stage pre-training of the specification understanding model completed in the first stage using historical test cases and chip specification documents; and after outputting a programming program that conforms to the test program for the test circuit using the trained firmware programming model based on the editable circuit and the test program, the method further includes: acquiring corresponding test cases and dynamically adjusting and training the specification understanding model using the specification documents. The training method for the parameter conversion model includes: acquiring all test parameters of the general-purpose test machine; generating a fully parameterized digital twin model through multi-level modeling and model synthesis, wherein the all test parameters include hardware parameters, circuit parameters, and action parameters; based on the fully parameterized digital twin model, selecting historical test cases and test codes from the historical test data of the general-purpose test machine, and training the parameter conversion model to obtain the parameter conversion model; after outputting a programming program that conforms to the test program for the test circuit using the trained firmware programming model according to the editable circuit and the test program, the method further includes: acquiring corresponding test cases and dynamically adjusting and training the parameter conversion model using the test code; The training method for the firmware programming model includes: performing a first-stage pre-training of the firmware programming model using the programming knowledge data of the control chip of the editable circuit; performing a second-stage pre-training of the firmware programming model using the test program and the firmware programming submodule library of the control chip; and after outputting a programming program that conforms to the test program for the test circuit based on the editable circuit and the test program using the trained firmware programming model, the method further includes: obtaining the corresponding programming program and updating the firmware programming submodule library; and dynamically adjusting and training the firmware programming model using the test program and the updated firmware programming submodule library.

7. An electronic device, comprising: A processor and a memory storing a program, characterized in that the program includes instructions that, when executed by the processor, cause the processor to perform the method according to any one of claims 1 to 5.

8. A non-transitory machine-readable medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 5.

9. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the method of any one of claims 1 to 5.

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