Server display control system and method, apparatus, device, medium, product

Abstract

The application discloses a server display control system and method, device, equipment, medium and product, relates to the technical field of servers, and through the first operating system with a faster starting rate on the substrate management controller, the judgment process of entering display control right after starting is entered, compared with the basic input / output system, the display control right can be quickly taken over, display output can be controlled as soon as possible after the server is started, and the switching of the display control right is performed after the basic input / output system completes initialization of the display module; in the judgment process of the display control right of the first operating system, the first operating system determines the ownership of the display control right according to the starting type of the server, adapts to various scenes such as normal starting and restart after abnormal power failure of the server, and ensures the timing consistency of the switching of the display control right under various running scenes of the server.

Description

Technical Field

[0001] This invention relates to the field of server technology, and in particular to server display control systems, methods, devices, equipment, media, and products. Background Technology

[0002] Server display control relies on the Basic Input / Output System (BIOS) completing the necessary hardware initialization before it can take over display output. When the server's hardware configuration is complex, the BIOS's hardware initialization process is lengthy, which can result in the server having no display for an extended period after power-on, making it impossible for users to perceive the server's system status.

[0003] How to control the display output as soon as possible after the server is powered on is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This invention provides a server display control system and method, apparatus, equipment, medium, and product to at least solve the problem of slow display output after the server is powered on in related technologies.

[0005] This invention provides a server display control system, including: a baseboard management controller and a basic input / output system;

[0006] The baseboard management controller includes a first operating system and a second operating system. After the baseboard management controller is powered on, the first operating system starts before the second operating system. After starting, it identifies the startup type of the server. If the startup type is a cold start, it calls the server's display module to control the display to show the first information. If the startup type is a warm restart, it maintains the display control of the display before the power failure.

[0007] After the basic input / output system starts up, it executes the server's power-on self-test process. After completing the initialization of the display module, it switches the display control rights with the baseboard management controller. After the switch is completed, it calls the display module to control the display to show the second information.

[0008] The present invention also provides a server display control method, applied to a baseboard management controller, comprising:

[0009] After power-on, the first operating system starts before the second operating system;

[0010] After the first operating system starts, it identifies the startup type of the server. If the startup type is a cold start, it calls the server's display module to control the display to show the first information; if the startup type is a warm restart, it maintains the display control of the display before the power failure.

[0011] After the server's basic input / output system starts up and completes the initialization of the display module, the first operating system switches the display control to the basic input / output system, so that the basic input / output system calls the display module to control the display to show the second information.

[0012] The present invention also provides a server display control device applied to a baseboard management controller, wherein the baseboard management controller includes a first operating system and a second operating system; the server display control device includes:

[0013] The identification unit is used to identify the startup type of the server after the baseboard management controller is powered on and the first operating system starts before the second operating system.

[0014] The display control unit is used to call the server's display module to control the display to show the first information if the startup type is cold start; and to maintain the display control of the display before the power failure if the startup type is warm restart.

[0015] A switching unit is used to switch display control to the basic input / output system after the first operating system starts up and completes the initialization of the display module on the server, so that the basic input / output system calls the display module to control the display to show the second information.

[0016] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described server display control methods.

[0017] The present invention also provides a non-volatile storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described server display control methods.

[0018] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described server display control methods.

[0019] Through this invention, the first operating system, which has a faster startup speed on the baseboard management controller, enters the display control determination process immediately after startup. Compared to the basic input / output system, it can quickly take over display control, enabling rapid control of the display output after the server is powered on. In contrast, the basic input / output system performs a power-on self-test process and completes the initialization of the display module before switching display control. In the first operating system's display control determination process, the first operating system identifies the server's startup type. If the startup type is a cold start, it calls the server's display module to control the display to show the first information. If the startup type is a warm restart, it maintains the display control of the display before the power failure, thus adapting to various scenarios such as normal server startup and restart after abnormal power failure, ensuring the consistency of the timing of display control switching under various operating scenarios. Attached Figure Description

[0020] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 An architecture diagram of a server display control system provided for an embodiment of the invention;

[0022] Figure 2 A server startup flowchart provided as an embodiment of the present invention;

[0023] Figure 3 A server shutdown flowchart provided as an embodiment of the present invention;

[0024] Figure 4 A power-on / off flowchart of a basic input / output system provided in an embodiment of the present invention;

[0025] Figure 5 A flowchart of a server display control method provided in an embodiment of the present invention;

[0026] Figure 6 A flowchart of another server display control method provided in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0028] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0029] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Here, we will first explain some key terms used in the embodiments of the present invention.

[0031] In traditional server architectures, during the initialization process of the Basic Input / Output System (BIOS), once the BIOS detects the graphics card, the video graphics array (VGA) controls the display of self-test information. After entering the Operating System (OS), display control is transferred to the OS, which then controls the graphics card's video graphics array based on the graphics card driver. Therefore, whether a server can display an image after booting up typically depends on how long it takes for the BIOS to complete the initialization of the graphics card's VGA after starting its power-on self-test.

[0032] Obviously, the time from server startup to displaying a screen varies depending on the server configuration. For example, under a certain processor architecture and at full configuration, it can take up to 4 minutes, resulting in users experiencing a long period of black screen and being unable to perceive the system status in real time. In addition, the initialization time also varies significantly when the server is equipped with different processor platforms (from 12 seconds to 4 minutes).

[0033] The above situations can cause users to experience black screens of varying durations after the server is powered on, sometimes requiring a long wait, and making it impossible to determine whether the server is in a normal startup state or experiencing an abnormality. In other words, users may not receive a response for an extended period after pressing the power button, resulting in a poor user experience.

[0034] To address the issue of slow display output after server startup, the server display control system, method, apparatus, device, medium, and product provided in this invention utilize a first operating system on the baseboard management controller with a faster startup speed. Upon startup, the first operating system immediately enters the display control determination process, allowing for faster takeover of display control compared to the basic input / output system. This enables rapid control of display output after server startup, whereas the basic input / output system performs a power-on self-test process and completes the initialization of the display module before switching display control. In the first operating system's display control determination process, the first operating system identifies the server's startup type. If the startup type is a cold start, it invokes the server's display module to control the display to show the first information. If the startup type is a warm restart, it maintains the display control as it did before power failure, thus adapting to various scenarios such as normal server startup and restart after abnormal power failure, ensuring the consistency of display control switching timing under various operating conditions.

[0035] Figure 1 This is an architecture diagram of a server display control system provided in an embodiment of the present invention.

[0036] like Figure 1 As shown, the server display control system provided in this embodiment of the invention may include: a baseboard management controller and a basic input / output system;

[0037] The baseboard management controller includes a first operating system and a second operating system. After the baseboard management controller is powered on, the first operating system starts before the second operating system. After starting, it identifies the startup type of the server. If the startup type is a cold start, it calls the server's display module to control the display to show the first information. If the startup type is a warm restart, it maintains the display control of the display before the power failure.

[0038] After the basic input / output system starts up, it executes the server's power-on self-test process. After completing the initialization of the display module, it switches the display control between the display module and the baseboard management controller. After the switch is completed, it calls the display module to control the display to show the second information.

[0039] It should be noted that the "baseboard management controller" in this embodiment of the invention can refer to a baseboard management controller board, which includes, in addition to the out-of-band monitoring master controller, various bus controllers, programmable logic units, memory, and other components. The "baseboard management controller" in this embodiment of the invention can also refer to the out-of-band monitoring master controller on the baseboard management controller board, which can be a single-core processor or a multi-core processor. In this embodiment of the invention, the baseboard management controller or the out-of-band monitoring master controller on the baseboard management controller board can be an ARM processor, on which the baseboard management controller's management system runs.

[0040] In this embodiment of the invention, the display module can be the display controller in the graphics card.

[0041] In this embodiment of the invention, the first operating system can be a real-time operating system, and the second operating system can be a non-real-time operating system. The first operating system enables the processor of the baseboard management controller to have real-time task processing capabilities. The second operating system undertakes the running responsibilities of the main operating system of the baseboard management controller, specifically including loading and scheduling the operating system kernel of the baseboard management controller, initializing and deploying user-mode services, and executing core functional modules such as server monitoring and management.

[0042] As a standalone system, the baseboard management controller needs to run an operating system capable of providing full operation, such as Contiki, HeliOS, or Linux. These operating systems typically employ fair task scheduling algorithms, which require shared processor time as the number of threads and processes increases, leading to uncertainty in task debugging; they can be termed non-real-time operating systems. For example, Linux is a multi-user, multi-tasking operating system based on the Portable Operating System Interface (POSIX), supporting multi-threading and multiple CPUs. Its powerful functionality supports the various tasks required by the baseboard management controller. However, a disadvantage of these non-real-time operating systems is the relatively long boot time required during server startup.

[0043] A baseboard management controller equipped with a real-time operating system (RTOS) and a non-real-time operating system can have the RTOS start and execute tasks before the non-real-time operating system during the server startup phase. Based on different control principles, when running on a processor, the RTOS typically has a higher response rate than the non-real-time operating system.

[0044] In this embodiment of the invention, the first operating system and the second operating system do not limit the type or priority of the operating system. The only difference between them is the different response rates after the baseboard management controller is powered on, which leads to different startup sequences.

[0045] In some optional embodiments of the present invention, the first operating system can be a program with real-time functionality, including a real-time operating system or bare-metal program code capable of implementing real-time functionality. The type of real-time operating system may include, but is not limited to, FreeRTOS, RTLinux, or real-time operating systems in other embedded systems.

[0046] The second operating system can include, but is not limited to, Contiki, HeliOS, and Linux.

[0047] In some optional embodiments of the present invention, the first operating system and the second operating system may both run on the core processor of the baseboard management controller and communicate with each other through inter-core communication. In other optional embodiments of the present invention, the first operating system and the second operating system may also have one running on the core processor of the baseboard management controller and the other running on the coprocessor of the baseboard management controller; for example, the first operating system runs on the coprocessor and the second operating system runs on the core processor.

[0048] In some optional embodiments of the present invention, a dual-system RTOS / Linux can run in the baseboard management controller. When using a multi-core baseboard management controller, one core processor can run the RTOS, while the remaining core processors run the Linux system.

[0049] During server cold boot, the Basic Input / Output System (PIS) needs to sequentially perform low-level operations such as Hardware Self-Test (POST), device enumeration, and memory initialization, resulting in significant delays in display signal output under traditional architectures. Simultaneously, the main operating system boot process of the baseboard management controller involves multi-level driver loading and service initialization, the time consumed of which also restricts the display output response speed. Engineering verification has shown that simply relying on the collaborative optimization of the PIS and the baseboard management controller's secondary operating system (main operating system) is insufficient to achieve ultra-fast display signal output.

[0050] In contrast, the boot path of the first operating system of the baseboard management controller has a significant time advantage: its bootloader (U-boot) can immediately trigger the boot process of the first operating system during initialization. After the real-time system starts, it can directly control the register layer of the display module according to the pre-configured display control parameters, bypassing the software overhead of the conventional display protocol stack. Ultimately, the display can output images within seconds after the server is powered on, effectively avoiding the timing bottleneck between the basic input / output system and the main operating system. This provides a deterministic delay guarantee for user interaction during the server startup phase, and it can quickly output displays under different processor architectures and server configurations.

[0051] This invention addresses the issue of coordinated control of a display by the first operating system of the baseboard management controller and the basic input / output system (PIS). In practical control, display control by the PIS takes priority, while the first operating system of the baseboard management controller performs display control before the PIS is able to control the display, and optionally when the PIS is unable to control the display due to an malfunction. Therefore, the first operating system of the baseboard management controller needs to be able to monitor changes in the server's power-on / off status signal and the status of the PIS's power-on self-test (POST) process.

[0052] In this embodiment of the invention, a first controller responsible for power-on / off timing control of the server can be connected to a first pin of the baseboard management controller. The first controller converts the power-on / off state to the state of the first pin, thereby transmitting the power-on / off power status signal to the first operating system of the baseboard management controller. A basic input / output system (PIS) can be connected to a second pin of the baseboard management controller. The PIS converts its power-on self-test (POST) state to the state of the second pin, thereby transmitting the PIS's POST state to the first operating system of the baseboard management controller.

[0053] The first pin can be designated as the power-on initial flag pin, and the second pin as the power-on completion flag pin.

[0054] The first controller can be a complex programmable logic device (CPLD). The first and second pins can be general-purpose input / output (GPIO) pins.

[0055] Figure 2 This is a flowchart of a server startup process provided in an embodiment of the present invention.

[0056] like Figure 2 As shown, after the user triggers the power-on using a device such as a power button, the server's first controller receives an interrupt signal and begins executing the power-on sequence. After completing the power-on sequence, the first controller sets the state of the first pin of the baseboard management controller to indicate that the power-on sequence is complete. Subsequently, the basic input / output system executes a series of power-on self-test (POST) procedures (such as performing hardware self-tests, reading and applying configuration information, and initializing peripheral devices) until the POST procedures are completed. After that, the second pin sets the state to indicate that the POST procedures have ended.

[0057] The default state of both the first and second pins is high. After completing the power-on sequence, the first controller pulls the first pin low, indicating that the power-on sequence is complete. After completing the power-on self-test (POST) process, the basic input / output system pulls the second pin low, indicating that the POST process is complete.

[0058] Figure 3 This is a flowchart of a server shutdown process provided in an embodiment of the present invention.

[0059] like Figure 3 As shown, when the power-on sequence and power-on self-test process have been completed, both the first and second pins are at a low level. After the user triggers the shutdown using a power switch or other device, the server's operating system completes the program shutdown process, and the Basic Input / Output System (PIS) notifies the Advanced Configuration and Power Interface (ACPI) to power off, and the power module receives the power-off command. The first controller then executes the shutdown sequence, and after the shutdown sequence is completed, it sets the state of the first pin high to indicate that the shutdown sequence is complete. After notifying the ACPI to power off, the PIS sets the second pin high. Based on the pin configuration, in some optional embodiments of this invention, the first operating system identifies the server's boot type, which may include: the first operating system identifies the timing state of the first pin of the baseboard management controller; if the first pin is in the first timing state, the boot type is determined to be a cold boot; if the first pin is in the second timing state, the boot type is determined to be a warm reboot; the first pin is connected to the server's first controller, which configures the first pin of the baseboard management controller to the first state after the server's power-on sequence is completed; the first pin defaults to the second state.

[0060] In this case, the first state and the second state can be either low or high.

[0061] The first timing state can be a transition from the second state to the first state, corresponding to the server's power-on sequence. When the first operating system detects that the state of the first pin has changed from the second state to the first state, it can determine that the server is powered on by AC power, thus identifying the server's startup type as a cold start. The second timing state can be maintaining the second state, meaning the server is powered on by AC power but with a delayed power-on. In this case, the first pin can act as a state maintenance trigger. When this pin remains in the off state (always off), the display module immediately enters a loop mode. At this time, the display source remains the baseboard management controller, and the first operating system does not process display update requests.

[0062] In some optional embodiments of the present invention, the identification of the server's boot type by the first operating system may further include: the first operating system accessing the boot type register of the baseboard management controller; if the boot type register is a first flag bit, the boot type is determined to be a cold boot; if the boot type register is a second flag bit, the boot type is determined to be a warm reboot. The first flag bit can be a corresponding bit of 1 (BIT0=1), corresponding to a cold boot, in which case the first operating system obtains display control; the second flag bit can be a corresponding bit of 0 (BIT0=0), corresponding to a warm reboot, in which case display control remains unchanged. The first flag bit and the second flag bit can also use opposite signs.

[0063] In other words, the boot type register of the baseboard management controller can be pre-configured to allow the first operating system to determine the server's boot type. The boot type register can be implemented using the system control unit (SCU) register of the baseboard management controller.

[0064] In practical applications, the first operating system can use any of the above methods to identify the server's boot type, or it can deploy both the first pin and the boot type register. In this case, the first operating system's judgment of the first pin and its judgment of the boot type register can be mutually verified.

[0065] In this embodiment of the invention, after obtaining display control, the first operating system calls the display module to control the display to show the first information. In some optional implementations of this invention, the first information may be information indicating that the server has started normally, such as the characters "THE SYSTEM IS POWER ON...".

[0066] In some alternative embodiments of the present invention, the first operating system calling the server's display module to control the display to show the first information may further include: the first operating system accessing the shared memory between the baseboard management controller and the basic input / output system to determine the power-on self-test phase in which the basic input / output system is located, and calling the display module to control the display to show the information of the power-on self-test phase.

[0067] In other words, shared memory can be used as a communication channel between the baseboard management controller and the basic input / output system. A first preset area can be divided in the shared memory. The basic input / output system writes the information of its power-on self-test (POST) stage into the first preset area. The first operating system reads the first preset area in the shared memory to determine the POST stage of the basic input / output system and displays the POST stage information on the display.

[0068] The first operating system can distinguish the completion status of the power-on self-test (POST) phase of the Basic Input / Output System (PIOS) after a warm reboot using the second pin of the baseboard management controller to determine whether to take over display control. Specifically, the first operating system's invocation of the display module to control the display to show the first information may include: if the first operating system detects that the second pin of the baseboard management controller is in the third state, it invoking the display module to control the display to show the first information; the second pin is connected to the PIOS, and the PIOS is also used to set the second pin to the fourth state after completing the POST process; the second pin is in the third state by default. The third and fourth states can be either high or low.

[0069] In other words, the third state corresponds to the state where the Basic Input / Output System (BIOS) has not completed the power-on self-test (POST) process, and the fourth state corresponds to the state where the BIOS has completed the POST process. After the server is powered off and then powered on again, the first operating system can determine the state of the second pin. If it is in the fourth state (POST not completed, possibly due to power-off or host reboot), the first operating system takes over display control to ensure that the system status remains visible upon restarting. At this time, whether it is powered off and then powered on or after a reboot, the first operating system can control the display to show the first information within a short period of time. After the BIOS executes the POST process to a certain stage, the BIOS takes over display control and continues to control the display to output the second information. The second information can be the BIOS POST information, such as the initialization information of components like the CPU and memory.

[0070] The server display control system provided in this embodiment of the invention utilizes a first operating system on the baseboard management controller, which has a faster startup speed. Upon startup, the first operating system immediately enters the display control determination process, allowing it to quickly take over display control compared to the basic input / output system. This enables rapid control of the display output after the server is powered on, whereas the basic input / output system performs a power-on self-test process and completes the initialization of the display module before switching display control. In the first operating system's display control determination process, the first operating system identifies the server's startup type. If the startup type is a cold start, it calls the server's display module to control the display to show the first information. If the startup type is a warm restart, it maintains the display control of the monitor as it was before the power failure. This adapts to various scenarios, such as normal server startup and restart after an abnormal power failure, ensuring the consistency of the timing of display control switching under various operating conditions.

[0071] To enable a smooth handover of display control between the board management controller and the basic input / output system, this embodiment of the invention also configures control logic for the display source register to identify the ownership of display control. The display source register can be implemented using the system control unit (SCU) register of the board management controller.

[0072] The first operating system can also be used to set the display source register of the baseboard management controller to the third flag bit before calling the server's display module to control the display to show the first information. When the display source register is set to the third flag bit, the corresponding baseboard management controller has control over the display; when the display source register is set to the fourth flag bit, the corresponding basic input / output system has control over the display. The third and fourth flag bits can have one corresponding bit set to 1 and the other corresponding bit set to 0.

[0073] In this embodiment of the invention, the display source register, as a key control node, can be configured by the baseboard management controller or the basic input / output system to coordinate the switching of display control.

[0074] To ensure the Basic Input / Output System (BIOS) receives priority access, the display source register can default to the fourth flag bit after the server restarts, meaning that display control belongs to the BIOS by default. The first operating system then invokes the server's display module to control the display to show the first information. This includes: the first operating system reclaiming display control by changing the display source register from the fourth flag bit to the third flag bit. Specifically, if the first operating system identifies the server's boot type as a cold boot after startup, it immediately modifies the display source register to the third flag bit to reclaim display control.

[0075] To avoid the first operating system repeatedly configuring the display source register by polling the pin status and register status of the board management controller, embodiments of the present invention can also configure a display flag register (showFlag) to identify the status of the display source register.

[0076] The first operating system can also be used to set the display flag register of the baseboard management controller to the fifth flag bit when calling the display module to control the display to show the first information, and to set the display flag register to the sixth flag bit when the basic input / output system changes from a completed power-on self-test (POST) state to a state where the POST is incomplete. Setting the display source register of the baseboard management controller to the third flag bit can be achieved by the first operating system checking the state of the display flag register before configuring the display source register; if the display flag register is the fifth flag bit, the display source register is not configured; if the display flag register is the sixth flag bit, the display source register is accessed and configured to the third flag bit. The fifth and sixth flag bits can each be either 1 or 0.

[0077] In other words, when the first operating system needs to control the display output, after operating the corresponding register, it sets the display flag register to the fifth flag bit, indicating that the data of the first operating system has been displayed. This avoids register corruption and abnormal character display caused by the first operating system repeatedly operating the register to display the first information during the polling process. When the power-on completion flag changes from completed to incomplete (i.e., the second pin changes from the fourth state to the third state in the above embodiment), the display flag register is set to the sixth flag bit. Subsequent times when the first operating system needs to control the display output, the corresponding register needs to be operated again.

[0078] In this embodiment of the invention, to ensure the stability of the display control performed by the first operating system, a monitoring thread can be set up to monitor the display control thread.

[0079] The first operating system calls the server's display module to control the display to show the first information. This can include: the first operating system calling a first thread to call the display module to control the display to show the first information; the first operating system also calls a second thread to monitor the running status of the first thread, and controls the first thread to restart to resume display control when the first thread is in an abnormal state. Here, the first thread is the display control thread, and the second thread is the monitoring thread. A watchdog mechanism can be used for monitoring, that is, the first thread is configured to perform a software watchdog feeding action every first cycle (e.g., 1 second), and the second thread is used to monitor the first thread. If the first thread fails to feed the watchdog on time for a first number of consecutive first cycles (e.g., 3 cycles), the second thread controls the first thread to restart, and can also record the first thread's fault log.

[0080] Therefore, this invention constructs a highly reliable dynamic display management system through the coordinated control of hardware registers and software monitoring. By precisely controlling multiple key registers, seamless display switching between the first operating system of the baseboard management controller and the basic input / output system is achieved. Simultaneously, a display flag register (showFlag) state machine mechanism ensures the integrity of the display data.

[0081] To configure the display source register in the baseboard management controller of the basic input / output system, a communication channel needs to be established between the baseboard management controller and the basic input / output system.

[0082] In some optional embodiments of the present invention, the first operating system is further configured to set the debug function register of the baseboard management controller to the seventh flag bit after the server's power-on sequence is completed, and to set the debug function register to the eighth flag bit after the basic input / output system completes the power-on self-test process; the seventh flag bit corresponds to enabling the bridging channel between the server's motherboard and the baseboard management controller's memory; the eighth flag bit corresponds to disabling the bridging channel; the debug function register is set to the eighth flag bit by default.

[0083] In this embodiment of the invention, the control logic of the debug function register of the baseboard management controller is pre-configured to control the switching of external access channels to the baseboard management controller's memory. The debug function register can be implemented using the system control unit register of the baseboard management controller.

[0084] The bridging channel between the server's motherboard and the baseboard management controller's memory can be a bridging channel between the Peripheral Component Interconnect (PCI) bus (or Peripheral Component Interconnect Express (PCIe) bus) and the Advanced High-performance Bus (AHB).

[0085] After the server's power-on sequence is completed (as described in the above embodiment, a first state indicating the completion of the server's power-on sequence is detected through the first pin of the baseboard management controller), the first operating system modifies the debug function register from the eighth flag bit to the seventh flag bit to open the bridging channel between the server motherboard and the baseboard management controller's memory. After detecting that the basic input / output system has completed the power-on self-test (as described in the above embodiment, a third state indicating the completion of the power-on self-test is detected through the second pin of the baseboard management controller), the debug function register modifies the debug function register from the seventh flag bit to the eighth flag bit to close the bridging channel between the server motherboard and the baseboard management controller's memory. During the time the bridging channel between the server motherboard and the baseboard management controller's memory is open, the basic input / output system can access the baseboard management controller through this bridging channel to configure the display source register.

[0086] Referring to the display source register described in the above embodiments, the basic input / output system (PIS) can switch display control rights with the board management controller (BMC) in the following ways: the PIS accesses the BMC via a bridging channel and sets the BMC's display source register to the fourth flag bit; when the display source register is the third flag bit, the corresponding BMC has control rights over the display, and when the display source register is the fourth flag bit, the corresponding PIS has control rights over the display.

[0087] In some optional embodiments of the present invention, the communication channel between the baseboard management controller and the basic input / output system can also employ shared memory. That is, the baseboard management controller and the basic input / output system can be connected via shared memory. The basic input / output system's switching of display control with the baseboard management controller can include: the basic input / output system interacting with the baseboard management controller via shared memory to exchange display control switching information, thereby switching display control. A second preset area can be partitioned in the shared memory. The basic input / output system writes the display control switching request into the second preset area. The first operating system, by reading the second preset area in the shared memory and determining that the basic input / output system can control the display output, stops controlling the display to output the first information. At this time, the first operating system can automatically modify the display source register from the third flag bit to the fourth flag bit, indicating that display control has been switched to the basic input / output system.

[0088] Based on the above embodiments, this embodiment of the invention provides an operation flow executed by the first operating system of a baseboard management controller after startup.

[0089] (1) Initialization Phase. After the server powers on and the first operating system of the baseboard management controller starts, the first operating system determines the server's boot type by reading the boot type register. Different boot types can be represented by the value of a single bit in the boot type register, such as BIT0=1 for cold boot and BIT0=0 for warm reboot. When the first operating system determines the boot type to be a cold boot, it gains display control. When the first operating system determines the boot type to be a warm reboot, display control remains unchanged. This determination result affects subsequent configuration strategies; strict adherence to hardware specifications is essential to ensure the reliability and stability of system startup.

[0090] (2) Power-on condition check. The system checks whether the server meets the power-on conditions. If it is not powered on, it first disables BIT0 of the debug function register. This switch forcibly disables the bridging channel between the PCIe bus and the AHB bus. If enabled, it can access the entire baseboard management controller memory space for use in the basic input / output system display. Therefore, to ensure system safety, this switch is not turned on when the system is powered off. At the same time, the first thread of the first operating system, which is used to perform display control, performs the software dongle feeding action once every first cycle. The second thread of the first operating system monitors the first thread. If it detects that the first thread has not performed the software dongle feeding action on time for the first number of consecutive first cycles, it determines that the first thread is abnormal and controls the first thread to restart, log, etc. The first cycle can be 1 second, that is, the second thread obtains the status of the first thread once every 1 second. The second thread can also be used to obtain the power-on and power-off status of the server.

[0091] (3) Server startup type determination and display control switching. After the server is powered on by AC power, if the server power button is pressed immediately, the first operating system takes over the display control by setting the display source register as the baseboard management controller, forming a dynamically switching display management system, which may include the following functions.

[0092] First: Initial allocation of control. First Operating System (SOS) rapid takeover: Within 5 seconds of the server system powering on, the SOS will illuminate the monitor to output initial information, such as "THE SYSTEM ISPOWER ON...", to inform the user that the server is in a normal boot-up state. This initial information may also include the server's current power-on self-test (POST) process or other basic status information, ensuring the user is immediately aware of the system startup process. Basic Input / Output System (PIS) delayed takeover: Depending on the server's hardware configuration, the PIS can complete initialization within 12 seconds to 4 minutes.

[0093] Second: Dynamic switching trigger conditions. Normal switching: During the power-on self-test process of the basic input / output system, after the initialization of the display module is completed, the basic input / output system can take over display control. At this time, the basic input / output system switches the display control to the basic input / output system, which can be used to output detailed information of the power-on self-test process.

[0094] Abnormal Recovery: If the boot completion flag is detected as incomplete (e.g., during shutdown or host restart), the primary operating system immediately regains control of the display, ensuring continuous visualization of the system status upon restart. During this time, after a shutdown and restart, the primary operating system can control the monitor for 5 seconds, outputting initial information. Later, when the basic input / output system (PIS) can control the display, it resumes control, continuing to manage the monitor's output. At this point, the user can see initialization information printed by components such as the CPU and memory on the monitor until the operating system is accessed.

[0095] Third: Configuration of display control. The display source register, as a key control node, can be configured by the primary operating system or basic input / output system to coordinate the switching of display control.

[0096] Fourth: User-visible output logic. First stage (First Operating System Control): Outputs initial information, such as "THESYSTEM IS POWER ON..." or other basic status information, ensuring the user is aware that booting is in progress and preventing the user from mistakenly believing a startup failure due to a prolonged black screen. Second stage (Basic Input / Output System Control): Dynamically outputs secondary information, such as hardware self-test information, until the operating system is entered. This mechanism achieves high reliability and real-time performance of the display system through dual protection of hardware registers and software monitoring.

[0097] (4) Checking the Power-On Self-Test (POST) status of the Basic Input / Output System. During the server startup process, the baseboard management controller dynamically manages the POST phase of the Basic Input / Output System through precise hardware register control and software status monitoring. This may include the following functions.

[0098] First: Power-on self-test (POST) completion status determination and security control. When the system detects that the basal input / output system has completed (power-on completion flag is set to complete), it immediately executes the debug function register configuration operation (BIT0=1) to forcibly disable the PCIe-to-AHB bridge channel. This operation prevents the basal input / output system from continuing to access the board management controller memory space after the POST process is completed (avoiding data leakage in sensitive areas).

[0099] Second: Periodic maintenance mechanism. Watchdog feeding: The first thread of the first operating system, used for display control, performs a software watchdog feeding operation every 1 second. If the watchdog is not fed on time 3 times in a row, the second thread forcibly restarts the first thread and records the log.

[0100] Third: Handling abnormal power-on self-test status. Control recovery: When the first operating system detects that the power-on completion flag has changed from complete to incomplete, the first operating system immediately regains control of the display and sets the display flag register (showFlag) to 1, enabling the first operating system to display output.

[0101] (5) Co-processing of the display flag register (showFlag) inside the baseboard management controller.

[0102] When the first operating system of the baseboard management controller needs to control the display, the first operating system sets the display flag register to the fifth flag bit, indicating that the display has already displayed data. This avoids register corruption and abnormal character display caused by multiple operations on the register to display character data during the polling process. When the power-on completion flag changes from complete to incomplete, the display flag register is set to the sixth flag bit. When the first operating system needs to control the display in the future, the corresponding register needs to be operated again.

[0103] Figure 4 A power-on / off flowchart of a basic input / output system provided for an embodiment of the present invention.

[0104] like Figure 4 As shown, users power on / off the server via a power switch (PowerButton) or by sending a command. During server startup, the Basic Input / Output System (BIOS) performs hardware initialization. Before taking over display control (usually after initializing the display module), the BIOS sets the display source register to control display source switching. After completing the power-on self-test (POST), the BIOS pulls the second pin of the board management controller low to indicate POST completion. If a power-off or restart command is issued, the BIOS raises the second pin of the board management controller high to indicate that the BIOS POST has changed from a completed power-on state to a partially completed power-on state.

[0105] Therefore, during server startup, a seamless switching mechanism for display control is established through the coordinated control of the primary operating system and the basic input / output system on the baseboard management controller, based on the coordinated management of the baseboard management controller's pins and hardware registers. Through precise scheduling by the baseboard management controller, the system achieves full-scenario adaptation from cold start to warm restart: during cold start, the primary operating system takes over the basic display output state within 5 seconds; during warm restart, a state preservation mechanism avoids repeated initialization. The BIT0 bit of the startup type register distinguishes the startup type, while the display source register triggers control transfer through mode switching and signal changes in the baseboard management controller's pins. Combined with PCI-to-AHB bridged permission management, system security is ensured. A redundant watchdog mechanism and the status indicators in the display flag register (showFlag) further guarantee system reliability. This deep integration of hardware specifications and software monitoring ultimately achieves a seamless transition of the display from the baseboard management controller's primary operating system to the basic input / output system during the boot process, providing a highly available display solution for critical business systems.

[0106] The server display control system provided in this invention can guarantee compatibility across multiple operating scenarios throughout the server's entire lifecycle. By setting up a collaborative control architecture between hardware registers and the pins of the baseboard management controller-baseboard management controller-basic input / output system, the system achieves full scenario coverage from cold start to warm restart, and from normal shutdown to abnormal interruption, ensuring that the display output maintains timing consistency and data integrity under any operating state. Table 1 shows 12 server power-on / off scenarios.

[0107] Table 1

[0108]

[0109] (1) Power management scenario compatibility.

[0110] In the server power management system, the display control logic for AC power-on scenarios (Scenarios 1-3) dynamically identifies cold and warm starts through the BIT0 bit of the boot type register. When the first operating system detects BIT0=1 (cold start state), if a power-on trigger is detected, it automatically triggers a complete power-on self-test process, including standard operation sequences such as hardware initialization and memory verification. At the same time, it resets the display control through the write protection mechanism of the display source register to ensure that the display output is strictly synchronized with the hardware state.

[0111] To address the specific requirements of Scenario 3 (delayed power-on after AC power is supplied), this embodiment of the invention introduces a mechanism where, when the first pin of the baseboard management controller remains in a powered-off state (always powered off), the display module immediately enters a loop mode. At this time, the display source in the display source register remains the baseboard management controller, and the first operating system does not process display update requests (i.e., since it is powered off, no information needs to be displayed). This mechanism, working in conjunction with the watchdog timer, ensures zero data loss and stable display throughout long standby periods.

[0112] (2) Fault tolerance mechanism for abnormal interruption scenarios.

[0113] For abnormal interruptions during the startup process of the Basic Input / Output System (PIS) (Scenarios 7-8), specifically for the Power Cycle scenario (Scenario 7), the system employs a phased control takeover strategy: when a power cycle signal is detected, the system will first shut down and then power on. During shutdown, the display source switches to the baseboard management controller. Upon power-on, the first operating system takes priority over display output, displaying preset basic status information. Once the PIS has initialized to a certain stage, control is switched back to the PIS, at which point the PIS takes over the second stage of display output (such as hardware self-test details). This process is achieved through mode switching in the display source register, ensuring seamless display content.

[0114] For the AC power outage scenario (Scenario 8), this embodiment of the invention introduces a chip default value recovery mechanism: when AC power is detected to be restored, the display source in the display source register automatically restores to the default basic input / output system mode. At this time, the first operating system determines the interrupt nature through the timing characteristics of the first pin of the baseboard management controller. If it is identified as AC power-on rather than a hot reboot, the display source register is immediately configured to reclaim display control. Similar to the power cycle scenario, the first operating system first outputs the basic display content of the first stage, and then the basic input / output system takes over the display output after completing the key hardware initialization.

[0115] The above design constructs a robust display management system for abnormal startup scenarios of the basic input / output system through register-level state machine control and hardware signal coordination. The power cycle scenario focuses on the orderly transfer of control, while the AC power recovery scenario strengthens the protection of the display source under the default value environment. Together, they ensure the continuity of display output and data integrity of the server after abnormal interruption.

[0116] (3) Seamless connection of the board management controller restart scenario.

[0117] In the baseboard management controller restart scenario (Scenarios 9-12) of the server management system, this embodiment of the invention implements a persistent display source configuration retention function. Unlike the behavior of register values ​​reverting to default values ​​after AC power failure, the system, through a special design of the display source register, can completely retain the display source configuration parameters during the baseboard management controller restart process. This mechanism is implemented through a dual-latch architecture: when a restart signal of the baseboard management controller is detected, the current display source configuration in the display source register is immediately written to a non-volatile memory block. After restarting, the first operating system automatically reads the historical values ​​of the display source control register from the non-volatile memory and restores the display output process according to the original display source configuration.

[0118] Through system-level verification, the server display control system provided in this embodiment of the invention can be applied to a variety of mainstream server architectures, covering multiple server platform models.

[0119] The embodiments of the present invention provide a server display control method. The method is described in detail below in conjunction with the execution flow of the server display control method.

[0120] Figure 5 This is a flowchart of a server display control method provided in an embodiment of the present invention.

[0121] like Figure 5 As shown, the server display control method provided in this embodiment of the invention, applied to the baseboard management controller, may include: S501: After power-on, the first operating system starts before the second operating system.

[0122] S502: After the first operating system starts, it identifies the startup type of the server. If the startup type is cold start, it calls the server's display module to control the display to show the first information; if the startup type is warm restart, it maintains the display control of the display before the power failure.

[0123] S503: After the server's basic input / output system starts up and completes the initialization of the display module, the first operating system switches the display control to the basic input / output system, so that the basic input / output system calls the display module to control the display to show the second information.

[0124] For a detailed description of the implementation of this invention, please refer to the above description of the server display control system embodiment.

[0125] Figure 6 A flowchart of another server display control method provided in an embodiment of the present invention.

[0126] like Figure 6As shown, in the server display control system described in the above embodiments, the first operating system in the baseboard management controller may include S601~S615 in the judgment steps after startup.

[0127] S601: Read the boot type register to obtain the boot type of the baseboard management controller.

[0128] S602: Determine if the server is powered on; if yes, proceed to S603; if no, proceed to S615.

[0129] S603: Determine if the boot type is cold boot; if yes, proceed to S604; if no, proceed to S605.

[0130] S604: Set the display source register to the third flag bit.

[0131] S605: Determine whether the basic input / output system has completed the power-on self-test process; if yes, proceed to S615; if no, proceed to S606.

[0132] S606: Determine if the display source register is the fourth flag (indicating that the basic input / output system has display control); if yes, proceed to S607; if no, proceed to S608.

[0133] S607: Set the display flag register to the sixth flag bit (indicating that the board management controller is not controlling the display output).

[0134] S608: Determine if the display flag register is the sixth flag bit (indicating that the board management controller is not controlling the display output); if yes, proceed to S609; if no, proceed to S610.

[0135] S609: Call the display module to control the display to show the first information, and set the display flag register to the fifth flag bit (indicating that the baseboard management controller controls the display output).

[0136] S610: Set the debug function register to the seventh flag to enable the bridge channel.

[0137] Perform the dongle feeding. The interval is the first cycle. The first cycle can be 1 second.

[0138] S611: Determine whether the power-on self-test process is complete; if yes, proceed to S613; if no, proceed to S612.

[0139] S612: Determine if the server is powered on; if not, proceed to S606; otherwise, proceed to S613.

[0140] S613: Set the debug function register to the eighth flag to disable the bridge channel.

[0141] Perform the dongle feeding. The interval is the first cycle. The first cycle can be 1 second.

[0142] S614: Determine whether the power-on self-test process has changed from completed to incomplete; if yes, proceed to S615; if no, proceed to S616.

[0143] S615: Set the display flag register to the sixth flag bit (indicating that the board management controller is not controlling the display output).

[0144] S616: Set the display source register to the third flag bit (indicating that the board management controller has display control rights), and return to S602.

[0145] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0146] Embodiments of the present invention also provide a server display control device applied to a baseboard management controller. The baseboard management controller includes a first operating system and a second operating system. The server display control device includes: an identification unit, used to identify the startup type of the server after the baseboard management controller is powered on and the first operating system starts before the second operating system; a display control unit, used to call the server's display module to control the display to display first information if the startup type is a cold start; and to maintain the display control of the display before power failure if the startup type is a warm restart; and a switching unit, used to switch the display control to the basic input / output system after the first operating system starts the server's basic input / output system and completes the initialization of the display module, so that the basic input / output system calls the display module to control the display to display second information.

[0147] For a description of the features in the embodiment corresponding to the server display control device, please refer to the relevant description in the embodiment corresponding to the server display control method, which will not be repeated here.

[0148] Embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described server display control method embodiments.

[0149] Embodiments of the present invention also provide a non-volatile storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described server display control method embodiments when running.

[0150] In one exemplary embodiment, the aforementioned non-volatile storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0151] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described server display control method embodiments.

[0152] Embodiments of the present invention also provide another computer program product, including a non-volatile storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described server display control method embodiments.

[0153] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0154] The server display control system, method, apparatus, device, medium, and product provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A server display control system, characterized in that, include: Baseboard management controller, basic input / output system; The baseboard management controller includes a first operating system and a second operating system; After the baseboard management controller is powered on, the first operating system starts before the second operating system. After startup, it identifies the startup type of the server. If the startup type is cold start, it modifies the display source register of the baseboard management controller from the fourth flag bit to the third flag bit to reclaim the display control. Then, it calls the display module of the server to control the display to display the first information. If the startup type is warm restart, it maintains the display control of the display before the power failure. After the basic input / output system starts up, it executes the server's power-on self-test process, and after completing the initialization of the display module, it switches the display control rights with the baseboard management controller. After the switch is completed, it calls the display module to control the display to show the second information. The basic input / output system initiates a switch of display control with the baseboard management controller, including: the basic input / output system sets the display source register to the fourth flag bit; When the display source register is the third flag bit, the corresponding baseboard management controller has control over the display; when the display source register is the fourth flag bit, the corresponding basic input / output system has control over the display.

2. The server display control system according to claim 1, characterized in that, The first operating system identifies the server's boot type, including: The first operating system accesses the boot type register of the baseboard management controller. If the boot type register is a first flag bit, the boot type is determined to be a cold boot; if the boot type register is a second flag bit, the boot type is determined to be a warm reboot.

3. The server display control system according to claim 1, characterized in that, The first operating system identifies the server's boot type, including: The first operating system identifies the timing state of the first pin of the baseboard management controller. If the first pin is in the first timing state, the startup type is determined to be a cold start; if the first pin is in the second timing state, the startup type is determined to be a warm restart. The first pin is connected to the first controller of the server. The first controller is used to configure the first pin of the baseboard management controller to a first state after the server's power-on sequence is completed; the first pin is in a second state by default.

4. The server display control system according to claim 1, characterized in that, The first operating system is also used to set the display flag register of the baseboard management controller to the fifth flag bit when calling the display module to control the display to display the first information, and to set the display flag register to the sixth flag bit when the basic input / output system changes from the power-on self-test process completion state to the power-on self-test process incomplete state; The first operating system sets the display source register of the baseboard management controller to the third flag bit, including: Before configuring the display source register, the first operating system checks the status of the display flag register. If the display flag register is the fifth flag bit, the display source register is not configured. If the display flag register is the sixth flag bit, the display source register is accessed and configured to the third flag bit.

5. The server display control system according to claim 1, characterized in that, The first operating system invokes the display module to control the display to show the first information, including: If the first operating system detects that the second pin of the baseboard management controller is in the third state, it calls the display module to control the display to show the first information; The second pin is connected to the basic input / output system, which is also used to set the second pin to the fourth state after completing the power-on self-test process; the second pin is in the third state by default.

6. The server display control system according to claim 1, characterized in that, The first operating system is also used to set the debug function register of the baseboard management controller to the seventh flag bit after the power-on sequence of the server is completed, and to set the debug function register to the eighth flag bit after the basic input / output system completes the power-on self-test process. The seventh flag bit corresponds to enabling the bridging channel between the motherboard of the server and the memory of the baseboard management controller; The eighth flag corresponds to closing the bridging channel; The debug function register is set to the eighth flag bit by default.

7. The server display control system according to claim 6, characterized in that, The basic input / output system switches display control between itself and the baseboard management controller, including: The basic input / output system accesses the baseboard management controller through the bridging channel and sets the display source register of the baseboard management controller to the fourth flag bit; When the display source register is set to the third flag bit, the corresponding baseboard management controller has control over the display; when the display source register is set to the fourth flag bit, the corresponding basic input / output system has control over the display.

8. The server display control system according to claim 1, characterized in that, The baseboard management controller and the basic input / output system are connected via a shared memory. The basic input / output system switches display control between itself and the baseboard management controller, including: The basic input / output system interacts with the baseboard management controller via the shared memory to display control switching information, thereby switching display control.

9. The server display control system according to claim 1, characterized in that, The first operating system invokes the server's display module to control the display to show the first information, including: The first operating system invokes a first thread to invoke the display module to control the display to show the first information; The first operating system is also used to call the second thread to monitor the running status of the first thread, and to control the first thread to restart in order to resume display control when the first thread is in an abnormal state.

10. The server display control system according to claim 1, characterized in that, The first piece of information is the information indicating that the server has started normally.

11. The server display control system according to claim 1, characterized in that, The first operating system invokes the server's display module to control the display to show the first information, including: The first operating system accesses the shared memory between the baseboard management controller and the basic input / output system to determine the power-on self-test (POST) phase of the basic input / output system, and calls the display module to control the display to show the information of the POST phase.

12. The server display control system according to any one of claims 1 to 11, characterized in that, The first operating system is a real-time operating system, and the second operating system is a non-real-time operating system.

13. A server display control method, characterized in that, Applications to baseboard management controllers include: After power-on, the first operating system starts before the second operating system; After the first operating system starts, it identifies the startup type of the server. If the startup type is cold start, it sets the display source register of the baseboard management controller from the fourth flag bit to the third flag bit to reclaim display control. Then, it calls the display module of the server to control the display to show the first information. If the startup type is warm restart, it maintains the display control of the display before the power failure. After the first operating system starts up the server's basic input / output system and completes the initialization of the display module, it switches the display control to the basic input / output system, so that the basic input / output system calls the display module to control the display to show the second information. The basic input / output system initiates a switch of display control with the baseboard management controller, including: the basic input / output system sets the display source register to the fourth flag bit; When the display source register is the third flag bit, the corresponding baseboard management controller has control over the display; when the display source register is the fourth flag bit, the corresponding basic input / output system has control over the display. The display source register defaults to the fourth flag bit after the server restarts.

14. A server display control device, characterized in that, The application is to a baseboard management controller, which includes a first operating system and a second operating system; the server display control device includes: The identification unit is used to identify the startup type of the server after the baseboard management controller is powered on and the first operating system starts before the second operating system. The display control unit is configured to, if the startup type is cold start, change the display source register of the baseboard management controller from the fourth flag bit to the third flag bit to reclaim display control, and then call the display module of the server to control the display to display the first information; if the startup type is hot restart, maintain the display control of the display before the power failure. A switching unit is used to switch display control to the basic input / output system after the first operating system starts up and completes the initialization of the display module on the server, so that the basic input / output system calls the display module to control the display to display the second information; The basic input / output system initiates a switch of display control with the baseboard management controller, including: the basic input / output system sets the display source register to the fourth flag bit; When the display source register is the third flag bit, the corresponding baseboard management controller has control over the display; when the display source register is the fourth flag bit, the corresponding basic input / output system has control over the display. The display source register defaults to the fourth flag bit after the server restarts.

15. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the server display control method as described in claim 13 when executing the computer program.

16. A non-volatile storage medium, characterized in that, The non-volatile storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the server display control method as described in claim 13.

17. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the server display control method as described in claim 13.

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