Verification method, system and device of display interface controller

Abstract

The invention relates to the technical field of peripheral verification, and discloses a verification method, system and device for a display interface controller. Wherein in the process that the display interface controller assembly sends the simulation image data to the display interface assembly, the simulation pixel data of the ith row is captured in real time through the display data comparison model; reading standard pixel data of the ith row from the standard pixel data file through a display data comparison model, and performing real-time consistency comparison on the simulation pixel data and the standard pixel data to obtain a consistency comparison result; and if the consistency comparison result shows that the simulation pixel data is different from the standard pixel data, pausing the operation of the hardware simulation accelerator so as to lock the scene where the pixel data error occurs in the verification environment. Therefore, on the premise of ensuring high credibility of the verification result, the debugging efficiency is improved from frame-level post backtracking to line-level in-event stopping, and the reliability and efficiency of verification of the display interface controller are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of peripheral device verification, and in particular to a display interface controller verification method, system and device. BACKGROUND

[0002] In today's chip industry, with the continuous enrichment of System-on-a-Chip (SoC) application scenarios, the product display interface technology (such as DisplayPort) verification capability has formed a multi-dimensional system, and its core is reflected in the interface protocol and controller function verification, high-speed signal and image integrity verification, and system-level function and performance verification three levels.

[0003] In the related art, the verification of the DP (DisplayPort) display interface controller mainly checks the correctness of the DP output image. The verification environment of the DP display interface controller is composed of three parts: Design Under Test (DUT), Speedbridge and real display device. In this verification environment, a frame of image data is packaged by the DUT to the display interface through the driving software operation, and the frame of image data is displayed on a real display device, and the correctness of the output image is checked by the human eye.

[0004] However, the related art has a certain response delay when displaying the frame of image data through the real display device, and therefore, a new display interface controller verification method needs to be proposed. SUMMARY

[0005] The present application aims to at least solve one of the technical problems in the related art. To this end, the present application proposes a display interface controller verification method, system and device. The main technical solutions adopted by the present application include:

[0006] In order to achieve the above purpose, the main technical solutions adopted by the present application include:

[0007] In a first aspect, the embodiments of the present application provide a display interface controller verification method, which is applied to a verification environment built based on a hardware simulation accelerator, a design-under-test model is run in the hardware simulation accelerator, the design-under-test model includes a display interface controller component and a display interface component, a display data comparison model implemented by using a synthesizable hardware description language is bound to an output end of the display interface controller component, the display data comparison model is used to detect consistency between simulation image data and standard image data, and a standard pixel data file of the standard image data is stored in the hardware simulation accelerator; the method comprises the following steps: in a process in which the display interface controller component sends simulation image data to the display interface component, simulation pixel data of an i-th row is captured in real time by using the display data comparison model; wherein i is a positive integer greater than or equal to 1; standard pixel data of the i-th row is read from the standard pixel data file by using the display data comparison model, and real-time consistency comparison is performed on the simulation pixel data and the standard pixel data, to obtain a consistency comparison result; and if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, the running of the hardware simulation accelerator is paused, so as to lock a scene in which pixel data error occurs in the verification environment.

[0008] In the above embodiments, the simulation pixel data is captured in real time by using the display data comparison model, and real-time consistency comparison is performed on the simulation pixel data and the standard pixel data of the corresponding row row by row, so that the limitation of needing to wait for an entire frame of display to perform verification is overcome, and pixel-level real-time verification is achieved. Moreover, the running of the hardware simulation accelerator is paused immediately when the simulation pixel data and the standard pixel data are inconsistent, so that the simulation scene is frozen in time when error occurs, and thus the problem of scene loss caused by simulation progress in advance is avoided. Therefore, on the premise of ensuring high reliability of verification results, the debugging efficiency is improved from frame-level post-tracing to row-level in-process stopping, and the reliability and efficiency of display interface controller verification are significantly improved.

[0009] Optionally, if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, the running of the hardware simulation accelerator is paused, which comprises the following steps: if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, a flag bit of the display data comparison model is written as a first preset value; and if it is monitored that the flag bit is equal to the first preset value, the running of the hardware simulation accelerator is paused. In the above embodiments, the pixel data comparison result is fed back in real time by using the flag bit, and when it is detected that the simulation data and the standard data are inconsistent, the flag bit of the display data comparison model is immediately written as the first preset value to trigger the hardware simulation accelerator to pause, so as to freeze the complete simulation scene when error occurs. Compared with the related art in which the output result is compared with a Golden image by using the naked eye, the data comparison is performed by using the display data comparison model, and the reliability of the verification result is obviously improved, so that high-precision and high-timeliness error positioning capability is provided for DP controller verification.

[0010] Optionally, the method further comprises: if the consistency comparison result indicates that the simulation pixel data is the same as the standard pixel data, exporting the simulation pixel data to a display device connected to the hardware simulation accelerator, so that the display device displays a simulation image corresponding to the simulation pixel data. In the above embodiment, by automatically comparing the simulation pixel data with the standard pixel data, the correct simulation data is triggered to be exported to the server when the data is completely matched, and the simulation image is automatically generated, realizing real-time visualization of the verification result, significantly improving the verification efficiency and accuracy, avoiding the delay problem of the traditional display device, and ensuring the rapid confirmation and automatic processing of data consistency, greatly reducing the manual intervention and debugging time.

[0011] Optionally, if the consistency comparison result indicates that the simulation pixel data is the same as the standard pixel data, exporting the simulation pixel data to a display device connected to the hardware simulation accelerator comprises: if the consistency comparison result indicates that the simulation pixel data is the same as the standard pixel data, writing a flag bit of a display data comparison model to a second preset value; and if the flag bit is detected to be equal to the second preset value, exporting the simulation pixel data to the display device. In the above embodiment, the pixel data comparison result is fed back in real time through the flag bit, and the simulation pixel data is automatically triggered to be exported to the server and a simulation image is generated when the data is consistent, realizing real-time visualization and automatic processing of the verification result, significantly improving the verification efficiency and accuracy, avoiding the delay problem of the traditional display device, and providing an efficient and accurate automatic solution for DP controller verification.

[0012] Optionally, the simulation pixel data is stored in a simulation pixel data file; and the display device displays the simulation image corresponding to the simulation pixel data by: scanning the simulation pixel data file, and drawing the scanned pixel data on a pre-created blank image to obtain the simulation image corresponding to the simulation pixel data. In the above embodiment, not only the format conversion error in the transmission process is effectively avoided through pixel-level data analysis, but also the speed of outputting the image is obviously improved compared with the traditional display method of displaying on the real display device through the speed bridge, and the single-frame output can realize fast image display.

[0013] Optionally, the simulation pixel data of the i-th row is captured in real time by the display data comparison model, comprising: monitoring a row synchronization signal of the image time sequence generator by the display data comparison model, and in response to a preset jump of the monitored row synchronization signal, writing the simulation pixel data of the i-th row into the hardware simulation accelerator. In the above embodiment, whether to capture data is determined by detecting the real-time state of the row synchronization signal, a verification window is constructed for real-time comparison row by row, and real-time and accurate capture of the pixel data at the hardware level is realized, so as to overcome the waiting delay problem of the whole frame transmission.

[0014] Optionally, the hardware simulation accelerator is communicatively connected with a server, the standard pixel data file is loaded into the hardware simulation accelerator from the server, and the standard pixel data in the standard pixel data file is obtained by traversing and analyzing each pixel point of the standard image data. In the above embodiment, through the cooperation of the server and the hardware simulation accelerator, the whole process from image analysis to data loading does not require manual intervention, and the verification efficiency is significantly improved. Moreover, the standard pixel data is generated bit by bit according to the pixel points, and completely matches the simulation pixel data, thereby providing an accurate benchmark for subsequent real-time pixel-level comparison.

[0015] In a second aspect, the embodiments of the present application provide a verification system of a display interface controller, which includes a hardware simulation accelerator, a design-under-test model is run in the hardware simulation accelerator, the design-under-test model includes a display interface controller component and a display interface component, a display data comparison model implemented by using a synthesizable hardware description language is bound to an output end of the display interface controller component, the display data comparison model is used to detect the consistency between simulation image data and standard image data, and a standard pixel data file of the standard image data is stored in the hardware simulation accelerator; the display data comparison model is configured to, in a process in which the display interface controller component sends the simulation image data to the display interface component, capture simulation pixel data of an i-th row in real time, read standard pixel data of the i-th row from the standard pixel data file, and perform real-time consistency comparison on the simulation pixel data and the standard pixel data to obtain a consistency comparison result; if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, the running of the hardware simulation accelerator is paused to lock a scene in which pixel data error occurs; wherein i is a positive integer greater than or equal to 1.

[0016] In the above embodiment, the display data comparison model is used to capture the simulation pixel data in real time, and perform real-time consistency comparison on the simulation pixel data and the standard pixel data of the corresponding row row by row, thereby overcoming the limitation that verification can be performed only after a whole frame of display, and realizing pixel-level real-time verification. Under the premise of ensuring high reliability of the verification result, the debugging efficiency is improved from frame-level post-tracing to row-level in-process stopping, thereby significantly improving the reliability and efficiency of the display interface controller verification.

[0017] Optionally, the verification system further comprises a server connected with the hardware simulation accelerator; the hardware simulation accelerator is configured to export the simulation pixel data to the server connected with the hardware simulation accelerator if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are the same; and the server is configured to receive the simulation pixel data and display a simulation image corresponding to the simulation pixel data. In the above embodiment, through the cooperation of the server and the hardware simulation accelerator, the whole process from image analysis to data loading does not need manual intervention, the hardware simulation accelerator is triggered to export the correct simulation data to the server when the data are completely matched, and a simulation image is automatically generated, thereby realizing real-time visualization of the verification result and significantly improving the verification efficiency and accuracy.

[0018] In a third aspect, the present application also provides a verification device of a display interface controller, comprising a memory for storing a program; and a processor for calling the program from the memory to enable the verification device to execute the method of any of the above embodiments.

[0019] In a fourth aspect, the present application also provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method of any of the above aspects.

[0020] In a fifth aspect, the present application also provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the steps of the method of any of the above aspects.

[0021] In a sixth aspect, the present application provides a computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the steps of the method of any of the above aspects. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the description of the specific embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0023] Figure 1a A flowchart of a verification method of a display interface controller in the related art;

[0024] Figure 1b A flowchart of a verification method of a display interface controller according to an embodiment of the present application;

[0025] Figure 2 A flowchart of a suspension running method according to an embodiment of the present application;

[0026] Figure 3 A flow chart of a method for deriving simulation pixel data according to an embodiment of the present application is provided;

[0027] Figure 4 A structural block diagram of a verification system of a display interface controller according to an embodiment of the present application is provided;

[0028] Figure 5 An internal structural diagram of a computer device according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0030] In the contemporary transition of Maslow's hierarchy of needs, human beings are crossing the threshold of material abundance and advancing to the spiritual plateau. With the rapid development of material civilization and the increasing spiritual demands, electronic devices are playing an increasingly important role in daily work and entertainment life. Since the release of Video Graphics Array (VGA) interface in 1987, the interconnection of image devices and graphic applications have developed rapidly, and after the release of DisplayPort (DP) in 2006, display technology has entered the all-digital high-definition era, which puts forward higher requirements on the verification capability of embedded chip and development board product research and development.

[0031] In today's chip industry, with the continuous enrichment of SoC application scenarios, the display interface technology (such as DisplayPort) verification capability of the product has formed a multi-dimensional system, which is mainly reflected in the interface protocol and controller function verification, high-speed signal and image integrity verification, and system-level function and performance verification three levels. According to the established rules of each interface protocol, the verification method of display interface technology is also constantly updated and developed, from the module-level verification environment based on IP Testbench, to the open source development framework based on Universal Verification Methodology (UVM), to the hardware simulation accelerator and Field Programmable Gate Array (FPGA) Register Transfer Level (RTL) level real-time simulation, the technologies for different verification levels and different function coverage scenarios have become more mature, and among them, the hardware simulation accelerator has become the core platform of display interface verification, which can meet the protocol stack verification needs of high-speed peripheral interfaces such as DP, can process multiple high-resolution and high-refresh-rate video streams in parallel, can detect IP or SoC-level design defects before product tape-out, and completely covers different verification scenarios of the above three levels, significantly improves the SoC verification coverage, and increases the credibility of chip verification results.

[0032] Specifically, the verification of the DP display interface controller mainly checks the correctness of the DP output image, and the following four methods can be used in the related art:

[0033] First, in terms of simulating real display scenarios, hardware simulation accelerators have more obvious advantages in real SoC scenario verification and real display device external debugging due to their ability to support real-time high-speed simulation of billion gate design scales. In the verification of the hardware simulation accelerator, the verification environment of the DP display interface controller is composed of three parts: the design under test, the speed bridge, and the real display device. In this verification environment, the DUT is operated by the driving software to package image data output to the display interface, the physical layer (PHY) is replaced on the interface to connect the package layer of the speed bridge, and then the image is displayed to a real display device, and the correctness of the output image is checked by the human eye. The system of this scheme can refer to FIG. 1, and the specific implementation steps are as follows: Figure 1a

[0034] S1: In the DUT, the software driver of the display interface controller sends image data, and the data is output to the DP peripheral interface in the form of pixel data (RGB color components) of each pixel point for external transmission;

[0035] ​S2: Since the DP-PHY used in the real chip is not synthesizable, it needs to be replaced by a synthesizable physical layer model, which is adapted and instantiated with a hardware description language (Verilog) to connect the speed bridge;

[0036] S3: The physical layer model also delivers the DP protocol package to the wrapper of the speed bridge in a way that meets the DP protocol transmission specification, and processes it through the speed bridge to balance the rate gap between the DUT simulated in the hardware simulator and the real display device;

[0037] S4: The speed bridge outputs the DP data to the real display device, such as a display, and the tester observes and judges the display result with the naked eye;

[0038] S5: If the display image meets the expectation, it is judged as passed;

[0039] S6: If the display image does not meet the expectation, such as appearing as a flower screen, spots, etc., the simulator needs to be paused and the current controller access address is read by the simulator, and these addresses are marked by setting triggers in the simulator. However, it should be noted that pausing is only a means, although this method will also pause the simulation, but since the image displayed on the display lags behind the simulation calculation progress in time, it takes a lot of time to locate the abnormal data. That is, since the simulator has run a considerable length or even many frames when displaying the image on the display, it is necessary to analyze the data corresponding to the access address from the current access address forward, or from the access head address of each frame backward, to check the correctness of the data corresponding to each pixel point to locate the problem.

[0040] Secondly, DUT behavior correctness checking is performed through assertion. In the use of general assertion, the System Verilog language is used to write assertions according to the DP interface behavior and combine them in the UVM verification environment. In the entrance and exit of DUT and UVM framework, entry bus assertion monitors, exit bus assertion monitors, register bus assertion monitors, etc. are added to complete bus behavior checking and coverage collection.

[0041] Thirdly, the protocol analyzer can also be applied in the verification of high-speed input and output (Input and Output IO) interfaces. The use of the protocol analyzer is to connect the entry of the protocol analyzer to the SpeedBridge in the hardware device form described in the prior art solution, and use the protocol analyzer instead of the real display. Its main application is in the field of protocol package capture and analysis, and it performs main link (Main Link) or auxiliary channel (AUX Channel) behavior analysis.

[0042] Fourthly, in the field of computer vision and image processing, there is an application of similarity comparison between two images using a cross-platform computer vision library (OpenCV). The application needs to rely on the OpenCV software framework. The similarity can be calculated by comparing the RGB values or grayscale values of the two images, based on the mean square deviation or structural similarity index, or by calling a function to calculate the histogram of the two images, and then using histogram distance measurement methods such as Bhattacharyya distance and Chi-square distance to calculate the similarity score of the two images. This image result comparison method is widely used in the upper application layer.

[0043] However, through analysis, several methods in the related art have the following limitations, specifically:

[0044] 1. Since the result needs to be judged by observing the display with the naked eye, and the minimum refresh scale of the display screen is one frame, the minimum judgment unit of the above method is one frame. In the display process of the related verification environment, the image needs to be transmitted through the speed bridge and the response delay of the speed bridge special display device from the simulator to the display, which takes about several minutes and the display speed is slow.

[0045] 2. Based on the above, since there is a large difference between the simulation speed of the simulator and the real time, by the time the display device displays the image, the simulator has been running for a long time. In the current related technical field, the correctness of the demonstration result can only be judged by the display result of the display. If the display result of the display has image display abnormalities such as screen flickering or spots, and the pixel data of the image needs to be analyzed, the simulation scene displayed by the simulator has already passed a long time, and the simulation waveform cannot be traced at this time. Since the simulator needs to specify a time node and a fixed waveform length when analyzing the waveform, it is difficult to find the accurate time point and estimate the waveform length to capture and analyze the waveform under this condition, which ultimately causes the problem of difficulty in debugging the display result by observing with the naked eye and huge human time cost (i.e., if data errors occur, the simulation needs to be completed to display the error result, and before the display result, the verifier does not know that the simulation has a problem).

[0046] 3. The display result is judged by directly observing with the naked eye, and the large resolution picture (such as 4096*2160) contains too many pixel points, and the display of a single pixel point on the display is too small. If there is a problem of individual pixel point display error, it is difficult to find the problem by the naked eye.

[0047] 4. The correctness check based on assertion depends on the System Verilog language and the UVM verification environment, which is overall non-synthesizable code for the simulator and cannot be synthesized into a netlist that can be recognized by the simulator.

[0048] 5. Although the protocol analyzer can capture data in the data channel, the protocol analyzer is generally expensive and requires a large hardware overhead on the SpeedBridge adapter. In general, the protocol analyzer cannot be truly applied in the pre-silicon verification of the product. Although the protocol analyzer has the ability to capture and analyze data, it cannot directly determine the correctness of the data without the original data. Therefore, a method is needed to obtain the original image data, and the process is relatively complex and has high complexity.

[0049] 6. In the related technical solutions, the OpenCV is used for image processing, and the result is still a theoretical calculation result, not a real result. Moreover, the OpenCV function code is non-synthesizable code for the simulator, and cannot be applied in the SOC verification of the simulator.

[0050] In summary, the related art lacks a comprehensive verification scheme that can integrate original data analysis, real-time data acquisition, real-time data analysis, fast image display, and fast Debug and waveform analysis in combination with the simulator. Moreover, the scheme needs to solve the problem of display result lag caused by the speed difference between the real display device and the simulator, avoid the loss of simulation site to make it impossible to locate and analyze the waveform, and ensure that the error processing and simulation are synchronized to maintain the effectiveness of the site positioning. In addition, the image correctness judgment in the related art by relying on the naked eye may lead to distorted results, so that the defects existing in the DUT cannot be found in the pre-silicon stage and are left to the post-silicon stage. The image display speed of the current verification environment is too slow, which limits the efficiency. More importantly, there is a lack of synthesizable data comparison code in the current simulator verification, which further increases the complexity and uncertainty of the verification.

[0051] Therefore, according to the embodiments of the present application, a verification method of a display interface controller is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0052] A verification method of a display interface controller is provided in the embodiment. The verification method is applied to a verification environment built based on a hardware simulation accelerator. A design-under-test model is run in the hardware simulation accelerator. The design-under-test model includes a display interface controller component and a display interface component. A display data comparison model implemented by using a synthesizable hardware description language is bound to an output end of the display interface controller component. The display data comparison model is used to detect consistency between simulation image data and standard image data. A standard pixel data file of the standard image data is stored in the hardware simulation accelerator. Figure 1b A flowchart of the verification method of the display interface controller according to the embodiment of the application is shown in FIG. 1. Figure 1b The flowchart includes the following steps.

[0053] In S110, simulation pixel data of an ith row is captured in real time by the display data comparison model in a process in which the display interface controller component sends simulation image data to the display interface component.

[0054] It should be noted that the design-under-test model can be a register transfer level (RTL) design entity mapped to the hardware simulation accelerator, which is also referred to as a design-under-test (DUT) and is deployed in a verification platform of the hardware simulation accelerator.

[0055] Specifically, the design-under-test model can include the display interface controller component and the display interface component. The display interface controller component can be a module for packaging and outputting simulation image data to a physical interface, which can be an IP core of a DP (Display Port) controller. The display interface component can be a port for transmitting a high-speed serialized video data stream, which can be a DP protocol interface.

[0056] For example, the design-under-test model (DUT) is a system-level container that contains the display interface controller module. The display interface controller module directly drives the display interface component (such as a DP interface) of the physical layer. That is, the DUT can be understood as a black box. The display interface controller component can be understood as a core engine for processing protocols in the box. The display interface component is a physical pin of the box. Specifically, in chip design verification, the display interface controller component encapsulates image data generated by the DUT according to a protocol (such as DP packaging). The display interface component outputs a high-speed serialized data stream. Finally, the data stream is output to an external display device through a connector.

[0057] The simulation image data can refer to a video stream data packet generated by the to-be-tested design model during runtime, which can include Main Link data such as RGB pixel values and the like, and information such as timing control. Specifically, a set of R / G / B component values of a single row of pixels in a single frame of the simulation image data can be used as simulation pixel data. Correspondingly, the standard image data can refer to a pre-stored golden reference image (Golden Image) used as a correctness benchmark for real-time comparison in the hardware simulation accelerator. A binary file generated by parsing the standard image data by pixels can be used as standard pixel data file, and the standard pixel data contained therein is aligned with the simulation pixel data.

[0058] Further, in the to-be-tested design model, the output end of the display interface controller component can be further bound with a display data comparison model implemented by using a synthesizable hardware description language, for detecting the consistency between the simulation image data and the standard image data.

[0059] The synthesizable hardware description language refers to a special programming language used for describing digital circuits and systems. For example, the synthesizable hardware description language can be VHDL or Verilog. It should be noted that, due to the running requirements of the simulator, when the simulator identifies the design code of the to-be-tested design model, the code needs to be first converted into a netlist that needs to be identified, and then the netlist is compiled into available resources of the simulator. However, in the process of conversion into the netlist, a step of synthesis needs to be performed, that is, the conversion into the netlist is obtained through synthesis, and therefore it is called synthesizable. The display data comparison model can refer to a special hardware logic module implemented by using a synthesizable hardware description language (such as Verilog). For example, the display data comparison model can be regarded as a synthesizable data code, which is bound to the output end of the display interface controller in the DUT. For example, the display data comparison model can actually be a Verilog model framework, which has a flag bit and two input ends. Specifically, the display data comparison model can be instantiated in the to-be-tested design model through a bind syntax, and can monitor the process of transmitting the simulation image from the display interface controller to the display interface signal in real time, so as to detect the consistency between the simulation image data and the standard image data. Therefore, since the display data comparison model is developed by using a synthesizable code, it can be recognized by the hardware simulation accelerator and combined into the to-be-tested design model after synthesis, and has a small synthesis area and is friendly to resource usage.

[0060] Specifically, in the process of the display interface controller sending the simulation image data to the display interface, the display data comparison model first monitors the data transmission state of the interface in real time. If a row transmission start signal is detected, for example, if it is detected that the data enable signal becomes a rising edge, the parallel data transmission line before the output of the display interface controller to the physical interface is latched by the state machine in the valid period of the data enable signal. Then the R / G / B components of each pixel point in the ith row of the transmission line are analyzed in real time. Finally, these component values are written into a specified continuous memory space of the hardware simulation accelerator as the ith row of simulation pixel data in the order of the pixels in the row, completing real-time capture. Wherein, the ith row can refer to the row number currently being processed in the display data transmission process, i is a dynamic variable, which can be any positive integer between 1 and the total number of rows. Since the display interface controller outputs data row by row, the display data comparison model can capture the ith row of pixel data currently being transmitted by monitoring the row transmission start signal when capturing data in real time, so as to compare with the pre-stored standard pixel data of the same row.

[0061] In some embodiments, the display data comparison model can capture the ith row of simulation pixel data in real time by monitoring the row synchronization signal of the image timing generator through the display data comparison model, and writing the ith row of simulation pixel data into the hardware simulation accelerator in response to the preset transition of the monitored row synchronization signal.

[0062] Wherein, the image timing generator (Video Timing Generator, VTG) is a hardware module for generating video display timing, and the output signals thereof can include a row synchronization signal (HSYNC), a field synchronization signal (VSYNC) and a data enable signal (DE) and the like. Wherein, the VTG row synchronization signal can refer to a signal indicating the start and end of each row of pixel data transmission, and the preset transition can refer to the level change trigger condition of the signal. For example, taking the row synchronization signal as a pulse signal, the preset transition can refer to signal pull-up or pull-down. Taking pull-up as an example, specifically, the display data comparison model determines that the ith row of data starts to be transmitted after detecting that the row synchronization signal is pulled up. Subsequently, the state machine in the display data comparison model processes the bit representing the RGB component in the data transmission line separately, so as to write the simulation pixel data of each pixel point in the ith row of the current row transmission into a certain memory space of the hardware simulation accelerator.

[0063] It needs to be understood that two scripts can be loaded in the display data comparison model, one is a code script in verilog language, and the other is an SDL (State Description Language) code script supported by the hardware simulation accelerator. Through the Verilog state machine, the corresponding data transmission line can be migrated from the controller interface to the state machine, so as to pull out the corresponding bit signal from the interface every time the simulation pixel data is transmitted. Then the current line of simulation pixel data in the signal is written into the memory (mem) space of the hardware simulation accelerator in real time, which can be regarded as a static random access memory (SRAM), and the data is readable and writable, finally realizing the synchronization of simulation progress and data capture storage.

[0064] Further, in the data storage process, the state machine also monitors the line synchronization signal in real time, and when the line synchronization signal jumps, it indicates that the first frame image starts to output, at which time the simulation pixel data of the ith line starts to enter the transmission stage. Correspondingly, the simulation pixel data of the ith line is captured and stored in real time. It needs to be noted that after the comparison result is obtained, the state machine will also pull up a comparison result indication signal. The SDL code script will respond to the comparison result indication signal, and when the signal is pulled up, the SDL will judge whether to execute the storage or pause command according to the correctness of the comparison result. When the storage command is executed, the mem dump operation is performed to pull the data in the mem space to the SRAM, and store the data in the real SRAM for subsequent display. When the pause command is executed, the simulation is paused and the error site is locked. Finally, through the display data comparison model, the jump of the VTG line synchronization signal is monitored in real time, the RGB pixel data transmitted by the DP interface is captured line by line, and the data is temporarily stored in the temporary memory and then stored in the SRAM by using the Verilog and SDL scripts, realizing the synchronization capture and storage of the pixel-level data, ensuring the complete synchronization of the simulation progress and the data comparison, which can avoid the frame-level delay of the traditional display device on the one hand, and can immediately pause the simulation and lock the error site when the data error is found in the subsequent comparison, solving the problem of waveform tracing caused by display lag, and significantly improving the verification efficiency and accuracy.

[0065] S120, reading the standard pixel data of the ith line from the standard pixel data file through the display data comparison model, and performing real-time consistency comparison on the simulation pixel data and the standard pixel data to obtain a consistency comparison result.

[0066] The standard pixel data can be image data that conforms to an expected correct result and is used as a reference for judgment. Specifically, the standard pixel data can be obtained by parsing a golden reference image, and it is standard data in verification, i.e., non-updated default correct data.

[0067] In some embodiments, the hardware simulation accelerator is communicatively connected with a server, the standard pixel data file is loaded into the hardware simulation accelerator from the server, and the standard pixel data in the standard pixel data file is obtained by traversing and parsing each pixel point of the standard image data.

[0068] The server can refer to a hardware device server independent of the design-under-test module, and can be connected with the DUT through a switch network. Specifically, the server can traverse and parse each pixel point of the standard image through a script, and extract the RGB component values as standard pixel data. The design-under-test model calls the SDL to perform the memory load function, and loads the standard data file composed of binary or hexadecimal standard pixel data from the server into the memory space of the hardware simulation accelerator. It should be noted that the standard image data is stored in the server, and the standard pixel data file obtained by processing the standard image data pixel by pixel is stored in the hardware simulation accelerator. Thus, through the cooperation of the server and the hardware simulation accelerator, the whole process from image parsing to data loading does not require manual intervention, significantly improving the verification efficiency. Moreover, the standard data is generated bit by bit according to the pixel points, and completely matches the simulation pixel data, providing an accurate reference for subsequent real-time pixel-level comparison.

[0069] It should be noted that when the display data comparison model reads and parses the standard data file already stored in the memory space of the hardware simulation accelerator, it also starts from the data of the first pixel point in the first row and parses one by one. This parsing method is completely consistent with the output display method of the DP protocol. Therefore, during chip verification, when the display data comparison model captures the i-th row of simulation pixel data, the process of parsing the standard pixel data in the standard pixel data file is simultaneous and matched. As long as the data is read bit by bit, when the i-th row of simulation pixel data is obtained, the standard pixel data of the same pixel point in the i-th row can also be obtained, and the format of the standard pixel data and the simulation pixel data is also matched.

[0070] Based on this, real-time consistency comparison is realized between the simulation pixel data and the standard pixel data at the pixel level. It should be noted that the trigger condition of the real-time consistency comparison can be the first jump of the row synchronization signal after the reset pull-up, which marks the beginning of the output of the first frame of picture and comparison can be performed. The end condition of the real-time consistency comparison can be the field synchronization signal of the image timing generator, which marks the end of the output of the picture. In addition, in order to facilitate subsequent simulator waveform analysis, since the minimum data granularity that can be obtained by using the row field synchronization signal is one row, the frequency of the real-time comparison can be determined based on the second jump of the row synchronization signal. If the second jump of the row synchronization signal occurs, it indicates that the pixels of the i-th row, that is, the current row, have been output, and then a comparison can be performed on all the pixel data of the current row. Specifically, during the comparison, the current pixel data is compared row by row at a time. For example, each pixel point can be composed of 6 hexadecimal values. During the comparison, the actual comparison logic is to compare the pixels bit by bit, that is, to compare a group of 6 values each time, but the overall processing unit is one row of data. For example, for a pure color picture with a format of 1920*1080, the data of each pixel point can be aabbcc (a total of 6 values), and the i-th row is 1920 aabbcc data. During the real-time consistency comparison, 1920 groups are compared at a time, that is, a total of 1920*6 values of the i-th row are compared at a time, and the consistency comparison result of the current row is output.

[0071] The consistency comparison result can be a verification conclusion generated by comparing the i-th row of simulation pixel data with the i-th row of standard pixel data through the display data comparison model. For example, if it is found that the RGB color components of all the pixel points in the i-th row, that is, the current row, are completely matched after comparison, the consistency comparison result of the row is that the comparison is the same, indicating that the simulation pixel data and the standard pixel data of the row are consistent, and the output of the row is correct; if it is found that the RGB components of any pixel point in the current row are not matched after comparison, the consistency comparison result of the row is that the comparison is different, indicating that the simulation pixel data and the standard pixel data of the row are inconsistent, and the output of the row is incorrect.

[0072] S130, if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, the running of the hardware simulation accelerator is suspended to lock the scene where the pixel data error occurs in the verification environment.

[0073] Specifically, if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are inconsistent, the display data comparison model generates an indication signal to indicate that the comparison is incorrect. Subsequently, in response to the indication signal, the hardware simulation accelerator triggers an emergency pause, thereby freezing the operation of the hardware simulation accelerator. Illustratively, at this time, the current state of the simulation accelerator in the verification environment is fixed, all computing processes of the simulation accelerator are also paused, and all memory states of the current simulation field are locked. At the same time, all signal waveforms stop updating, thereby preserving the complete context at the time of the error. Then, based on the frozen simulation field, the time stamp, line number (i.e., the i-th line), and the position of the error pixel where the error occurs can be accurately located using the signal waveforms, thereby locking the field where the pixel data error occurs. Further, using the error field shown in the waveforms, a Debug process can be performed to directly analyze the data correctness and the behavior correctness of the entire SOC system.

[0074] Optionally, in addition to the standard RGB888 format, a plurality of formats (such as ARGB8888 and RGB565) can be supported, and the data bit swizzle function of the controller can be supported to complete more verification scenarios. Further, in a graphics processing system, this approach can also be extended to verify the operation results of other components, such as a video encoding and decoding unit.

[0075] In the above embodiments, the simulation pixel data is captured in real time by the display data comparison model, and is compared with the corresponding standard pixel data in real time on a line-by-line basis, thereby overcoming the limitation of needing to wait for the entire frame to be displayed before verification can be performed, and achieving pixel-level real-time verification. Moreover, when the simulation pixel data and the standard pixel data are inconsistent, the operation of the hardware simulation accelerator is immediately paused, thereby ensuring that the simulation field is frozen in time when the error occurs, and thereby avoiding the problem of field loss due to the simulation progress being ahead of schedule. Thus, while ensuring high reliability of the verification results, the debugging efficiency is improved from frame-level post-mortem backtracking to line-level in-process interception, thereby significantly improving the reliability and efficiency of the display interface controller verification.

[0076] In some embodiments, please refer to the accompanying drawings Figure 2 If the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, the operation of the hardware simulation accelerator is paused, including:

[0077] S210, if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, a flag bit of the display data comparison model is written as a first preset value.

[0078] The flag bit of the display data comparison model can be a 1-bit hardware status register predefined in the display data comparison model, which is used to represent the state of the current line pixel data comparison result in real time, and can also be used as a basis for triggering the simulator to pause the hardware.

[0079] The first preset value can be a predefined hardware logic level value. For example, the flag of the display data comparison model can be an error (ERROR) indication signal of the display data comparison model, and the first preset value can be a high level, i.e., 1. When the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, the display data comparison model writes the value of the ERROR indication signal as 1, i.e., pulls up the ERROR indication signal, to indicate that there is pixel data mismatch in the current row, so as to trigger the subsequent response.

[0080] S220, if it is monitored that the flag is equal to the first preset value, suspending the running of the hardware simulation accelerator.

[0081] Specifically, the state machine of the display data comparison model can monitor the flag, i.e., the ERROR indication signal, in real time. When it is monitored that the ERROR indication signal is pulled up, the state machine immediately sends a suspension request to the SDL script. Then, the SDL script can further call the suspension instruction of the hardware simulation accelerator, for example, can trigger a pause trigger, so as to suspend the running of the hardware simulation accelerator and freeze the current state of the simulator immediately. Further, based on the frozen simulation scene, the signal waveform can be used to accurately locate the timestamp, line number and error pixel position of the error occurrence through the trigger point, to perform the Debug process.

[0082] In the above embodiment, the pixel data comparison result is fed back in real time through the flag. When it is detected that the simulation data and the standard data are inconsistent, the flag of the display data comparison model is written as the first preset value to trigger the suspension of the hardware simulation accelerator and freeze the complete simulation scene at the time of error occurrence. It should be noted that the display data comparison model is instantiated in the DUT, i.e., it runs in the simulator, so the data comparison is performed in real time. Compared with the manner in the related art that the result can be observed only after a whole frame is output, the real-time data comparison is more convenient for Debug and confirmation of the problem scene. Meanwhile, compared with the manner in the related art that the output result is verified by naked eyes compared with the Golden image, the use of the display data comparison model for data comparison can obviously improve the credibility of the verification result, and provides high-precision and high-timeliness error positioning capability for the DP controller verification.

[0083] In some embodiments, if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are the same, the simulation pixel data is exported to a display device connected with the hardware simulation accelerator, so that the display device displays a simulation image corresponding to the simulation pixel data.

[0084] The display device can be an external terminal device connected to the hardware simulation accelerator and can be used to receive and present the simulation image. The display device can be connected to a display interface component, for example, and can receive simulation image data from the hardware simulation accelerator through a high-speed serial data stream output by the display interface component, convert the data into a visual image, and display the image. Alternatively, the display device can also be a server. Specifically, if it is found that the RGB color components of all the pixel points in the current row are completely matched, that is, the consistency comparison result is the same, it indicates that the simulation pixel data and the standard pixel data are consistent, and the output is correct. At this time, the display data comparison model also generates an indication signal to indicate that the comparison is correct, and then in response to the indication signal, a storage export operation is performed, that is, the storage export function (such as the memory dump function) of the hardware simulation accelerator is triggered, and finally the simulation pixel data is integrated into a file by the storage export function and exported to the display device connected to the hardware simulation accelerator, so that the display device displays the simulation image corresponding to the simulation pixel data.

[0085] In the above embodiments, by automatically comparing the simulation pixel data and the standard pixel data, the hardware simulation accelerator is triggered to export the correct simulation data to the display device when the data is completely matched, and the simulation image is automatically generated, which realizes real-time visualization of the verification result, significantly improves the verification efficiency and accuracy, avoids the delay problem of the traditional display device, and ensures the fast confirmation and automatic processing of data consistency, greatly reducing the manual intervention and debugging time.

[0086] In some embodiments, please refer to the accompanying drawings Figure 3 If the consistency comparison result indicates that the simulation pixel data and the standard pixel data are the same, the simulation pixel data is exported to the display device connected to the hardware simulation accelerator, including:

[0087] S310, if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are the same, the flag bit of the display data comparison model is written as a second preset value.

[0088] Specifically, the flag bit of the display data comparison model can still be the ERROR indication signal of the display data comparison model, and the second preset value can be a low level, that is, 0. If the consistency comparison result indicates that the simulation pixel data and the standard pixel data are the same, the display data comparison model can write the value of the ERROR indication signal as 0, that is, pull down the ERROR indication signal, indicating that the current row of pixel data is matched, so as to trigger the subsequent response.

[0089] Optionally, the flag bit of the display data comparison model can also be a PASS indication signal of the display data comparison model, and the second preset value can also be a high level, that is, 1. When the consistency comparison result shows that the simulation pixel data and the standard pixel data are the same, the display data comparison model writes the value of the PASS indication signal as 1, that is, pulls up the PASS indication signal, which also indicates that the current row of pixel data is matched, so as to trigger the subsequent response.

[0090] S320, if it is monitored that the flag bit is equal to the second preset value, the simulation pixel data is exported to the display device.

[0091] Specifically, if it is found after comparison that the RGB color components of all pixel points in the current row are completely matched, that is, the consistency comparison result is the same, the display data comparison model pulls up the PASS indication signal. After the SDL script monitors that the PASS indication signal is pulled up, the memory dump function of the simulator is further used, that is, the simulation pixel data is exported to the display device, so that the display device displays the simulation image corresponding to the simulation pixel data.

[0092] In the above embodiment, the pixel data comparison result is fed back in real time through the flag bit, and the storage export function is automatically triggered when the data is consistent to export the simulation pixel data to the display device and generate the simulation image, realizing real-time visualization and automatic processing of the verification result, significantly improving the verification efficiency and accuracy, avoiding the delay problem of the traditional display device, and ensuring that the whole process does not need manual intervention through hardware comprehensive code, greatly reducing the debugging time and labor cost, providing an efficient and accurate automatic solution for DP controller verification.

[0093] In some embodiments, the simulation pixel data is stored in a simulation pixel data file. The display device displays the simulation image corresponding to the simulation pixel data by scanning the simulation pixel data file and drawing the scanned pixel data on a pre-created blank image to obtain the simulation image corresponding to the simulation pixel data.

[0094] The simulation pixel data file can be a binary or hexadecimal format data file generated by the hardware simulation accelerator, used to store the simulation pixel data captured from the DP controller in real time, and the file format can be.mem.

[0095] Exemplarily, the display device can also be a server. The server is taken as an example to illustrate the display device. Specifically, when starting the verification operation of the display interface controller, a blank mem file with the same name can also be created in the server. During the entire verification process of the display interface controller, the server can always monitor the state change of the file. When the consistency comparison result is the same, the hardware simulation accelerator integrates the simulation pixel data into a file and exports the file to the server. Since the names are the same, the mem file can be automatically updated. Then, when the server detects that the file is updated, a post-processing script is automatically triggered, that is, the simulation pixel data in the mem file is read and scanned and analyzed to convert the simulation pixel data into an RGB matrix, that is, the simulation pixel data file is scanned to obtain the pixel data. Subsequently, the image library is used to fill the pixel data obtained by scanning on the pre-created blank image, and the pixel data is drawn point by point to the blank image to generate a simulation result with the same resolution as the standard image, and finally a simulation image corresponding to the simulation pixel data is obtained.

[0096] Optionally, the simulation pixel data file and the simulation image also support mutual conversion, so that the data and the image can be conveniently output as specific files, thereby facilitating the application expansion of comparison and post-processing.

[0097] In the above embodiment, not only the format conversion error in the transmission process is effectively avoided through pixel-level data analysis, but also the whole process from data export to image display is in an automatic manner. The output image speed is obviously improved compared with the traditional display method of displaying on a real display device through a speed bridge, and single-frame output can achieve fast graphic display.

[0098] The display interface controller verification method provided in the embodiments of the present specification is applied to a verification environment built based on a hardware simulation accelerator. The hardware simulation accelerator runs a design-under-test model. The design-under-test model includes a display interface controller component and a display interface component. A display data comparison model implemented by using a synthesizable hardware description language is bound to the output end of the display interface controller component. The display data comparison model is used to detect the consistency between simulation image data and standard image data. The hardware simulation accelerator stores a standard pixel data file of the standard image data. Simulation pixel data is stored in a simulation pixel data file. The method includes the following steps:

[0099] S402, in the process that the display interface controller component sends simulation image data to the display interface component, the line synchronization signal of the image timing generator is monitored through the display data comparison model. In response to the preset jump of the monitored line synchronization signal, the simulation pixel data of the ith row is written into the hardware simulation accelerator. Wherein, i is a positive integer greater than or equal to 1.

[0100] S404, the hardware simulation accelerator is communicatively connected with a server, the standard pixel data file is loaded into the hardware simulation accelerator from the server, and the standard pixel data in the standard pixel data file is obtained by traversing and analyzing each pixel point of the standard image data.

[0101] S406, the display data comparison model reads the i-th row of standard pixel data from the standard pixel data file, and performs real-time consistency comparison between the simulation pixel data and the standard pixel data to obtain a consistency comparison result.

[0102] S408, if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, a flag bit of the display data comparison model is written as a first preset value.

[0103] S410, if it is monitored that the flag bit is equal to the first preset value, the running of the hardware simulation accelerator is paused to lock the scene where the pixel data error occurs in the verification environment.

[0104] S412, if the consistency comparison result indicates that the simulation pixel data and the standard pixel data are the same, the flag bit of the display data comparison model is written as a second preset value.

[0105] S414, if it is monitored that the flag bit is equal to the second preset value, the simulation pixel data is exported to a display device end connected with the hardware simulation accelerator,

[0106] S416, the simulation pixel data file is scanned, the scanned pixel data is drawn on a pre-created blank image to obtain a simulation image corresponding to the simulation pixel data, and the display device displays the simulation image corresponding to the simulation pixel data.

[0107] It should be understood that, although each step in the above flowchart is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps of the above flowchart can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0108] The verification system of the display interface controller provided by the embodiments of the present specification also provides a verification system of a display interface controller, which will be described below with reference to Figure 4The verification system comprises a hardware simulation accelerator 410, a design-under-test model 420 running in the hardware simulation accelerator 410, a display interface controller component 401 and a display interface component 403 contained in the design-under-test model 420, a display data comparison model 430 implemented in a synthesizable hardware description language and bound to an output end of the display interface controller component 401, the display data comparison model 430 being configured to detect consistency between simulation image data and standard image data, and a standard pixel data file of the standard image data stored in the hardware simulation accelerator 410.

[0109] The display data comparison model 430 is configured to capture the i-th row of simulation pixel data in real time in a process in which the display interface controller component 401 sends simulation image data to the display interface component 403, read the i-th row of standard pixel data from the standard pixel data file, and perform real-time consistency comparison between the simulation pixel data and the standard pixel data to obtain a consistency comparison result. If the consistency comparison result indicates that the simulation pixel data and the standard pixel data are different, the running of the hardware simulation accelerator is paused to lock the scene in which pixel data error occurs in a verification environment built based on the hardware simulation accelerator. Here, i is a positive integer greater than or equal to 1.

[0110] Specifically, in the process in which the display interface controller component 401 sends simulation image data to the display interface component 403, the display data comparison model 430 first monitors the interface data transmission state in real time. When the transmission of data is detected, the display data comparison model 430 analyzes the i-th row of simulation pixel data in the transmission line in real time, that is, the current row, and writes the simulation pixel data in the order of pixels in the row into a designated continuous memory space of the hardware simulation accelerator, thereby completing real-time capture.

[0111] Subsequently, the i-th row of standard row pixel data, that is, the current row, is read from the standard pixel data file by using the transmission characteristics of the design-under-test model 420, and real-time consistency comparison between the simulation pixel data and the standard pixel data is performed pixel by pixel. Specifically, in the comparison, all pixel data in the current row is compared one by one at one time in units of rows, and finally a consistency comparison result is obtained. For example, if it is found after comparison that the RGB color components of all pixel points in the i-th row are completely matched, the consistency comparison result of the row is that the comparison is the same. If it is found after comparison that the RGB components of any pixel point in the i-th row are not matched, the consistency comparison result of the row is that the comparison is different.

[0112] Further, if the consistency comparison result shows that the simulation pixel data is different from the standard pixel data, the running of the hardware simulation accelerator is suspended to lock the field where the pixel data error occurs in the verification environment built based on the hardware simulation accelerator. Specifically, if the consistency comparison result shows that the i-th row of simulation pixel data is inconsistent with the standard pixel data, the display data comparison model generates an indication signal to indicate that the i-th row of comparison is incorrect. Then, in response to the indication signal, the hardware simulation accelerator triggers an emergency suspension, thereby freezing the running of the hardware simulation accelerator. Subsequently, based on the frozen simulation field, a Debug process can be performed, and the i-th row of error field shown in the waveform can be directly used for data correctness and overall SOC system behavior correctness analysis.

[0113] It should be noted that while the display data comparison model performs the above operation, the verification of the hardware simulation accelerator can also proceed normally. Please continue to refer to Figure 4 The verification environment of the display interface controller is composed of three parts: a design-under-test model, a speed bridge, and a device. The display interface component 403 of the design-under-test model can have four transmission channels, namely channel 0, channel 1, channel 2, and channel 3. In addition, since the physical layer used in the real chip cannot be synthesized, it needs to be replaced by a synthesizable physical layer model, which corresponds to the four channels of the display interface component 403. The physical layer model can also deliver data to the packaging layer. The packaging layer has data signals and clock signals, which can be connected to the speed bridge through instantiation of the hardware description language (Verilog) connection, corresponding to the data signals and clock signals in the speed bridge. Then, after processing by the speed bridge, the rate gap between the design-under-test model simulated in the hardware simulation accelerator and the device is balanced, and finally the data can be output to the device through the speed bridge, which can be a real display device such as a display for observation and judgment of the correctness of the display result by the verification personnel. In the above embodiment, the display data comparison model is used to capture simulation pixel data in real time and perform real-time consistency comparison with the corresponding standard pixel data row by row, overcoming the limitation of needing to wait for the entire frame to be displayed for verification, and achieving pixel-level real-time verification. Moreover, when the simulation pixel data is inconsistent with the standard pixel data, the running of the hardware simulation accelerator is immediately suspended, ensuring that the simulation field is frozen in time when an error occurs, thereby avoiding the problem of field loss due to simulation progress ahead of schedule. Thus, under the premise of ensuring high reliability of the verification result, the debugging efficiency is improved from frame-level post-tracing to row-level in-process stopping, significantly improving the reliability and efficiency of the display interface controller verification.

[0114] In some embodiments, please continue to refer to Figure 4 The verification system further includes a server 440 in communication connection with the hardware simulation accelerator 410.

[0115] The hardware simulation accelerator 410 is configured to export the simulation pixel data to the server 440 in communication connection with the hardware simulation accelerator if the consistency comparison result shows that the simulation pixel data and the standard pixel data are the same.

[0116] The server 440 is configured to receive the simulation pixel data and display a simulation image corresponding to the simulation pixel data.

[0117] Optionally, the display device can also be the server. It should be noted that the standard image data is stored in the server 440, and the standard pixel data file obtained by performing pixel-by-pixel processing on the standard image data is stored in the hardware simulation accelerator 410. After determining that the simulation pixel data and the standard pixel data are the same, when it is necessary to quickly display the simulation image corresponding to the simulation pixel data, the simulation pixel data is exported from the hardware simulation accelerator through the storage export function of the hardware simulation accelerator, and the exported is the simulation pixel data file in the integrated format, which is also stored in the server 440.

[0118] Specifically, if it is found that the RGB color components of all the pixel points in the current row are completely matched after comparison, that is, the consistency comparison result is comparison same, it indicates that the simulation pixel data and the standard pixel data are consistent and the output is correct. At this time, the display data comparison model will also generate an indication signal to indicate that the comparison is correct, and then in response to the indication signal, a storage export operation is performed, that is, the memory dump function of the hardware simulation accelerator is triggered to integrate the simulation pixel data into a file and export it to the server in communication connection with the hardware simulation accelerator, so that the server displays a simulation image corresponding to the simulation pixel data.

[0119] In the above embodiment, through the cooperation of the server and the hardware simulation accelerator, the whole process from image analysis to data loading does not require manual intervention, and by automatically comparing the simulation pixel data with the standard pixel data, the hardware simulation accelerator is triggered to export the correct simulation data to the server when the data is completely matched, and a simulation image is automatically generated, realizing real-time visualization of the verification result and significantly improving the verification efficiency and accuracy.

[0120] The specific limitations of the display interface controller verification system can be referred to the limitations of the display interface controller verification method in the above, which will not be repeated here. Each module in the above display interface controller verification system can be realized by software, hardware and their combinations. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to call and execute the operations corresponding to the above modules by the processor.

[0121] The verification device of the display interface controller in the embodiment is in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0122] The verification device of the display interface controller in the embodiment is in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0123] The memory is configured to store the program.

[0124] The processor is configured to call the program from the memory, so that the verification device executes the method in any of the above embodiments.

[0125] The specific limitations of the verification device of the display interface controller can be referred to the limitations of the verification method of the display interface controller in the above, which will not be described here. Each module in the verification device of the display interface controller can be realized by software, hardware and combinations thereof, in whole or in part. Each module can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor calls and executes the operations corresponding to each module.

[0126] The embodiment of the present application further provides a computer device, which can be a terminal, and the internal structure diagram thereof can be as shown in Figure 5 The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The communication interface of the computer device is configured to perform wired or wireless communication with an external terminal. The wireless communication can be achieved through WIFI, mobile cellular network, NFC (Near Field Communication) or other technologies. The computer program is executed by the processor to implement a verification method of a display interface controller. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0127] Those skilled in the art can understand, Figure 5The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0128] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network and stored in the local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller or the programmable hardware include a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor or the hardware, the method shown in the above embodiments is implemented.

[0129] The embodiments of the present application provide a computer program product, which includes computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method of any embodiment of the present application.

[0130] The method, system and device for verifying the display interface controller described in the above embodiments can be implemented by a computer chip or entity, or by a product having certain functions. A typical implementation device is a computer. Specifically, the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0131] For the convenience of description, the above device is described as various units divided by functions. Of course, the functions of each unit can be implemented in the same or more software and / or hardware in the implementation of the present application.

[0132] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0133] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams. In the description of this specification, references to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The various embodiments in this specification are described in a progressive manner; similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. Since they are basically similar to the method embodiments, the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments. The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A verification method for a display interface controller, characterized in that, The method is applied in a verification environment built on a hardware simulation accelerator, in which a design-under-test (DIT) model runs. The DIT model includes a display interface controller component and a display interface component. A display data comparison model implemented using a synthesizable hardware description language is bound to the output of the display interface controller component. This display data comparison model is used to detect the consistency between simulated image data and standard image data. The hardware simulation accelerator stores a standard pixel data file of the standard image data. The method includes: During the process of the display interface controller component sending the simulated image data to the display interface component, the simulated pixel data of the i-th row is captured in real time through the display data comparison model; where i is a positive integer greater than or equal to 1. The standard pixel data of the i-th row is read from the standard pixel data file by the display data comparison model, and the simulated pixel data and the standard pixel data are compared in real time to obtain the consistency comparison result. If the consistency comparison result indicates that the simulated pixel data and the standard pixel data are different, the operation of the hardware simulation accelerator is paused to lock the scene where the pixel data error occurred in the verification environment.

2. The method according to claim 1, characterized in that, If the consistency comparison result indicates that the simulated pixel data and the standard pixel data are different, the operation of the hardware simulation accelerator is paused, including: If the consistency comparison result indicates that the simulated pixel data and the standard pixel data are different, the flag bit of the display data comparison model is set to the first preset value. If the flag bit is detected to be equal to the first preset value, the operation of the hardware simulation accelerator is paused.

3. The method according to claim 1, characterized in that, The method further includes: If the consistency comparison result indicates that the simulated pixel data and the standard pixel data are the same, the simulated pixel data is exported to a display device connected to the hardware simulation accelerator so that the display device displays the simulated image corresponding to the simulated pixel data.

4. The method according to claim 3, characterized in that, If the consistency comparison result indicates that the simulated pixel data and the standard pixel data are the same, the simulated pixel data is exported to a display device connected to the hardware simulation accelerator, including: If the consistency comparison result indicates that the simulated pixel data and the standard pixel data are the same, the flag bit of the display data comparison model is set to the second preset value. If the flag bit is detected to be equal to the second preset value, the simulated pixel data is exported to the display device.

5. The method according to claim 3, characterized in that, The simulated pixel data is stored in a simulated pixel data file; the display device displays the simulated image corresponding to the simulated pixel data in the following manner: The simulated pixel data file is scanned, and the scanned pixel data is drawn on a pre-created blank image to obtain the simulated image corresponding to the simulated pixel data.

6. The method according to claim 1, characterized in that, The step of capturing simulated pixel data of the i-th row in real time through the display data comparison model includes: The display data comparison model is used to monitor the line synchronization signal of the image timing generator. In response to the preset transition of the monitored line synchronization signal, the simulated pixel data of the i-th line is written into the preset memory space of the hardware simulation accelerator.

7. The method according to any one of claims 1 to 6, characterized in that, The hardware emulation accelerator is connected to a server. The standard pixel data file is loaded into the hardware emulation accelerator from the server. The standard pixel data in the standard pixel data file is obtained by traversing and parsing each pixel of the standard image data.

8. A verification system for a display interface controller, characterized in that, The verification system includes a hardware simulation accelerator, in which a design under test (DUT) model runs. The DUT model includes a display interface controller component and a display interface component. A display data comparison model implemented using a synthesizable hardware description language is bound to the output of the display interface controller component. The display data comparison model is used to detect the consistency between simulated image data and standard image data. The hardware simulation accelerator stores a standard pixel data file of the standard image data. The display data comparison model is configured to capture the simulated pixel data of the i-th row in real time during the process of the display interface controller component sending the simulated image data to the display interface component; Read the standard pixel data of the i-th row from the standard pixel data file, and perform a real-time consistency comparison between the simulated pixel data and the standard pixel data to obtain a consistency comparison result; if the consistency comparison result shows that the simulated pixel data and the standard pixel data are different, pause the operation of the hardware simulation accelerator to lock the scene where the pixel data error occurred in the verification environment built based on the hardware simulation accelerator; where i is a positive integer greater than or equal to 1.

9. The verification system according to claim 8, characterized in that, The verification system also includes a server that is communicatively connected to the hardware simulation accelerator; The hardware simulation accelerator is configured to export the simulated pixel data to a server that is communicatively connected to the hardware simulation accelerator if the consistency comparison result shows that the simulated pixel data and the standard pixel data are the same. The server is configured to receive the simulated pixel data and display the simulated image corresponding to the simulated pixel data.

10. A verification device for a display interface controller, characterized in that, include: Memory, used to store programs; A processor for calling a program from the memory to cause the verification device to perform the method as described in any one of claims 1 to 7.

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