Interleaved servo patterns in data storage devices

Abstract

The present disclosure describes example control circuits, data storage devices, and methods for parallel self-servo writing of interleaved servo patterns in a data storage device. The data storage device may include a plurality of heads that actuate over different surfaces of the data storage device and receive read signals in parallel from two different heads over two different surfaces. The servo wedge regions of the two surfaces can be offset to enable independent phase determination when servo patterns are written in parallel to the two surfaces using their respective heads.

Description

Technical Field

[0001] This disclosure relates to a self-servo writing process for a data storage device. In particular, this disclosure relates to the use of data storage device hardware circuitry that may include read / write paths for two-dimensional magnetic recording to write servo tracks on two magnetic heads in an interleaved servo pattern. Background Technology

[0002] The self-servo write (SSW) process is a critical step in the manufacture of hard disk drives (HDDs), which are widely used for data storage in various computing devices. This process involves creating servo tracks on the disk surface within the HDD. The drive's control system uses these servo tracks to precisely position the read / write head above the data tracks during operation. The accuracy of the servo track write is crucial to the drive's performance, as it directly affects the magnetic recording density and reliability of data storage.

[0003] Traditionally, servo track writing can be divided into two main methods: external and internal. External servo writing requires writing positioning information onto the disk before it is assembled into the HDD, typically using specialized equipment. In contrast, internal writing, or SSW, utilizes the HDD's own read / write heads to write servo information after the disk assembly is installed in the drive. SSW offers the advantage of aligning the servo tracks with the drive's final assembled state, taking into account any changes that may occur during assembly.

[0004] The SSW process begins when the disk surface is initially blank. As the disk rotates, a servo writer embedded within the HDD writes a series of helical reference patterns onto the disk, such as sweeping the write head between the inner and outer diameters at a known rate and writing known magnetic conversion patterns. These helical reference patterns provide positioning information that can be used to write production servo patterns onto the disk surface.

[0005] Figure 1A An example servo pattern is shown. Figure 1A The existing disk format includes multiple servo sectors 60-6 recorded in a circle around disk 2. N These servo sectors define multiple servo tracks, with data track 4 defined relative to the servo tracks. Each servo sector 6 i It may include a preamble 8 for storing a periodic pattern and a synchronization mark 10 for storing a special pattern for synchronizing with the symbols of the servo data field 12. The periodic pattern allows for appropriate gain adjustment and timing synchronization of the read signal. The servo data field 12 stores coarse head positioning information, such as the track address, for positioning the head above the target data track during seek operations. Each servo sector 6 iIt may further include a servo pulse group 14 (e.g., A, B, C, and D pulses), which includes multiple successive transitions recorded at precise intervals and offsets relative to the centerline of the data track. The servo pulse group 14 provides fine head position information for centerline tracking while accessing the data track during write / read operations. In some configurations, the servo and data tracks can be combined to form different physical regions written at different track densities or frequencies, such as from the inner diameter (Z0) of the disk to the outer diameter (Z2).

[0006] Self-servo writing can be a lengthy process, especially for data storage devices containing a large number of storage media platters. For example, some HDD form factors can include up to 10 platters, each with two storage media surfaces. Therefore, it can be advantageous to use multiple read / write heads to write servo tracks in parallel on multiple surfaces. However, the HDD control circuitry cannot be designed to support simultaneous reading and writing by different heads on different surfaces. While dedicated control circuitry (with appropriate interfaces and data channels to and from the internal heads and actuators) can be provided externally to the HDD control circuitry or added to the internal HDD circuitry, the impact of hardware used only during the self-servo writing process on the HDD cost may be undesirable.

[0007] When using onboard hardware as a parallel self-servo write control circuit for parallel self-servo writing, improvements to the phase control technique are required. Summary of the Invention

[0008] Various aspects of a data storage device supporting parallel self-servo writing are described, particularly an interleaved servo pattern for improved phase control. This interleaved servo pattern utilizes control circuitry in the data storage device that supports both self-servo writing and production read / write operations. The data storage device is configured to perform two-dimensional magnetic recording (TDMR) using multiple read / write elements on each head and corresponding read / write paths.

[0009] One general aspect includes a data storage device having a first storage medium surface and a second storage medium surface, the first storage medium surface including a first servo pattern and the second storage medium surface including a second servo pattern, wherein: the first servo pattern and the second servo pattern are written in parallel to define corresponding portions of the first servo pattern and the second servo pattern; and the phase of the first servo pattern of a portion of the first servo pattern is different from the phase of the second servo pattern of the corresponding portion of the second servo pattern.

[0010] Specific implementations may include one or more of the following features: A first servo pattern may include a first plurality of servo wedge regions; a second servo pattern may include a second plurality of servo wedge regions; and in corresponding portions of the first and second servo patterns, the first plurality of servo wedge regions may be offset from the second plurality of servo wedge regions. The offset time between the first plurality of servo wedge regions and the second plurality of servo wedge regions may be half of the wedge-to-wedge timing of the first servo pattern. A portion of the first servo pattern may have a first track value per inch; a corresponding portion of the second servo pattern may have a second track value per inch; and the first track value per inch may be different from the second track value per inch. The data storage device may include control circuitry configured to, during a self-servo write operation: determine a first target head positioned above a surface of a first storage medium; determine a second target head positioned above a surface of a second storage medium; determine a first servo pattern phase; write a servo pattern segment of a servo wedge region of a first servo pattern using the first target head and the first servo pattern phase; determine a second servo pattern phase; and write a servo pattern segment of a servo wedge region of a second servo pattern using the second target head and in response to a wait offset time. The control circuitry may include a servo pulse pattern writer and is further configured to, during a self-servo write operation: use the servo pulse pattern writer to generate a servo pattern segment of a servo wedge region of a first servo pattern; and use the servo pulse pattern writer to generate a servo pattern segment of a servo wedge region of a second servo pattern. The control circuit can also be configured, during a self-servo write operation, to: read a first reference signal from the surface of a first storage medium using a first target head; determine a first frequency offset value for determining the phase of a first servo pattern based on the first reference signal; read a second reference signal from the surface of a second storage medium using a second target head; and determine a second frequency offset value for determining the phase of a second servo pattern based on the second reference signal. The control circuit can also be configured, during a self-servo write operation, to: determine a first set of timestamps based on the first reference signal; process the first set of timestamps through a first timing loop to generate a first timing value, wherein the first frequency offset value is determined based on the first timing value; update a first frequency offset register in the control circuit using the first frequency offset value; determine a second set of timestamps based on the second reference signal; process the second set of timestamps through a second timing loop to generate a second timing value, wherein the second frequency offset value is determined based on the second timing value; and update a second frequency offset register in the control circuit using the second frequency offset value.The control circuit can also be configured, during a wedge repetitive yaw learning operation: determine a first target head positioned above a first storage medium surface; determine a second target head positioned above a second storage medium surface; use the first target head to read servo pattern segments of the sequential servo wedge region of the first servo pattern; use the second target head and alternately read servo pattern segments of the sequential servo wedge region of the first servo pattern, wherein the first and second servo patterns are read in the same loops on the first and second storage medium surfaces; calculate a first set of wedge repetitive yaw correction values ​​for the sequential servo wedge region of the first servo pattern; and calculate a second set of wedge repetitive yaw correction values ​​for the sequential servo wedge region of the second servo pattern. The control circuit can also be configured, during a read / write operation, to switch between operations on the first storage medium surface and operations on the second storage medium surface at a switching time half that of the wedge-to-wedge timing, a switching time shorter than that between storage medium surfaces having substantially aligned servo wedge regions.

[0011] Another general aspect includes a method comprising, in a data storage device, positioning a first read / write head above a first storage medium surface using a first servo pattern; performing a first storage operation at a first target location based on the first servo pattern using the first read / write head and the first storage medium surface; positioning a second read / write head above a second storage medium surface using a second servo pattern in the data storage device, wherein the first servo pattern and the second servo pattern are written in parallel to define corresponding portions of the first servo pattern and the second servo pattern, and a phase of the first servo pattern for a portion of the first servo pattern differs from the phase of the second servo pattern for a corresponding portion of the second servo pattern; and performing a second storage operation at a second target location based on the second servo pattern using the second read / write head and the second storage medium surface.

[0012] Specific implementations may include one or more of the following features: A first servo pattern may include a first plurality of servo wedges; a second servo pattern may include a second plurality of servo wedges; and in corresponding portions of the first and second servo patterns, the first plurality of servo wedges may be offset from the second plurality of servo wedges. The offset time between the first plurality of servo wedges and the second plurality of servo wedges may be half of the wedge-to-wedge timing of the first servo pattern. A portion of the first servo pattern may have a first track value per inch; a corresponding portion of the second servo pattern may have a second track value per inch; and the first track value per inch may be different from the second track value per inch. The method may include, during a self-servo write operation: determining a first servo pattern phase; using a first head, writing a servo pattern segment of a servo wedge region of the first servo pattern using the first servo pattern phase; determining a second servo pattern phase; and using a second head and in response to a waiting offset time, writing a servo pattern segment of a servo wedge region of the second servo pattern using the second servo pattern phase. The method may include, during a self-servo write operation: using a servo pulse pattern writer in a data storage device to generate servo pattern segments of a servo wedge region of a first servo pattern; and using a servo pulse pattern writer to generate servo pattern segments of a servo wedge region of a second servo pattern. The method may also include, during a self-servo write operation: using a first read head to read a first reference signal from the surface of a first storage medium; determining a first frequency offset value for determining the phase of the first servo pattern based on the first reference signal; using a second read head to read a second reference signal from the surface of a second storage medium; and determining a second frequency offset value for determining the phase of the second servo pattern based on the second reference signal. The method may include, during a self-servo write operation: determining a first set of timestamps based on a first reference signal; processing the first set of timestamps through a first timing loop to generate a first timing value, wherein a first frequency offset value is determined based on the first timing value; updating a first frequency offset register in a data storage device using the first frequency offset value; determining a second set of timestamps based on a second reference signal; processing the second set of timestamps through a second timing loop to generate a second timing value, wherein a second frequency offset value is determined based on the second timing value; and updating a second frequency offset register in a data storage device using the second frequency offset value.The method may include, during a wedge repetitive yaw learning operation: using a first read head to read servo pattern segments of a sequential servo wedge region of a first servo pattern; using a second read head and alternating with reading servo pattern segments of a sequential servo wedge region of a second servo pattern, wherein the first and second servo patterns are read in the same loops on the first and second storage medium surfaces; calculating a first set of wedge repetitive yaw correction values ​​for the sequential servo wedge region of the first servo pattern; and calculating a second set of wedge repetitive yaw correction values ​​for the sequential servo wedge region of the second servo pattern.

[0013] Another general aspect includes a data storage device comprising: a first magnetic head actuated above a surface of a first storage medium; a second magnetic head actuated above a surface of a second storage medium; means for determining a first servo pattern phase; means for writing servo pattern segments of a servo wedge region of a first servo pattern onto the surface of the first storage medium using the first magnetic head and the first servo pattern phase; means for determining a second servo pattern phase; and means for writing servo pattern segments of a servo wedge region of a second servo pattern onto the surface of the second storage medium using the second magnetic head and the second servo pattern phase, and in response to waiting for an offset time from the first servo pattern, wherein the first servo pattern and the second servo pattern are written in parallel to define corresponding portions of the first servo pattern and the second servo pattern, and the first servo pattern phase of a portion of the first servo pattern is different from the second servo pattern phase of the corresponding portion of the second servo pattern.

[0014] This disclosure describes various aspects of innovative techniques capable of improving self-servo writing to reduce manufacturing time / cost of data storage devices, while also controlling the cost impact on control circuitry within the data storage device. Various embodiments include operating and control circuitry to overcome or at least reduce problems previously encountered in data storage devices, and are therefore more efficient, reliable, and / or cost-effective than other data storage devices. That is, the various embodiments disclosed herein include hardware and / or software with capabilities to improve the cost, quality, and manufacturing time of data storage devices, for example, by using control circuitry and interleaved servo patterns that support dual-head parallel self-servo writing (hereinafter referred to as self-servo writing or SSW) and single-head read / write operations in the data storage device. Therefore, the embodiments disclosed herein provide various improvements to data storage devices and computing systems including such data storage devices. Attached Figure Description

[0015] The techniques described herein are illustrated in the accompanying drawings by way of example rather than limitation, in which the same reference numerals are used to refer to similar elements.

[0016] Figure 1A This is a schematic diagram of a prior art disk format that includes multiple servo sectors that define servo tracks.

[0017] Figure 1B and Figure 1C This is a schematic diagram of a prior art data storage device in the form of a disk drive, which includes at least one read / write head actuated above the disk surface using control circuitry, and a corresponding side view of an arm / actuator assembly for two sets of read / write heads.

[0018] Figure 2A and Figure 2B This is a schematic diagram of the control circuitry operating in two different modes to support self-servo write and read / write operations.

[0019] Figure 2C and Figure 2D It is used for Figure 2A and Figure 2B A schematic diagram of another example servo interface circuit in self-servo write and read / write operation modes.

[0020] Figure 3A This is a configuration block diagram of a data storage device, which includes control circuitry and a storage medium format that is written using self-servo write.

[0021] Figure 3B yes Figure 3A The diagram shows an additional feature of the configuration of the data storage device, which is used to support interleaved servo patterns with independent phase control.

[0022] Figure 4A This is a schematic diagram illustrating parallel self-servo writing using two heads with corresponding preamplifier circuits.

[0023] Figure 4B It shows the use Figure 4A A schematic diagram of self-servo writing of interleaved servo patterns by two heads.

[0024] Figure 5A and Figure 5B This is an example preamplifier configuration for parallel self-servo writing using TDMR heads.

[0025] Figure 5C This is an example preamplifier configuration for parallel self-servo writing using a single read head.

[0026] Figure 5D This is an example selection logic unit used to control the switching of the preamplifier circuit between self-servo write mode and read / write operation mode.

[0027] Figure 6A and Figure 6B It is an example logic component used to determine the servo control signals for parallel self-servo writing.

[0028] Figure 7A and Figure 7B This is a schematic diagram illustrating an example method for learning wedge-region repetitive yaw correction in parallel with the writing medium scan pattern.

[0029] Figure 7C and Figure 7D This is a schematic diagram of another example method for learning repetitive yaw correction in the wedge region in parallel with the writing medium scan pattern.

[0030] Figure 8 This is an example method for parallel self-servo writing using a drive control circuit.

[0031] Figure 9 This is an example method for parallel self-servo writing of interleaved servo patterns with independent phase control.

[0032] Figure 10 This is an example method for wedge-region repetitive yaw correction training with optional media scan pattern parallel writing.

[0033] Figure 11 This is an example method for switching between self-servo write and driver configuration operations and production read / write operations. Detailed Implementation

[0034] Parallel self-servo write (SSW) based on concurrent SSW filling, using onboard data storage electronics and independent micro dual-stage actuator position control, can reduce SSW test time without significantly impacting the cost of the electronics. In some configurations, the data storage device reads one head in parallel from the upper preamplifier circuitry and one head from the lower preamplifier circuitry, based on a previously written helical reference pattern. Helical position and timing detection are handled using the storage device controller and a decoupled two-dimensional magnetic recording (TDMR) channel. Separate microactuator drivers for the heads on both sets provide individual positioning based on the shared voice coil motor (VCM) position. The SSW firmware can calculate the position and phase errors of both heads in parallel. The VCM can track the average decoupled position error signal (PES), while each microactuator compensates for its corresponding PES. In some configurations, phase control can also be handled separately for each head. In some configurations, multiple positioning based on previously written helices can be used to write a better helix before finally writing the concentric servo tracks and corresponding servo sectors used to produce the servo pattern.

[0035] exist Figure 1BIn this context, the control circuitry 20 of the data storage device (such as a hard disk drive (HDD)) processes the read signal 42 emitted from the read / write head 16 to demodulate the servo sectors 380-38. N The control circuit 20 generates a position error signal (PES), which represents the error between the actual position of the read / write head and the target position relative to the target track during track following operations. The control circuit 20 filters the PES using a suitable compensation filter to generate multiple control signals for positioning the read / write head 16 relative to the surface of the disk 22. A VCM control signal can be applied to a VCM 46, which rotates the actuator arm 18 about a pivot, thereby radially actuating the read / write head 16 above the disk 22 in a direction that reduces PES. A milli-actuator control signal 48 can be applied to a piezoelectric actuator 36 on a suspension 17 near the tip of the arm 18 to provide fine lateral positioning, further reducing PES. This actuator may hereafter be referred to as a milli-actuator or a suspension actuator. In some configurations, an additional actuator, such as a micro-actuator positioned closer to the read / write head 16 and receiving another control signal from the control circuit 20, can be provided on the suspension 17. This actuator may subsequently be referred to as a micro-actuator or a head actuator. Servo sector 380-38 N This can include any suitable location information, such as servo track and wedge zone addresses for coarse positioning, and servo pulses for fine positioning, as referenced above. Figure 1A The servo pulse can include any suitable pattern, such as... Figure 1A The diagram shows an amplitude-based servo pattern or a phase-based servo pattern. During data read / write operations, the control circuit 20 can use data from servo sectors 380-38. N The feedback positions the read / write head 16 on the disk 22 to seek and follow the desired data track for data reading and writing operations. For example, the control circuit 20 can receive host storage commands from the host 24 via the host interface and determine the corresponding data read and write operations to read previously written data from the disk 22 or write new data to the disk 22.

[0036] exist Figure 1C The image shows a side view of the heads and disk stack of a data storage device consisting of multiple disks 22 and corresponding read / write heads 16. For example, each disk 22 may include two recordable storage medium surfaces located on opposite surfaces of the disk and read by a corresponding read / write head. Figure 1CIn this configuration, the disk stack includes four disks, eight storage medium surfaces, and eight corresponding heads. The heads and disks can be grouped. For example, disk 22A and head 16A can correspond to a first group of heads and media, and disk 22B and head 16B can correspond to a second group of heads and media. In some configurations, a single VCM 46 can provide overall positioning of the two head groups on the corresponding medium surfaces. In some configurations, separate actuators can include separate VCMs (and receive corresponding control signals) for different head groups. Furthermore, each arm can include one or more arm or head actuators 36, such as piezoelectric microactuators, located somewhere along the length of the suspension 17. Each suspension or head actuator can be individually controlled when the corresponding head is an active head for reading or writing data. In some configurations, each head group can include corresponding preamplifier circuitry and flexible circuitry connections to the data storage device controller circuitry.

[0037] Figure 2A and Figure 2B An example configuration of control circuitry 200 is shown, which is used to position the heads in two head groups organized in a data storage device. Figure 2A In this context, the control circuit 200 is configured to perform data read / write operations based on servo data written during a self-servo write operation, and... Figure 2B In this configuration, control circuitry 200 is configured for self-servo write operations (during the self-servo write portion of the manufacturing and testing process). In the illustrated configuration, control circuitry 200 includes servo interface circuitry 210, servo control circuitry 230 (sometimes referred to as a servo interface controller), flexible circuitry 240, preamplifier circuitry 270, read / write channel 280, and various connections (such as wires or traces) and interfaces (R pins or connectors). Control circuitry 200 interacts with head assembly 260 for actuator control and read / write signals. For each head assembly, only a portion of a suspension assembly 262 is shown, but each head assembly may include multiple suspensions and heads corresponding to the number of storage media surfaces in a disk stack. For example, a four-platter HDD may include eight suspensions / heads organized into two groups of four heads, or a ten-platter HDD may include twenty suspensions / heads organized into two groups of ten heads. The control circuit 200 can be switchable to select any head (and corresponding actuator) from each stack for parallel SSW operation; therefore, only the control path for the selected head is shown.

[0038] Servo interface circuitry 210 may include a set of motor or actuator drivers for positioning the read / write head above a medium surface. Servo interface circuitry 210 may receive digital servo control signals calculated by servo control logic unit 230 to generate analog control signals for the respective motor or actuator. Each circuit used to generate the analog control signals for the motor or actuator may be referred to as a motor or actuator control circuit. For example, servo interface circuitry 210 may include a VCM digital-to-analog converter (DAC) 212 configured to receive digital position control signals for the VCM and convert them into a pair of analog control signals suitable for driving the VCM to the desired position. A micro-actuator DAC 214 may be configured to provide actuator control signals to a micro-actuator of the selected read / write head (e.g., a piezoelectric actuator on a suspension near the end of the arm) during read / write mode, or to a micro-actuator of a second read / write head during self-servo write mode. The milli-actuator DAC 214 can be configured to receive a digital position control signal for the milli-actuator or for a second micro-actuator in parallel self-servo write mode, and convert the digital position control signal into an analog control signal provided to the actuator via the biphase driver block 222. The micro-actuator DAC 216 can be configured to provide actuator control signals to the micro-actuator of the selected head (e.g., the piezoelectric actuator closest to the head) during read / write mode or self-servo write mode. The micro-actuator DAC 216 can be configured to receive a digital position control signal for the selected micro-actuator and convert the digital position control signal into an analog control signal provided to the actuator. In some configurations, the micro-actuator DAC 216 can be coupled to a pair of biphase driver circuits 222 and 224. The biphase driver circuits 222 and 224 can amplify the same and opposite phases of the analog control signal before sending the analog control signal from the micro-actuator DAC 216 to the micro-actuator of the selected head. The dual-phase driver circuits 222 and 224 can generate AC control signals for the connected microactuators. This configuration supports read / write modes. In parallel self-servo write mode, microactuator DAC 216 drives only block 224, while block 222 is controlled by DAC 214.

[0039] The servo interface circuit 210 may include one or more switches for changing the operation and / or control path of the DAC between a self-servo write mode and a data read / write mode. For example, switch 218 may determine whether the milli-actuator DAC 214 is electrically connected to the milli-actuator of the target head in read / write mode, or control one of the micro-actuators during self-servo write mode. Switch 220 may select whether the biphase driver circuit 222 is connected to the milli-actuator DAC 214 or the micro-actuator DAC 216.

[0040] exist Figure 2A In this configuration, switch 218 is closed, connecting the micro-actuator DAC 214 to the micro-actuator of the target head for read / write operations, and the selection of the preamplifier determines which head is being controlled (from the first head group or the second head group). Switch 220 is turned on for path 220.2 to connect the micro-actuator DAC 216 to biphase driver circuits 222 and 224. This allows the micro-actuator DAC 216 to also drive the micro-actuator of the target head for read / write operations based on the preamplifier determining which head is being controlled. This mode corresponds to regular read / write.

[0041] exist Figure 2B In this configuration, switch 218 is turned off, thereby disconnecting the micro-actuator DAC 214 from the micro-actuator. Switch 220 is turned on for path 220.1 to connect the micro-actuator DAC 214 to the biphase driver circuit 222, thereby controlling the micro-actuator of one of the target heads, while the micro-actuator DAC 216 remains connected to the biphase driver circuit 224 to control the micro-actuator of the other target head for parallel self-servo writing.

[0042] In some configurations, the servo interface circuit 210 may include multiple interface connections 226.1-226.6 to connect control paths from the DAC to corresponding motors or actuators via the flexible circuit 240. For example, the flexible circuit 240 may include multiple wires or traces connecting to pin interfaces from the servo interface circuit 210 and providing electrical connections to input interface connections on the corresponding motor or actuator assembly. The flexible circuit 240 may include an interface connector 242 that connects to board-based circuitry in a data storage device, such as a printed circuit board assembly (PCBA) including a device controller, servo interface circuit 210, servo control logic unit 230, and channel 280. For illustrative purposes, the interface connection 272 between channel 280 and preamplifier circuit 270 is shown separately, but this interface connection may be part of the same pin interface 242 and traces passing through the flexible circuit 240. The flexible circuit 240 may receive a pair of VCM control signals 244 and electrically connect them in the VCM control path to the VCM of the moving head stack. Flexible circuit 240 can receive milliactor control signal 246 and electrically connect it to the milliactor of the target head in the milliactor control path. In some configurations (described later), an additional DAC may be present in servo interface circuit 210 to drive the milliactor using milliactor control signal 246 during self-servo write mode. Flexible circuit 240 can receive microactor control signals 248, 250, 252, and 254 to electrically connect microactor DAC 216 and / or milliactor DAC 214 in the microactor control path to the microactor of the target head.

[0043] The servo control logic unit 230 can generate motor and actuator control signals for adjusting the positioning of the read / write head above the medium surface. The servo control logic unit 230 can receive position error signals 288 and 290 from channel 280 using a combination of hardware and software, and generate digital VCM and actuator control signals in the form of digital adjustment values ​​for changing the position of the corresponding motor or actuator. For example, the servo control logic unit 230 can generate a digital VCM control signal 236, a milli-actuator control signal 234, and a micro-actuator control signal 232. In some configurations, the servo control logic unit 230 can also provide control signals (not shown) for selecting the switching configuration of switches 218 and 220 and switching between data read / write mode and self-servo write mode.

[0044] The head assembly 260 may include electronics, motors, and actuators for positioning the heads above the storage medium and generating read and write signals to interact with the storage medium. Each suspension assembly in the suspension assembly 262 may support a corresponding head 268 above the surface of the storage medium and is generally positioned by rotating the head stack relative to the disk stack via a VCM. Each suspension assembly 262 may include multiple two-stage or multi-stage actuators for increasingly finer positioning. For example, each suspension assembly 262 may include a milli-actuator 264 capable of laterally adjusting the position of a portion of the suspension within the actuator range and a micro-actuator 266 capable of laterally adjusting the position of the head 268 near the distal end of the suspension. In some configurations, the milli-actuator may be referred to as a suspension actuator (positioning a portion of the suspension), and the micro-actuator may be referred to as a head actuator (actuating the position of the head at the end of the suspension). As described above, the servo interface circuit 210 may provide control signals to two or more actuators to control one or more target heads. For example, during a data read / write operation, the head 268.1 on the suspension assembly 262.1 can be selected as the target head, and actuator control signals can be sent to the milli-actuator 264.1 and the micro-actuator 266.1; alternatively, the head 268.2 on the suspension assembly 262.2 can be selected as the target head, and actuator control signals can be sent to the milli-actuator 264.2 and the micro-actuator 266.2. During self-servo write mode, heads 268.1 and 268.2 can be selected for parallel self-servo write, and actuator control signals can be sent in parallel to micro-actuators 266.1 and 266.2.

[0045] The preamplifier circuit 270 controls and amplifies the read and write signals between the channel 280 and the head 268. In some configurations, each head group has a corresponding preamplifier circuit 270, such as preamplifier circuit 270.1 for the upper group and preamplifier circuit 270.2 for the lower group. Each preamplifier circuit 270 can be configured to provide write and read signals to selected heads in its head group and connect read and write paths to corresponding interfaces of the channels. In the illustrated configuration, head 268 is a TDMR head comprising two read elements and one write element. The preamplifier circuit 270 and channel 280 are configured with corresponding read and write channels. For example, preamplifier circuit 270.1 includes two read channels 274 and 276 and a write channel 278 for connection to a corresponding interface 272 of channel 280 via flexible circuitry 240. Preamplifier circuit 270.2 also includes selective electrical connections to read channels 274 and 276 and write channel 278. Preamplifier circuit 270 can be configured to receive control signals from channel 280 and / or an associated controller to select which heads and corresponding connections to the read and write channels are active. During data read / write mode, only one preamplifier circuit 270 and the selected head 268 can be active to provide two read signals from the read elements on that head. During parallel self-servo write mode, each preamplifier can select a head and provide only one read signal (selected between two read elements on each head), such that the two read channels 274 and 276 receive a single read signal from each head, and channel 280 can decouple the read signals to calculate the individual PES values ​​of the two heads in parallel.

[0046] In some configurations, additional controller logic can be used to select between a data read / write mode and a self-servo write mode for the preamplifier 270. For example, mode selection logic 282 can communicate with channel 280 or an associated controller to receive a head selection control signal 284 and send a corresponding preamplifier control signal 286 to the preamplifier circuit 270. The read / write control signal can be configured to selectively send the preamplifier control signal 286 to only one preamplifier circuit at a time. Mode selection logic 282 can provide a second control signal and a corresponding switch to send head and element selection control information in parallel to both preamplifier circuits 270 via the preamplifier control signal 286.

[0047] exist Figure 2C and Figure 2D Another example configuration of the servo interface circuit 291 for the control circuit 200 is shown in the figure. Figure 2CConfiguration 202 for self-servo write operation mode is shown, and Figure 2D Configuration 204 for data read / write operation modes is shown. The VCM DAC 212 and microactuator DAC 216 can be essentially as described above regarding... Figure 2A and Figure 2B The operation is performed as described.

[0048] As shown in configuration 202, the milli-actuator DAC 214 can also perform essentially the same during self-servo writing. Figure 2B The operation is performed and connected at 220.1 to a dual-phase driver 222 to generate actuator control signals 226.3 and 226.4 for the micro-actuator on the suspension of the second head. A third actuator DAC 292 (referred to as S-DAC 292) is configured to generate control signals for the micro-actuator during parallel self-servo writing. S-DAC 292 can generate control signals from a servo controller (such as...) Figure 2B The servo controller 230 receives a third digital actuator control signal 293 and provides control signals to control the milliactors via 226.7 and 226.8. Note that these actuator control signals may supplement one or more control signals for voice-controlled motors used to position the head stack. The servo interface circuit 291 may include a digital signal processor (DSP) 295 and a demultiplexer 296. These components may be disabled or bypassed during parallel self-servo writing. For example, the demultiplexer 296 may include or be connected to a switch 297 configured to disconnect the demultiplexer 296 from the outer channel 294.1 and the inner channel 294.2 during self-servo writing operations. Similarly, the DSP 295 may be disabled simultaneously. Without the operation of the demultiplexer 296, the S-DAC 292 may control the milliactors for the suspensions of the two head groups and the heads supporting the target write pair. In some configurations, the milliactors driving the head pair for parallel servo writing are connected to move in opposite directions. Therefore, the micro-actuator control signal 226 will drive the read / write head to move in the opposite direction, thereby allowing coupled position control within the limits of the micro-actuator travel. Configuration 202 may include additional pins for connection to electrically adjacent components. In some configurations, switches 220 and 297 may toggle between modes only when both the micro-actuator and the micro-actuator are disabled, such as when the read / write head is parked between operations.

[0049] As shown in configuration 204, the DSP 295 and demultiplexer 296 can be activated during data read / write operations. For example, switch 297 can connect demultiplexer 296 to inner channel 294.2 and disconnect S-DAC 292 from inner channel 294.2. DSP 295 can modify digital control signal 234 to drive a second branch of actuator control signals provided by S-DAC 292, thereby facilitating the switching process of the milli-actuator to outer channel 294.1. By generating milli-actuator control signal 226.7 for the outer head and milli-actuator control signal 226.8 for the remaining heads, the control signals generated by milli-actuator DAC 214 and S-DAC 292 can each contribute to the control of the milli-actuator for the target head during read / write operations.

[0050] Figure 3A A portion of an example control circuit 300 and a storage medium 360 for a data storage device (such as an HDD) are shown. In the example shown, the control circuit 300 may include one or more hardware controllers. Controller 302 may include a storage device controller configured to receive host storage commands and process writing, reading, and managing non-volatile storage media (such as storage medium 360) stored in a disk drive. Figure 1A , Figure 1B and / or Figure 1C The controller 302 is responsible for storing data on a magnetic media disk. In some embodiments, the controller 302 may correspond to a separate host interface read / write path to a subset of the disk surface in a data storage device having multiple controllers. In some embodiments, the controller 302 may be configured to manage servo, read / write, and self-servo write operations of one or more actuators, heads, and corresponding writer and reader elements.

[0051] Controller 302 may include processor 304, memory 306, host interface 308, and access to buffer memory 310. Controller 302 may also include read / write channel 320 and servo controller 342, which includes servo processor 344 and servo logic unit 346. In some embodiments, one or more of host interface 308, read / write channel 320, and servo controller 342 may be embodied in a separate package, such as an application-specific integrated circuit (ASIC), system-on-a-chip (SoC), or other dedicated circuitry that interfaces with processor 304 and memory 306 to perform their respective functions. Controller 302 may include physical and electrical interfaces for connection to buffer memory 310, power supply (not shown), preamplifier 322, servo interface controller 348, other controllers, and / or other circuitry. In some embodiments, components of controller 302 may be interconnected via a bus including one or more conductors that allow communication between components. For example, processor 304, memory 306, host interface 308, read / write channel 320 and / or servo controller 342 may be components attached to printed circuit board assembly (PCBA) 350, which provides one or more interconnect conductors between components.

[0052] Processor 304 may include any type of conventional processor or microprocessor that interprets and executes instructions. Processor 304 may include multiple hardware processors configured to operate independently or in combination (such as multiple processor cores performing thread operations) to execute one or more instruction sets. Memory 306 may include random access memory (RAM) or another type of dynamic storage device storing information and instructions executed by processor 304, and / or read-only memory (ROM) or another type of static storage device storing static information and instructions for use by processor 304 and / or any suitable storage element, such as a system portion of hard disk media or a solid-state storage element. Memory 306 may be configured to store controller firmware 312 including instructions comprising one or more modules or submodules for operation of a particular data storage device, and processor 304 may execute these instructions, including controlling communication with other components (such as host interface 308, buffer memory 310, read / write channel 320, and servo controller 342).

[0053] The controller firmware 312 may include firmware for operating the control circuitry 300 and the corresponding data storage device in different operating modes. For example, the controller firmware 312 may support a self-servo write mode 314 for writing a servo pattern to the storage medium using the control circuitry 300. In some configurations, the self-servo write mode 314 may be initiated in the data storage device after assembly and may be able to write a desired servo pattern similar to that shown for the storage medium 360. The self-servo write mode 314 may begin from one or more blank storage medium surfaces and / or surfaces previously written with a spiral reference pattern. In some configurations, the self-servo write mode 314 may include a series of iteratively written spiral reference patterns and writes and rewrites of servo sectors (such as servo sector 364) until the desired servo pattern and corresponding quality metrics are achieved. After the desired servo pattern and servo performance level are achieved, the controller firmware 312 may terminate the self-servo write mode 314 and initiate a data read / write mode 316 to write and read data in data tracks defined relative to the servo pattern. For example, data read / write mode 316 can be the remaining configuration and testing of the data storage device by the control circuitry 300, as well as the production configuration during its production life in the field operation.

[0054] Reference storage medium surface 360 ​​illustrates an example servo format generated by self-servo write mode 314 for use during data read / write mode 316. Data track formats can be configured relative to servo formats, but they may not include a one-to-one mapping of data tracks to servo tracks. For example, a servo format may define concentric servo tracks 362 defined by servo sectors 364.1-364.n. Servo sectors 364 and corresponding servo tracks 362 can have different data rates, which are selected to make fuller use of the different track lengths and speeds from the inner diameter (ID) 360.1 to the outer diameter (OD) 360.2 of the rotating disk. Data tracks can be configured to cover servo tracks, with the data track format being concentric tracks where each track forms a different loop with its start and end points on the same circumference; or continuous tracks where the tracks form a continuous spiral with start and end points not on the same circumference, and can support different track densities and track regions relative to the servo format. In some configurations, servo tracks 362 can be organized into regions with different track densities or frequencies. A servo region can refer to a set of concentrically adjacent servo tracks that share a nominal track density and / or frequency similar to each other but different from adjacent regions. Each pair of adjacent servo regions can also define a region boundary 366 between them. When crossing region boundaries, special operations may be required to manage servo writes and / or servo positioning. For example, positioning information, timing, and channel settings may change when crossing region boundaries. Track configuration can be stored in a set of media configuration parameters for servo and data track formats for use by other components of the system, such as read / write channels 320 and the servo controller 342.

[0055] Host interface 308 may include any transceiver-like mechanism that enables the data storage device to communicate with other devices and / or systems, such as the host system for which the storage device provides data storage. Host interface 308 may include a host storage interface conforming to one or more storage interface standards, such as Serial Advanced Technology Attachment (SATA) interface, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), High Speed ​​Peripheral Computer Interface (PCIe), Universal Serial Bus (USB), etc., for connecting host interface 308 to a peripheral interface or network port.

[0056] Buffer memory 310 may include RAM, flash memory, or another type of dynamic storage device for storing host data and other information transferred between the storage medium of the storage device and the host (via host interface 308). In some embodiments, buffer memory 310 is a storage device separate from memory 306 and the disk surface or other non-volatile memory of the data storage device.

[0057] The read / write channel 320 may include one or more dedicated circuits configured to process binary data to be written to the disk surface using analog write signals and process analog read signals from the disk surface back into binary data. For example, the read / write channel 320 may include a write path consisting of various data scramblers, travel-limiting (RLL) encoders, iterative error-correcting (ECC) encoders, pre-compensation circuitry, and other data or signal processing components. The read / write channel 320 may include a read path consisting of various amplifiers, filters, equalizers, analog-to-digital converters (ADCs), soft information detectors, iterative ECC decoders, and other data or signal processing components. Write channel components may include write channel circuitry, and read channel components may include read channel circuitry, but these circuits may share some components. The read / write channel 320 may provide analog write signals to and receive analog read signals from a preamplifier 322, which controls and amplifies signals traveling to and from the read / write head. During data read / write operation mode 316, binary data for recording to the storage medium can be received from the controller firmware 312 by the read / write channel 320, and decoded data from the read / write channel 320 can be passed to the controller firmware 312 and / or routed to the buffer memory 310 for communication with the host. The read / write channel 320 can also separate servo read signals from data read signals to support the servo controller 342.

[0058] In some configurations, the read / write channel 320 may include an analog front-end 324 configured to receive an analog read signal from the preamplifier 322 and convert it into a digital read signal for processing by other components of the read / write channel 320. For example, the analog front-end 324 may include an analog-to-digital converter (ADC), timing circuitry, and one or more filters, equalizers, and / or other signal conditioning components for generating digital read data. In some configurations, the analog front-end 324 and / or other components of the read / write channel 320 may support the operation of the servo controller 342. For example, the read signal received by the preamplifier 322 and the analog front-end 324 may provide a servo read signal based on the read head response generated when the head passes through the servo sector 364 during self-servo write, track seek, track follow, and other servo operations. In some configurations, the read / write channel 320 and the analog front-end 324 may be configured for TDMR read / write operations and interface with the TDMR head via the preamplifier 322. For example, each TDMR head may include a single writer element and two reader elements, and during TDMR read / write operations, the read / write channel 320 may receive two read signals from the head in parallel to read servo and user data. The analog front-end 324 may be configured with a TDMR interface 324.1, which includes two read channel inputs and one write channel output to receive data and send it to the selected head. In self-servo write mode, the two read channels may be decoupled to generate separate read signals from the two heads in parallel, and separate servo read signals and corresponding position error signals are provided in the servo controller 342.

[0059] In some configurations, the read / write channel 320, servo controller 342, and / or controller 302 may include self-servo write functions for operation during self-servo write mode 314. These functions may be configured in firmware running on controller 302 and / or its sub-components. For example, reference spiral detector 326 may include logic components for generating position information based on one or more spiral reference patterns previously written to the surface of the storage medium. The magnetic transitions and information contained in the spiral reference pattern may differ from the production servo pattern of the write servo sector 364 or the user data pattern from the data track, and different position information and associated position error signals may be used. Reference spiral detector 326 may be configured with logic components for processing read signals received from the target head to generate position information and / or PES.

[0060] SSW pattern generator 328 can generate write signals to the target head for writing production servo sectors and / or improved spiral reference patterns. For example, during self-servo write mode, read / write channel 320 can write servo sectors to the storage medium surface in parallel using the write elements of two heads. The servo pattern can be defined for the data storage device in firmware 312, including frequency, servo track identifier, pulse pattern, and other data patterns, and SSW pattern generator 328 can generate corresponding write signals via preamplifier 322 and target heads with position and timing based on SSW servo feedback. During parallel self-servo write, read / write channel 320 and / or servo controller 342 can determine the head position relative to the previously written self-servo write reference spiral, and can use the active head and the corresponding storage medium surface to write the next track of the servo pattern for the product, provided that the head position is calculated to be within the acceptable error tolerance of the reference spiral. In some configurations, the SSW pattern generator 328 can support the generation and writing of interleaved servo patterns, where servo wedge regions written to a pair of surfaces in parallel writing are offset from each other, such as offsetting the wedge regions to half of the wedge region timing. Interleaved servo patterns can support independent phase control between SSW write pairs, as described below. Figure 3B Further description.

[0061] The region trimming logic unit 332 may include specific functions for addressing region boundaries 366 and addressing overlay issues that may arise from writing on previous servo patterns during self-servo writes. For example, rework of a production servo pattern may result in residual patterns from previous iterations, where the new pattern cannot completely cover the old pattern, especially due to varying thermal characteristics and different thermal compensation values, making precise alignment difficult. Subsequent servo regions may be slightly offset towards the ID and / or OD directions from their target location. Therefore, a second parallel fill on the same surface, outside the range of the new pattern, may result in residual servo tracks from previous runs not being covered. These residual tracks will appear at region boundaries or at the ID and OD edges of each servo region. Such duplicate tracks can confuse the servo controller during read / write modes. The region trimming logic unit 332 may include logic for writing an erase band at the ID and OD edges of servo sector writes to ensure no residual patterns remain. The width of the erase band may be based on the maximum inter-run thermal drift to ensure that even if the thermal state changes worse between self-servo writes, no residual servo data is resulted, and unnecessary servo patterns are trimmed.

[0062] The preamplifier control logic unit 334 may include logic for selecting a target head via preamplifier 322. For example, during read / write operation mode 316, a control signal may be sent to a preamplifier that includes a head group containing the target head, and this control signal indicates the target head that will receive and generate read / write signals for read / write operations. For example, preamplifier control logic unit 334 may generate one or more serial enable control signals to activate one or both preamplifiers. During self-servo write mode 314 using parallel servo write, preamplifier control logic unit 334 may be configured to send SSW head selection signals 336 in parallel to two preamplifiers. For example, the read / write selection control signal may be supplemented with a split signal and selection logic to direct the head selection control signal to both preamplifiers.

[0063] The servo controller 342 may include one or more dedicated circuits configured to process servo data (such as position error signals) from the disk surface and provide control signals to position the actuators in a closed-loop control system. The servo controller 342 may also receive commands from the processor 304 for positioning operations, such as seek, track following, load, unload, sweep, idle, and other actuator positioning operations. The servo controller 342 may also implement a servo error recovery process to recover from servo errors. The servo controller 342 may also operate during a self-servo write mode 314 to provide position control relative to a previously written spiral reference pattern for writing servo sectors 364. In some embodiments, the servo controller 342 may include a servo processor 344 and a servo logic unit 346 (stored in servo memory). For example, the servo processor 344 may be dedicated processor circuitry, and the servo logic unit 346 may be firmware stored in RAM associated with the dedicated processor to provide dedicated computing resources for managing servo functions. The servo controller 342 can receive servo read signals from the disk surface using preamplifier 322, and provide them to the servo controller 342 via channel 320. The servo controller 342 can provide servo control signals to the servo interface controller 348 to provide control signals to multiple motors and / or actuators. For example, the servo controller 342 can provide control signals to the VCM and at least two actuators, as described above with respect to Figure 2.

[0064] In some configurations, servo logic unit 346 may include logic components for operating differently between self-servo write mode 314 and read / write operation mode 316. For example, during self-servo write mode 314, servo logic unit 346 may implement SSW VCM logic unit 346.1, SSW head 1 logic unit 346.2, and SSW head 2 logic unit 346.3. Each head may be configured to track a spiral reference pattern on its corresponding disk surface to obtain a track per inch (TPI) reference; note that different heads / disks can be configured for different target TPI values. SSW VCM logic unit 346.1 may include logic components for determining VCM position adjustment based on two PES received from different heads. For example, VCM logic unit 346.1 may use one of the two heads as the master head and provide coarse positioning for tracking on the master head. In another example, VCM logic unit 346.1 may use the average of the PES from the two heads. The SSW head 1 logic unit 346.2 and SSW head 2 logic unit 346.3 can provide DC drift compensation using milli-actuator and micro-actuator capabilities and corresponding DC adjustment values ​​up to the travel distance of each milli-actuator and micro-actuator. The SSW head 1 logic unit 346.2 and SSW head 2 logic unit 346.3 can include logic for using PES from the respective heads and adjustments made by the VCM logic unit 346.1 to determine the position adjustment for their respective actuators. For example, the micro-actuator of each head 346.5 can receive a position compensation signal based on the expected correction offset of the head's PES to the VCM position. In some configurations, a master or pilot head can provide DC and AC position control, and another head can follow using AC position control. In some configurations, the SSW head 1 logic unit 346.2 and SSW head 2 logic unit 346.3 can also include logic for managing the relationship between their respective positions. For example, if the travel distance limit of one actuator is reached, the pilot head can pause writing for one revolution to allow the hysteresis head to catch up and return to its actuator's range. In some configurations, DC can be rejected on both heads simultaneously. For example, N% of the track DC PES of one head can be subtracted from the PES of the other head to keep the DC PES of the two heads equal and opposite. In other examples, the 346.6 milli-actuators of each head can receive a low-frequency (including DC) position compensation signal to remove the PES offset of both heads based on half of the expected correction. The heads on both sets move half of the expected amount in opposite directions, resulting in a combined offset removal amount.

[0065] Thermal drift logic unit 346.7 may include compensation logic for adjusting the positioning loop during self-servo writes to compensate for relative positional changes between parallel heads caused by thermal variations during self-servo write operations. When servo patterns are filled in parallel on two disk surfaces, the two heads and / or reference helices may slowly drift relative to each other due to thermal expansion of the head stack and / or disk stack and motor. Thermal drift logic unit 346.7 can compensate for the difference in head position from a nominal (initial or cold) value to a compensation value that increases as the device heats up by injecting a compensation value into the actuator's position control. If the head drifts too far, milli-actuators and micro-actuators may not be able to compensate for the head position difference due to the limited actuator travel distance. In some configurations, thermal drift logic unit 346.7 may ignore a portion of the PES and gradually change the ignored amount (compensation value) during SSW operations. To limit the effect on track squeezing, the compensation value may change slowly, and at each radial position, the compensation value may be a direct current (DC) or a constant value referred to as PESDC discharge. During parallel filling, the radial position of any given servo track can depend on the thermal state and thermal history of the driver, as determined by the PES thermal compensation value.

[0066] Figure 3B Additional features of controller 302 are shown, relating to parallel writing of self-servo write interleaved servo patterns with independent phase control and wedge-region repetitive yaw (WRRO) correction based on the interleaved servo patterns. For example, controller 302 may include additional logic in read / write channel 320 for independent phase control at servo interleaved offsets using SSW pattern generator 328. Servo logic unit 346 may support additional features for WRRO correction learning, and firmware 312 may include features for writing (and subsequently testing) media test patterns between servo wedges.

[0067] As described above, the read / write channel 320 can be configured with multiple read channels 370 to support TDMR. Each read channel 370.1 and 370.2 may include an independent analog front-end that provides a corresponding digital read signal to the demodulator 372. Demodulators 372.1 and 372.2 may include logic components for detecting timestamps from a servo reference or servo format on the surface of the target storage medium. For example, demodulator 372 may detect timestamp values ​​from the read data based on adjacent servo address tag pairs (SAMs) along the servo or reference track, such as SAM2SAM timestamps. Demodulator 372 may provide timestamps to timing loops 374 for each read channel 370. Each timing loop 374.1 and 374.2 may include logic components for determining how the timestamp values ​​from demodulator 372 differ from the target frequency of the read channel 370. For example, each timing loop 374 may be implemented in firmware that determines a common portion of the SAM2SAM timing and the current frequency difference (δ) from that common portion. Frequency offset calculator 376 can use these timing values ​​to determine a frequency offset value used to control the frequency of the next servo wedge to be written. For example, each frequency offset calculator 376.1 and 376.2 may include logic components for determining an offset value using the frequency difference from the timing values, which is used to adjust the phase of the next segment of the servo pattern to be written, and these determinations are performed individually for each of the two heads. In some configurations, the offset value generated by frequency offset calculator 376 can be set in a frequency offset register, which the corresponding write channel uses to write the servo pattern segment. Although read channels 370.1 and 370.2 can operate in parallel, they can be configured to operate with servo interleaving offset 378 between them. For example, read channel 370.1 can use a servo pattern to determine the SSW phase control of a head / disk surface that is offset from the head / disk servo pattern determined by read channel 370.2 by half the wedge-to-wedge timing. The servo pattern on one disk surface will be offset or shifted relative to the servo pattern being written to the other disk in parallel.

[0068] Box 380 further describes the flow of parallel phase control for the interleaved servo pattern. Read signals 382.1 and 382.2 are received from the head pair for the parallel SSW via two preamplifiers through corresponding read channels 370.1 and 370.2. Demodulators 372.1 and 372.2 determine timestamps 384.1 and 384.2 based on their respective read signals 382.1 and 382.2, and pass the timestamps 384.1 and 384.2 to timing loops 374.1 and 374.2. Timing loops 374.1 and 374.2 generate timing values ​​386.1 and 386.2 based on the timestamps 384.1 and 384.2 read from their respective disk surfaces, and provide the timing values ​​386.1 and 386.2 to frequency offset calculators 376.1 and 376.2. Frequency offset calculators 376.1 and 376.2 can determine offset values ​​388.1 and 388.2 using the timing difference from timing values ​​386.1 and 386.2. Offset values ​​388.1 and 388.2 can update the phase control value in the frequency offset register, which is used to determine the phase of the next servo segment to be written to the corresponding disk surface. Although this read signal processing occurs in parallel for two different read channels, their operation is offset due to servo interleaving offset 378, which causes the servo wedges on one disk surface to be offset and misaligned with the servo wedges on the other disk. The servo wedges at corresponding radial positions and the parallel write servo track groups on the two surfaces can be aligned with the disk area between the servo wedges on the other disk surface. Each servo wedge on one surface can be aligned between the corresponding positions of two adjacent servo wedges on the other surface.

[0069] In some configurations, the same SSW pattern generator 328 can be used to generate servo pattern segments written by two heads. For example, the SSW pattern generator 328 can generate different servo pattern segments for parallel write servo patterns on two disks, and generate them sequentially and alternately between the two heads / surfaces. The pulse pattern writer 328.1 can generate a pulse pattern for each servo segment, and switches between generating pulse patterns written by one head and then by the other head due to the interleaving offset between the two heads. The pulse pattern writer 328.1 can allow the respective heads and write channels to write different pulse patterns to different disk surfaces with independently controlled phases during parallel SSW operations.

[0070] Servo logic unit 346 may include logic for learning wedge repeatability yaw variations using position error signals (PES) and calculating correction values ​​for each servo wedge and track. For example, after writing servo tracks via a self-servo write operation, a wedge repeatability yaw learning operation can be used to calculate WRRO correction values ​​for each servo wedge and track on both parallel surfaces. More specifically, due to the interleaved servo pattern, servo logic unit 346 can switch between servo data read from two heads and process PES data from each head to calculate their respective WRRO correction values ​​during the same revolution of the disk stack (and therefore on both storage media surfaces). Parallel TDMR servo reads can learn WRRO correction values ​​in parallel, and thus reduce test time during the manufacture and testing of TDMR data storage devices. The circuit configuration for implementing parallel SSW described herein also allows parallel processing of servo data from the interleaved servo pattern without adding additional pins and lines to channels or flexible circuitry or additional analog-to-digital converters or repetitive servo signal processing hardware. In some configurations, the servo processor 344 and read / write channel 320 can support a servo sampling rate of 390. The servo sampling rate 390 can be configured to be a multiple of the normal sampling rate for servo read operations, such as double the sampling rate of the servo read channel. Furthermore, the servo processor 344 and the firmware running on it may require sufficient processing speed to support the parallel computation of the double sampling rate and WRRO correction values. For example, path length and microprocessor interrupt service routine (ISR) time must be able to handle the required computation.

[0071] Servo logic unit 346 can be configured to receive PES (Printer Equivalent Sequences) of the two TDMR heads from the corresponding servo read channels, where each PES represents the error or difference between the actual position of the head and the target position relative to the target servo track. PES Repeatability Oscillation (RRO) calculator 392 can calculate the repeatability scillation or pulse correction value for each sequential servo wedge region along the servo track based on the PES. RRO can represent the incorrect radial position of the servo pulse in each servo track, and more specifically, the variation in the seam position based on the phase-based reverse polarity of the servo pulse. These write errors (generated during SSW operation and also due to the finite and uncertain / noise quantity of magnetic particles in each servo bit, as the state of the bit at the edge may be random) can be mapped and used to generate RRO correction values, which can be applied by servo controller 342 during future servo positioning operations (including production data storage (read / write) operations). PES RRO calculator 392 can be configured to determine RRO correction values ​​sequentially and alternately between read signals from the two heads and their corresponding storage medium surfaces and the servo pattern. In some configurations, the wedge-shaped RRO logic unit 394 may include logic for calculating the RRO correction value at the center of the write or read track (using the PES RRO calculator 392). For example, the RRO logic unit 394 could determine the RRO correction value for each head using a single rotation during a single rotation, but this could be significantly off-center from the track. Interleaved servo patterns allow the TDMR read channels (comprising two independent read channels) to time-multiplex and decode the PES from both surfaces and heads in parallel.

[0072] The continuous WRRO logic unit 396 can improve the WRRO correction value by using multiple values ​​per servo track and, in some configurations, interpolating between these values ​​to provide a continuous range of correction values ​​for positions deviating from the track. Dual-surface parallel learning can provide efficiency for parallel learning of WRRO on two surfaces (and corresponding heads), and using the continuous WRRO logic unit 396 can eliminate concerns about data track alignment between the two surfaces or the effects of temperature drift beyond the microactuator's travel range. For example, the continuous WRRO logic unit 396 can learn WRRO correction values ​​at four equal distances per servo track. In some configurations, this learning can be performed using servo track following (based on alignment with the NQ pulses in the servo pulse pattern) or by enabling circular track following. The continuous WRRO logic unit 396 can be configured for multiple servo track offsets 396.1 (such as two or more offset positions), which determine the number of read operations and the RRO correction value determined for each servo track. In some configurations, four offset positions based on a quarter-track offset can provide a series of RRO correction values ​​across the servo track width. In some configurations, the sequential RRO logic unit 396 can measure PES RRO based on enabling circular tracks at other offset values, including non-integer offset positions, such as 3.5 or 4.5 offset positions per servo track. More offset positions improve the accuracy of the WRRO correction values, but should be balanced against WRRO learning time and storage overhead to store a larger number of correction values ​​per servo track.

[0073] In some configurations, the continuous WRRO logic unit 396 may include a sample interpolator 396.2 configured to insert one or more values ​​between each offset WRRO correction value. While the inserted values ​​may not be as accurate as the sampled values, they can be more accurate than corrections based on the most recent WRRO correction value. For example, the inserted values ​​can be determined based on averaging adjacent pairs of sampled offset WRRO correction values ​​and / or linearly mapping multiple interpolated values ​​incrementally (as a function of track distance) along a line connecting two adjacent offset values. In some configurations, the interpolated values ​​can be calculated during the learning process within a processing window between the calculations of the PES RRO correction values, and the interpolated values ​​are stored as additional WRRO values ​​for the corresponding servo wedge region and track segment. In some configurations, the interpolated values ​​may not need to be stored during WRRO learning and can be generated and stored later during the testing process, or dynamically generated during runtime, to save WRRO storage overhead, assuming the servo processor 344 has sufficient processing speed.

[0074] In some configurations, the continuous WRRO logic unit 396 may include a spiral learning logic unit 396.3 to use a spiral trajectory to move the WRRO learning operation from one loop to the next without seeking and positioning between tracks. For example, the spiral learning logic unit may be configured with a spiral trajectory that moves the head by a quarter track offset per loop (assuming an offset of 4). Continuous track following on the spiral trajectory eliminates seek and positioning time between tracks, and because learning is independent of the data track pattern, the spiral learning logic unit 396.2 can be used regardless of whether data is written on circular or spiral tracks. The movement per loop along the spiral trajectory can be determined by dividing the servo track width by the number of offset positions (not necessarily an integer).

[0075] In some configurations, the sequential WRRO logic unit 396 may include an initial value logic unit 396.4, which is configured to use WRRO information from previous turns of the servo segment corresponding to the servo wedge and track. For example, using four servo track offsets, the WRRO error or correction value from the previous turns can be used to set the initial WRRO learning value, such as the turn at WRRO offset 1 / 4 providing an initial value for learning the WRRO correction value at WRRO offset 2 / 4. Based on the offset (N) of each servo track i, the sequential WRRO turns (per rotation) can be denoted as WRRO_i_1 / N, WRRO_i_2 / N, WRRO_i_3 / N to WRRO_i_N / N. The initial WRRO value of the current track i (for the wedge segment) can be WRRO_i_1 / N_init, WRRO_i_2 / N_init, WRRO_i_3 / N_init, WRRO_i_4 / N_init. Generates by learning (1, 2... N) using multiple sequential WRRO track offsets:

[0076] WRRO_i_3 / N=α1*WRRO_i_1 / N+α2*WRRO_i_2 / N

[0077] WRRO_i_4 / N=α1*WRRO_i_2 / N+α2*WRRO_i_3 / N

[0078] …

[0079] WRRO_i+1_2 / N=α1*WRRO_i_N / N+α2*WRRO_i+1_1 / N (next track)

[0080] In some configurations, the least-squares solutions for α1 and α2 can be obtained from the above equations. After this training or learning step, α1 and α2 can be used to determine the initial WRRO correction value using adjacent (previous) WRRO correction values. For example, for trajectory j offset 3 / N, WRRO_j_3 / N_init = α1*WRRO_j_1 / N + α2*WRRO_j_2 / N, and then WRRO_j_3 / N is learned using the regular WRRO function processing based on PES RRO.

[0081] In some configurations, the servo logic unit 346 may include or access a correction data repository 396.5, configured to store WRRO correction values ​​determined during WRRO learning operations. For example, the correction data repository 396.5 may include one or more data structures and / or parameters and functions stored in non-volatile memory accessible to the servo processor 344 and retrieved during runtime servo operations to provide WRRO correction values ​​during track following operations. In some configurations, the correction data repository 396.5 may include a set of WRRO correction values ​​mapped to servo track and wedge addresses used to identify each WRRO correction value. The correction data repository 396.5 may include multiple values ​​corresponding to servo track offsets 396.1 for each servo track and wedge. In some configurations, the correction data repository 396.5 may include one or more interpolation values ​​(generated by a sample interpolator 396.2) between WRRO correction values, determined for each read offset in a set of correction values ​​stored for each servo track and wedge.

[0082] In some configurations, the WRRO learning operation can be combined with the writing of media test patterns to further improve the efficient use of testing time during the storage device manufacturing process. For example, the media test pattern can be written to the data area between servo wedges of the storage medium with the same rotations used to read servo segments for WRRO learning. Firmware 312 may include media test pattern logic 398 configured to write predetermined test patterns to the data area of ​​the storage medium to support additional media testing, characterization, and / or mapping for determining defects in the data track format. For example, media test pattern logic 398 may be configured to write one or more tone patterns to the area between servo wedges. Media test pattern logic 398 may include logic for writing tone scan patterns to the storage medium and performing tone scan read operations after writing the tone scan patterns. In some configurations, the tone scan pattern can be written with a different (fewer) number of rotations than used for WRRO learning. For example, for a WRRO offset of 4 or greater, the tone pattern can be written with 1 or 2 rotations per servo track instead of 4 or more rotations per servo track. In the example of four WRRO learning offsets and two test pattern write cycles per servo track, each servo track can use four rotations, with a WRRO learning read operation performed in each rotation and a tone scan pattern write performed every other rotation. By alternating between each cycle of test pattern writes on one surface and another of the interleaved servo surfaces, media test patterns can be written to two surfaces in half-servo track increments over four cycles for WRRO learning. In the case of writing a media test pattern once per servo track, media test pattern writes can alternate between cycles in which only WRRO read operations occur and cycles in which test pattern writes are performed on one or another of the interleaved storage media surfaces. The media test pattern logic unit 398 can include alternating multiple tone scan patterns, such as dual-frequency media test patterns. For example, the media test pattern logic unit 398 can write a first tone scan pattern on one servo track, write a second tone scan pattern on the next servo track, and alternate between them across servo tracks. (The following is in conjunction with...) Figures 7A to 7D A sample configuration combining WRRO learning operations with media test pattern writing is further described.

[0083] In some configurations, the WRRO learning track spacing (servo track spacing divided by the amount of WRRO learning offset) can be narrower than the write width of the target head to ensure that the tone scan pattern covers all media areas between the servo wedges. During subsequent tone scan read operations, tone signals can be read in parallel from the staggered surfaces using a single reader operation similar to that used for SSW operations, although without TDMR servo and TDMR WRRO. To use TDMR servo and TDMRWRRO during tone scan reads, one surface can be read at a time using the full TDMR functionality of the target head and TDMR read channels. In some configurations, tone scan read cycles can also be used for additional WRRO learning operations. For example, WRRO correction values ​​learned during tone scan write operations can be updated based on additional read samples during tone scan read cycles. In configurations where spiral trajectory WRRO learning is used with dual-frequency media test patterns, tone scan reads may also need to follow a spiral trajectory. In some configurations, the media test pattern may include a tone scan pattern written at the same frequency on each cycle / servo track, and phase alignment at each half-track or track spacing. This phase-aligned tone scan pattern allows tone scan reads at any location (whether circular or helical) while providing sufficient phase control during test pattern writing. With phase-aligned tone scan patterns, data patterns can be written in phase alignment, such as when using bit-patterned media recording and corresponding media, head, and channel capabilities.

[0084] Figure 4AA parallel self-servo write process 400 of a data storage device with two heads and corresponding preamplifier circuitry is illustrated. The storage medium stack includes two groups of disks 410 arranged around a spindle 412. The upper group includes disk surfaces 410.1.1-410.1.n, and the lower group includes disk surfaces 410.2.1-410.2.n. Each disk includes two storage medium surfaces 414 for magnetically recording data on opposite (upper and lower) surfaces of the disk. A head 420 is actuated above each surface and suspended by a corresponding suspension 424. Each suspension 424 may include a fixed portion attached to an arm 422 and a flexible portion extending toward the corresponding disk surface. In some configurations, an actuator 426 (such as a piezoelectric milli-actuator) may be positioned at the junction of the fixed portion of the suspension portion and operable for lateral positioning of the suspension 424. In some configurations, a second actuator 428 (such as a piezoelectric microactuator) can be positioned near the head 420 at the distal end of the suspension portion 424 and operable for further lateral positioning. Due to the size of the actuators and their relative distance from the heads, the arm actuator 426 of the suspension portion 424 of the moving arm 422 can have a greater travel distance or range than the head actuator 428 of the adjacent head 420, but the head actuator 428 can have higher precision for finely positioning the read / write element at the desired location on the disk. Furthermore, in SSW mode, only the arm actuator 426 for parallel write head groups can be controlled to move in the opposite direction, allowing it to be used to correct DC and low-frequency offsets between the two heads. On the other hand, the head actuator 428, with a more limited range of motion, is controlled individually by the group, allowing it to correct not only low-frequency errors including offsets but also high-frequency errors for accurate placement of the servo pattern at the desired location. The heads 420 and corresponding suspensions 424 are similarly arranged in groups. The upper group may include heads 420.1-420.n and their corresponding arms 422, and the lower group may include heads 420.n+1-420.n+n. Each group of heads is electrically connected to a corresponding preamplifier circuit, such as preamplifier 432.1 for the upper head group and preamplifier 432.2 for the lower head group. In some configurations, one preamplifier group may have more heads than the other. In such configurations, parallel self-servo writes and other parallel operations can be used across paired subsets of the two groups, and the extra heads / surfaces can be written using a single head / surface self-servo write. For example, if one head group has n heads and another head group has n+x heads, the maximum number of n heads can be self-servo written or WRRO learned in parallel using the methods described herein, and the remaining x heads on the second stack can be written and configured using a single head operation.

[0085] During parallel self-servo writing, the control circuitry uses a reference spiral 416 from the surface of the storage medium to provide positional information for writing servo sectors or servo wedges. The reference spiral 416 may be a previously written spiral reference pattern and is present on each disk surface at the start of servo sector writing. Heads 420.1-420.n can be used to write servo sectors to the upper group of disks in parallel with heads 420.n+1-420.n+n writing servo sectors to the lower group. Due to the disk stacking and head stacking mechanism, it is preferable to use head pairs that minimize the vertical distance between heads for parallel writing. In some configurations, write pairs 440.1-440.n are selected to pair the write with heads / surfaces in the same sequential position within each head group. For example, head 420.1 writing surface 414.1 will be paired with head 420.n+1 writing surfaces 414.n-+-1 as write pair 440.1. Each surface can be written sequentially downwards to head 420.n for writing to surface 414.n and head 420.n+n for writing to surface 414.n+n, respectively. In some configurations, write pairs 440 can be selected in a different order than top to bottom. Other pairings are also possible, such as nearest to farthest pair, or pairing top surface heads from one set with bottom surface heads from another set. When each pair is selected, servo tracks can be written in two rounds (rotations or revolutions of disk 410) as servo write tracks 442.j and 442.j+1, with servo wedges 444.j.1 to 444.jm written sequentially to both disk surfaces simultaneously. The heads move half track offset 448 between rounds, and the second round of servo write track 442.j+1 can write the other half of the servo sector into the same sequence of servo wedges 444.j+1.1-444.j+1.m. In the example shown, each servo track 446 is written along the servo wedge sequence in two rounds to complete a full cycle, where m is the number of servo wedges in the servo format. In some configurations, when preamplifiers are wired to their respective head groups, adjacent heads can be wired to alternative preamplifiers to minimize read / write crosstalk, thereby bringing parallel-filled write pairs closer together with less cross-head movement.

[0086] Figure 4B A schematic diagram of a cross-head / medium pair parallel write interleaved servo pattern is shown. For example, servo track 446 can be written using a selected head pair, such as heads 420.1 and 420.n+1 from two head groups, as shown. Figure 4AAs shown, the two head groups have interleaved servo pattern offsets of 460 to support independent phase control between servo patterns written in parallel. During SSW operation, heads 420.1 and 420.n+1 can be selected as target heads for parallel SSW using drive circuitry (including the TDMR channel). Servo track writing 442.j for the first half of the servo segment can be initiated for head 420.1 in parallel (with the same media stack rotation) with servo track writing 452.j for the first half of the servo segment for head 420.n+1. If head 420.1 can write half a servo segment of servo wedge 444.j.1, then during offset 460, head switch 450 can allow head 420.n+1 to write half a servo segment of servo wedge 454.j.1. During the interval of the next offset cycle, another head switch can return write control to head 420.1 to write the first half segment of servo wedge 444.j.2. This pattern can continue for parallel SSWs of the first half segments of servo wedges 454.j.2, 444.j.3, and 454.j.3, and so on, switching between heads 420.1 and 420.n+1 during the offset interval until the last servo wedge of rotation is reached at servo wedges 444.jm and 454.jm.

[0087] Once a rotation is complete, servo control can shift heads 420.1 and 420.n+1 by half track offset 458 to write the latter half of each servo segment of the corresponding servo track using write tracks 442.j+1 and 452.j+1 in the next rotation of the media stack. Head 420.1 can write the latter half of the servo segment at servo wedge 444.j+1.1, and then head switch 450 allows head 420.n+1 to write the latter half of the servo segment at servo wedge 454.j+1.1 during offset 460. In the interval of the next offset cycle, another head switch can return write control to head 420.1 to write the latter half of the segment at servo wedge 444.j+1.2. This pattern can continue to be used for the parallel SSW of the latter half of the servo wedge segments 454.j+1.2, 444.j+1.3, and 454.j+1.3, and so on, switching between heads 420.1 and 420.n+1 during the offset interval, until the last servo wedge segment of the rotation is reached at servo wedge segments 444.j+1.m and 454.j+1.m. Then, the servo track can be completed, and the other half of the track offset can position the head for the next rotation, thus starting the next servo track in the servo area, continuing the corresponding servo wedge segment at the staggered servo pattern offset 460 on the paired disk surface. In another configuration, instead of using a half-track offset 458 between the first half tracks 442.j and 452.j and the second half tracks 442.j+1 and 452.j+1, each servo wedge region on each parallel write surface in the parallel write surface is written with an offset of 0.5 tracks divided by the number of wedge regions per revolution, resulting in a spiral product servo pattern with a slope of one track per revolution. Because the half-track offset 458 is extended to all wedge regions via constant-speed motion rather than through a seek / positioning process, the time cost of writing the servo pattern is lower.

[0088] like Figures 5A to 5D As shown, many example preamplifier configurations and adjacent circuitry can be used for parallel self-servo writing. Figure 5AIn the example configuration 502, preamplifier circuits 510.1 and 510.2 are included. Preamplifier circuit 510.1 is electrically connected to a set of TDMR heads 512.1-512.n. Each TDMR head 512 includes two read elements 514 electrically connected to the input interface of a corresponding sensor amplifier 516. For example, read elements 514.1.1 and 514.1.2 are connected to sensor amplifiers 516.1.1 and 516.1.2, respectively; read elements 514.2.1 and 514.2.2 are connected to sensor amplifiers 516.2.1 and 516.2.2, respectively; and read elements 514.n.1 and 514.n.2 are connected to sensor amplifiers 516.n.1 and 516.n.2, respectively. Preamplifier circuit 510.2 is electrically connected to another set of TDMR heads 512.n+1-512.nn. Reading elements 514.n+1.1 and 514.n+1.2 are connected to sensor amplifiers 516.n+1.1 and 516.nn2, respectively; reading elements 514.n+2.1 and 514.n+2.2 are connected to sensor amplifiers 516.n+2.1 and 516.n+2.2, respectively; and reading elements 514.n+n.1 and 514.n+n.2 are connected to sensor amplifiers 516.n+n.1 and 516.n+n.2, respectively.

[0089] In preamplifier circuits 510.1 and 510.2, sensor amplifiers 516 are connected in pairs to A and B switching circuits 518, which are configured to switch amplified read signals from corresponding readout elements for connection to opposing multiplexers 520. For example, amplified read signals from sensor amplifiers 516.1.1 and 516.1.2 are switched via switching circuit 518.1 to connect the read signal from sensor amplifier 516.1.1 to multiplexer 520.2, and the read signal from sensor amplifier 516.1.2 to multiplexer 520.1. A similar configuration operates sensor amplifiers 516.2.1 and 516.2.2 via switching circuit 518.2 and sensor amplifiers 516.n.1 and 516.n.2 via switching circuit 518.n. The preamplifier circuit 510.2 is configured similarly for sensor amplifiers 516.n+1.1 and 516.n+1.2 via switching circuit 518.n+1, for sensor amplifiers 516.n+2.1 and 516.n+2.2 via switching circuit 518.n+2, and for sensor amplifiers 516.n+n1 and 516.nn2 via switching circuit 518.n+n.

[0090] Multiplexer 520 may be a circuit configured to select from amplified read signals to selectively connect these read signals to read driver 522, which interfaces with read channel 532 of channel 530. In some configurations, multiplexer 520 may select the target head and the corresponding read sensor based on a control signal received at the corresponding control signal input 524. During data read / write operations, a pair of read signals from a pair of read elements in the target head may be selected by multiplexers 520.1 and 520.2 and passed to read drivers 522.1 and 522.2, respectively. During self-servo write operations, only one of multiplexers 520.1 and 520.2 may be enabled, and a single read signal may be selected from the target head to be provided to one of read drivers 522.1 or 522.2. Preamplifier 510.2 can be similarly configured such that preamplifiers 510.1 and 510.2 can be alternately activated as needed for reading from two read elements of the target head in their head group. During a self-servo write operation, only one of multiplexers 520.4 or 520.3 can be enabled, and a single read signal can be selected from the parallel target heads to be provided to one of the read drivers 522.4 or 522.3. The corresponding read driver 522 associated with the active multiplexer can provide an amplified read signal via an interface to read channel input 532 in channel 530. In the example shown, during a self-servo write operation, multiplexer 520.1 provides an amplified read signal from the target head connected to preamplifier 510.1 to read driver 522.1 to provide read signal 540.1 to read channel input 532.1, and multiplexer 520.4 provides an amplified read signal from the target head connected to preamplifier 510.2 to read driver 522.4 to provide parallel read signal 540.2 to read channel input 532.2.

[0091] During a self-servo write operation, read channel 530 can be configured to decouple the received read signals 540.1 and 540.2 and process them separately to determine their respective servo position information and PES. For example, the analog front end of channel 530 may include a separate variable gain amplifier (VGA) configured to receive the pair of read signals through read channel inputs 532.1 and 532.2 and direct them through a separate read processing channel to extract servo information from the respective read signals. In some configurations, read channel 530 may be configured similarly to read / write channel 320 in Figure 3.

[0092] In some configurations, head selection and preamplifier control can be managed by controller 534, such as a hardware controller configured similarly to controller 302 in Figure 3. Controller 534 can generate preamplifier control signals and send them to control signal inputs 524.1 and 524.2 to control preamplifier circuits 510.1 and 510.2, respectively. During read / write operations, controller 534 can send control signals to the active preamplifier connected to the target head for read / write operations, and the absence of a control signal to the other preamplifier when it is active can effectively disable that preamplifier from performing read / write operations. During parallel self-servo write operations, both preamplifiers 510 may need to be active and receive parameters for selecting the target head, read sensor, and read path (multiplexer to read driver to read channel input). For example, controller 534 can be configured to generate a pair of preamplifier control signals to be simultaneously sent to control signal inputs 524.1 and 524.2 to set the corresponding preamplifier parameters, but the preamplifier parameters can be different for each preamplifier. In some configurations, controller 534 may include local logic components for generating parallel control signals during self-servo write operations to control preamplifier circuits 510.1 and 510.2 in parallel.

[0093] Figure 5B An alternative example of configuration 504 using preamplifier circuits 510.1 and 510.2 is shown. The preamplifier circuits 510.1 and 510.2, their corresponding heads 512, and channels 530 are as follows... Figure 5AThe configuration is described above. In this example, preamplifier circuits 510.1 and 510.2 can operate in read / write operation mode. When a target head is selected in the head group including heads 512.1-512.n, multiplexers 520.1 and 520.2 can select an amplified read signal from a pair of read sensors on that head and direct the read signal to read drivers 522.1 and 522.2. TDMR read signals 542.1 and 542.2 can be sent to channel inputs 532.1 and 532.2 and the corresponding coupled TDMR read channels for processing position information (and stored data) from these signals. When a target head is selected in the head group including heads 512.n+1-512.n+n, multiplexers 520.3 and 520.4 can select an amplified read signal from a pair of read sensors on that head and direct the read signal to read drivers 522.3 and 522.4. TDMR read signals 542.3 and 542.4 can be sent to channel inputs 532.1 and 532.2 and the corresponding coupled TDMR read channels for processing position information (and stored data) from these signals.

[0094] In configuration 504, an alternative controller 536 is shown that does not include local generation of parallel preamplifier control signals for control signal inputs 524.1 and 524.2. Controller 536 can be configured similarly to controller 302 in FIG. 3. Controller 536 may include control logic unit 550, which may include firmware instructions for selectively activating control signal generator 552 to generate data read / write operation control signals, which are selectively sent to control signal input 524.1 (when preamplifier 510.1 is active) or control signal input 524.2 (when preamplifier 510.2 is active). Control logic unit 550 may include additional shunt signal generator 554 to generate additional shunt signals to initialize selection logic unit 556, thereby generating parallel preamplifier control signals to control signal inputs 524.1 and 524.2. See next question. Figure 5D Further description of example selection logic component circuit 590 is provided.

[0095] Figure 5CAn alternative example configuration 506 for parallel self-servo writing using non-TDMR heads and preamplifiers is shown. Preamplifier circuits 560.1 and 560.2 are configured with a single sensor amplifier 566 to a single read sensor 564 on each head 562. For example, preamplifier circuit 560.1 supports a head group including heads 562.1-562.n and receives read signals from corresponding read sensors 564.1-564.n via sensor amplifiers 566.1-566.n. Preamplifier circuit 560.2 supports another head group including heads 562.n+1-562.n+n and receives read signals from corresponding read sensors 564.n+1-564.n+n via sensor amplifiers 566.n+n-566.n+n. Preamplifier circuits 560.1 and 560.2 each include a single multiplexer 570 and a read driver 572 for selecting a read signal from a target head and providing that read signal to a read channel input 582 of channel 580. For example, each sensor amplifier 566.1-566.n is connected to multiplexer 570.1 for selective connection to read driver 572.1, and each sensor amplifier 566.n+1-566.n is connected to multiplexer 570.2 for selective connection to read driver 572.2. Preamplifier circuits 560.1 and 560.2 may also include control signal inputs 574.1 and 574.2, respectively, for receiving preamplifier control signals to select the active preamplifier and head for read / write operations, and to activate the preamplifier and select the target head for parallel self-servo writing. During read / write operation mode, read drivers 572.1 and 572.2 can alternately send read signals 544.1 and 544.2 to the corresponding read channel inputs 582.1 and 582.2 for processing via the corresponding read channel. During parallel self-servo write mode, read drivers 572.1 and 572.2 can send read signals 544.1 and 544.2 in parallel to the corresponding read channel inputs 582.1 and 582.2 for processing via the decoupled read channel to extract position information. Additional traces for the parallel read signals can be provided on a flexible circuit (not shown) between read driver 572 and read channel input 582.

[0096] In configuration 506, channel 580 includes separate read channel inputs 582.1 and 582.2, similar to... Figure 5A and Figure 5B The TDMR read channel in the controller 584. Figure 5BThe controller 536 is configured and includes a similar control logic unit 550 that interfaces with selection logic unit 556 for controlling two preamplifier modes via control signal inputs 574.1 and 574.2. We note here that configuration 506 is a non-TDMR version of configuration 504. For simplicity, the non-TDMR version of configuration 502 is omitted here. A controller similar to 534 can be used to change... Figure 5C The controller 584 in the configuration is used to establish a non-TDMR version of configuration 502.

[0097] Figure 5D An example selection logic unit circuit 590 is shown, such as the selection logic unit circuits that can be used in configurations 504 and 506. Example configuration 508 is shown in the context of a configuration similar to configuration 504. Preamplifier circuits 510.1 and 510.2 are controlled via corresponding control signal inputs 524.1 and 524.2. Controller 536 includes a control signal generator 552 and a split signal generator 554. In the illustrated configuration, control signal generator 552 generates read / write operation (single active preamplifier and head) control signals, such as a serial enable control signal, and provides this control signal to selection logic unit 590, while split signal generator 554 can generate a pair of control signals to split the preamplifier control signal and provide the selected control signal in parallel to the corresponding control signal inputs 524.1 and 524.2. For example, a pair of signals generated by the split signal generator 554 may include a head selection signal for the preamplifier circuit 510.2, such as a second serial enable control signal, and a split signal selection signal for directing control signals from control signal 552 to preamplifier circuit 510.1 in parallel. The control signals generated by control signal generator 552 and split signal generator 554 may be received by selection logic unit 590. In some configurations, selection logic unit circuit 590 may include hardware logic added to controller 536, or be provided as part of a separate device or flexible circuitry between controller 536 and preamplifier circuits 510.1 and 510.2.

[0098] The selection logic unit circuit 590 may include a pair of NOT gates 592.1 and 592.2 for control signals from the split signal generator 554. NOT gate 592 can control the selection of the control signals sent to gates 594.1 and 594.2. OR gate 594.1 can evaluate the pair of NOT gate signals from 592.1 and 592.2, and OR gate 594.2 can evaluate the selection signal of the preamplifier circuit 510.2 with the signal from NOT gate 592.2. AND gates 596.1 and 596.2 can determine the control signals selectively sent to control signal inputs 524.1 and 524.2, respectively. AND gates 596.1 and 596.2 can provide a single preamplifier / head selection control signal from the control signal generator 552 during read / write operations, or modified control signals based on gates 594.1 and 594.2, respectively, during parallel self-servo write operations. Other configurations of the selection logic unit circuit 590 are possible. During parallel self-servo writing, read signals from both heads enter each TDMR channel and are processed in parallel to generate off-track position control and downtrack timing control. The write signal timing is time-multiplexed between the two heads; that is, there is a write head switch for writing on the first surface and then writing to the second surface, thereby producing an interleaved write pattern with a half-wedge offset in the downtrack direction.

[0099] Figure 6A An example VCM compensator logic unit 600 is shown, which can determine a total VCM position adjustment 622 based on each head position measurement 626. A reference position 610 can be subtracted from the first head position measurement 626.1 at a summing node 612.1 to form a first head PES 616.1. Similarly, the reference position 610 can be subtracted from the second head position measurement 626.2 at a summing node 612.2 to form a second head PES 616.2. Each head PES 616 can be summed at a summing node 614 and divided by 2 by a gain 618 to obtain an average PES, which can then be processed by the VCM compensator 620 to obtain the total VCM position adjustment 622. The overall VCM position adjustment 622 can be applied to the motor control circuit to simultaneously change the positions of the first and second magnetic heads 626.1 and 626.2 via the VCM and the first arm dynamics system 624.1, and the VCM and the second arm dynamics system 624.2, respectively.

[0100] Figure 6BAnother example compensator logic unit 602 is shown, which can determine a per-head actuator compensation value 632 and a total VCM position adjustment 648 based on a per-head position measurement result 654. A reference position 610 can be subtracted from the first head position measurement result 654.1 at a summing node 612.1 to form a first head PES 616.1. The first head PES 616.1 can be processed by a first actuator compensator 630.1 to produce a first actuator compensation value 632.1. The first actuator compensation value 632.1 can be processed by the first actuator model 636.1 to generate an estimated first actuator position, which can then be subtracted from the first head PES 616.1 at the summation node 638.1 to generate the first head decoupling PES 640.1. Simultaneously, the reference position 610 can be subtracted from the second head position measurement result 654.2 at the summation node 612.2 to form the second head PES 616.2. The second head PES 616.2 can be processed by the second actuator compensator 630.2 to generate the second actuator compensation value 632.2. The second actuator compensation value 632.2 can be processed by the second actuator model 636.2 to generate an estimated second actuator position, which can then be subtracted from the second head PES 616.2 at the summation node 638.2 to generate the second head decoupling PES 640.2. The first head decoupling PES 640.1 and the second head decoupling PES 640.2 can be added at the summation node 642, divided by 2, and passed through the VCM compensator to obtain the total VCM position adjustment 648. The total VCM position adjustment 648 and the first actuator compensation value 632.1 can be applied to the motor control circuit and the first actuator, respectively, to change the first head position 654.1 via the superposition of the VCM and the first arm dynamics system 650.1 and the first actuator dynamics system 634.1. At the same time, the second actuator compensation value 632.2 can be applied to the second actuator to change the position 654.2 of the second head via the superposition of the VCM and the second arm dynamics system 650.2 and the second actuator dynamics system 634.2. Figure 6A and Figure 6B The actuator position control system architecture shown is applicable to the parallel self-servo write described in the previous chapters and the parallel continuous WRRO learning described next.

[0101] Figures 7A to 7B Figure 700 illustrates the parallel continuous WRRO learning operation across head pairs 710.1 and 710.n+1. In the example shown, for the first servo track i ( Figure 7A ), rotate four times at the four learning offsets 720.1-720.4, and for the next servo track i+1 ( Figure 7B The head 720.5-720.8 rotates four times at four learning offsets. The interleaved servo pattern across the head / media pair allows servo wedges to be read alternately based on their relative interleaved servo offsets. Therefore, during rotation 1 of i+1 / 4 720.1, read operation 724.1 can alternate between offset servo wedges of the interleaved servo pattern. For example, head 710.n+1 can read sequential servo wedges 724.1.1, 724.1.3, and 724.1.5 at the first learning offset (i+1 / 4) in the same loop as head 710.1 can read 724.1.2, 724.1.4, and 724.1.6. In some configurations, parallel WRRO learning can be combined with writing a media test pattern in the same set of loops on each servo track. For example, during the first revolution at i+1 / 4720.1, head 710.1 can write a first tone scan pattern across the media surface between servo wedge regions. While head 710.n+1 is reading the offset servo wedge region of its media servo pattern and between servo wedge region read operations of head 710.1, tone scan pattern write operations 722.1.1, 722.1.2, and 722.1.3 can be performed by head 710.1.

[0102] Each sequential loop 720.1-720.8 can shift the head 710.1 and 710.n+1 by a WRRO learning offset, such as a quarter of the servo track width. For example, starting from the first loop at i+1 / 4, the head position can be shifted by a quarter of the servo track to the second loop at i+2 / 4. If a circular track is used, a seek positioning operation can occur between two loops. If a helical track is used, the head position can be gradually shifted in the transverse track direction as the disk rotates, and therefore, during the travel of the sequential servo wedge, the head moves in the downward track direction, causing the head position to shift by the WRRO learning offset when it reaches the corresponding servo wedge on the next loop. In one example where WRRO learns 4 offset positions per track, the head will move at a constant speed of 1 / 4 track per loop as the disk rotates.

[0103] exist Figures 7A to 7BIn the example shown, each servo track may only need to have the media test pattern written once. Therefore, tone scan pattern 1 can be written to the media surface corresponding to head 710.1 during the first round at i+1 / 4720.1, and to the media surface corresponding to head 710.n+1 during the third round at i+3 / 4. The second round at i+2 / 4720.2 and the fourth round at i+4 / 4720.2.4 may not include tone scan pattern writing operations, and only include alternating WRRO learning read operations. For example, the second round at i+2 / 4720.2 can alternate between read operations 724.2.1, 724.2.3, and 724.2.5 of head 710.n+1 and read operations 722.2.2, 724.2.4, and 724.2.6 of head 710.1.

[0104] In some configurations, the medium test pattern can be a dual-frequency test pattern that alternates between tone scan patterns with different phases, such as a first tone scan pattern and a second tone scan pattern with different phase alignment. Figure 7B As shown, from the 5th loop at i+1+1 / 4720.5 to the 8th loop at i+1+4 / 4720.8, a similar WRRO training and tone scan pattern writing method can be used to write different tone scan patterns into alternating tracks.

[0105] Figures 7C to 7D Figure 702 illustrates parallel sequential WRRO learning operations across head pairs 710.1 and 710.n+1, where a medium test pattern is written at half-servo track intervals during the WRRO learning operation. Writing each tone scan pattern in two phase-aligned rounds allows for full pattern writing regardless of the writer width. In the example shown, for the first servo track i ( Figure 7C ), rotate four times at the four learning offsets 730.1-730.4, and for the next servo track i+1 ( Figure 7DThe head rotates four times at four learning offsets 730.5-730.8. During the first rotation at i+1 / 4 730.1, read operation 734.1 can alternate between offset servo wedges of the interleaved servo pattern. For example, head 710.n+1 can read sequential servo wedges 734.1.1, 734.1.3, and 734.1.5 at the first learning offset (i+1 / 4) in the same rotation as head 710.1 can read 734.1.2, 734.1.4, and 734.1.6. During the first rotation at i+1 / 4 730.1, head 710.1 can write a first tone scan pattern across the media surface between the servo wedges. While head 710.n+1 is reading the offset servo wedge region of its media servo pattern and between servo wedge region read operations of head 710.1, tone scan pattern write operations 732.1.1, 732.1.2, and 732.1.3 can be performed by head 710.1 to obtain tone scan pattern 1. During the +2nd revolution at i2 / 4730.2, head 710.n+1 can write the first tone scan pattern across the media surface between servo wedge regions. While head 710.n is reading the offset servo wedge region of its media servo pattern and between servo wedge region read operations of head 710.n+1, tone scan pattern write operations 732.2.1, 732.2.2, and 732.2.3 can be performed by head 710.n+1 to obtain tone scan pattern 1. For the third turn at i+3 / 4730.3 and the fourth turn at i+4 / 4730.4, the tone scan pattern 1 can be repeated, with phase alignment controlled with the previous half track. The head movement per turn can be substantially as for... Figure 7A and Figure 7B The management is described above. In some configurations, the media test pattern can be a dual-frequency test pattern, which alternates between tone scan patterns with different frequencies, such as a first tone scan pattern and a second tone scan pattern with different frequencies. Figure 7D As shown, from the 5th loop at i+1+1 / 4730.5 to the 8th loop at i+1+4 / 4730.8, a similar WRRO training and tone scan pattern writing method can be used to write different tone scan patterns into alternating tracks.

[0106] like Figure 8 As shown, the control circuit 300 can be configured according to the usage of... Figures 2A to 6B The example method for parallel self-servo writing of the various components described herein is to operate according to method 800 illustrated in boxes 810 to 836.

[0107] At frames 810 and 812, a first and a second magnetic head are actuated above the respective surfaces of the storage medium. For example, a controller may be responsible for controlling the movement of two heads selected from different head groups in a data storage device, wherein the first and second heads are suspended on arms above the surface of the storage medium and positioned by a combination of at least one VCM and at least one actuator on the arm supporting each head.

[0108] At blocks 814 and 816, different readout elements are selected for parallel operation. For example, the controller may send control signals to two different preamplifier circuits to identify the first and second target readout elements and the readout sensors to be used on these readout elements. This may include selecting one of two readout elements from each TDMR readout element.

[0109] At blocks 818 and 820, a read signal can be generated from the selected read head and element. For example, a preamplifier can activate a read voltage for the target head and read element, and receive sensor read signals generated by the first target head, the second target head, and the read element.

[0110] At block 822, read signals can be received in parallel via corresponding preamplifier circuitry. For example, the channel associated with the controller may include two read channel inputs connected to the preamplifier circuitry, and read signals from each preamplifier may be received in parallel.

[0111] At blocks 824 and 826, a PES value can be determined for each head based on the received read signal. For example, channel decoupling operations can determine separate first and second PES values ​​for the first and second heads.

[0112] At box 828, a head stack can be positioned for two heads. For example, the controller can determine VCM adjustment based on two PES values ​​to move the head stack, which includes the head group and the first and second target heads.

[0113] At boxes 830 and 832, the position of the two heads relative to the head stack can be controlled. For example, the servo controller can provide head-specific actuator adjustment values ​​to the actuators on the corresponding arms of the first and second heads.

[0114] At boxes 834 and 836, servo tracks can be written in parallel to the surfaces of two storage media. For example, the controller can send servo pattern write signals to both the first and second target heads via their respective preamplifiers in response to the position of the heads relative to the SSW reference screw being within the corresponding error tolerance.

[0115] like Figure 9As shown, the control circuit 300 can operate according to an example method of parallel self-servo writing of interleaved servo patterns with independent phase control, i.e., according to method 900 illustrated in blocks 910 to 956.

[0116] At boxes 910 and 912, a pair of target heads can be identified for parallel self-servo write operations. For example, the controller can select a first target head and a second target head for the SSW from each head group.

[0117] At boxes 914 and 916, a reference pattern can be read from the corresponding storage medium surface of the target head. For example, the controller can use the read element on each head, along with the corresponding preamplifier and read channel, to read a previously written servo reference pattern from the first and second storage medium surfaces corresponding to the target head.

[0118] At 918 and 920, method 900 may include a series of blocks 922 to 930 and blocks 934 to 942 for independently determining the servo pattern phase of an interleaved servo pattern to be written to the corresponding storage medium surface. For example, blocks 922 to 932 may be performed by a TDMR read channel path selected for a first target head to determine the phase of the next servo segment to be written to the first disk surface, and blocks 934 to 944 may be performed by a TDMR read channel path selected for a second target head.

[0119] At boxes 922 and 934, the corresponding read signals can be demodulated. For example, the corresponding read channels can receive and demodulate read signals from the first target head and the second target head.

[0120] At boxes 924 and 936, the timestamp can be determined from the demodulated read signal. For example, the corresponding read channel can determine the SAM2SAM timestamp from the demodulated read signal.

[0121] At boxes 926 and 938, timestamps can be processed using a timing loop. For example, the corresponding read channel can use a firmware timing loop to compare the time between timestamps with the required timing of each read signal in the read signals and the corresponding servo wedge to be written.

[0122] At boxes 928 and 940, timing values ​​can be determined. For example, the corresponding read channel can output timing values ​​corresponding to the target timing and the difference or error value determined from the read signal.

[0123] At boxes 930 and 942, the frequency offset can be calculated or determined. For example, the controller can determine, based on the corresponding read signal and its timing error value, that different frequency offsets can be calculated to correct the phase, thereby writing the next servo segment in each servo pattern.

[0124] At boxes 932 and 944, the frequency offset register can be updated for the corresponding write channel. For example, when writing the next servo segment in the corresponding servo pattern, the controller can update the frequency offset register used to control the timing of the write channel. The frequency offset register of the first target head can be updated first at box 932 to write the corresponding servo segment, and after the head switching at box 956, the frequency offset register of the second target head can be updated at box 944.

[0125] At boxes 946 and 948, servo segment patterns can be generated. For example, the corresponding write channel can use the same servo pattern generator to generate the pulse pattern to be written to its corresponding servo pattern.

[0126] At boxes 950 and 954, a servo segment of the next servo wedge in each servo pattern can be written. For example, at box 950, the first target head can write the next servo segment to the first storage medium surface. At box 956, a head switch can be performed to switch the write head to the second surface. Subsequently, the frequency offset register is updated at box 944, and the servo segment pattern is generated at box 948. Furthermore, to interleave the two servo patterns, the writing of the servo segment by the second target head at box 954 can be delayed by waiting for an offset time at box 952. The servo pattern interleaving offset time, such as half the wedge-to-wedge timing of the servo pattern, can shift the downlink track position of each servo wedge on the second storage medium surface relative to the corresponding servo wedge on the first storage medium surface. After waiting for the offset time at box 952, the segmentation of the servo wedge can be performed on the second surface at box 954. Therefore, when each servo wedge is written in parallel during the same revolution of the disk stack, it can have independently controlled phase and offset positions at corresponding physical locations on the two storage media. As described elsewhere, the corresponding physical locations written by the servo TPI during the same revolution on the two disk surfaces can also differ.

[0127] like Figure 10 As shown, the control circuit 300 can operate according to an example method of wedge repetitive yaw correction training with optional parallel writing of a medium scan pattern, namely, according to method 1000 illustrated in blocks 1010 to 1048.

[0128] At box 1010, the offset position of each servo track can be determined. For example, the controller can be configured with the required number of offset positions for each servo track for multiple rotations and to learn the read operation for each servo track.

[0129] At box 1012, a first media scan pattern can be determined. For example, in some configurations, the controller can be configured to use at least one tone scan pattern for media scanning.

[0130] At box 1014, a second media scan pattern can be defined. For example, in some configurations, the controller can be configured for dual-frequency media scanning and perform media scanning using two tone scan patterns with different frequencies.

[0131] At box 1016, the loops in WRRO learning can be determined and performed. For example, the controller can initiate a series of loops for the disk stack and learn the WRRO correction value for each head / media pair in parallel using two target heads, and optionally write the media scan pattern determined at boxes 1012 and 1014.

[0132] At box 1018, the active media scan write operation can be determined. For example, in some configurations, the controller can determine whether the next round includes a tone pattern write based on the desired media scan tone scan pattern, and if so, which head / medium and which tone pattern should be written. For example configurations of different WRRO learning rounds and whether / which tone scan write operations can be active in that round, please refer to [link to relevant documentation]. Figures 7A to 7D .

[0133] At boxes 1020 and 1022, a pair of target heads can be determined for parallel WRRO learning operations. For example, the controller can select a first target head and a second target head from each head group for WRRO learning.

[0134] At blocks 1024 and 1028, servo pattern segments can be read from each head at the current learning downtrack track offset position. For example, as the first and second target heads pass through corresponding servo wedges on their respective storage medium surfaces, they can each generate read signals and update the head control position signals for their respective heads. Due to the servo pattern offset between the interleaved servo patterns on their respective storage medium surfaces, the servo wedge of the second target head can be offset from the servo wedge of the first target head, and at block 1026, the controller can switch to the second reader head, and at block 1028, wait for the interleaved servo pattern offset time before reading the servo pattern with the second target head. By time-multiplexing between the first and second reader heads during readout and using preamplifier logic, readback TDMR signals from both surfaces can be sent to the same read channel for PES demodulation, eliminating the need for a second read channel for the second head, thus reducing costs.

[0135] At boxes 1030 and 1032, an initial WRRO correction value for the learning track offset of the current loop can be determined. For example, in some configurations, the controller can use the WRRO correction values ​​determined for the servo wedge region at the previous loop and learning track offset to determine the initial value, and calculate the correction value for the current loop and track offset based on that initial value.

[0136] At boxes 1034 and 1036, the WRRO correction value for the learning track offset of the current loop can be determined. For example, the controller can determine the WRRO correction value for the current loop and track offset based on the PES RRO and, in some configurations, based on the initial WRRO correction value determined at boxes 1030 and 1032.

[0137] At boxes 1038 and 1040, WRRO correction values ​​for the learned track offset can be stored. For example, when each WRRO correction value is determined, the controller can write the value into a data structure in non-volatile memory that maps the value to the storage medium surface, servo track, wedge region, and track offset.

[0138] At boxes 1042 and 1044, one of the read / write heads can be used to selectively write a media scan pattern between servo wedge regions. For example, in some configurations, if the controller determines that one of the target heads is the active head for writing the media scan tone pattern during the current cycle of WRRO learning (at box 1018), the tone pattern can be written by the target head into a portion of the medium along a read / write path of the current servo track offset between the servo wedge regions. Within a complete cycle, only one write head is selected to perform the media scan pattern writing.

[0139] At box 1046, WRRO correction values ​​can be interpolated between correction values ​​for sequential loops at the same servo wedge region. For example, the controller can calculate one or more interpolated WRRO correction values ​​for each target head, servo wedge region, and sequential pair of loops. In some configurations, interpolation between correction values ​​may not be calculated during the WRRO learning process, and such calculations may be performed after the learning operation, such as during further configuration or during runtime during servo operation.

[0140] At box 1048, the number of revolutions can be incremented. For example, when one revolution and the associated WRRO learning read and optional tone scan write are complete, the controller can determine the initialization of the next revolution and return to box 1016. In some configurations, seek / position operations can reposition the target head to the next offset track position, or a helical trajectory can effectively reposition the head during the previous revolution so that it is at the next offset position upon completion of the previous revolution.

[0141] like Figure 11As shown, the control circuit 300 can operate according to an example method of switching between self-servo write and drive configuration operations (such as WRRO learning and media scan pattern writing) and production read / write operations, namely, method 1100 illustrated in blocks 1110 to 1142. In some configurations, blocks 1110 to 1120 can be performed during drive manufacturing, testing, and configuration, and at 1102, the data storage device can be put into production use, and blocks 1122 to 1142 are performed throughout the entire lifespan of the data storage device.

[0142] At box 1110, a self-servo write operation can be performed. For example, the controller can use drive circuitry to write an interleaved servo pattern to use the corresponding TDMR heads to write to all disk surfaces in a parallel disk stack.

[0143] At box 1112, a WRRO learning operation can be performed. For example, the controller can perform multiple rotations per servo track to generate the WRRO correction value for the servo track written at box 1110.

[0144] At box 1114, a media test pattern can be written. For example, the controller can write a tone scan pattern between servo wedge zones. In some configurations, the tone scan pattern can be written at box 1112 during the rotation of the same media stack used for WRRO learning operations.

[0145] At box 1116, the actuator control circuitry can be switched for TDMR read / write operations. For example, the controller can switch from parallel operation of the target head pair to normal TDMR read / write operation, which supports more efficient SSW, WRRO learning, and media test pattern writing operations, using read and write sensors from a single head and the corresponding channel paths for servo control and read / write operations.

[0146] At box 1118, media testing operations can be performed. For example, the controller can use the TDMR capability of the read / write head and control circuitry to perform a media scan read operation to characterize the media.

[0147] At box 1120, data tracks can be defined. For example, the controller can be configured with a specific data track format relative to the servo pattern and media capabilities of various regions across different media surfaces.

[0148] At box 1122, the read / write head can be selected. For example, a data storage command can be received from the host system, and the controller can determine the target media location and corresponding read / write head for the corresponding read / write operation.

[0149] At box 1124, a servo read signal can be received from the selected read head. For example, the controller can receive a read signal from the servo wedge region passing under the read head from the TDMR head. At box 1126, during the parallel SSW operation at box 1110, the servo pattern being read can have been written in independently controlled phases.

[0150] At box 1128, a position error signal can be determined based on the read signal. For example, the controller can process the TDMR read signal through the read channel to generate a PES fed to the servo controller for controlling the head position on the storage medium surface. At box 1130, the PES value can be corrected for known WRRO errors using the WRRO correction value generated and stored at box 1112. At box 1142, WRRO correction values ​​can be interpolated between the stored correction values. For example, the controller can calculate one or more interpolated WRRO correction values ​​for the current target head and servo wedge region based on adjacent offset values ​​determined during WRRO learning.

[0151] At box 1132, control signals can be determined based on position error signals. For example, the servo controller and servo interface circuitry can determine the control signals for the voice coil motor, micro-actuator, and milli-actuator of the target head.

[0152] At box 1134, a control signal can be sent to the actuator for the selected head. For example, the control signal determined at box 1132 can be sent to the corresponding actuator of the target head.

[0153] At box 1136, the selected read / write head can be positioned. For example, a control signal sent at box 1134 can adjust various actuators to position the selected read / write head for read / write operations.

[0154] At box 1138, storage operations can be performed. For example, at box 1120, the controller can use the read / write elements of the selected head to read data and / or write data to the data tracks defined between the servo wedges. In some configurations, at box 1140, using storage locations on corresponding physical servo track positions on the surface of paired storage media written in parallel with the interleaved servo pattern, sequential read / write operations can have shorter switching times.

[0155] The foregoing describes a parallel self-servo write technique based on data storage device hardware and software capable of switching between parallel self-servo write mode and data read / write operation mode, and a specific configuration with an interleaved servo pattern featuring independent phase control and improved WRRO learning. In the above description, numerous specific details are set forth for illustrative purposes. However, it will be apparent that the disclosed technique can be practiced without any given subset of these specific details. In other instances, structures and devices are shown in block diagram form. For example, the disclosed technique is described with reference to specific hardware in some of the specific embodiments described above.

[0156] The phrase "an embodiment" or "implementation" as used in this specification means that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one embodiment or specific implementation of the disclosed technology. The phrase "in an embodiment" appearing throughout this specification does not necessarily refer to the same embodiment or specific implementation.

[0157] Some parts of the detailed description above can be presented in terms of the procedures and symbolic representations of operations on data bits within computer memory. A procedure can generally be considered a self-consistent sequence of operations that leads to a result. Operations may involve the physical manipulation of physical quantities. These quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. These signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0158] These and similar terms may be associated with appropriate physical quantities and may be considered as labels applied to those quantities. Unless otherwise explicitly stated from the preceding discussion, it should be understood that throughout the description, discussions using terms such as “processing” or “operation” or “calculation” or “determining” or “displaying” may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in computer system registers and memories, and converts that data into other data similarly represented as physical quantities in computer system memories or registers or other such information storage, transmission, or display devices.

[0159] The disclosed technology may also relate to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for a desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic disks; read-only memory (ROM); random access memory (RAM); erasable programmable read-only memory (EPROM); electrically erasable programmable read-only memory (EEPROM); magnetic cards or optical cards; flash memory including a Universal Serial Bus (USB) key with non-volatile memory; or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0160] The disclosed technology may be implemented entirely in hardware, entirely in software, or in a form that includes both hardware and software elements. In some embodiments, the technology is implemented in software, which includes, but is not limited to, firmware, resident software, and microcode.

[0161] Furthermore, the disclosed technology may take the form of a computer program product accessible from a non-transitory computer-usable or computer-readable medium that provides program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, the computer-usable or computer-readable medium may be any apparatus that may contain, store, transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device.

[0162] A computing system or data processing system suitable for storing and / or executing program code will include at least one processor (e.g., a hardware processor) directly or indirectly coupled to a memory element via a system bus. The memory element may include local memory, mass storage, and cache memory used during the actual execution of the program code, which provides temporary storage for at least some of the program code to reduce the number of times code must be retrieved from the mass storage during execution.

[0163] Input / output or I / O devices (including but not limited to keyboards, displays, indicators, etc.) can be directly or coupled to the system through an intermediate I / O controller.

[0164] Network adapters can also be coupled to the system, enabling the data processing system to be coupled to other data processing systems or remote printers or storage devices via an intermediate private or public network. Modems, cable modems, and Ethernet cards are just a few of the types of network adapters currently available.

[0165] The terms storage medium, storage device, and data block are used interchangeably throughout this disclosure to refer to the physical medium in which data is stored.

[0166] Finally, the processes and displays presented herein may not inherently relate to any particular computer or other device. Various general-purpose systems can be used with programs based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the desired methodological operations. The necessary structures for various such systems will be apparent from the description above. Furthermore, no particular programming language is referenced in the description of the disclosed techniques. It should be understood that the teachings of the techniques described herein can be implemented using various programming languages.

[0167] The foregoing description of the implementation of the inventive technology and techniques has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the inventive technology and techniques to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. It is intended that the scope of the inventive technology and techniques be free from this detailed description. The inventive technology and techniques may be implemented in other specific forms without departing from their spirit or essential characteristics. Similarly, specific naming and classification of modules, routines, features, attributes, methods, and other aspects are not mandatory or essential, and mechanisms for implementing the inventive technology and techniques or their features may have different names, classifications, and / or formats. Furthermore, the modules, routines, features, attributes, methods, and other aspects of the inventive technology may be implemented as software, hardware, firmware, or any combination of the three. Moreover, wherever a component (e.g., a module) is implemented as software, it may be implemented as a standalone program, as part of a larger program, as multiple separate programs, as a static or dynamic link library, as a kernel-loadable module, as a device driver, and / or in every and any other manner known now or in the future in computer programming. Furthermore, the technologies and techniques of this invention are by no means limited to implementation in any particular programming language or for any particular operating system or environment. Therefore, the disclosure of the technologies and techniques of this invention is intended to be illustrative and not restrictive.

Claims

1. A data storage device, the data storage device comprising: A first storage medium surface, the first storage medium surface including a first servo pattern; and The second storage medium surface includes a second servo pattern, wherein: The first servo pattern and the second servo pattern are written in parallel to define corresponding portions of the first servo pattern and the second servo pattern. and The first servo pattern phase of a portion of the first servo pattern is different from the second servo pattern phase of the corresponding portion of the second servo pattern.

2. The data storage device according to claim 1, wherein: The first servo pattern includes a first plurality of servo wedge regions; The second servo pattern includes a second plurality of servo wedge regions; and In the corresponding portions of the first servo pattern and the second servo pattern, the first plurality of servo wedge regions are offset from the second plurality of servo wedge regions.

3. The data storage device according to claim 2, wherein the offset time between the first plurality of servo wedge regions and the second plurality of servo wedge regions is half of the wedge-to-wedge timing of the first servo pattern.

4. The data storage device according to claim 1, wherein: A portion of the first servo pattern has a first track value per inch; The corresponding portion of the second servo pattern has a second track value per inch; and The first track value per inch is different from the second track value per inch.

5. The data storage device of claim 1, further comprising a control circuit configured to: during a self-servo write operation: Determine the first target magnetic head positioned above the surface of the first storage medium; Determine the second target magnetic head positioned above the surface of the second storage medium; Determine the phase of the first servo pattern; Using the first target head, the servo pattern segment of the servo wedge region of the first servo pattern is written using the first servo pattern phase; Determine the phase of the second servo pattern; and Using the second target head and in response to the waiting offset time, the servo pattern segment of the servo wedge region of the second servo pattern is written using the second servo pattern phase.

6. The data storage device of claim 5, wherein the control circuitry includes a servo pulse pattern writer and is further configured to: during a self-servo write operation: Using the servo pulse pattern writer, the servo pattern segment of the servo wedge region of the first servo pattern is generated; and The servo pattern segment of the servo wedge region of the second servo pattern is generated using the servo pulse pattern writer.

7. The data storage device of claim 5, wherein the control circuitry is further configured to: during a self-servo write operation: The first reference signal is read from the surface of the first storage medium using the first target magnetic head; A first frequency offset value for determining the phase of the first servo pattern is determined based on the first reference signal; The second reference signal is read from the surface of the second storage medium using the second target magnetic head; as well as A second frequency offset value for determining the phase of the second servo pattern is determined based on the second reference signal.

8. The data storage device of claim 7, wherein the control circuitry is further configured to: during the self-servo write operation: The first set of timestamps is determined based on the first reference signal; The first set of timestamps is processed by a first timing loop to generate a first timing value, wherein the first frequency offset value is determined based on the first timing value; Update the first frequency offset register in the control circuit using the first frequency offset value; The second set of timestamps is determined based on the second reference signal; The second set of timestamps is processed by a second timing loop to generate a second timing value, wherein the second frequency offset value is determined based on the second timing value; as well as The second frequency offset register in the control circuit is updated using the second frequency offset value.

9. The data storage device of claim 5, wherein the control circuitry is further configured to: during the wedge-region repetitive yaw learning operation: Determine the first target magnetic head positioned above the surface of the first storage medium; Determine the second target magnetic head positioned above the surface of the second storage medium; The first target head is used to read the servo pattern segments of the sequential servo wedge region of the first servo pattern; Using the second target head and alternating with the servo pattern segments of the sequential servo wedge region of the first servo pattern, the servo pattern segments of the sequential servo wedge region of the second servo pattern are read, wherein the first servo pattern and the second servo pattern are read in the same circle on the first storage medium surface and the second storage medium surface; Calculate the first set of wedge repeatability yaw correction values ​​for the sequential servo wedge region of the first servo pattern; as well as Calculate the second set of wedge repeatability yaw correction values ​​for the sequential servo wedge region of the second servo pattern.

10. The data storage device of claim 5, wherein the control circuitry is further configured to switch between operations on the first storage medium surface and operations on the second storage medium surface during read / write operations at a switching time of half the wedge-to-wedge timing, the switching time being shorter than that between storage medium surfaces having substantially aligned servo wedges.

11. A method, the method comprising: In a data storage device, a first servo pattern is used to position a first magnetic head above the surface of a first storage medium. At a first target location based on the first servo pattern, a first storage operation is performed using the first magnetic head and the surface of the first storage medium. In the data storage device, a second servo pattern is used to position the second magnetic head above the surface of the second storage medium, wherein: The first servo pattern and the second servo pattern are written in parallel to define corresponding portions of the first servo pattern and the second servo pattern; and The phase of the first servo pattern of a portion of the first servo pattern is different from the phase of the second servo pattern of the corresponding portion of the second servo pattern; and A second storage operation is performed at a second target location based on the second servo pattern using the second magnetic head and the surface of the second storage medium.

12. The method according to claim 11, wherein: The first servo pattern includes a first plurality of servo wedge regions; The second servo pattern includes a second plurality of servo wedge regions; and In the corresponding portions of the first servo pattern and the second servo pattern, the first plurality of servo wedge regions are offset from the second plurality of servo wedge regions.

13. The method of claim 12, wherein the offset time between the first plurality of servo wedge regions and the second plurality of servo wedge regions is half of the wedge-to-wedge timing of the first servo pattern.

14. The method of claim 11, wherein: A portion of the first servo pattern has a first track value per inch; The corresponding portion of the second servo pattern has a second track value per inch; and The first track value per inch is different from the second track value per inch.

15. The method of claim 11, further comprising during a self-servo write operation: Determine the phase of the first servo pattern; Using the first magnetic head, the servo pattern segment of the servo wedge region of the first servo pattern is written using the first servo pattern phase; Determine the phase of the second servo pattern; and Using the second magnetic head and in response to the waiting offset time, the servo pattern segment of the servo wedge region of the second servo pattern is written using the second servo pattern phase.

16. The method of claim 15, further comprising during the self-servo write operation: Using the servo pulse pattern writer in the data storage device, the servo pattern segment of the servo wedge region of the first servo pattern is generated; and The servo pattern segment of the servo wedge region of the second servo pattern is generated using the servo pulse pattern writer.

17. The method of claim 15, further comprising during a self-servo write operation: The first reference signal is read from the surface of the first storage medium using the first magnetic head; A first frequency offset value for determining the phase of the first servo pattern is determined based on the first reference signal; The second reference signal is read from the surface of the second storage medium using the second magnetic head; as well as A second frequency offset value for determining the phase of the second servo pattern is determined based on the second reference signal.

18. The method of claim 17, further comprising during a self-servo write operation: The first set of timestamps is determined based on the first reference signal; The first set of timestamps is processed by a first timing loop to generate a first timing value, wherein the first frequency offset value is determined based on the first timing value; Update the first frequency offset register in the data storage device using the first frequency offset value; The second set of timestamps is determined based on the second reference signal; The second set of timestamps is processed by a second timing loop to generate a second timing value, wherein the second frequency offset value is determined based on the second timing value; as well as The second frequency offset register in the data storage device is updated using the second frequency offset value.

19. The method of claim 11, further comprising, during the repetitive yaw learning operation in the wedge region: The first magnetic head is used to read the servo pattern segments of the sequential servo wedge region of the first servo pattern; Using the second magnetic head and alternating with reading the servo pattern segments of the sequential servo wedge region of the first servo pattern, reading the servo pattern segments of the sequential servo wedge region of the second servo pattern, wherein the first servo pattern and the second servo pattern are read in the same loop on the surface of the first storage medium and the surface of the second storage medium; Calculate the first set of wedge repeatability yaw correction values ​​for the sequential servo wedge region of the first servo pattern; as well as Calculate the second set of wedge repeatability yaw correction values ​​for the sequential servo wedge region of the second servo pattern.

20. A data storage device, the data storage device comprising: A first magnetic head is actuated above the surface of a first storage medium; The second magnetic head is actuated above the surface of the second storage medium; Components used to determine the phase of the first servo pattern; A component for using the first magnetic head and writing a servo pattern segment of a servo wedge region of a first servo pattern onto the surface of the first storage medium using the first servo pattern phase; Components used to determine the phase of the second servo pattern; and A component for using the second magnetic head and writing servo pattern segments of a servo pattern wedge region of the second servo pattern onto the surface of the second storage medium, using the second servo pattern phase and in response to an offset time from the first servo pattern, wherein: The first servo pattern and the second servo pattern are written in parallel to define corresponding portions of the first servo pattern and the second servo pattern; and The phase of the first servo pattern of a portion of the first servo pattern is different from the phase of the second servo pattern of the corresponding portion of the second servo pattern.

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