Dynamic control of data transient rise time based on process, temperature, voltage (pvt) data in memory devices

Abstract

A memory device includes an array of memory cells of a non-volatile memory and an input / output (IO) buffer coupled to the array. The IO buffer includes a main pull-up transistor coupled between a power supply and ground and coupled to a data fast (DQ) output line. The IO buffer includes a selectable pull-up transistor coupled in parallel with the main pull-up transistor. The IO buffer includes a logic device coupled to the selectable pull-up transistor. The logic device selects a customized number of selectable pull-up transistors for use during a transient period of data transfer at the DQ output line based on process, voltage, temperature (PVT) data associated with the memory device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of memory devices, and in particular to dynamically controlling data transient rise time based on process, temperature, and voltage (PVT) data in a memory device. BACKGROUND

[0002] In some memory devices, such as low power double data rate (LPDDR) memory devices, a low voltage, swing terminated logic device (LVSTL) based protocol uses a pull-up transistor to determine an output from an input / output (IO) buffer, the pull-up transistor calibrated based on training that employs values read from an external ZQ (e.g., impedance / quality factor) resistor. However, this approach has settled on whether to add a fixed number of additional pull-up transistors to the main transistor in order to improve the rise time to meet a particular output high voltage (VOH) level. However, adding a fixed number of pull-up transistors based on varying process, temperature, voltage (PVT) values experienced on the memory device is insufficient, the varying process, temperature, voltage (PVT) values affecting the rise time of the data quick (DQ) output of the IO buffer. BRIEF DESCRIPTION OF DRAWINGS

[0003] The present disclosure is illustrated by way of example, and not limitation, in the figures of the accompanying drawings.

[0004] Figure 1 is a block diagram of a system including a host device and a memory device having an IO buffer in accordance with various embodiments.

[0005] Figure 2 is a simplified block diagram of a portion of an IO buffer in accordance with some embodiments.

[0006] Figure 3 is a plot showing different eye diagrams for comparing no pulse acceleration to employing eight additional pull-up transistors to employing twelve additional pull-up transistors in accordance with several embodiments.

[0007] Figure 4A is a circuit diagram of an IO buffer implemented for selectively adding a custom number of pull-up transistors in accordance with some embodiments.

[0008] Figure 4B is a plot showing transition timing with acceleration pulses employed within an IO buffer in accordance with some embodiments.

[0009] Figure 5 is a flowchart of a method for calibrating an effective pull-up transistor size in accordance with PVT data in accordance with some embodiments associated with Figure 4A

[0010] Figure 6 ​is a circuit diagram of an IO buffer according to other embodiments for selectively adding a particular voltage bias to the substrate of a pull-up transistor.

[0011] Figure 7 is a flowchart of a method for dynamically changing an effective pull-up transistor size according to PVT data according to Figure 6

[0012] Figure 8 is a flowchart of a method for dynamically changing an effective pull-up transistor strength according to PVT data according to Figure 6

[0013] Figure 9 shows a diagrammatic representation of a machine in the example form of a computing system within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein can be executed. DETAILED DESCRIPTION

[0014] As discussed, adding a fixed number of pull-up transistors to the main pull-up transistor based on varying PVT values experienced on the memory device that affect the rise time of the data quick (DQ) output of the IO buffer is insufficient. For example, for fast data transients, only a small number of pull-up transistors can be used to reach the VOH level, while for slow data transients, a larger number of pull-up transistors can be used to reach the VOH level. Thus, deciding whether to add a fixed number of transistors can enable improvement for either fast or slow data transient conditions, but not both.

[0015] More specifically, the cause of the difference between the direct current (DC) behavior and the alternating current (AC) behavior in the DQ output of the IO buffer based on VOH-based training is the different overdrive levels of the pull-up transistors. This training can be based on PVT values obtained such as during ZQ calibration, which will be discussed in more detail. By way of example, when the Vgs and Vds levels are small (e.g., Vgs equals Vdd-VOH and Vds equals Vddq-VOH), additional pull-up transistors benefit fast data transient conditions (e.g., overdrive is small). In contrast, when overdrive is large (e.g., Vgs = Vdd and Vds = Vddq), additional pull-up transistors benefit slow data transient conditions. Thus, during the speed-up pulse for the data transient period, adding a small number of pull-up transistors can be insufficient for slow data transient conditions, while adding a large number of pull-up transistors can result in overshoot and ringing for fast data transient conditions. For this reason, adding (or not adding) a fixed static size pull-up transistor (single or multiple) is insufficient due to changing PVT conditions of the memory device.

[0016] ​​The present disclosure addresses the aforementioned deficiencies (as well as other deficiencies to be discussed in greater detail below) by dynamically customizing the size of the pull-up transistor(s) within the IO buffer based on the value of the most recently computed PVT value. For example, the custom size of the total number of pull-up transistors should be large enough to compensate for slow data transient conditions, while not causing an overshoot in fast data transient conditions.

[0017] In some embodiments, a memory device includes an array of memory cells, a set of memory registers to store PVT data associated with the memory device, and an input / output (IO) buffer coupled to the array and the set of memory registers. In such embodiments, the IO buffer includes a main pull-up transistor coupled between a power supply and a ground and coupled to a data quick (DQ) output line. The IO buffer can also include a plurality of selectable pull-up transistors coupled in parallel with the main pull-up transistor. The IO buffer can also include a logic device coupled to the plurality of selectable pull-up transistors, the logic device to select a custom number of the plurality of selectable pull-up transistors for use during a transient period of data transfer at the DQ output line based on the PVT data.

[0018] In other embodiments, the IO buffer of the memory device instead includes a bank of pull-up transistors coupled between a power supply and a ground and coupled to a data quick (DQ) output line, and the threshold voltages of the bank of pull-up transistors instead dynamically vary through a body voltage bias. For example, the IO buffer can include a voltage regulator to generate a bias voltage. The IO buffer can also include a logic device coupled to the bank of pull-up transistors and the voltage regulator. The logic device can be configured to selectively apply the bias voltage to a substrate of the bank of pull-up transistors for use during a transient period of data transfer at the DQ output line based on the PVT data.

[0019] Accordingly, advantages of systems and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, enabling an IO buffer of a non-volatile memory device, such as a LPDDR NOR flash memory, to customize the effective size of a transistor bank according to a latest PVT value (single or multiple) such as a most recently measured ZQ value, which can be associated with different process corners. Using these ZQ values enables more accurate VOH-level calibration of the IO buffer and is able to compensate for different speed data transients in the DQ output lines. The improved calibration level enables a more defined eye diagram to be achieved at the DQ output lines, resulting in more accurate sampling of data from the eye diagram. The calibration values discussed can also be stored in local memory registers and can be updated during a simulation or characterization period to update the effective size of the pull-up transistor, for example, based on changing PVT conditions. These and additional advantages will be apparent to those of ordinary skill in the art in view of the following description.

[0020] Figure 1 is a block diagram of a system 100 including a host device 190 and a memory device 102 having an IO buffer 110 in accordance with various embodiments. In some embodiments, the memory device 102 is a type of LPDDR device, but can be any kind of non-volatile memory. In particular, the memory device 102 can include, but is not limited to, a Serial Peripheral Interface (SPI) Physical Layer (PHY) 105 to interface with SPI-based devices, a plurality of memory banks 115 (any portion of which can be referred to herein as an array of memory cells), an IO buffer 110 to interface with the host device 190, and a plurality of on-board sensors 122. In some embodiments, the SPI PHY 105 is an interface to perform non-volatile memory functions such as reading and writing Serial Presence Detect (SPD) EEPROM, firmware updates, or accessing other control and configuration settings that can or can not be directly related to core memory read operations performed via the IO buffer 110 host memory interface.

[0021] In some embodiments, the on-board sensors 122 include a temperature detector, a voltage detector, and / or a ring oscillator that can provide at least some aspects of PVT data if not obtained through ZQ calibration. In some embodiments, the host device 190 is a controller that functions on behalf of a host system that interacts with the memory device 102. For example, the host device can be operably coupled to the memory device and configured to store data to and retrieve data from the array of memory cells.

[0022] In some embodiments, the IO buffer 110 is a LPDDR-based interface (e.g., PHY component) configured to supply data read out from the plurality of memory banks 115 to the host device 190. In another embodiment, the IO buffer 110 can also supply data received from the host device 190 to be written to the plurality of memory banks 115 (not shown in the middle). Figure 1 In embodiments, the IO buffer 110 includes a read data buffer (RDB) 112A and a read address buffer (RAB) 112B. Circuitry and logic of the IO buffer 110 referenced herein can be understood to variably exchange data with either or both of the RDB 112A and the RAB 112B.

[0023] In various embodiments, the IO buffer 110 includes interface pins (or pads) coupled to lines to the host device 190, including 16 DQs (eight on each side of the IO buffer 110), a DQS line carrying data strobes, and other data lines. In addition, the IO buffer 110 includes or is coupled to a ZQ pin, which is coupled to a ZQ resistor 116 located outside of the memory device 102.

[0024] In some embodiments, the data strobe functionality of the memory device 102 can be trained to sample as close to the center (or widest point) of the data eye of the data transmitted via the DQ output lines as possible. As an example only, a LPDDR4-based interface can use mismatched DQS-DQ paths to enable high-speed performance and save power in the memory device 102. Thus, the DQS strobe can be trained to reach the DQ latches aligned with the data eye center. The SDRAM DQ receivers can be located at the DQ pads and have a shorter internal delay in the memory device 102 than the DQS signal. The DQ receivers can latch the data present on the DQ bus when the DQS arrives at the latches, and the training is achieved by delaying the DQ signal relative to the DQS so that the data eye arrives centered on the receiver latches with the DQS transition.

[0025] In addition, ZQ calibration can be employed prior to and during operation of the memory device 102 to maintain different parameter values consistent with changes in process, temperature, and voltage (PVT) values. A multi-purpose command (MPC) can be used to initiate ZQ calibration, which calibrates the output driver impedance across process, temperature, and voltage, for example, based on readings taken at the ZQ resistor 116. In some embodiments, ZQ calibration occurs in the background of device operation, and a dual-channel device shares common ZQ circuitry between channels, which follows a protocol that allows for channel independence.

[0026] In some embodiments, there are two ZQ calibration modes initiated with MPC commands: ZQCal Start and ZQCal Latch. The ZQCal Start command can initiate a calibration procedure of the memory device 102, and the ZQCal Latch command can capture the results and load the results into the drivers of the memory device 102, which can also be stored in a memory register. The ZQCal Start command can be issued at any time when the memory device 102 is not in a power down state. The ZQCal Latch command can be issued at any time outside of power down after tZQCAL has expired and all DQ bus operations have completed. The command and address (CA) bus can be maintained in a de-selected state during tZQLAT to allow updating of on-die termination (ODT) calibration settings. In some embodiments, the following mode register fields modifying I / O parameters cannot change after the ZQCal Start command and before tZQCAL expires: PU-Cal (pull-up calibration VOH point); PDDS (pull-down drive strength and RX termination); DQ-ODT (DQ ODT value); and CA-ODT (CA ODT value).

[0027] In some embodiments of LVSTL, the DQ bus needs to be terminated, so when the host device 190 reads from the memory device 102, the memory device 102 sends data on the DQ bus and the host device 190 needs to terminate the bus. In the CA entry, the host device 190 can send CA on the CS bus (a different bus than DQ), and the memory device 102 can terminate the CS bus using ODT circuitry on the die.

[0028] Figure 2 is a simplified block diagram of a portion 200 of the IO buffer 110 Figure 1 ) according to some embodiments. The portion 200 of the IO buffer 110 includes one or more pull-up transistors 202 coupled in series with one or more pull-down transistors 204. An ODT transistor 208 can be coupled to a DQ output line 214 and enabled when data is received. The ODT transistor 208 can be used to ensure signal integrity, reliable operation, and compatibility with the host device 190. A VOH voltage can be an output high voltage generated by a resistive voltage division between the one or more pull-up transistors 202 and the ODT transistor 208.

[0029] Figure 3 is a plot showing different eye diagrams of the IO buffer 110 for comparing no pulse acceleration with employing eight additional pull-up transistors to employing 12 additional pull-up transistors according to several embodiments. These eye diagrams are from the DQ output of the IO buffer 110, as Figure 2 and Figure 4AAs shown, this will be discussed below. For example, these superimposed eye diagrams include a first eye diagram 301 showing a data eye without an acceleration pulse, a second eye diagram 303 showing a data eye when employing eight additional pull-up transistors (enabled via an acceleration pulse), and a third eye diagram 305 showing a data eye when employing 12 additional pull-up transistors (enabled via an acceleration pulse).

[0030] As can be seen, the slope of the data transient portion 301T of the first eye diagram 301 is less than the data transient portion 305T of the third eye diagram 305, and the data transient portion of the second eye diagram 303 is between them. Thus, the data eye associated with the third eye diagram 305 is wider and more pronounced than the data eye associated with the first eye diagram 301. This facilitates DQS gating to sample data from the data eye better and more accurately.

[0031] In some embodiments, the acceleration pulse can be a pull-down acceleration pulse during a pull-down transient period, shown as pull-down transient period 310T, which comes before each pull-up data transient period or portion (e.g., marked by 301T and 305T). In alternatives to the disclosed embodiments, the transistors and / or resistors can be selected to vary the strength of one or more pull-down transistors 204 (e.g., also as discussed below with reference to FIG. 4). In this way, the principles of the present disclosure can be similarly employed with respect to the pull-down transient portion 310T in relation to a change in the strength of the pull-down transistors of the IO buffer 110. If an acceleration pulse is to be applied during the pull-down transient period, each of the second eye diagram 303 and the third eye diagram 305 in the region of the pull-down transient period 310T will be more pronounced, e.g., have an increased slope similar to the slope of the data transient portion 305T. Figure 4A to Figure 4B and Figure 6 As can be seen, the slope of the data transient portion 301T of the first eye diagram 301 is less than the data transient portion 305T of the third eye diagram 305, and the data transient portion of the second eye diagram 303 is between them. Thus, the data eye associated with the third eye diagram 305 is wider and more pronounced than the data eye associated with the first eye diagram 301. This facilitates DQS gating to sample data from the data eye better and more accurately.

[0032] Figure 4A is a circuit diagram of an IO buffer 400 implemented for selectively adding a custom number of pull-up transistors in accordance with some embodiments. In embodiments, the IO buffer 400 is at least a portion of the IO buffer 110 of Figure 1 In embodiments, the IO buffer 400 includes a buffer 40 coupled to an OR gate 44, which is coupled to a pull-down transistor 48. A pulldown enable (pulldown_en) signal can be asserted at an input of the buffer 40 to activate the pull-down transistor 48. In embodiments, the IO buffer 400 includes a buffer 50 coupled to an OR gate 54, which is coupled to a pull-up transistor 58. In some embodiments, the pull-down transistor 48 source-drain is coupled to the pull-up transistor 58. A pullup enable (pullup_en) signal can be asserted at an input of the buffer 50 to activate the pull-up transistor 58.

[0033] In at least some embodiments, pull-up transistor 58 is understood to be a main pull-up transistor, which includes one transistor or a fixed number of multiple pull-up transistors coupled between a power supply and ground and coupled to a data quick (DQ) output line 450. In some embodiments, a variable resistor 440 is coupled in series to a source of pull-up transistor 58. In some embodiments, pull-up transistor 58 is enabled when IO buffer 400 is transmitting data and has a default size for maintaining a DC value of VOH.

[0034] In at least some embodiments, IO buffer 400 further includes a plurality of selectable pull-up transistors 438 coupled in parallel with the main pull-up transistor (e.g., pull-up transistor 58). In some embodiments, a variable resistor 442A...442N (of a plurality of variable resistors 442) is coupled in series to a source of each selectable pull-up transistor of the plurality of selectable pull-up transistors 438. In some embodiments, IO buffer 400 further includes a set of memory registers 403 for storing PVT data associated with memory device 102. In some embodiments, the set of memory registers 403 includes one of a hardwired register or a memory cell, for example, at a reserved address within an array of memory cells within a plurality of memory banks 115 Figure 1 ) In the embodiments shown herein, the transistors are n-type metal-oxide-semiconductor (NMOS) transistors, but in other embodiments, the designs shown can be inverted and can employ p-type or PMOS transistors, as will be understood by those skilled in the art.

[0035] IO buffer 400 can further include a logic device 402 coupled to the plurality of selectable pull-up transistors 438 and the plurality of variable resistors 442. In at least some embodiments, logic device 402 selects a customized number of the plurality of selectable pull-up transistors 438 during transient periods of data transmission at DQ output line 450 based on the PVT data. In this way, the total size of the pull-up transistors can be selectively customized to compensate for changes in PVT values associated with memory device 102. In some embodiments, the customized number of the selection of the plurality of selectable pull-up transistors 438 is based in part on a type of LPDDR memory of the plurality of memory banks 115.

[0036] In at least some embodiments, logic device 402 further trims a resistance of each variable resistor 442 coupled in series to the selected customized number of selectable pull-up transistors of the plurality of selectable pull-up transistors 438 based on the PVT data. This trimming can include reducing the resistance to only a wire resistance and thus can add or remove resistance to each selectable pull-up transistor (whether selected or not) to customize a pull-up strength of each branch with the selectable pull-up transistors.

[0037] In some embodiments, the PVT data is a value derived from a ZQ calibration most recently performed via a ZQ resistor 116 coupled externally to a ZQ pin of the memory device 102. In other embodiments, the PVT data includes a value most recently obtained from one of on-board sensors 122, such as a temperature detector, a voltage detector, or a ring oscillator located on the memory device 102.

[0038]

[0039] Table 1

[0040] In at least some embodiments, the logic device 402 stores a range of PVT values indexed for a number of selectable pull-up transistors in a data structure 404 in the set of memory registers 403. The logic device 402 can further select a customized number of the plurality of selectable pull-up transistors 438 based on PVT data corresponding to the range of PVT values and optionally also based on a type (or mode) of the memory device 102. Table 1 is an example data structure with ZQ value ranges populated in a first column and indexed for different types of LPDDR-based devices in subsequent columns. As can be observed, sometimes no additional pull-up transistors need to be selected, and sometimes no acceleration pulse need to be applied.

[0041] In some embodiments, the logic device 402 includes a multiplexer 408 with different numbers of the plurality of selectable pull-up transistors 438 stored in the data structure 404 as inputs and a most recent value of the PVT data as a selector. The logic device 402 can also include an AND gate 424 (or other logic gate) with an output of the multiplexer 408 as an input and a line 426 carrying an acceleration pulse applied during a transient period. The AND gate 424 (or other logic gate) can also include an output coupled to gates of the plurality of selectable pull-up transistors 438, for example, to enable the number of selectable pull-up transistors of the plurality of selectable pull-up transistors 438 output by the multiplexer 408.

[0042] In some embodiments, there can be many data structures stored in the set of memory registers 403, each storing a different range of PVT values indexed for a different number of the plurality of selectable pull-up transistors 438, for example, to enable customization in cases where PVT data is obtained, for example, from on-board sensors 122 or for other process corners. Thus, in some embodiments, the logic device 402 stores a plurality of ranges of PVT values in each of a plurality of data structures, each range indexed for a predetermined number of the plurality of selectable pull-up transistors to be selected for a particular process corner.

[0043] By way of example only, Table 2 illustrates a first data structure storing temperature values in the first column and voltage values in the first row, both indexed for different numbers of the plurality of selectable pull-up transistors 438 for a typical process corner associated with a typical speed of data transients at the DQ output lines (see Figure 3 The data transient portion 301T of Table 2 is indexed for different numbers of the plurality of selectable pull-up transistors 438 for a typical process corner (TT) associated with a typical speed of data transients at the DQ output lines.

[0044] TT 0.9 1 1.2 -45–25 12 8 6 25–50 24 12 8 50–75 48 24 12 75–100 63 48 24 100–125 63 63 48 125–150 63 63 63

[0045] Table 2

[0046] Table 3 illustrates a second data structure storing temperature values in the first column and voltage values in the first row, both indexed for different numbers of the plurality of selectable pull-up transistors 438 for a fast process corner (FF) associated with a fast speed of data transients at the DQ output lines (e.g., faster than the typical speed).

[0047] FF 0.9 1 1.2 -45–25 8 4 2 25–50 20 8 4 50–75 44 20 8 75–100 59 44 20 100–125 59 59 44 125–150 59 59 59

[0048] Table 3

[0049] Table 4 illustrates a third data structure storing temperature values in the first column and voltage values in the first row, both indexed for different numbers of the plurality of selectable pull-up transistors 438 for a slow process corner (SS) associated with a slow speed of data transients at the DQ output lines (e.g., slower than the typical speed).

[0050] SS 0.9 1 1.2 -45–25 16 12 10 25–50 28 16 12 50–75 52 28 16 75–100 63 52 28 100–125 63 63 52 125–150 63 63 63

[0051] Table 4

[0052] While only three tables are illustrated here for three exemplary process corners (TT, FF, SS), many additional PVT-dependent tables are contemplated for additional process corners. For example, the number of process corners depends on foundry processes, e.g., and for NMOS and PMOS devices and then based on resistor corners (e.g., SS NMOS, SS PMOS, SS resistor; SS NMOS, SS PMOS, typical resistor; or SS NMOS, FF PMOS, typical resistor; etc.) can result in two slow and fast corners (slow and slowest, fast and fastest). These additional process corners add additional permutations of PVT value ranges, and thus also increase the number of assignments of pull-up transistors and / or variable resistors.

[0053] Therefore, in at least some embodiments, logic device 402 stores multiple ranges of PVT values ​​in a first data structure, each range being an index of a first number of selectable pull-up transistors 438 selected for a typical process inflection point associated with a typical speed of data transients at the DQ output line. Logic device 402 may also store multiple ranges of PVT values ​​in a second data structure, each range being an index of a second number of selectable pull-up transistors 438 selected for a fast process inflection point associated with a speed of data transients faster than the typical speed. Logic device 402 may also store multiple ranges of PVT values ​​in a third data structure, each range being an index of a third number of selectable pull-up transistors 438 selected for a slow process inflection point associated with a speed of data transients slower than the typical speed. Logic device 402 may also select one of a first number, a second number, or a third number of selectable pull-up transistors 438 based on the PVT data corresponding to the ranges of PVT values ​​and the speed of the data transient. As discussed, these process inflection points may be multiplied at more than three possible process inflection points; therefore, these are merely exemplary.

[0054] Figure 4B This is a graph illustrating transition timing (with acceleration (or pull-up) pulses during transition timing) within the I / O buffer 400 according to some embodiments. As shown, in some embodiments, for example during a transition from a zero bit value to a one bit value, the pull-up or acceleration pulse is activated at the start of the data transition between bits. In embodiments, this is the data transition period during which additional pull-up transitions can help strengthen and widen the data eye, as referenced... Figure 3 The subject of discussion.

[0055] Figure 5 It is based on and Figure 4A A flowchart of a method 500 for calibrating the effective pull-up transistor size based on PVT data, from some associated embodiments, is provided. Method 500 may be executed by a processing logic device, which may include hardware (e.g., a processing device, circuitry, dedicated logic device, programmable logic device, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 4A The logic device 402 of the I / O buffer 400 performs the operation. Although shown in a specific sequence or order, the order of operations can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations can be performed in different orders, and some operations can be performed in parallel. In addition, one or more operations may be omitted in some embodiments. Therefore, not all the operations shown are required in every embodiment, and other process flows are possible.

[0056] At operation 510, processing logic monitors for a DQ transient period, e.g., at a bit transition in data being transferred through IO buffer 400.

[0057] At operation 520, processing logic reads PVT values from a set of memory registers 403, e.g., the most recently stored PVT values.

[0058] At operation 530, processing logic selects one or more of a plurality of selectable pull-up transistors 438 based on the PVT values.

[0059] At operation 540, processing logic determines whether IO buffer 400 is in a DQ transient period. In some embodiments, processing logic detects a pull-up pulse or an acceleration pulse and thus knows that IO buffer is in a DQ transient period. If no, at operation 540, processing logic loops back to operation 530 and continues to wait for entry into a data transient period, but already knows how many selectable pull-up transistors to select. If yes at operation 540, processing logic transitions through the transient period with the selected pull-up transistors of the plurality of selectable pull-up transistors 438.

[0060] At operation 550, processing logic de-selects the selected pull-up transistors after the DQ transient period, e.g., such that no additional pull-up transistors need be employed to maintain a VOH DC level after the DQ transient period.

[0061] At operation 560, processing logic updates data structure 404 based on the DQ transient waveform, e.g., the slope steepness. The update to data structure 404 can further calibrate the range of PVT values for a particular number of the plurality of selectable pull-up transistor indices, which can then be statically applied during real-time operation.

[0062] After completing a data transfer and updating data structure 404, method 500 can loop back to operation 510 to continue monitoring for a next DQ transient period and performing continued calibration of IO buffer. As previously discussed, method 500 can also be applied to pull-down transient periods selected from a set of a plurality of selectable pull-down transistors, and thus be performed directly after the above operations once IO buffer transitions into a pull-down transient period.

[0063] Figure 6 is a circuit diagram of an IO buffer 600 implemented to selectively add a particular voltage bias 610 to a substrate of a pull-up transistor in accordance with other embodiments. In embodiments, IO buffer 600 is Figure 1at least a portion of the IO buffer 110. In embodiments, the IO buffer 600 includes a buffer 40 coupled to an OR gate 44 (or other logic gate) coupled to a pulldown transistor 48. A pulldown enable (pulldown en) signal can be asserted at an input of the buffer 40 to activate the pulldown transistor 48. In embodiments, the IO buffer 600 includes a buffer 50 coupled to an OR gate 54 (or other logic gate) coupled to a pullup transistor group 638, such as a plurality of pullup transistors coupled in parallel.

[0064] In embodiments, the pullup transistor group 638 is coupled between a power supply and ground and to a data quick (DQ) output line 650. In some embodiments, the pulldown transistor 48 source-drain is coupled to the pullup transistor group 638. A pullup enable (pullup en) signal can be asserted at an input of the buffer 50 to activate the pullup transistor group 638. In some embodiments, the IO buffer 600 includes a plurality of variable resistors 642 each coupled in series to a source of a respective pullup transistor in the pullup transistor group 638.

[0065] In at least some embodiments, the IO buffer 600 includes a set of memory registers 603 for storing process, voltage, temperature (PVT) data associated with the memory device. In some embodiments, the set of memory registers 403 includes one of a hardwired register or a memory cell, such as at a reserved address within an array of memory cells within a plurality of memory banks 115 Figure 1 ).

[0066] In some embodiments, the IO buffer 600 also includes a voltage regulator 605 to generate a bias voltage 610. The IO buffer 600 can also include a logic device 602 coupled to the pullup transistor group 638, the plurality of variable resistors 642, and the voltage regulator 605. In some embodiments, the logic device 602 is to selectively apply the bias voltage 610 to a substrate of the pullup transistor group 638 during a transient period of data transmission at the DQ output line 650 based on the PVT data. For example, the logic device 602 can set the bias voltage of the voltage regulator 605 based on a current value of the PVT data. The bias voltage 610 can effectively change a threshold voltage of transistors within the pullup transistor group 638, which is similar to Figure 4A embodiments of FIG. 1, achieving the same result of customizing the strength of the pullup transistors, but via altering the threshold voltage of a fixed number of transistors.

[0067] In some embodiments, logic device 602 includes a multiplexer 614 to switch between a ground voltage and a bias voltage 610. Logic device 602 may also include a buffer 618 coupled between multiplexer 614 and pull-up transistor group 638. In some embodiments, logic device 602 determines that the PVT value of the PVT data fails to meet a threshold, and in order to selectively apply bias voltage 610, logic device 602 applies a positive bias voltage that causes a decrease in the threshold voltage of the pull-up transistors within the pull-up transistor group. Reference Figure 7 Discuss the additional functions of logic device 602.

[0068] In at least some embodiments, logic device 602 further adjusts the resistance of each variable resistor 642, which is series-coupled to a selected pull-up transistor in selectable pull-up transistor group 638, based on PVT data. This adjustment may include reducing the resistance to line resistance only and thus adding or removing resistance to each selectable pull-up transistor (whether selected or not) to customize the pull-up strength of each branch with selectable pull-up transistors.

[0069] In some embodiments, logic device 602 includes a gate voltage regulator 645 (which may also be a voltage regulator 605 in some embodiments) to generate an regulated gate voltage. For example, along with applying a bias voltage 610 to the pull-up transistor group 638, logic device 602 may cause the gate voltage regulator 645 to adjust the gate voltage of the pull-up transistors in the pull-up transistor group 638. In some embodiments, for example, the regulated gate voltage may be a reduced gate voltage that facilitates the selection of an additional pull-up transistor from the pull-up transistor group 638. The ability to select an additional pull-up transistor provides additional margin to strengthen the pull-up voltage of all coupled pull-up transistors during data transient periods.

[0070] Figure 7 It is based on Figure 6 A flowchart of another embodiment of a method 700 for dynamically changing the effective pull-up transistor size based on PVT data. Method 700 can be executed by a processing logic device, which may include hardware (e.g., processing device, circuit system, dedicated logic device, programmable logic device, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 700 is performed by… Figure 6The logic device 602 of the IO buffer 600 performs. Although shown in a particular sequence or order, the order of the operations can be modified unless otherwise specifically stated. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations can be performed in a different order, and some operations can be performed in parallel. Additionally, one or more operations can be omitted in some embodiments. Thus, not all operations illustrated in the figures can be required, and other processes can be possible.

[0071] At operation 710, the processing logic performs the PVT-based calibration previously discussed in detail, such as ZQ calibration.

[0072] At operation 720, the processing logic selects a fixed number of pull-up transistors (e.g., in the pull-up transistor group 638) based on the PVT / ZQ values from the ZQ calibration (or from reading the sensor 122 Figure 1 ) and prior to selectively applying a bias voltage.

[0073] At operation 730, the processing logic determines whether the PVT or ZQ values are less than a threshold, e.g., fail to meet the threshold. If the threshold is not met, then at operation 740, the processing logic raises the bias voltage 610, as discussed with reference to FIG. 6. Figure 6 Method 700 can then loop back through operations 710 and 720, e.g., by causing the ZQ calibration to be rerun after the bias voltage is applied to generate new ZQ values and select an updated fixed number of transistors from the pull-up transistor group 638 based on the new ZQ values. The second pass through operations 710 and 720 can be performed at least once.

[0074] If at operation 740, the PVT or ZQ values do meet the threshold, e.g., exceed the threshold, then the processing logic can perform operations 750 and 760.

[0075] At operation 750, the processing logic stores the PVT or ZQ values in a memory register.

[0076] At operation 760, the processing logic stores the bias voltage value in a memory register 603. The processing logic can then employ the stored PVT / ZQ values and bias voltage corresponding to the stored bias voltage value to bias the pull-up transistor group 638 during operation of the IO buffer 600.

[0077] In some embodiments, the processing device can also determine, via simulation or characterization of the operation of the pull-up transistor group during the data transient, that the bulk transistor threshold voltage provided by the updated fixed number of transistors is insufficient to achieve a predetermined slope of the data transient. In such a case, the processing device can further reduce or eliminate the bias voltage applied to the substrate of the transistor group.

[0078] Figure 8 is according to Figure 6 a flowchart of a method 800 for dynamically changing effective pull-up transistor strength according to PVT data according to other embodiments. The method 800 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 800 is performed by the logic device 602 of the IO buffer 600 of Figure 6 Although illustrated in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations can be performed in a different order, and some operations can be performed in parallel. Additionally, one or more operations can be omitted in some embodiments. Thus, not all of the operations shown can be required in every implementation, and other processes can be possible.

[0079] At operation 810, the processing logic performs the PVT-based calibration previously discussed in detail, such as ZQ calibration.

[0080] At operation 820, the processing logic selects a fixed number of pull-up transistors (e.g., in the pull-up transistor group 638) based on the PVT / ZQ values from the ZQ calibration (or from reading the sensor 122 Figure 1 )) and prior to selectively applying a bias voltage.

[0081] At operation 830, the processing logic determines whether the PVT or ZQ values are less than a threshold, e.g., fail to meet the threshold. If the threshold is not met, then at operation 840, the processing logic adjusts the gate voltage of the pull-up transistor group 638, as discussed with reference to Figure 6 The method 800 can then loop back through operations 810 and 820, e.g., by causing the ZQ calibration to be rerun to generate new ZQ values and select an updated fixed number of transistors from the pull-up transistor group 638 based on the new ZQ values after the gate voltage is adjusted. The second pass through operations 810 and 820 can be performed at least once. In this way, the processing logic also adjusts the selected fixed number of transistors in the pull-up transistor group 638 based on the adjusted gate voltage.

[0082] If at operation 840, the PVT or ZQ values do meet the threshold, e.g., exceed the threshold, then the processing logic can perform operations 850 and 860.

[0083] At operation 850, the processing logic stores the PVT or ZQ values in a memory register.

[0084] At operation 860, the processing logic stores the adjusted gate voltage value in the memory register 603. The processing logic can then employ the stored PVT / ZQ value and adjust the gate voltage corresponding to the stored adjusted gate voltage value to update the effective strength of the pull-up transistor set 638 during operation of the IO buffer 600.

[0085] In some embodiments, the processing device can also determine, via simulation or characterization of the operation of the pull-up transistor set during the data transient, that the updated fixed number of transistors provides insufficient body transistor threshold voltage to achieve a predetermined slope of the data transient. In such a case, the processing device can further reduce or eliminate the bias voltage applied to the substrate of the transistor set.

[0086] Figure 9 Shown is a diagrammatic representation of the machine in the example form of a computing system 900 within which a set of instructions can be executed for causing the machine to perform any one or more of the methodologies discussed herein. In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet. The machine can operate in the capacity of a server or a client device in client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine can be a host computing system or computer, an automotive computing device, a server, a network device for an automotive network such as a controller area network (CAN) or local interconnect network (LIN), or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein. Implementation of the conversion page and section can be in the computing system 900.

[0087] The computing system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0088] The processing device 902 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or both. More particularly, the processing device can be complex instruction set computing (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processing device implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 902 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processing device, or the like. In one embodiment, the processing device 902 can include one or more processing device cores. The processing device 902 is configured to execute the instructions 926 for performing the operations discussed herein. In one embodiment, the processing device 902 can be a part of the system 100 of Figure 1

[0089] Alternatively, the computing system 900 can include other components as described herein. The computing system 900 can also include a network interface device 908 that is communicatively coupled to a network 920. The computing system 900 can also include a video display unit 910 (e.g., a liquid crystal display (LCD)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a signal generation device 916 (e.g., a speaker), or other peripheral devices. Furthermore, the computing system 900 can include a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932. In another embodiment, the computing system 900 can include a chipset (not shown) that refers to a set of integrated circuits or chips that are designed to work with the processing device 902 and control communication between the processing device 902 and external devices. For example, the chipset can be a group of chips on a motherboard that links the processing device 902 to very high-speed devices such as main memory 904 and a graphics controller, and to lower-speed peripheral buses such as USB, PCI or ISA buses.

[0090] The data storage device 918 can include the computer-readable storage medium 924 on which is stored the instructions 926 embodying any one or more of the methodologies of functions described herein. The instructions 926 can also reside completely, or at least partially, within the main memory 904 and / or within the processing device 902 during execution thereof by the computing system 900, as processing logic; the main memory 904 and the processing device 902 also constituting computer-readable storage media.

[0091] The computer-readable storage medium 924 can also be used to store the instructions 926 utilized by the processing device 902, such as with respect to the Figure 1 ​The described) and / or containing a software library of methods invoking the above applications to store instructions 926. While the computer-readable storage medium 924 is shown in an example embodiment to be a single medium, the term "computer-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable storage medium" shall also be taken to include any medium that is capable of storing the set of instructions for execution by the machine and that causes the machine to perform any one or more of the methodologies of the present embodiments. The term "computer-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

[0092] In the description above various features are described which can be implemented in software, firmware, and / or hardware. For the sake of clarity, the numerous individual components

[0093] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware, such as a microcontroller, associated with a non-transitory medium to store code adapted to be executed by the microcontroller. Accordingly, in one implementation, a reference to a module refers to the hardware specifically configured to recognize and / or execute the code to be held on a non-transitory medium. Further, in another implementation, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another implementation, the term module (in this example) can refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are shown are quite clear, while in others, they are not. For example, a first and a second module can share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one implementation, use of the term logic can encompass hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0094] In one implementation, the use of the phrase 'configured to' refers to an arrangement, manufacture, making, and / or design of devices, hardware, logic, or elements, or placing them together or providing them for sale, to perform a specified or determined task. In this example, if its devices or elements are designed to perform a specified task, then it is 'configured to' perform that specified task, even if not operating. As a purely illustrative example, a logic gate can provide a 0 or 1 during operation. But a logic gate that is 'configured to' provide an enable signal to a clock does not include every potential logic gate that can provide a 1 or 0. Rather, it is the logic gate that is coupled in a certain way, such that the 1 or 0 output during operation will enable the clock. Again, note that the use of the term 'configured to' does not require operation, but rather focuses on the potential state of the devices, hardware, and / or elements, where in the potential state the devices, hardware, and / or elements are designed to perform a particular task when the devices, hardware, and / or elements are operating.

[0095] Further, in one implementation, the use of the phrases 'to', 'capable of', and / or 'operable to' refers to some devices, logic, hardware, and / or elements being designed such that the devices, logic, hardware, and / or elements are capable of being used in a prescribed manner. Note that, as described above, in one implementation, the use of 'to', 'capable of', and / or 'operable to' refers to the potential state of the devices, logic, hardware, and / or elements, where the devices, logic, hardware, and / or elements are not operating, but are designed such that the devices are capable of being used in a prescribed manner.

[0096] As used herein, a value includes a number, a state, a logic state, or any known representation of the result of a computation. Commonly, the use of a logic level, a logic value, or a value of logic is referred to as 1 and 0, which simply represent binary logic states. For example, 1 refers to a high logic level and 0 refers to a low logic level. In one implementation, a storage cell, such as a transistor or a flash cell, is capable of holding a single logic value or multiple logic values. However, other representations of values in computer systems have been used. For example, the decimal number 10 can also be represented as the binary value 1010 and the hexadecimal letter A. Thus, a value includes any representation of information capable of being saved in a computer system.

[0097] Some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, is conceived to be a self- consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0098] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as "receiving", "adjusting" or the like, refer to the actions and processes of a computing system, or similar electronic computing device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computing system's registers and memories into other data similarly represented as physical quantities within the computing system memories or registers or other such information storage, transmission or display devices.

[0099] The words "example" or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term "an embodiment" or "one embodiment" or "some embodiments" or the like throughout is not intended to mean the same embodiment or the same embodiments unless specifically so stated.

[0100] The embodiments described herein can also relate to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can comprise a general-purpose hardware that is selectively activated or reconfigured by firmware stored in the apparatus. Such firmware can be stored in a non-transitory computer-readable storage medium, such as, but not limited to, NVM, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, flash memory, or any type of media suitable for storing electronic instructions. The term "computer-readable storage medium" should be taken to include a single medium or multiple media that store a set of or multiple sets of instructions. The term "computer-readable medium" should also be taken to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a hardware processor and that causes the hardware processor to perform any one or more of the methodologies of the present embodiments. Therefore, the term "computer-readable storage medium" should be taken to include, but is not limited to, solid-state memories, optical media, magnetic media, any medium that is capable of storing a set of instructions for execution by a hardware processor, and any medium that is capable of storing, encoding or carrying a set of instructions for execution by a hardware processor and that causes the hardware processor to perform any one or more of the methodologies of the present embodiments.

[0101] The above description sets forth numerous specific details such as examples of specific systems, components, methods and so forth in order to provide a thorough understanding of several embodiments of the present disclosure. However, it will be apparent to one skilled in the art that at least some embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present disclosure. Thus, the specific details set forth above are merely exemplary. Particular embodiments can vary from these exemplary details and still be contemplated to be within the scope of the present disclosure.

[0102] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0103] In the description herein, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail, but rather in a block diagram format in order to avoid unnecessarily obscuring the understanding of the description.

[0104] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

Claims

1. A memory device, comprising: An array of memory cells in a non-volatile memory; as well as An input / output (I / O) buffer, coupled to the array, wherein the I / O buffer includes: The main pull-up transistor is coupled between the power supply and ground and to the data fast (DQ) output line; Multiple selectable pull-up transistors are coupled in parallel with the main pull-up transistor; and A logic device coupled to the plurality of selectable pull-up transistors, the logic device selecting a custom number of the plurality of selectable pull-up transistors based on process, voltage, and temperature (PVT) data associated with the memory device for use during transient periods of data transmission at the DQ output line.

2. The memory device according to claim 1, wherein, The I / O buffer includes a Low Power Double Data Rate (LPDDR) based interface, and wherein the selected custom number of the plurality of selectable pull-up transistors is in part based on the type of the LPDDR based interface.

3. The memory device of claim 1, further comprising a set of memory registers coupled to the I / O buffer and used for storing the PVT data, wherein, The main pull-up transistor includes a fixed number of pull-up transistors.

4. The memory device according to claim 1, wherein, The I / O buffer also includes a plurality of variable resistors, each variable resistor being coupled in series to the source of a corresponding pull-up transistor among the plurality of selectable pull-up transistors, wherein the logic device further adjusts the resistance of each variable resistor coupled to a selected custom number of the plurality of selectable pull-up transistors based on the PVT data.

5. The memory device according to claim 1, wherein, The PVT data includes one of the following: The value derived from the most recent ZQ calibration performed on the ZQ resistor, which is externally coupled to the ZQ pin of the memory device; or The most recently obtained value from one of the temperature detector, voltage detector, or ring oscillator located on the memory device.

6. The memory device according to claim 1, wherein, The logic device is also used for: A range of PVT values, indexed for the number of the plurality of selectable pull-up transistors, is stored in a data structure within a set of memory registers; and Based on the PVT data corresponding to the range of the PVT values, the custom number of the plurality of selectable pull-up transistors is selected.

7. The memory device according to claim 6, wherein, The logic device includes: A multiplexer, comprising a plurality of selectable pull-up transistors stored in the data structure as inputs, and including the most recent value of the PVT data as a selector; and The logic gate includes the output of the multiplexer and a line carrying the acceleration pulse applied during the transient period as input, and includes an output coupled to the gate of the plurality of selectable pull-up transistors.

8. The memory device according to claim 1, wherein, The logic device is also configured to store multiple ranges of PVT values ​​in each of multiple data structures, each range being indexed for a predetermined number of the multiple selectable pull-up transistors to be selected for a particular process inflection point.

9. A system comprising: Non-volatile memory device, comprising: An array of memory cells; and An input / output (I / O) buffer, coupled to the array, wherein the I / O buffer includes: The main pull-up transistor is coupled between the power supply and ground and to the data fast (DQ) output line; A plurality of selectable pull-up transistors coupled in parallel with the main pull-up transistor; and Logic devices, coupled to the plurality of selectable pull-up transistors, to select a custom number of the plurality of selectable pull-up transistors based on process, voltage, and temperature (PVT) data associated with the memory device for use during transient periods of data transmission at the DQ output line; and A host device, operatively coupled to the memory device, retrieves data from the array via the I / O buffer.

10. The system according to claim 9, wherein, The I / O buffer includes a Low Power Double Data Rate (LPDDR) based interface, and wherein the selected custom number of the plurality of selectable pull-up transistors is in part based on the type of the LPDDR based interface.

11. The system of claim 9, further comprising a set of memory registers coupled to the I / O buffer and storing the PVT data, wherein, The main pull-up transistor includes a fixed number of pull-up transistors.

12. The system according to claim 9, wherein, The I / O buffer also includes a plurality of variable resistors, each variable resistor being coupled in series to the source of a corresponding pull-up transistor among the plurality of selectable pull-up transistors, wherein the logic device further adjusts the resistance of each variable resistor coupled to a selected custom number of the plurality of selectable pull-up transistors based on the PVT data.

13. The system according to claim 9, wherein, The PVT data includes one of the following: The value derived from the most recent ZQ calibration performed on the ZQ resistor, which is externally coupled to the ZQ pin of the memory device; or The most recently obtained value from one of the temperature detector, voltage detector, or ring oscillator located on the memory device.

14. The system according to claim 9, wherein, The logic device is also used for: A range of PVT values, indexed for the number of the plurality of selectable pull-up transistors, is stored in a data structure within a set of memory registers; and Based on the PVT data corresponding to the range of the PVT values, the custom number of the plurality of selectable pull-up transistors is selected.

15. The system according to claim 14, wherein, The logic device includes: A multiplexer includes a different number of selectable pull-up transistors stored in the data structure as inputs, and includes the most recent value of the PVT data as a selector; and The logic gate includes the output of the multiplexer and a line carrying the acceleration pulse applied during the transient period as input, and includes an output coupled to the gate of the plurality of selectable pull-up transistors.

16. The system according to claim 9, wherein, The logic device is also configured to store multiple ranges of PVT values ​​in each of the multiple data structures, each range value being indexed for a predetermined number of the multiple selectable pull-up transistors to be selected for a particular process inflection point.

17. A memory device, comprising: An array of memory cells in a non-volatile memory; as well as An input / output (I / O) buffer, coupled to the array, wherein the I / O buffer includes: Pull-up transistor array, coupled between power supply and ground and coupled to the data fast (DQ) output line; Voltage regulator, used to generate bias voltage; and A logic device coupled to the pull-up transistor group and the voltage regulator, the logic device selectively applying the bias voltage to the substrate of the pull-up transistor group based on process, voltage, and temperature (PVT) data associated with the memory device for use during transient periods of data transmission at the DQ output line.

18. The memory device according to claim 17, wherein, The I / O buffer includes an interface based on Low Power Double Data Rate (LPDDR), and the memory device further includes a set of memory registers coupled to the I / O buffer for storing the PVT data.

19. The memory device according to claim 17, wherein, The logic device is also used to set the bias voltage of the voltage regulator based on the current value of the PVT data.

20. The memory device according to claim 17, wherein, The logic device is also used for: It was determined that the PVT value of the PVT data failed to meet the threshold; and In order to selectively apply the bias voltage, the logic device is used to apply a positive bias voltage, which causes the threshold voltage of the pull-up transistors in the pull-up transistor group to decrease.

21. The memory device according to claim 17, wherein, The IO buffer also includes multiple variable resistors, each of which is connected in series to the source of a corresponding pull-up transistor in the pull-up transistor group, and wherein the logic device further adjusts the resistance of each variable resistor based on the PVT data.

22. The memory device according to claim 17, wherein, The PVT data is the ZQ value derived from the most recent ZQ calibration performed from the ZQ resistor coupled externally to the ZQ pin of the memory device, and wherein the logic device is further configured to: Before selectively applying the bias voltage, a fixed number of transistors are selected from the pull-up transistor group based on the ZQ value; After applying the bias voltage, the ZQ calibration is rerun to generate a new ZQ value; and Based on the new ZQ value, an updated fixed number of transistors are selected from the pull-up transistor group.

23. The memory device according to claim 22, wherein, The logic device is also used for: The simulation or characterization of the operation of the pull-up transistor group during the data transient period determines that the updated fixed number of transistors provides a body transistor threshold voltage insufficient to achieve a predetermined slope for the data transient; and Reduce or eliminate the bias voltage applied to the substrate of the transistor array.

24. The memory device according to claim 22, wherein, The logic device is also used to store the value of the bias voltage and the new ZQ value into a set of memory registers included in or coupled to the I / O buffer.

25. The memory device according to claim 22, wherein, The logic device is also used for: Based on the ZQ value, adjust the gate voltage of the pull-up transistor group; and Based on the adjusted gate voltage, a fixed number of transistors in the pull-up transistor group are selected.

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