Memory

Abstract

The invention provides a memory which at least comprises a storage structure and a control structure, bit lines in the storage structure extend in a first direction, word lines in the storage structure extend in a second direction, the storage structure and the control structure are stacked in a third direction, and the third direction is perpendicular to the first direction and the second direction; bit lines in the storage structures are electrically connected with the control structure through bit line contact structures, and the bit line contact structures contained in the same storage structure are located in a first contact area, a second contact area and a third contact area of the storage structure. The first contact area, the second contact area and the third contact area are sequentially arranged in the first direction and extend in the second direction.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and in particular, to a memory. BACKGROUND

[0002] The memory controls reading, writing and refreshing of data through word lines and bit lines. In the process of reading data, a sense amplifier needs to amplify the read data based on the voltage difference between a target bit line and a complementary bit line, so as to effectively obtain the data stored in the memory cell; wherein the target bit line refers to the bit line connected to the memory cell corresponding to the activated word line.

[0003] It can be understood that the voltage difference between the target bit line and the complementary bit line will have a great influence on data amplification. When the voltage difference between the target bit line and the complementary bit line is less than the minimum voltage difference required for data amplification by the sense amplifier, the amplified data may be incorrect. SUMMARY

[0004] Embodiments of the present application provide a memory, which is at least beneficial to reduce the routing pressure of the conductive layer in which the word line or the bit line is located.

[0005] According to some embodiments of the present application, a memory is provided, comprising: a storage structure and a control structure, the bit lines in the storage structure extend along a first direction, the word lines extend along a second direction, the storage structure and the control structure are stacked along a third direction, the third direction is perpendicular to the first direction and the second direction; the bit lines in the storage structure are electrically connected to the control structure through bit line contact structures, the bit line contact structures contained in the same storage structure are located in a first contact area, a second contact area and a third contact area of the storage structure, the first contact area, the second contact area and the third contact area are arranged in sequence along the first direction and extend along the second direction.

[0006] In some embodiments, the number of tracks in which the bit line contact structures corresponding to each of the first contact area, the second contact area and the third contact area are located is less than or equal to half of the number of the corresponding bit lines.

[0007] In some embodiments, the number of tracks in which the bit line contact structures corresponding to part of the first contact area, the second contact area and the third contact area are located is less than half of the number of the corresponding bit lines.

[0008] In some embodiments, the memory structure comprises a first memory array and a second memory array located on opposite sides of the control structure in the third direction, the control structure is configured to control the first memory array and the second memory array, the number of lines in which the bit line contact structures of each region are located in the first memory array or the second memory array is less than or equal to half of the number of bit lines arranged in the second direction.

[0009] In some embodiments, the projections of the bit line contact structures corresponding to the first memory array and the bit line contact structures corresponding to the second memory array in the third direction coincide.

[0010] In some embodiments, two bit line contact structures in the same region and located adjacent in the second direction are misaligned in the first direction.

[0011] In some embodiments, each of the memory arrays comprises a first bit line region and a second bit line region arranged in the first direction, a plurality of bit lines arranged in the second direction are provided in the first bit line region and the second bit line region, at odd positions, the bit lines of the first bit line region and the bit lines of the second bit line region in the first memory array are connected, and the bit lines of the first bit line region and the bit lines of the second bit line region in the second memory array are connected, at even positions, the bit lines of the first bit line region in the first memory array are connected with the bit lines of the first bit line region in the second memory array, and the bit lines of the second bit line region in the first memory array are connected with the bit lines of the second bit line region in the second memory array.

[0012] In some embodiments, the projections of the bit line contact structures corresponding to the bit lines adjacent to the odd positions in the third direction are in different regions, and the projections of the bit line contact structures corresponding to the bit lines adjacent to the even positions in the third direction are in different regions.

[0013] In some embodiments, at some even positions, the bit lines of the first bit line region in the first memory array are connected with the bit lines of the first bit line region in the second memory array to form target bit lines, and the bit lines of the second bit line region in the first memory array are connected with the bit lines of the second bit line region in the second memory array to form complementary bit lines.

[0014] In some embodiments, the memory further comprises: in the first direction, a third storage array and a fourth storage array located on opposite sides of the first storage array, a fifth storage array and a sixth storage array located on opposite sides of the second storage array, a projection of the third storage array and the fifth storage array in the third direction at least partially overlaps, a projection of the fourth storage array in the third direction at least partially overlaps, in the partial even positions, a bit line of a first bit line region in the first storage array and a bit line of a first bit line region in the second storage array are connected, a bit line of a second bit line region in the first storage array and a bit line of a second bit line region in the fifth storage array are connected, the bit line of the first bit line region in the first storage array and the bit line of the second bit line region in the third storage array are mutually referenced, a bit line of a second bit line region in the first storage array and a bit line of a second bit line region in the second storage array are connected, a bit line of a first bit line region in the fourth storage array and a bit line of a first bit line region in the sixth storage array are connected, the bit line of the second bit line region in the first storage array and the bit line of the first bit line region in the fourth storage array are mutually referenced.

[0015] The technical scheme provided by the embodiments of the present application has at least the following advantages:

[0016] By controlling the bit line contact structure BLC electrically connected with the bit line BL to be in three different regions of the storage structure AR, the number of bit line contact structures BLC in each region and the number of required wirings for connecting the bit line contact structures BLC in the same region are reduced, thereby reducing the wiring density requirement and the wiring number requirement of another wiring layer connected with the bit line, and facilitating to increase the wiring width and the wiring spacing of another wiring layer while ensuring that the wiring density meets the actual requirement. BRIEF DESCRIPTION OF DRAWINGS

[0017] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the present embodiments, unless otherwise specified, the figures in the drawings do not constitute a proportional limitation.

[0018] Figure 1 The structural diagram of the memory provided by some embodiments of the present application is shown in the figure;

[0019] Figure 2 The structural diagram of the memory in another embodiment of the present application is shown in the figure;

[0020] Figure 3 For Figure 2 The top view of the structural diagram shown in the figure. DETAILED DESCRIPTION

[0021] The embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0022] Figure 1 The structural schematic diagram of the memory provided in the embodiments of the present application.

[0023] With reference to Figure 1 The memory comprises a storage structure AR and a control structure CMC, bit lines BL in the storage structure AR extend along a first direction X, word lines (not shown) extend along a second direction Y, the storage structure AR and the control structure CMC are stacked along a third direction Z, and the third direction Z is perpendicular to the first direction X and the second direction Y; the bit lines in the storage structure AR are electrically connected with the control structure CMC through bit line contact structures BLC, and the bit line contact structures BLC included in the same storage structure AR are located in a first contact area R1, a second contact area R2 and a third contact area R3 of the storage structure AR, and the first contact area R1, the second contact area R2 and the third contact area R3 are arranged in sequence along the first direction X and all extend along the second direction Y.

[0024] In the embodiments of the present application, by controlling the bit line contact structures BLC electrically connected with the bit lines BL to be located in three different areas of the storage structure AR, the number of the bit line contact structures BLC in each area and the number of the required wires for connecting the bit line contact structures BLC in the same area are reduced, so as to reduce the wire density requirement and the number requirement of the wires of another wire layer connected with the bit lines, and to ensure that the wire density meets the actual requirement while increasing the wire width and the wire spacing of the another wire layer.

[0025] The embodiments of the present application will be described in detail below with reference to the drawings.

[0026] In some embodiments, a memory structure AR may include one or more memory arrays. When the memory structure AR includes multiple memory arrays, the multiple memory arrays are stacked with the control structure CMC along a third direction Z, and at least one of the memory arrays includes a bit line contact structure (BLC) simultaneously located in a first contact region R1, a second contact region R2, and a third contact region R3 of the memory structure AR. The multiple memory arrays may be located on the same side of the control structure CMC or on opposite sides of the control structure CMC. In still other embodiments, the bit line contact structure (BLC) included in each memory array of the memory structure AR is simultaneously located in the first contact region R1, the second contact region R2, and the third contact region R3 of the memory structure AR. In yet other embodiments, a memory structure AR includes only one memory array, which itself serves as the memory structure.

[0027] When the memory structure AR contains one or more memory arrays, the control structure may contain one or more control arrays. Each memory array and each control array resides on an independent wafer, and the memory arrays and control arrays are electrically connected via bonding structures. One or more memory arrays and one or more control arrays are stacked in a third-direction Z-axis, with the specific stacking order depending on actual needs. When the control structure contains only one control array, the control array itself constitutes the control structure.

[0028] For example, in Figure 1 In the illustrated embodiment, the memory structure AR includes a first memory array A1 and a second memory array A2, which are located on different wafers / chips. The control structure CMC contains only one control array, located on a separate wafer / chip independent of the memory structure AR. The first memory array A1 and the second memory array A2 are located on opposite sides of the control structure CMC in the third direction Z, and both the first memory array A1 and the second memory array A2 are controlled by the control structure CMC. The bit line bonding structure HP electrically connected to the first memory array A1 and the control structure CMC is located on the first surface of the control structure CMC, and the bit line bonding structure HP electrically connected to the second memory array A2 and the control structure CMC is located on the second surface of the control structure CMC.

[0029] It should be noted that the bit line bonding structure HP can be directly or indirectly connected to the bit line. This application does not limit this connection; it is merely used to specify that the voltage signal received by the bit line bonding structure HP originates from the bit line BL. During voltage signal transmission, phase inversion and other processing can be performed. In the embodiments of this application, the bit line bonding structure HP is directly connected to the bit line through multiple conductive layers and multiple contact structures to directly receive the voltage signal on the bit line BL.

[0030] In some embodiments, in the third direction Z, the orthographic projection of each bit line contact structure BLC in each storage array coincides with the orthographic projection of the corresponding bit line bonding structure HP; in other embodiments, in the third direction Z, the orthographic projection of different bit line contact structures BLC coincides with the orthographic projection of the corresponding bit line bonding structure HP in terms of the direction and distance of the connecting line, i.e., the orthographic projection of the plurality of bit line contact structures BLC coincides with the orthographic projection of the plurality of bit line bonding structures HP after translation. In some embodiments, the bit line contact structure BLC is directly connected to the bit line and directly connected to the first interconnection layer, and is electrically connected to the corresponding bit line bonding structure HP through the first interconnection layer and other conductive layers.

[0031] It can be understood that when the orthographic projection of the bit line contact structure BLC coincides with the orthographic projection of the corresponding bit line bonding structure HP or the deviation is within an allowable range, the first positional relationship of the bit line contact structure BLC with the above three contact regions is the same as the second positional relationship of the orthographic projection of the bit line bonding structure HP in the third direction Z with the above three contact regions. At this time, the orthographic projection of the bit line bonding structure HP corresponding to the first storage array A1 and the orthographic projection of the bit line bonding structure HP corresponding to the second storage array A2 are both located in the first contact region R1, the second contact region R2 and the third contact region R3 of the storage structure AR at the same time.

[0032] In addition, in some embodiments, in the third direction Z, the orthographic projection of the bit line bonding structures HP electrically connected by the bit lines at the same position in different storage arrays (for example, the first storage array A1 and the second storage array A2) at least partially coincides. In this way, it is beneficial to shorten the distance between different bonding structures HP electrically connected through the control structure CMC, or to shorten the distance between different bonding structures HP connected to the sense amplifier inside the control structure CMC, thereby improving the performance of the memory. Further, the orthographic projection of the bit line contact structures BLC electrically connected by the bit lines at the same position in different storage arrays coincides.

[0033] In other embodiments, the wiring manner of the bit lines BL in the first storage array A1 and the second storage array A2 can be the same, and accordingly, in the third direction Z, the orthographic projection of the bit line contact structure BLC corresponding to the first storage array A1 and the orthographic projection of the plurality of bit line contact structures BLC contained in the second storage array A2 can be a coinciding relationship or a translation relationship. The translation relationship means that after translation in the first direction X and / or the second direction Y, the orthographic projection of the plurality of bit line contact structures BLC contained in the first storage array A1 can coincide with the orthographic projection of the plurality of bit line contact structures BLC contained in the second storage array A2.

[0034] The first contact region R1, the second contact region R2 and the third contact region R3 can be rectangular regions with spacing between each other, and the widths of the three regions in the first direction X are equal, and the regions are staggered in the first direction X and coincide in the second direction Y. Alternatively, there can be no gap between the first contact region R1, the second contact region R2 and the third contact region R3, that is, the region where the storage structure AR is located can be divided into three parts in the first direction X to form the first contact region R1, the second contact region R2 and the third contact region R3. Alternatively, the region where the storage structure AR is located can be divided into five parts in the first direction X, and then the first part, the third part and the fifth part are used as the first contact region R1, the second contact region R2 and the third contact region R3. At this time, the first contact region R1, the second contact region R2 and the third contact region R3 have spacing between each other, and the width of the spacing between adjacent regions in the first direction X is equal to the width of each region.

[0035] It should be noted that no matter how the region is divided, the first contact region R1 always contains one side of the storage structure AR in the first direction X, the third contact region R3 always contains the other side of the storage structure AR in the first direction X, and the second contact region R2 always has the same symmetry axis in the first direction X as the storage structure AR.

[0036] In some embodiments, the number of lines of the bit line contact structure BLC corresponding to each of the first contact region, the second contact region and the third contact region is less than or equal to half of the number of corresponding bit lines. In this way, it is beneficial to reduce the number of lines and the line density of the first interconnection layer connected by the bit line contact structure BLC, so that the first interconnection layer can have a larger line spacing and a larger line width, thereby reducing the unit length resistance of the wire in the first interconnection layer while ensuring that the number of wires in the first interconnection layer is sufficient.

[0037] It should be noted that in the case of increasing the lateral width of the line / wire, the vertical height of the line / wire can be effectively increased, otherwise the process defects will be caused due to the increase of the aspect ratio, so that the performance of the wire is not as expected. In other words, by increasing the line spacing of the first interconnection layer, it is beneficial to increase the cross-sectional area of the wire in the first interconnection layer and reduce the unit length resistance of the wire.

[0038] In this context, a "track" can be understood as an ideal or predetermined path of unlimited length. Tracks can have bends, but the main part of a track is usually a straight line. Under ideal conditions, different tracks on the same conductive layer can be considered as different parallel straight lines extending in the same direction. During signal transmission, each conductive layer contains multiple traces. A single trace may reside in only one track or multiple tracks. The arrangement of tracks defines the cross-sectional area of ​​the traces (including lateral width and vertical height) and the spacing between adjacent traces, ensuring that the resistance per unit length of the trace meets requirements and reducing signal crosstalk between adjacent traces. Tracks on different conductive layers can have different lateral widths and spacing. Spacing refers to the distance between the center lines of one track and the center lines of another track along the track arrangement direction.

[0039] In the conductor layer where the bit line BL is located, if the bit line BL is a straight line of finite length, then each bit line BL can be considered to be in a trace, and the cross-sectional area of ​​the trace is the cross-sectional area of ​​the bit line. At the same time, different bit lines BL arranged along the extension direction of the trace can be in the same trace. In some embodiments, the trace density in the first interconnect layer is half of the trace density in the bit line conductive layer (equivalent to the trace spacing in the first interconnect layer being twice the trace spacing in the bit line conductive layer). The trace width in the first interconnect layer can be greater than the width of the bit line, or even greater than twice the width of the bit line. The orthographic projection of a trace in the first interconnect layer in the third direction Z coincides with the orthographic projection of each of the two adjacent bit lines.

[0040] For example in Figure 1 In the illustrated embodiment, the first memory structure A1 includes eight bit lines. A first target bit line BLA1 is located on the first bit line track; a second target bit line BLA2 and a second complementary bit line BLB2 are located on the second bit line track; a third target bit line BLA3 is located on the third bit line track; a fourth target bit line BLA4 and a fifth target bit line BLA5 are located on the fourth bit line track; a sixth target bit line BLA6 is located on the fifth bit line track; a seventh target bit line BLA7 and a seventh complementary bit line BLB7 are located on the sixth bit line track; an eighth target bit line BLA8 is located on the seventh bit line track; and a ninth target bit line BLA9 and a tenth target bit line BLA10 are located on the eighth bit line track. The orthogonal projection of two tracks in the bit line conductive layer onto the third direction Z can fall into the orthogonal projection of one track in the first interconnect layer, or both can coincide with the corresponding track portions in the first interconnect layer. For example, the orthographic projections of the first bit line track and the second bit line track fall into the orthographic projection of the first track in the first interconnect layer, or the orthographic projection of the first bit line track falls into the orthographic projection of the first track in the first interconnect layer, and the orthographic projections of the second bit line track and the third bit line track fall into the orthographic projection of the second track in the first interconnect layer.

[0041] In some embodiments, the number of tracks where the bit line contact structures BLC in the first contact region R1, the second contact region R2 and the third contact region R3 are located is less than half of the number of the corresponding bit lines, and the number of tracks where the bit line contact structures BLC in the remaining regions are located is equal to half of the number of the corresponding bit lines. It can be understood that as long as the number of tracks where the bit line contact structures BLC in any region are located is not greater than half of the number of the corresponding bit lines, the number of tracks of the first interconnection layer corresponding to different regions can be equal, for example, the number of tracks of the first interconnection layer is half of the number of tracks of the bit line conductive layer or is one more than the number of tracks of the bit line conductive layer, so as to ensure the reasonable arrangement of the tracks in the first interconnection layer.

[0042] In some embodiments, referring to Figure 1 , the number of tracks where the bit line contact structures BLC in each region of the first storage array A1 and the second storage array A2 are located is less than or equal to half of the number of the bit lines arranged in the second direction Y. For example, in the first contact region R1 and the third contact region R3, the number of tracks where the bit line contact structures BLC are located is 3; in the second contact region R2, the number of tracks where the bit line contact structures BLC are located is 4, wherein the two bit line contact structures BLC corresponding to the second target bit line BLA2 and the second complementary bit line BLB2 are located in the same track, and the two bit line contact structures BLC corresponding to the seventh target bit line BLA7 and the seventh complementary bit line BLB7 are located in the same track. At this time, the tracks corresponding to the second target bit line BLA2 and the second complementary bit line BLB2 in the second contact region R2 can be provided with two segments of independent traces in the same track, and different traces are connected to different bit line contact structures BLC for inputting or outputting voltage signals in the bit line BL, and the tracks corresponding to the seventh target bit line BLA7 and the seventh complementary bit line BLB7 in the second contact region R2 are the same, which will not be described here.

[0043] Similarly, in some embodiments, the number of tracks where the bit line bonding structures corresponding to the first contact region R1, the second contact region R2 and the third contact region R3 are located is less than half of the number of the corresponding bit lines, and the number of tracks where the bit line bonding structures HP in the remaining regions are located is equal to half of the number of the corresponding bit lines.

[0044] In some embodiments, for two bit line contact structures BLC adjacent in the second direction Y and in the same region, the bit line contact structures BLC are staggered in the first direction X. In this way, the distance between any two bit line contact structures BLC is increased, and signal crosstalk between the bit line contact structures is reduced. In some embodiments, each memory array includes a first bit line region and a second bit line region arranged along the first direction X, and a plurality of bit lines arranged along the second direction Y are arranged in the first bit line region and the second bit line region. In odd positions, the bit lines of the first bit line region and the bit lines of the second bit line region in the first memory array are connected, and the bit lines of the first bit line region and the bit lines of the second bit line region in the second memory array are connected. In even positions, the bit lines of the first bit line region in the first memory array and the bit lines of the first bit line region in the second memory array are connected, and the bit lines of the second bit line region in the first memory array and the bit lines of the second bit line region in the second memory array are connected.

[0045] In Figure 1 In the embodiment shown, the first memory array A1 and the second memory array A2 are composed of a first bit line region RG1 and a second bit line region RG2 arranged along the first direction X, the first bit line region RG1 and the second bit line region RG2 are equal in area and are rectangular, and a plurality of bit lines BL arranged along the second direction Y are arranged in the first bit line region RG1 and the second bit line region RG2. The bit lines BL include a target bit line BLA and a complementary bit line BLB having a reference relationship with each other, and the target bit line BLA and the complementary bit line BLB are both a kind of bit lines BL, and only different names are taken to emphasize the complementary relationship. Figure 1 In the embodiment shown, eight bit lines BL arranged along the second direction Y are arranged in the first bit line region RG1 and the second bit line region RG2. It can be understood that four of the eight bit lines BL are in odd positions, and the other four are in even positions, and the bit lines BL in odd positions and the bit lines BL in even positions are arranged alternately. In the direction toward the paper, the first bit line (i.e., the first target bit line BLA1 and the first complementary bit line BLB1) is in the first odd position.

[0046] Specifically, in the first storage array A1, at the first odd position, the bit lines of the first bit line region RG1 and the second bit line region RG2 are connected to form the first target bit line BLA1; at the second odd position, the bit lines of the first bit line region RG1 and the second bit line region RG2 are connected to form the third target bit line BLA3; at the third odd position, the bit lines of the first bit line region RG1 and the second bit line region RG2 are connected to form the sixth target bit line BLA6; at the fourth odd position, the bit lines of the first bit line region RG1 and the second bit line region RG2 are connected to form the eighth target bit line BLA8. Correspondingly, at the first odd position to the fourth odd position of the second storage array A2, the bit lines of the first bit line region RG1 and the second bit line region RG2 are connected to form the first complementary bit line BLB1, the third complementary bit line BLB3, the sixth complementary bit line BLB6 and the eighth complementary bit line BLB8, respectively.

[0047] In addition, in the first bit line region RG1 of the first storage array A1 and the second storage array A2, at the first even position, the bit line of the first storage array A1 and the bit line of the second storage array A2 are connected to form the second target bit line BLA2; at the second even position, the bit line of the first storage array A1 and the bit line of the second storage array A2 are connected to form the fourth target bit line BLA4; at the third even position, the bit line of the first storage array A1 and the bit line of the second storage array A2 are connected to form the seventh target bit line BLA7; at the fourth even position, the bit line of the first storage array A1 and the bit line of the second storage array A2 are connected to form the ninth target bit line BLA9. Correspondingly, in the second bit line region RG1 of the first storage array A1 and the second storage array A2, at the first even position to the fourth even position, the bit line of the first storage array A1 and the bit line of the second storage array A2 are connected to form the second complementary bit line BLB2, the fifth target bit line BLA5, the seventh complementary bit line BLB7 and the tenth target bit line BLA10, respectively.

[0048] It can be understood that the positions of the target bit line BLA and the complementary bit line BLB are equal, and the present application only emphasizes that the mth target bit line BLA and the mth complementary bit line BLB are in a reference relationship with each other, m is a positive integer, and the two bit lines BL (i.e. the target bit line BLA and the complementary bit line BLB) connected to the same sense amplifier and performing sense amplification are in a reference relationship with each other. In the actual read-write operation process, one of the target bit line BLA and the complementary bit line BLB is connected to the bit line corresponding to the activated word line, and the voltage changes in the charge sharing stage, and the other one is a reference bit line, and the voltage does not change in the charge sharing stage.

[0049] In some embodiments, the projections of the bit line bonding structures corresponding to adjacent odd-numbered bit lines in the third direction are in different regions, and the projections of the bit line bonding structures corresponding to adjacent even-numbered bit lines in the third direction are in different regions. These different regions refer to two different regions among the first contact region R1, the second contact region R2, and the third contact region R3. This arrangement helps avoid the concentration of bit line contact structures (BLCs) corresponding to three consecutive bit lines in the same region. This allows different bit line contact structures (BLCs) to be electrically connected to different conductors in the first interconnect layer, even when the conductors in each region of the first interconnect layer are straight, enabling independent signal input or output. In other words, it reduces the routing difficulty in the first interconnect layer, improves the regularity of the routing, and ensures that the routing lengths of different bit line contact structures (BLCs) in the first interconnect layer remain consistent, balancing the parasitic resistance and capacitance of the connections between different bit lines and their corresponding bit line bonding structures.

[0050] Specifically, in Figure 1 In the illustrated embodiment, regarding bit lines at odd-numbered positions, the bit line contact structure BLC corresponding to the first target bit line BLA1, the first complementary bit line BLB1, the sixth target bit line BLA6, and the sixth complementary bit line BLB6 is located in the second contact region R2; the bit line contact structure BLC corresponding to the third target bit line BLA3 and the third complementary bit line BLB3 is located in the first contact region R1; and the bit line contact structure BLC corresponding to the eighth target bit line BLA8 and the eighth complementary bit line BLB8 is located in the third contact region R3. Regarding bit lines at even-numbered positions, the bit line contact structure BLC corresponding to the second target bit line BLA2, the second complementary bit line BLB2, the seventh target bit line BLA7, and the seventh complementary bit line BLB7 is located in the second contact region R2; the bit line contact structure BLC corresponding to the fourth target bit line BLA4 and the ninth target bit line BLA9 is located in the first contact region R1; and the bit line contact structure BLC corresponding to the fifth target bit line BLA5 and the tenth target bit line BLA10 is located in the third contact region R3.

[0051] In some embodiments, at a subset of even-numbered locations, bit lines of the first bit line region in the first memory array and bit lines of the second bit line region in the second memory array are connected to form a target bit line, and bit lines of the second bit line region in the first memory array and bit lines of the second bit line region in the second memory array are connected to form a complementary bit line. In this embodiment, in the first memory array and the second memory array, at a subset of even-numbered locations, the bit lines of the first bit line region and the bit lines of the second bit line region are mutually referenced, while at another subset of even-numbered locations, the bit lines of the first bit line region and the bit lines of the second bit line region are not mutually referenced, and their reference bit lines are also different.

[0052] Specifically, in Figure 1In the shown embodiment, in the first even position and the third even position, the bit lines of the first bit line region RG1 and the bit lines of the second bit line region RG2 in the first storage array A1 are reference to each other, and the bit lines of the first bit line region RG1 and the bit lines of the second bit line region RG2 in the second storage array A2 are reference to each other. Specifically, in the first even position, the second target bit line BLA2 and the second complementary bit line BLB2 are reference to each other, and in the third even position, the seventh target bit line BLA7 and the seventh complementary bit line BLB7 are reference to each other.

[0053] Further, in the shown embodiment, in the second even position and the fourth even position, the bit lines of the first bit line region RG1 and the bit lines of the second bit line region RG2 in the first storage array A1 are independent of each other, and are not in reference to each other, and the bit lines of the first bit line region RG1 and the bit lines of the second bit line region RG2 in the second storage array A2 are independent of each other, and are not in reference to each other. Specifically, in the second even position, the fourth target bit line BLA4 and the fifth target bit line BLA5 are not in reference to each other, and in the fourth even position, the ninth target bit line BLA9 and the tenth target bit line BLA10 are not in reference to each other. Figure 1

[0054] In some embodiments, in the same storage array, if the bit lines of the first bit line region RG1 and the bit lines of the second bit line region RG2 are independent of each other in a certain even position, then in the even position, the bit line contact structures BLC corresponding to the bit lines of the first bit line region RG1 are located in the first contact region R1, and the bit line contact structures BLC corresponding to the bit lines of the second bit line region RG2 are located in the third contact region R3, i.e., the bit line contact structures BLC corresponding to the bit lines of the first bit line region RG1 and the bit lines of the second bit line region RG2 are arranged in the edge region, i.e., the first contact region R1 and the third contact region R3; if the bit lines of the first bit line region and the bit lines of the second bit line region are reference to each other in a certain even position, then in the even position, the bit line contact structures BLC corresponding to the bit lines of the first bit line region and the bit lines of the second bit line region are both in the middle region, i.e., the second contact region R2. By arranging the bit line contact structures BLC corresponding to the different bit lines that are reference to each other in the same region, the distance between the different bit lines that are reference to each other and the corresponding sense amplifiers is shortened, and the distance between the different bit lines that are reference to each other and the corresponding sense amplifiers is relatively short. By arranging the bit line contact structures BLC corresponding to the different bit lines that are not reference to each other in the edge region, while realizing that the bit lines in the current storage structure and the bit lines in other storage structures are reference to each other, the distance between the different bit lines that are reference to each other and the corresponding sense amplifiers is shortened.

[0055] ​It can be understood that different bit lines connected to each other refer to the same sense amplifier, and different bit lines independent of each other are connected to different sense amplifiers. For two bit lines independent of each other in the same even position, they can form a mutual reference relationship with the bit lines in the adjacent storage structure, or they can be used as redundant bit lines or idle bit lines. The redundant bit lines play a repairing role, and the idle bit lines play a role in simplifying the process and balancing the regional stress.

[0056] In Figure 1 In the embodiment shown in the figure, in the first even position and the third even position, the bit line bonding structures corresponding to the second target bit line BLA2 and the second complementary bit line BLB2 connected to each other are both in the second contact area R2, the bit line bonding structures corresponding to the seventh target bit line BLA7 and the seventh complementary bit line BLB connected to each other are both in the second contact area R2, the bit line bonding structures corresponding to the fourth target bit line BLA4 and the fifth target bit line BLA5 independent of each other are respectively in the first contact area R1 and the third contact area R3, and the bit line bonding structures corresponding to the ninth target bit line BLA9 and the tenth target bit line BLA10 independent of each other are respectively in the first contact area R1 and the third contact area R3.

[0057] In other embodiments, the bit line bonding structures corresponding to the two bit lines connected to each other can also be located in adjacent regions to improve the flexibility of the layout design of the control structure.

[0058] In some embodiments, Figure 2 Structure diagram of the memory in some other embodiments of the present application; Figure 3 Structure diagram of the memory in some other embodiments of the present application; Figure 2 The top view of the structure diagram shown in the figure. Referring to Figure 2 and Figure 3The memory further comprises: in the first direction X, a third storage array A3 and a fourth storage array A4 located on opposite sides of the first storage array Al, a fifth storage array A5 and a sixth storage array A6 located on opposite sides of the second storage array A2, projections of the third storage array A3 and the fifth storage array A5 in the third direction Z at least partially overlap, projections of the fourth storage array A4 and the sixth storage array A6 in the third direction Z at least partially overlap, in the partial even positions, the bit lines of the first bit line region RG1 in the first storage array Al and the bit lines of the first bit line region RG1 in the second storage array A2 are connected, the bit lines of the second bit line region RG2 in the third storage array A3 and the bit lines of the second bit line region RG2 in the fifth storage array A5 are connected, the bit lines of the first bit line region RG1 in the first storage array Al and the bit lines of the second bit line region RG2 in the third storage array A3 are references to each other, the bit lines of the second bit line region RG2 in the first storage array Al and the bit lines of the second bit line region RG2 in the second storage array A2 are connected, the bit lines of the first bit line region RG1 in the fourth storage array A4 and the bit lines of the first bit line region RG1 in the sixth storage array A6 are connected, the bit lines of the second bit line region RG2 in the first storage array Al and the bit lines of the second bit line region RG1 in the fourth storage array A4 are references to each other.

[0059] Specifically, in the second even position, the bit lines of the first bit line region RG1 in the first storage array Al and the bit lines of the first bit line region RG1 in the second storage array A2 are connected to form a fourth target bit line BLA4, the bit lines of the second bit line region RG2 in the third storage array A3 and the bit lines of the second bit line region RG2 in the fifth storage array A5 are connected to form a fourth complementary bit line BLB4, the fourth target bit line BLA4 and the fourth complementary bit line BLB4 are references to each other; in the second even position, the bit lines of the second bit line region RG2 in the first storage array Al and the bit lines of the second bit line region RG2 in the second storage array A2 are connected to form a fifth target bit line BLA5, the bit lines of the first bit line region RG1 in the fourth storage array A4 and the bit lines of the first bit line region RG1 in the sixth storage array A6 form a fifth complementary bit line BLB5, the fifth target bit line BLA5 and the fifth complementary bit line BLB5 are references to each other.

[0060] In the fourth even position, the bit lines of the first bit line region RG1 in the first storage array Al are connected with the bit lines of the first bit line region RG1 in the second storage array A2 to form a ninth target bit line BLA9, the bit lines of the second bit line region RG2 in the third storage array A3 are connected with the bit lines of the second bit line region RG2 in the fifth storage array A5 to form a ninth complementary bit line BLB9, the ninth target bit line BLA9 and the ninth complementary bit line BLB9 are referenced to each other; likewise, in the fourth even position, the bit lines of the second bit line region RG2 in the first storage array Al are connected with the bit lines of the second bit line region RG2 in the second storage array A2 to form a tenth target bit line BLA10, the bit lines of the first bit line region RG1 in the fourth storage array A4 and the bit lines of the first bit line region RG1 in the sixth storage array A6 form a tenth complementary bit line BLB10, the tenth target bit line BLA10 and the tenth complementary bit line BLB10 are referenced to each other.

[0061] In Figure 2 In the embodiment shown, the first storage array Al and the second storage array A2 correspond to the first control structure Cl and are located on opposite sides of the first control structure Cl in the third direction Z, the third storage array A3 and the fifth storage array A5 correspond to the second control structure C2 and are located on opposite sides of the second control structure C2 in the third direction Z, and the fourth storage array A4 and the sixth storage array A6 correspond to the third control structure C3 and are located on opposite sides of the third control structure C3 in the third direction Z. The bit line connection rule inside the third storage array A3 and the fourth storage array A4 can be the same as that of the first storage array Al, and the positions of the bit line contact structures connected by the third storage array A3 and the fourth storage array A4 on the corresponding storage structure can be the same as those of the bit line contact structures connected by the first storage array Al on the corresponding storage structure.

[0062] In Figure 2 In the embodiment shown, the first storage array Al and the second storage array A2 correspond to the first control structure Cl and are located on opposite sides of the first control structure Cl in the third direction Z, the third storage array A3 and the fifth storage array A5 correspond to the second control structure C2 and are located on opposite sides of the second control structure C2 in the third direction Z, and the fourth storage array A4 and the sixth storage array A6 correspond to the third control structure C3 and are located on opposite sides of the third control structure C3 in the third direction Z. The bit line connection rule inside the third storage array A3 and the fourth storage array A4 can be the same as that of the first storage array Al, and the positions of the bit line contact structures connected by the third storage array A3 and the fourth storage array A4 on the corresponding storage structure can be the same as those of the bit line contact structures connected by the first storage array Al on the corresponding storage structure.

[0063] In the embodiment shown, the first storage array Al and the second storage array A2 correspond to the first control structure Cl and are located on opposite sides of the first control structure Cl in the third direction Z, the third storage array A3 and the fifth storage array A5 correspond to the second control structure C2 and are located on opposite sides of the second control structure C2 in the third direction Z, and the fourth storage array A4 and the sixth storage array A6 correspond to the third control structure C3 and are located on opposite sides of the third control structure C3 in the third direction Z. The bit line connection rule inside the third storage array A3 and the fourth storage array A4 can be the same as that of the first storage array Al, and the positions of the bit line contact structures connected by the third storage array A3 and the fourth storage array A4 on the corresponding storage structure can be the same as those of the bit line contact structures connected by the first storage array Al on the corresponding storage structure. Figure 2In the embodiment, the position of the fourth complementary bit line BLB4 in the third storage array A3 is the same as the position of the fifth target bit line BLA5 in the first storage array A1, the position of the fifth complementary bit line BLB5 in the fourth storage array A4 is the same as the position of the fourth target bit line BLA3 in the first storage array A1, the two with the same position can be regarded as a repeating unit, and the bit line bonding structures corresponding to the two fall into the same region of different storage structures, for example, the fourth complementary bit line BLB4 and the fifth target bit line BLA3 fall into the third contact region R3 of the second control structure C2 and the first control structure C1 respectively.

[0064] In the embodiment of the present application, by controlling the bit line contact structure BLC electrically connected with the bit line BL to be in three different regions of the storage structure AR, the number of bit line contact structures BLC in each region and the number of required wires for connecting the bit line contact structures BLC in the same region are reduced, so as to reduce the wire density requirement and the number requirement of the other wire layer connected with the bit line, and facilitate to ensure that the wire density meets the actual requirement while increasing the wire width and the wire spacing of the other wire layer.

[0065] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present application, therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A memory, comprising: The application relates to a memory structure and a control structure, wherein bit lines extend in a first direction and word lines extend in a second direction, the memory structure and the control structure are stacked in a third direction, and the third direction is perpendicular to the first direction and the second direction. The bit lines in the memory structure are electrically connected to the control structure through bit line contact structures, and the bit line contact structures included in the same memory structure are located in a first contact area, a second contact area and a third contact area of the memory structure, the first contact area, the second contact area and the third contact area are arranged in sequence in the first direction and extend in the second direction. The number of channels in which the bit line contact structures corresponding to each of the first contact area, the second contact area and the third contact area are located is less than or equal to half of the number of the corresponding bit lines.

2. The memory of claim 1, wherein, The number of channels in which the bit line contact structures corresponding to part of the first contact area, the second contact area and the third contact area are located is less than half of the number of the corresponding bit lines.

3. The memory of claim 2, wherein, The memory structure comprises a first memory array and a second memory array located on opposite sides of the control structure in the third direction, and the control structure is used for controlling the first memory array and the second memory array, the number of channels in which the bit line contact structures located in each region of the first memory array or the second memory array are located is less than or equal to half of the number of the bit lines arranged in the second direction.

4. The memory of claim 3, wherein, The projections of the bit line contact structures corresponding to the first memory array and the bit line contact structures corresponding to the second memory array in the third direction are coincident.

5. The memory of claim 4, wherein, Two bit line contact structures located in the same region and in adjacent channels in the second direction are staggered in the first direction.

6. The memory of any one of claims 1-5, wherein, Each of the memory arrays comprises a first bit line region and a second bit line region arranged in the first direction, and a plurality of bit lines arranged in the second direction are arranged in the first bit line region and the second bit line region, on odd positions, the bit lines in the first bit line region and the second bit line region in the first memory array are connected, and the bit lines in the first bit line region and the second bit line region in the second memory array are connected, on even positions, the bit lines in the first bit line region in the first memory array are connected with the bit lines in the first bit line region in the second memory array, and the bit lines in the second bit line region in the first memory array are connected with the bit lines in the second bit line region in the second memory array.

7. The memory of claim 4, wherein, The projections of the bit line contact structures corresponding to the bit lines adjacent to the odd positions in the third direction are located in different regions, and the projections of the bit line contact structures corresponding to the bit lines adjacent to the even positions in the third direction are located in different regions.

8. The memory of claim 7, wherein, On part of the even positions, the bit lines in the first bit line region in the first memory array are connected with the bit lines in the first bit line region in the second memory array to form target bit lines, and the bit lines in the second bit line region in the first memory array are connected with the bit lines in the second bit line region in the second memory array to form complementary bit lines.

9. The memory of claim 8, wherein, The application further relates to 10. The memory of claim 8, wherein, ​ In the first direction, a third memory array and a fourth memory array located on opposite sides of the first memory array, a fifth memory array and a sixth memory array located on opposite sides of the second memory array, a projection of the third memory array and the fifth memory array in the third direction at least partially coincide, a projection of the fourth memory array in the third direction at least partially coincide, in the partial even position, a bit line of a first bit line region in the first memory array and a bit line of a first bit line region in the second memory array are connected, a bit line of a second bit line region in the third memory array and a bit line of a second bit line region in the fifth memory array are connected, the bit line of the first bit line region in the first memory array and the bit line of the second bit line region in the third memory array are mutual reference, a bit line of a second bit line region in the first memory array and a bit line of a second bit line region in the second memory array are connected, a bit line of a first bit line region in the fourth memory array and a bit line of a first bit line region in the sixth memory array are connected, the bit line of the second bit line region in the first memory array and the bit line of the first bit line region in the fourth memory array are mutual reference.

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