Memory and memory system including ECC decoder circuit and method of operating same

Abstract

The invention relates to a memory and a memory system including an ECC decoder circuit and a method of operating the same. The memory may include: a plurality of data terminals; a plurality of data receiving circuits configured to receive data and parity bits through the plurality of data terminals; an error correction code (ECC) decoder circuit configured to detect an error in the data and the parity using the data and the parity; and an error storage circuit configured to store a history of errors detected by the ECC decoder circuit.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0058552, filed on May 2, 2024, and Korean Patent Application No. 10-2024-0094726, filed on July 18, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Various embodiments of this disclosure relate to memories and memory systems. Background Technology

[0004] In the early stages of the semiconductor memory industry, memory chips were made by distributing multiple intact dies with defect-free memory cells on a wafer. However, as memory capacity has gradually increased, it has become increasingly difficult to manufacture memory without any defective memory cells; today, it is practically impossible to manufacture such memory. One way to solve this problem is to use redundant memory cells to repair defective memory cells.

[0005] Another approach is to use error-correcting code circuitry (i.e., ECC engine) in the memory system to correct errors that occur in the memory cells as well as errors that occur when data is transferred during the read and write processes of the memory system. Summary of the Invention

[0006] According to embodiments of the present disclosure, a memory may include: a plurality of data terminals; a plurality of data receiving circuits configured to receive data and parity bits through the plurality of data terminals; an error correction code (ECC) decoder circuit configured to use the data and parity bits to detect errors in the data and parity bits; and an error storage circuit configured to store a history of errors detected by the ECC decoder circuit.

[0007] According to embodiments of this disclosure, a memory system may include: a plurality of data lines; a first data clock line and a second data clock line; a memory controller configured to transmit data and parity bits through the plurality of data lines, and to transmit a data clock through the first data clock line and the second data clock line; and a memory configured to receive a data clock through the first data clock line and the second data clock line, and to receive data and parity bits transmitted through the plurality of data lines synchronously with the data clock, wherein the memory may include: an ECC decoder circuit configured to detect errors in the data and parity bits based on the data and parity bits; and an error storage circuit configured to store a historical record of errors detected by the ECC decoder circuit for each data line.

[0008] According to an embodiment of the disclosure, an operation method of a memory system can include generating, by a memory controller, parity bits based on data; transmitting, by the memory controller, a data clock through first and second data clock lines; transmitting, by the memory controller, the data and the parity bits through a plurality of data lines; receiving, by a memory, the data clock through the first and second data clock lines; receiving, by the memory, the data and the parity bits through the plurality of data lines in synchronization with the data clock; detecting, by the memory, errors in the data and the parity bits based on the data and the parity bits; and storing, by the memory, a history of error occurrences for each of the data lines.

[0009] According to an embodiment of the disclosure, a memory system can include a plurality of data lines; a data clock line; a memory controller configured to transmit data and parity bits to the plurality of data lines and to transmit a data clock to the data clock line; and a memory configured to receive the data and the parity bits through the plurality of data lines in synchronization with the data clock transmitted through the one or more data clock lines, and to store a history of errors detected by decoding the received data and parity bits for each of the data lines. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating a memory system according to an embodiment of the disclosure.

[0011] Figure 2 is a block diagram illustrating a memory according to an embodiment of the disclosure. Figure 1

[0012] Figure 3 is a block diagram illustrating a data receiving circuit according to an embodiment of the disclosure. Figure 2

[0013] Figure 4 is a block diagram illustrating a data output circuit according to an embodiment of the disclosure. Figure 2

[0014] Figure 5 is a block diagram illustrating a memory controller according to an embodiment of the disclosure. Figure 1

[0015] Figure 6 is a flowchart illustrating a process of a training operation for adjusting timing of data and a data clock of a memory system according to an embodiment of the disclosure. Figures 1 to 5 DETAILED DESCRIPTION

[0016] Various embodiments of the disclosure relate to a technique of performing a training operation by using an error correction function of a memory. ​​​​​

[0017] According to embodiments of the disclosure, a training operation can be performed by using an error correction function of a memory.

[0018] Hereinafter, various embodiments according to the technical spirit of the disclosure will be described below with reference to the accompanying drawings.

[0019] Figure 1 is a block diagram of a memory system 100 according to an embodiment of the disclosure. Figures 1 to 6 The drawing of FIG. 1 illustrates only a portion of the memory system 100 directly related to the transmission of data and a data clock.

[0020] Referring to Figure 1 , the memory system 100 can include a memory controller 110 and a memory 150.

[0021] The memory controller 110 can control read and write operations of the memory 150 according to a request of a host, and the memory 150 can perform the read and write operations under the control of the memory controller 110.

[0022] A data line DATA LINE can be a line for transmitting data between the memory controller 110 and the memory 150. During a write operation, data can be transmitted from the memory controller 110 to the memory 150, and during a read operation, data can be transmitted from the memory 150 to the memory controller 110. In Figure 1 , a case in which the number of data lines DATA LINE is 12 is described. In order to correct errors in data transmitted between the memory controller 110 and the memory 150, parity bits can be transmitted on the data lines DATA LINE together with the data.

[0023] A data clock line WCK LINE can be a line for transmitting a data clock from the memory controller 110 to the memory 150. In Figure 1 , a case in which the data clock line WCK LINE is two lines is described since the data clock is a differential signal. The data clock can be a clock used by the memory 150 to receive data transmitted through the data line DATA LINE during a write operation.

[0024] A read data strobe signal line RDQS LINE can be a line for transmitting a read data strobe signal from the memory 150 to the memory controller 110. In Figure 1 , a case in which the read data strobe signal line RDQS LINE is two lines is described since the read data strobe signal is a differential signal. The read data strobe signal can be a signal used by the memory controller 110 to receive data transmitted through the data line DATA LINE during a read operation.

[0025] In order for the memory 150 to correctly receive data transmitted through the data lines DATALINE, timing adjustment between data transmitted through the data lines DATALINE and a data clock transmitted through the data clock lines WCK LINE is essential, and a training operation for timing adjustment is referred to as "WCK-DQ training".

[0026] WCK-DQ training is generally performed during a period in which data is not input to / from the memory 150 (for example, an all-bank refresh state (i.e., an all-bank refresh operation period)). WCK-DQ training is performed by the following procedure. First, a predetermined data pattern is stored in the memory 150. A data clock and data having the predetermined data pattern are transmitted from the memory controller 110 to the memory 150, and the memory 150 receives the data based on the data clock. The memory 150 compares the received data with the predetermined data pattern and counts the number of errors for each data line DATALINE. The error count result of the memory 150 is transmitted to the memory controller 110, and the memory controller 110 adjusts the timing of the data and the data clock based on the result.

[0027] The procedure of WCK-DQ training can be complicated because WCK-DQ training needs to store a predetermined data pattern in the memory 150 using, for example, a mode register write (MRW) operation, and detect errors by comparing data received by the memory 150 with the data pattern stored during the training operation. Hereinafter, a method of performing a training operation using an error correction code (ECC) decoder circuit included in the memory 150 is described.

[0028] Figure 2 is a block diagram illustrating a memory 150 according to an embodiment of the disclosure. Figure 1 The block diagram of the memory 150 shown in

[0029] Referring to Figure 2 , the memory 150 can include data terminals DQ0 to DQ11, data clock terminals WCK and WCKB, read data strobe signal terminals RDQS and RDQSB, data reception circuits (RX) 201_0 to 201_11, a data clock receiver 203, a strobe generation circuit (DQS GEN) 209, data transmission circuits (TX) 205_0 to 205_11, a read data strobe signal transmitter 207, an ECC decoder circuit (ECC DEC) 211, an ECC encoder circuit (ECC ENC) 213, an error storage circuit 215, and a memory core 220.

[0030] The data clock terminals WCK and WCKB are connected to the data clock lines (by Figure 1The reference sign "WCK LINE" in the figure indicates). The data clock receiver 203 can receive the data clock transmitted through the data clock terminals WCK and WCKB, and transmit the received data clock to the data reception circuits 201_0 to 201_11 and the strobe generation circuit 209. Since the data clock is a differential signal, this is indicated in the figure with the reference sign "x2".

[0031] The data terminals DQ0 to DQ11 are connected to the data lines DATA LINE. During a write operation and a read operation, data can be transmitted to and received from each of the data terminals DQ0 to DQ11 in a burst length (BL) of 24. That is, during a write operation, 24 bits of data (and a parity bit) can be serially input to each of the data terminals DQ0 to DQ11, and during a read operation, 24 bits of data (and a parity bit) can be serially output to each of the data terminals DQ0 to DQ11.

[0032] The data reception circuits 201_0 to 201_11 can receive the data DATA and the parity bit PAR transmitted through the data terminals DQ0 to DQ11. The data reception circuits 201_0 to 201_11 can operate in synchronization with the data clock received by the data clock receiver 203. The data reception circuits 201_0 to 201_11 can receive the data DATA and the parity bit PAR of the data terminals DQ0 to DQ11, convert the received data DATA and the parity bit PAR in a serial-to-parallel manner, and output the converted data and the parity bit. The data reception circuits 201_0 to 201_11 can receive a signal of 288 (= 12 * 24) bits input to the 12 data terminals DQ0 to DQ11, of which 272 bits can be data DATA and 16 bits can be a parity bit PAR.

[0033] The strobe generation circuit 209 can generate a read data strobe signal based on the data clock transmitted from the data clock receiver 203. Since the read data strobe signal is a differential signal, this is indicated in the figure with the reference sign "x2". The read data strobe signal can be transmitted to the data transmission circuits 205_0 to 205_11 and the read data strobe signal transmitter 207. The read data strobe signal transmitter 207 can transmit the read data strobe signal to the read data strobe signal terminals RDQS and RDQSB. The read data strobe signal terminals RDQS and RDQSB are terminals connected to the read data strobe signal lines (indicated by the reference sign "RDQS LINE" in the figure). Figure 1

[0034] ​The data transmission circuit 205_0 to 205_11 can transmit the data DATA and the parity PAR transmitted from the ECC encoder circuit 213 to the data terminals DQ0 to DQ11. The data transmission circuit 205_0 to 205_11 can operate in synchronization with the read data strobe signal. The data transmission circuit 205_0 to 205_11 can convert the data DATA and the parity PAR in a parallel-to-serial manner, and then output the converted data and parity to the data terminals DQ0 to DQ11.

[0035] The ECC decoder circuit 211 can detect and correct errors in the data DATA and the parity PAR using the data DATA and the parity PAR transmitted from the data reception circuit 201_0 to 201_11. That is, the ECC decoder circuit 211 can detect errors in the data DATA and the parity PAR transmitted from the memory controller 110, and correct the detected errors. The ECC decoder circuit 211 can generate a syndrome SYNDROME using the data DATA and the parity PAR. The syndrome SYNDROME is information indicating which bit of the data DATA and which bit of the parity PAR have errors. The ECC decoder circuit 211 can correct errors by inverting bits corresponding to the syndrome SYNDROME. The syndrome SYNDROME generated by the ECC decoder circuit 211 can be transmitted to the error storage circuit 215.

[0036] The error storage circuit 215 can store a history of errors detected by the ECC decoder circuit 211. The error storage circuit 215 can receive the syndrome SYNDROME from the ECC decoder circuit 211, and store a history of error occurrences for each data terminal DQ0 to DQ11 using the syndrome SYNDROME. Specifically, the error storage circuit 215 can count and store the number of errors occurring for each data terminal DQ0 to DQ11. Since the syndrome SYNDROME includes information about which bit of the data DATA and the parity PAR of 288 bits contains an error, the error storage circuit 215 can identify that there is an error in the data or the syndrome corresponding to the data terminal among the data terminals DQ0 to DQ11 using the syndrome SYNDROME, and accumulate and store a history of the error. The error history information ERR_LOG stored in the error storage circuit 215 can be transmitted to the memory controller 110 at the request of the memory controller 110. The error history information ERR_LOG can be transmitted to the memory controller 110 through the data transmission circuit 205_0 to 205_11.

[0037] The memory core 220 can receive and store the data DATA' processed by the ECC decoder circuit 211 during a write operation. Also, the memory core 220 can send the stored data DATA' to the ECC encoder circuit 213 during a read operation. The memory core 220 represents a place where data is stored in the memory 150, and can include a plurality of storage units storing data and a circuit writing and reading data to and from the plurality of storage units.

[0038] The ECC encoder circuit 213 can generate the parity PAR using the data DATA' read from the memory core 220 during a read operation. That is, the ECC encoder circuit 213 can encode the data DATA' and generate the parity PAR for correcting errors in the data DATA' in the memory controller 110. Since the parity PAR is just generated during an encoding operation and no error correction operation is performed, the data DATA' input to the ECC encoder circuit 213 and the data DATA output from the ECC encoder circuit 213 can be the same during the encoding operation.

[0039] Figure 1 The number of data terminals DQ, the value of BL, the number of bits of the parity PAR, etc. in Figure 2 are only examples, and can be changed at any time according to design.

[0040] Figure 3 is a block diagram illustrating a data reception circuit 201_0 according to an embodiment of the disclosure. Figure 2

[0041] Referring to Figure 3 , the data reception circuit 201_0 can include a data receiver 310 and a serial-to-parallel conversion circuit (S2P) 320.

[0042] The data receiver 310 can receive a signal from the data terminal DQ0. The serial-to-parallel conversion circuit 320 can convert the reception result of the data receiver 310 in a serial-to-parallel manner. Since a 24-bit signal is serially transmitted in a burst length (BL) of 24 through the data terminal DQ0 at BL=24, the serial-to-parallel conversion circuit 320 can perform a serial-to-parallel conversion operation at 1:24. The serial-to-parallel conversion circuit 320 can perform data alignment and serial-to-parallel conversion operations using a data clock transmitted from the data clock receiver 203.

[0043] The other data reception circuits 201_1 to 201_11 other than the data reception circuit 201_0 can also be configured in the same manner as the data reception circuit 201_0 illustrated in Figure 3 .

[0044] Figure 4 ​is a block diagram illustrating the data transmitting circuit 205_0 according to an embodiment of the present disclosure. Figure 2 is a block diagram illustrating the data transmitting circuit 205_0 according to an embodiment of the present disclosure.

[0045] Referring to Figure 4 , the data transmitting circuit 205_0 can include a data transmitter 410, a parallel-to-serial conversion circuit (P2S) 420, and a selection circuit 430.

[0046] The selection circuit 430 can select one of the signal transmitted from the ECC encoder circuit 213 and the error history information ERR_LOG. The selection circuit 430 can select the signal transmitted from the ECC encoder circuit 213 during a read operation, and select the error history information ERR_LOG when the memory 150 transmits the error history information ERR_LOG to the memory controller 110 according to a request of the memory controller 110.

[0047] The parallel-to-serial conversion circuit 420 can convert the signal selected by the selection circuit 430 in a parallel-to-serial manner. The parallel-to-serial conversion circuit 420 can perform a parallel-to-serial conversion operation at 24:1, and use a read data strobe signal generated by the strobe generation circuit 209 to perform the parallel-to-serial conversion operation.

[0048] The data transmitter 410 can transmit the conversion result of the parallel-to-serial conversion circuit 420 to the data terminal DQ0.

[0049] Although Figure 2 the error history information ERR_LOG is output through the data transmitting circuits 205_0 to 205_11, the error history information ERR_LOG can be output through some of the data transmitting circuits 205_0 to 205_11 when the number of bits of the error history information ERR_LOG is small. In this case, the selection circuit 430 can be omitted in the data transmitting circuit among the data transmitting circuits 205_0 to 205_11 that does not output the error history information ERR_LOG.

[0050] Figure 5 is a block diagram illustrating the data transmitting circuit 205_0 according to an embodiment of the present disclosure. Figure 1 is a block diagram illustrating the data transmitting circuit 205_0 according to an embodiment of the present disclosure.

[0051] Referring to Figure 5The memory controller 110 may include data terminals DQ0 to DQ11, data clock terminals WCK and WCKB, read data strobe signal terminals RDQS and RDQSB, data receiving circuits (RX) 501_0 to 501_11, read data strobe signal receiver 503, data clock generation circuit (WCK GEN) 509, data clock timing adjustment circuit (WCK DLY) 510, data transmission circuits (TX) 505_0 to 505_11, data clock transmitter 507, ECC decoder circuit (ECC DEC) 511, and ECC encoder circuit (ECC ENC) 513.

[0052] The read data strobe signal terminals RDQS and RDQSB are connected to the read data strobe signal line. Figure 1 (Indicated by the reference numeral "RDQS LINE" in the attached figure). The read data strobe signal receiver 503 can receive read data strobe signals sent to the read data strobe signal terminals RDQS and RDQSB, and transmit the received read data strobe signals to the data receiving circuits 501_0 to 501_11. Since the read data strobe signals are differential signals, they are indicated by the reference numeral "x2" in the figure.

[0053] Data terminals DQ0 through DQ11 are connected to the data line. During write and read operations, data can be sent to and received in burst lengths (BL) of 24 bits at each of data terminals DQ0 through DQ11. That is, during a read operation, 24 bits of data (and a parity bit) can be serially input to each of data terminals DQ0 through DQ11, while during a write operation, 24 bits of data (and a parity bit) can be serially output to each of data terminals DQ0 through DQ11.

[0054] Data receiving circuits 501_0 to 501_11 can receive data DATA and parity bit PAR transmitted through data terminals DQ0 to DQ11. Data receiving circuits 501_0 to 501_11 can operate synchronously with the read data strobe signal received by read data strobe signal receiver 503. Data receiving circuits 501_0 to 501_11 can receive data DATA and parity bit PAR from data terminals DQ0 to DQ11, convert the received data DATA and parity bit PAR in a serial-to-parallel manner, and output the converted data and parity bit. Data receiving circuits 501_0 to 501_11 can receive 288 (=12*24) bits of signal input to the 12 data terminals DQ0 to DQ11, where 272 bits can be data DATA and 16 bits can be parity bit PAR.

[0055] The data clock generation circuit 509 can generate a data clock for transmitting data from the memory controller 110 to the memory 150. Since the data clock is a differential signal, it is indicated with the reference numeral "x2" in the drawing. The data clock generated by the data clock generation circuit 509 can be transmitted to the data transmission circuit 505_0 to 505_11 and the data clock timing adjustment circuit 510.

[0056] The data clock timing adjustment circuit 510 can adjust the timing of the data clock transmitted from the memory controller 110 to the memory 150. The data clock timing adjustment circuit 510 can delay the data clock and transmit the delayed data clock to the data clock transmitter 507, and the delay value of the data clock timing adjustment circuit 510 can be adjusted by the error history information ERR_LOG transmitted from the memory 150. The data clock transmitter 507 can transmit the data clock whose timing is adjusted by the data clock timing adjustment circuit 510 to the data clock terminals WCK and WCKB. The data clock terminals WCK and WCKB are terminals connected to the data clock lines (indicated by the reference numeral "WCK LINE" in the drawing) in the memory 150. Figure 1

[0057] The data transmission circuit 505_0 to 505_11 can transmit the data DATA and the parity PAR transmitted from the ECC encoder circuit 513 to the data terminals DQ0 to DQ11. The data transmission circuit 505_0 to 505_11 can operate in synchronization with the data clock generated by the data clock generation circuit 509. The data transmission circuit 505_0 to 505_11 can convert the data DATA and the parity PAR in a parallel-to-serial manner and then output the converted data and parity to the data terminals DQ0 to DQ11.

[0058] The ECC decoder circuit 511 can detect and correct errors in the data DATA and the parity PAR using the data DATA and the parity PAR transmitted from the data reception circuit 501_0 to 501_11. That is, the ECC decoder circuit 511 can detect errors in the data DATA and the parity PAR transmitted from the memory 150 and correct the detected errors. The data DATA" is data processed by the ECC decoder circuit 511.

[0059] The ECC encoder circuit 513 can generate the parity PAR using the data DATA" (i.e., the write data) to be transmitted from the memory controller 110 to the memory 150. Since the parity PAR is just generated during the encoding operation and the error correction operation is not performed, the data DATA" input to the ECC encoder circuit 513 and the data DATA output from the ECC encoder circuit 513 can be the same during the encoding operation.​

[0060] Figure 6 is a flowchart illustrating a process of a training operation for adjusting the timing of data and a data clock of the memory system 100 according to an embodiment of the disclosure. Figures 1 to 5

[0061] Referring to FIG. 6, Figure 6 In operation 601, a training mode for adjusting the timing of data and a data clock can be set. The training operation for controlling the timing of data and a data clock is referred to as a "WCK-DQ training operation." The training operation is generally performed during a period in which no data is transmitted between the memory 150 and the memory controller 110 (e.g., an all-bank refresh state (i.e., a period of all-bank refresh operation)).

[0062] In operation 603, the ECC encoder circuit 513 of the memory controller 110 can generate the parity bits PAR using the data DATA".

[0063] In operation 605, the data clock transmitter 507 of the memory controller 110 can transmit the data clock to the data clock line WCK LINE, and in operation 607, the data transmission circuit 505_0 to 505_11 can transmit the data DATA and the parity bits PAR to the data line DATA LINE.

[0064] In operation 609, the data clock receiver 203 of the memory 150 can receive the data clock from the data clock line WCK LINE, and in operation 611, the data reception circuit 201_0 to 201_11 can receive the data DATA and the parity bits PAR from the data line DATA LINE in synchronization with the data clock received by the data clock receiver 203.

[0065] In operation 613, the ECC decoder circuit 211 of the memory 150 can detect errors in the data DATA and the parity bits PAR using the data DATA and the parity bits PAR received by the data reception circuit 201_0 to 201_11.

[0066] In operation 615, the error storage circuit 215 of the memory 150 can count and store the errors detected by the ECC decoder circuit 211 for each data line DATA LINE (i.e., each data terminal DQ0 to DQ11).

[0067] ​In operation 617, the memory controller 110 can request the history of error occurrence from the memory 150. The request can be performed by the memory controller 110 applying a mode register read (MRR) command to the memory 150. In operation 619, in response to the request, the memory 150 can transmit the error history information ERR LOG stored in the error storage circuit 215 to the memory controller 110.

[0068] In operation 621, the data clock timing adjustment circuit 510 of the memory controller 110 can adjust the timing of the data clock using the error history information ERR LOG transmitted from the memory 150.

[0069] Figure 6 The processes 603, 605, 607, 609, 611, 613, 615, 617, 619, and 621 can be performed multiple times. For example, the training operation can be performed such that the processes 603, 605, 607, 609, 611, 613, and 615 are repeatedly performed 10 times, the processes 617, 619, and 621 are performed once, the processes 603, 605, 607, 609, 611, 613, and 615 are repeatedly performed 10 times again, and then the processes 617, 619, and 621 are performed once.

[0070] Although the above has described embodiments according to the technical spirit of the present disclosure with reference to the accompanying drawings, this is only for describing embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above-described embodiments. Those skilled in the art to which the present disclosure pertains can make various types of substitutions, modifications, and changes to the embodiments without departing from the technical spirit of the present disclosure defined in the appended claims, and it should be understood that these substitutions, modifications, and changes belong to the scope of the present disclosure. Furthermore, the embodiments can be combined to form additional embodiments.

Claims

1. A memory, comprising: Multiple data terminals; Multiple data receiving circuits receive data and parity bits through the multiple data terminals; An ECC decoder circuit, which: detects errors in the data and the parity bit based on the data and the parity bit, where ECC stands for Error Correction Code; and An error storage circuit that stores a historical record of errors detected by the ECC decoder circuit.

2. The memory according to claim 1, wherein, The error storage circuit stores a historical record of errors occurring at each data terminal.

3. The memory according to claim 2, wherein, The error storage circuit counts and stores the number of errors occurring at each data terminal.

4. The memory according to claim 2, wherein, The multiple data receiving circuits operate synchronously with the data clock.

5. The memory according to claim 4, further comprising: First data clock terminal; Second data clock terminal; as well as A data clock receiver, which receives the data clock through the first data clock terminal and the second data clock terminal and transmits the data clock to the plurality of data receiving circuits.

6. The memory according to claim 4, wherein, Each of the plurality of data receiving circuits includes: Data receiver; and A serial-to-parallel conversion circuit, which converts the received result of the data receiver in a serial-to-parallel manner in sync with the data clock.

7. The memory according to claim 2, wherein, The history of error occurrences stored in the error storage circuit is sent to the memory controller upon request.

8. The memory according to claim 5, further comprising: A memory core that stores data processed by the ECC decoder circuitry; An ECC encoder circuit that generates the parity bit based on data read from the memory core; and Multiple data transmission circuits, which transmit the data read from the memory core and the parity bit generated by the ECC encoder circuit through the multiple data terminals.

9. The memory according to claim 8, wherein, The multiple data transmission circuits operate synchronously with the data read strobe signal.

10. The memory according to claim 9, further comprising: A gating generation circuit generates the read data gating signal based on the data clock; First data read strobe signal terminal; Second data read strobe signal terminal; as well as A read data strobe signal transmitter that transmits the read data strobe signal through the first read data strobe signal terminal and the second read data strobe signal terminal.

11. The memory according to claim 7, wherein, The error storage circuit receives the corrector generated by the ECC decoder circuit.

12. A memory system, comprising: Multiple data cables; First data clock line and second data clock line; A memory controller, which: transmits data and parity bits via the plurality of data lines, and transmits a data clock via the first data clock line and the second data clock line; and The memory receives the data clock via the first data clock line and the second data clock line, and synchronously receives the data and the parity bit transmitted via the plurality of data lines. The memory includes: An ECC decoder circuit that: detects errors in the data and the parity bit based on the data and the parity bit; and An error storage circuit, which stores a historical record of errors detected by the ECC decoder circuit for each data line.

13. The memory system according to claim 12, wherein, The error storage circuit counts and stores the number of errors that occur on each data line.

14. The memory system according to claim 12, wherein, The memory also includes multiple data receiving circuits, which receive the data and the parity bit synchronously with the data clock through the multiple data lines.

15. The memory system according to claim 14, wherein, Each of the plurality of data receiving circuits includes: Data receiver; and A serial-to-parallel conversion circuit, which converts the received result of the data receiver in a serial-to-parallel manner in sync with the data clock.

16. The memory system according to claim 12, in, The historical record of the error stored in the error storage circuit is sent from the memory to the memory controller, and The memory controller adjusts the timing of the data to be transmitted and the data clock based on the historical record of the errors sent from the memory.

17. A method of operating a memory system, the memory system comprising a memory and a memory controller, the method comprising: The memory controller generates parity bits based on the data; The memory controller transmits the data clock via the first data clock line and the second data clock line; The memory controller transmits the data and the parity bit via multiple data lines; The memory receives the data clock via the first data clock line and the second data clock line; The memory receives the data and the parity bit synchronously with the data clock via the plurality of data lines; The memory detects errors in the data and the parity bit based on the data and the parity bit. as well as The memory stores a historical record of errors occurring on each data line.

18. The operating method according to claim 17, further comprising: The memory sends a history of the errors to the memory controller. as well as The memory controller adjusts the data clock and the timing of the data based on the history of the errors.

19. The operating method according to claim 18, wherein, Sending the historical record of the error occurrence and adjusting the data clock and the timing of the data are performed during a period in which there is no data transmission or reception between the memory and the memory controller.

20. The operating method according to claim 19, wherein, The time period includes all memory bank refresh operation periods of the memory.

21. A memory system, comprising: Multiple data cables; One or more data clock lines; A memory controller, which: transmits data and parity bits to the plurality of data lines, and transmits a data clock to the one or more data clock lines; and A memory that: receives the data and the parity bit through the plurality of data lines in synchronization with the data clock transmitted through the one or more data clock lines, and stores a history of errors detected by decoding the received data and parity bit on each data line.

22. The memory system according to claim 21, wherein, The memory sends the error history to the memory controller upon request.

23. The memory system according to claim 22, wherein, The memory controller adjusts the data clock and timing of the data to be transmitted based on the historical record of the errors sent from the memory.

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