Method, system and device for testing parameters of NAND FLASH

Abstract

The invention discloses an NAND FLASH parameter testing method, system and device, and the method comprises the steps: transmitting a parameter reading command to a target storage chip based on a preset communication protocol, the target storage chip being a to-be-tested NAND FLASH chip; judging whether parameter data fed back by the target storage chip according to the parameter reading command is received or not; if the parameter data is received, analyzing the parameter data to obtain a test result; and if the parameter data is not received, executing a read-write erasing test on the target storage chip to obtain a test result. When the parameter data cannot be directly read, the parameter data is determined by executing the read-write erasing test on the target storage chip, so that the test result is obtained, and the flexibility of parameter test is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, and particularly relates to a NAND FLASH parameter testing method, system and device. BACKGROUND

[0002] NAND FLASH (Flash Memory) is a common non-volatile memory. With the increasing demand for memory capacity and performance of embedded systems and electronic devices, NAND FLASH, as a low-cost and easy-to-integrate memory, has become the first choice for solutions. NAND FLASH is widely used in embedded systems and electronic devices. However, for embedded systems and electronic devices, the parameters of NAND FLASH are particularly critical. However, the parameters of NAND FLASH of different manufacturers and models are different.

[0003] However, the existing parameter testing method mostly relies on the identification information pre-set by the manufacturer, such as an ID (Identity Document, identity number) table, a parameter configuration table or an internal marking block of NAND FLASH to identify the parameters. However, this lacks the ability to cope with parameter changes and cannot be used for rapid verification of unknown NAND FLASH, causing poor flexibility of parameter testing.

[0004] Therefore, there is still an urgent need for a method that can improve the flexibility of parameter testing. SUMMARY

[0005] The main purpose of the present application is to provide a NAND FLASH parameter testing method, system and device to solve the problem of lack of ability to cope with parameter changes, inability to be used for rapid verification of unknown NAND FLASH and poor flexibility of parameter testing.

[0006] To achieve the above purpose, the present application provides a NAND FLASH parameter testing method, which comprises:

[0007] sending a parameter reading command to a target storage chip based on a preset communication protocol, wherein the target storage chip is a NAND FLASH chip to be tested;

[0008] determining whether parameter data fed back by the target storage chip according to the parameter reading command is received;

[0009] if the parameter data is received, analyzing the parameter data to obtain a test result;

[0010] if the parameter data is not received, performing read-write-erase testing on the target storage chip to obtain a test result.

[0011] In some embodiments, the parsing the parameter data obtains a test result, including:

[0012] The parsing the parameter data obtains a storage page size, a storage block size and a total number of storage blocks of the target storage chip;

[0013] The test result of the target storage chip containing the storage page size, the storage block size and the total number of storage blocks is generated.

[0014] In some embodiments, the performing read-write-erase test on the target storage chip obtains a test result, including:

[0015] The write test on the target storage chip determines a storage page size, and the erase test on the target storage chip determines a storage block size;

[0016] The total capacity of the target storage chip is obtained, and the total number of storage blocks is determined according to the total capacity and the storage block size;

[0017] The test result of the target storage chip containing the storage page size, the storage block size and the total number of storage blocks is generated.

[0018] In some embodiments, the performing write test on the target storage chip determines a storage page size, and the performing erase test on the target storage chip determines a storage block size, including:

[0019] The first data and the second data are generated;

[0020] The write test on the target storage chip is performed according to the first data, and the erase test on the target storage chip is performed according to the second data;

[0021] It is judged whether the write test and the erase test are successful;

[0022] If the write test and the erase test are both successful, a storage page size and a storage block size are obtained;

[0023] If the write test fails, the first data is updated, and the write test on the target storage chip according to the first data is re-performed;

[0024] If the erase test fails, the second data is updated, and the erase test on the target storage chip according to the second data is re-performed.

[0025] In some embodiments, the generating the test result of the target storage chip containing the storage page size, the storage block size and the total number of storage blocks, including:

[0026] characteristics of the storage page size, the storage block size and the total number of the storage blocks are extracted to obtain feature data;

[0027] The preset model library is queried according to the feature data, and it is determined whether the model corresponding to the feature data is queried;

[0028] When the model corresponding to the feature data is queried, it is determined that the model corresponding to the feature data is a target model, and the test result is generated according to the target model, the storage page size, the storage block size and the total number of the storage blocks.

[0029] In some embodiments, after it is determined whether the model corresponding to the feature data is queried, the method further comprises:

[0030] When the model corresponding to the feature data is not queried, the feature data is input into a preset model prediction model to obtain a predicted model;

[0031] The storage page size, the storage block size and the total number of the storage blocks of the predicted model are obtained;

[0032] It is determined whether the storage page size, the storage block size and the total number of the storage blocks of the predicted model are consistent with the storage page size, the storage block size and the total number of the storage blocks of the target storage chip;

[0033] When they are consistent, it is determined that the preset model is the target model, and the test result is generated according to the target model, the storage page size, the storage block size and the total number of the storage blocks;

[0034] When they are inconsistent, the preset model prediction model is updated, and the feature data is input into the preset model prediction model again to obtain a predicted model.

[0035] In some embodiments, before the parameter reading command is sent to the target storage chip based on the preset communication protocol, the method further comprises:

[0036] A target protocol command is obtained by traversing a preset protocol command set;

[0037] The target protocol command is sent to the target storage chip;

[0038] When the target storage chip responds to the target protocol command, the protocol corresponding to the target protocol command is determined as the preset communication protocol, and the traversal of the preset protocol command set to obtain the target protocol command is stopped;

[0039] When the target storage chip does not respond to the target protocol command, the traversal of the preset protocol command set to obtain the target protocol command is continued.

[0040] In some embodiments, after the generating the test result of the target storage chip containing the storage page size, the storage block size and the total number of the storage blocks, the method further comprises:

[0041] generating a test report according to the test result;

[0042] sending the test report to a host computer, and / or saving the test report.

[0043] The application further provides a NAND FLASH parameter testing system, comprising a NAND FLASH and a testing device; the NAND FLASH parameter testing system can execute the NAND FLASH parameter testing method in any one of the above embodiments.

[0044] The application further provides a NAND FLASH parameter testing device, comprising:

[0045] at least one processor; and,

[0046] a memory in communication connection with the at least one processor; wherein,

[0047] the memory stores instructions executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the NAND FLASH parameter testing method in any one of the above embodiments.

[0048] The application improves the flexibility of parameter testing by sending a parameter reading command to a target storage chip based on a preset communication protocol, judging whether parameter data fed back by the target storage chip according to the parameter reading command is received, analyzing the parameter data to obtain a test result if the parameter data is received, and performing read-write-erase testing on the target storage chip to obtain a test result if the parameter data is not received. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 a flowchart of the NAND FLASH parameter testing method in the embodiments of the application;

[0050] Figure 2 another flowchart of the NAND FLASH parameter testing method in the embodiments of the application;

[0051] Figure 3 another flowchart of the NAND FLASH parameter testing method in the embodiments of the application;

[0052] Figure 4 Another flowchart of the parameter testing method of the NAND FLASH in the embodiment of the present application is shown in FIG. 11.

[0053] Figure 5 Another flowchart of the parameter testing method of the NAND FLASH in the embodiment of the present application is shown in FIG. 11.

[0054] Figure 6 Another flowchart of the parameter testing method of the NAND FLASH in the embodiment of the present application is shown in FIG. 11.

[0055] Figure 7 Another flowchart of the parameter testing method of the NAND FLASH in the embodiment of the present application is shown in FIG. 11.

[0056] Figure 8 Another flowchart of the parameter testing method of the NAND FLASH in the embodiment of the present application is shown in FIG. 11.

[0057] Figure 9 Another flowchart of the parameter testing method of the NAND FLASH in the embodiment of the present application is shown in FIG. 11.

[0058] Figure 10 Another flowchart of the parameter testing method of the NAND FLASH in the embodiment of the present application is shown in FIG. 11.

[0059] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0060] The embodiments of the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0061] It should be noted that all the directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly.

[0062] It should be further noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or can have a middle element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or can have a middle element.

[0063] In addition, the descriptions related to "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of the ordinary skilled in the art, when the combination of technical solutions appears contradictory or cannot be realized, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application.

[0064] To achieve the above object, the present application provides a NAND FLASH parameter testing method, which comprises the following steps:

[0065] In step S110, a parameter reading command is sent to a target storage chip based on a preset communication protocol, wherein the target storage chip is a NAND FLASH chip to be tested;

[0066] In step S120, it is judged whether the parameter data fed back by the target storage chip according to the parameter reading command is received;

[0067] In step S130, if the parameter data is received, the parameter data is parsed to obtain a test result;

[0068] In step S140, if the parameter data is not received, a read-write-erase test is performed on the target storage chip to obtain a test result.

[0069] In the present embodiment, with reference to Figure 1 and Figure 9 The NAND FLASH parameter testing method can be applied to a NAND FLASH parameter testing system. The NAND FLASH parameter testing system comprises a NAND FLASH and a testing device, and the testing device can comprise a communication interface, wherein the communication interface can be multiple, and the communication interface of the testing device can be connected with the NAND FLASH, so as to communicate with the NAND FLASH. In the present embodiment, the execution subject of the method steps is the testing device.

[0070] It can be understood that the parameters of the NAND FLASH can include a storage page size, a storage block size and a total number of storage blocks of the NAND FLASH, and the parameters of the NAND FLASH are highly related to the performance of the NAND FLASH. When it is necessary to reasonably and efficiently use the NAND FLASH, it is particularly important to test the parameters of the NAND FLASH. However, the existing parameter testing methods mostly rely on the identification information pre-set by the manufacturer, such as an ID (Identity Document, identity number) table, a parameter configuration table or a NAND FLASH internal marker block to identify the parameters. However, this lacks the ability to cope with parameter changes and cannot be used for rapid verification of unknown NAND FLASH, causing the problem of poor flexibility of parameter testing. However, when the parameter data cannot be directly read, the present application determines the parameter data by performing read-write-erase testing on the target storage chip, thereby obtaining the test result, and improves the flexibility of parameter testing.

[0071] When a user needs to perform parameter testing on a target storage chip, the target storage chip can be connected with the communication interface of the testing device, so that the testing device can determine the communication protocol used by the target storage chip, and determine the communication protocol as a preset communication protocol. Then, the testing device can communicate with the target storage chip based on the preset communication protocol. The target storage chip is a NAND FLASH chip to be tested. The testing device can send a parameter reading command to the target storage chip based on the preset communication protocol.

[0072] The testing device sends the parameter reading command to the target storage chip, and can determine whether the feedback of the target storage chip is received. The testing device determines whether the parameter data fed back by the target storage chip according to the parameter reading command is received. For example, when the target storage chip saves the parameter configuration table pre-set by the manufacturer, the target storage chip can read the parameter configuration table in response to the parameter reading command when the parameter reading command is received, so as to obtain the parameter data, and then feed back the parameter data to the testing device. At this time, the testing device can receive the parameter data (the parameter data fed back by the target storage chip according to the parameter reading command). When the target storage chip does not save the parameter configuration table pre-set by the manufacturer, the target storage chip cannot respond to the parameter reading command when the parameter reading command is received, so as to feed back to the testing device. At this time, the testing device cannot receive the parameter data.

[0073] When the parameter data is received, the testing device can analyze the parameter data, thereby obtaining the test result. When the parameter data is not received, the testing device can perform read-write-erase testing on the target storage chip, thereby testing the parameter data, and analyzing the parameter data to obtain the test result.

[0074] The parameter reading command is sent to the target storage chip based on the preset communication protocol, it is judged whether the parameter data fed back by the target storage chip according to the parameter reading command is received, if the parameter data is received, the test result is obtained by analyzing the parameter data, if the parameter data is not received, the read-write-erase test is performed on the target storage chip to obtain the test result, when the parameter data cannot be directly read, the parameter data is determined by performing the read-write-erase test on the target storage chip, so that the test result is obtained, and the flexibility of the parameter test is improved.

[0075] In some embodiments, the aforementioned analyzing the parameter data to obtain the test result comprises:

[0076] Step S150, the parameter data is analyzed to obtain the storage page size, the storage block size and the total number of storage blocks of the target storage chip;

[0077] Step S151, the test result of the target storage chip containing the storage page size, the storage block size and the total number of storage blocks is generated.

[0078] In the embodiment, referring to Figure 2 , when the step S130 is performed, the test device can obtain the storage page size, the storage block size and the total number of storage blocks. The test device can analyze the parameter data to obtain the storage page size (Page Size), the storage block size (Block Size) and the total number of storage blocks (Total Number of Blocks) of the target storage chip. The storage page size is the size of the smallest read-write unit in the NAND FLASH, and all data reading and writing operations are performed in units of storage pages. The storage block size is the size of the smallest erase unit in the NAND FLASH, which is composed of multiple continuous storage pages, and the erase operation must cover the entire storage block. The total number of storage blocks is the total amount of storage blocks contained in the entire NAND FLASH, which determines the total capacity of the NAND FLASH (the total capacity is equal to the product of the storage block size and the total number of storage blocks).

[0079] After the test device obtains the storage page size, the storage block size and the total number of storage blocks, the test result can be generated according to the storage page size, the storage block size and the total number of storage blocks. The test device generates the test result of the target storage chip containing the storage page size, the storage block size and the total number of storage blocks.

[0080] In some embodiments, the aforementioned performing the read-write-erase test on the target storage chip to obtain the test result comprises:

[0081] Step S160, the write test is performed on the target storage chip to determine the storage page size, and the erase test is performed on the target storage chip to determine the storage block size;

[0082] Step S161, obtaining the total capacity of the target storage chip, and determining the total number of storage blocks according to the total capacity and the storage block size;

[0083] Step S162, generating the test result of the target storage chip containing the storage page size, the storage block size and the total number of storage blocks.

[0084] In the embodiment, the test device performs the write test and the erase test on the target storage chip when performing step S140. Figure 3 For example, the test device can perform the write test on the target storage chip by writing 1Kb (Kilobyte) data to determine the storage page size. The test device can perform the erase test on the target storage chip to determine the storage block size. For example, the test device can perform the write test on the target storage chip by writing 1Mb (Megabyte) data to determine the storage block size.

[0085] After determining the storage page size and the storage block size, the test device can obtain the total capacity of the target storage chip. For example, generally, the packaging of the target storage chip is marked with the total capacity of the target storage chip, such as a 512Gb (Gigabyte) memory card, a 128Gb storage chip, etc. The user can input the total capacity of the target storage chip marked on the packaging into the test device. At this time, the test device can obtain the total capacity of the target storage chip. Alternatively, the test device can continuously write data into the target storage chip until it cannot be written, and determine the total amount of data written, which is the total capacity of the target storage chip.

[0086] After obtaining the storage block size and the total capacity, the test device can determine the total number of storage blocks according to the total capacity and the storage block size. For example, the total number of storage blocks can be obtained by dividing the total capacity by the storage block size.

[0087] After obtaining the storage page size, the storage block size and the total number of storage blocks, the test device can generate the test result according to the storage page size, the storage block size and the total number of storage blocks. The test device generates the test result of the target storage chip containing the storage page size, the storage block size and the total number of storage blocks.

[0088] In some embodiments, the foregoing write test on the target storage chip to determine the storage page size and the erase test on the target storage chip to determine the storage block size include:

[0089] Step S170, generating the first data and the second data;

[0090] Step S171, performing the write test on the target storage chip according to the first data, and performing the erase test on the target storage chip according to the second data;

[0091] Step S172, judging whether the write test and the erase test are tested successfully;

[0092] Step S173, if the write test and the erase test are tested successfully, obtaining the storage page size and the storage block size;

[0093] Step S174, if the write test is tested unsuccessfully, updating the first data, and re-executing the write test on the target storage chip according to the first data;

[0094] Step S175, if the erase test is tested unsuccessfully, updating the second data, and re-executing the erase test on the target storage chip according to the second data.

[0095] In the embodiment, referring to Figure 4 , the test device can perform multiple tests when executing step S160, so as to determine the storage page size and the storage block size. The test device first generates the first data and the second data. The first data is used for the write test, and the second data is used for the erase test. When the write test and the erase test are tested successfully, the test device can obtain the storage page size and the storage block size. When the write test is tested unsuccessfully, the test device updates the first data, and re-executes the write test on the target storage chip according to the first data. When the erase test is tested unsuccessfully, the test device updates the second data, and re-executes the erase test on the target storage chip according to the second data.

[0096] For example, the write test, wherein the storage page is the minimum read-write unit in the NAND FLASH (not writable across the storage page), the test device can determine the storage page size through the step-by-step write-verify method. The test device first generates the first data, which can be the data with the size of 1Kb. The test device writes the data with the size of 1Kb into the storage page, and then reads the data of the storage page to obtain the page read data. If the page read data is consistent with the data with the size of 1Kb, it is determined that the storage page size is greater than or equal to 1Kb. At this time, the first data can be increased to the data with the size of 2Kb, and the test is performed again. If the page read data is not consistent with the data with the size of 1Kb, it is determined that the storage page size is less than 1Kb. At this time, the first data can be reduced to the data with the size of 512 bytes. The test device iteratively tests (such as writing 4Kb, 256 bytes, etc., wherein the first data can be updated according to the binary rule relationship) until the "maximum complete writable size" is found, that is, the storage page size.

[0097] For example, an erase test, in which a storage block is the minimum erase unit in a NAND FLASH (erasing will clear the data of the entire storage block), the test device can determine the storage block size by erase-verify. The test device first generates second data, which can be 1Mb in size. The test device writes the 1Mb data to a storage block, then erases the data of the storage block, and detects whether the 1Mb data is completely erased. If the 1Mb data is completely erased, it is determined that the storage block size is greater than or equal to 1Mb, at which point the second data can be increased, to 2Mb, and the test is performed again. If the 1Mb data is not completely erased, it is determined that the storage block size is less than 1Mb, at which point the second data can be reduced, to 512Kb. The test device iteratively tests (such as writing 4Mb, 256Kb, etc., where the second data can be updated according to the binary rule relationship) until the "maximum complete erasable size" is found, which is the storage block size.

[0098] In some embodiments, the aforementioned generating a test result of the target storage chip containing the storage page size, the storage block size, and the total number of storage blocks includes:

[0099] At step S180, feature extraction is performed on the storage page size, the storage block size, and the total number of storage blocks to obtain feature data.

[0100] At step S181, the pre-set model library is queried according to the feature data, and it is determined whether the model corresponding to the feature data is queried.

[0101] At step S182, when the model corresponding to the feature data is queried, it is determined that the model corresponding to the feature data is the target model, and a test result is generated according to the target model, the storage page size, the storage block size, and the total number of storage blocks.

[0102] In this embodiment, with reference to Figure 5 , the test device can generate a test result containing the model when performing step S151 or step S162. The test device can perform feature extraction on the storage page size, the storage block size, and the total number of storage blocks to obtain feature data.

[0103] The test device can save a pre-set model library. The pre-set model library can be configured by a user and saved to the test device. For example, the user can collect various models and parameter data of NAND FLASH, perform feature extraction on the parameter data to obtain feature data, bind the feature data and the model, and generate a pre-set model library according to the feature data and the model. Then the pre-set model library is saved to the test device.

[0104] After obtaining the characteristic data, the test equipment can query the preset model library according to the characteristic data, so as to determine whether the model corresponding to the characteristic data is queried. For example, the test equipment queries the preset model library with the characteristic data to check whether consistent characteristic data is saved in the preset model library. When there is consistent characteristic data, the corresponding model can be found. When there is no consistent characteristic data, the corresponding model cannot be found.

[0105] When the model corresponding to the characteristic data is queried, the test equipment can determine the model corresponding to the characteristic data as the target model, and then generate the test result according to the target model, the storage page size, the storage block size and the total number of storage blocks.

[0106] In some embodiments, after the foregoing determination of whether the model corresponding to the characteristic data is queried, the method further includes:

[0107] Step S190, when the model corresponding to the characteristic data is not queried, inputting the characteristic data into a preset model prediction model to obtain a predicted model;

[0108] Step S191, obtaining the storage page size, the storage block size and the total number of storage blocks of the predicted model;

[0109] Step S192, determining whether the storage page size, the storage block size and the total number of storage blocks of the predicted model are consistent with the storage page size, the storage block size and the total number of storage blocks of the target storage chip;

[0110] Step S193, when the storage page size, the storage block size and the total number of storage blocks of the predicted model are consistent with the storage page size, the storage block size and the total number of storage blocks of the target storage chip, determining that the preset model is the target model, and generating the test result according to the target model, the storage page size, the storage block size and the total number of storage blocks;

[0111] Step S194, when the storage page size, the storage block size and the total number of storage blocks of the predicted model are not consistent with the storage page size, the storage block size and the total number of storage blocks of the target storage chip, updating the preset model prediction model, and re-executing the inputting of the characteristic data into the preset model prediction model to obtain the predicted model.

[0112] In the embodiment, with reference to Figure 6 After step S181, the test equipment can also predict the model. When the model corresponding to the characteristic data is not queried, the test equipment can input the characteristic data into a preset model prediction model to obtain a predicted model. The preset model prediction model can be configured on the test equipment, and the preset model prediction model is configured by a user according to requirements.

[0113] The test equipment obtains the predicted model, queries the predicted model, and thus obtains the storage page size, the storage block size and the total number of storage blocks corresponding to the predicted model. Then, it is determined whether the storage page size, the storage block size and the total number of storage blocks of the predicted model are consistent with the storage page size, the storage block size and the total number of storage blocks of the target storage chip.

[0114] In the consistent case, the test device can determine the preset model as the target model, and then generate the test result according to the target model, the storage page size, the storage block size, and the total number of storage blocks. In the inconsistent case, the test device can update the preset model prediction model, and re-perform the inputting of the feature data into the preset model prediction model to obtain the predicted model. For example, in the inconsistent case, the test device can notify the user of the prediction failure, and then let the user train a new preset model prediction model, and then input the new preset model prediction model into the test device; at this time, the test device can update the preset model prediction model according to the new preset model prediction model.

[0115] In some embodiments, the foregoing sending of the parameter read command to the target storage chip based on the preset communication protocol further comprises:

[0116] Step S200: obtaining a target protocol command by traversing the preset protocol command set;

[0117] Step S201: sending the target protocol command to the target storage chip;

[0118] Step S202: when the target storage chip responds to the target protocol command, determining the protocol corresponding to the target protocol command as the preset communication protocol, and stopping the obtaining of the target protocol command by traversing the preset protocol command set;

[0119] Step S203: when the target storage chip does not respond to the target protocol command, continuing to obtain the target protocol command by traversing the preset protocol command set.

[0120] In this embodiment, with reference to Figure 7 Before performing step S110, the test device can also determine the preset communication protocol. The test device can have a preset protocol command set, and the preset protocol command set can include all known protocol commands. The test device can first obtain a target protocol command by traversing the preset protocol command set. For example, the protocol commands in the preset protocol command set can be arranged in order, and the test device can first extract the protocol command ranked first in the preset protocol command set as the target protocol command.

[0121] After the test device obtains the target protocol command, the test device can send the target protocol command to the target storage chip. When the target storage chip receives the target protocol command, if the protocol used by the target storage chip is associated with the target protocol command, the target storage chip can respond to the target protocol command; if the protocol used by the target storage chip is not associated with the target protocol command, the target storage chip cannot respond to the target protocol command.

[0122] When the target storage chip responds to the target protocol command, the test device can determine the preset communication protocol corresponding to the target protocol command as the preset communication protocol, and then stop executing the target protocol command obtained by traversing the preset protocol command set. For example, the protocol commands in the preset protocol command set can be arranged in order, the test device first extracts the protocol command arranged first from the preset protocol command set, determines it as the target protocol command, and when the target storage chip responds to the target protocol command, the test device can no longer extract the protocol command arranged second from the preset protocol command set, thereby ending the traversal.

[0123] When the target storage chip does not respond to the target protocol command, the test device will continue to execute the target protocol command obtained by traversing the preset protocol command set. For example, the protocol commands in the preset protocol command set can be arranged in order, the test device first extracts the protocol command arranged first from the preset protocol command set, determines it as the target protocol command, and when the target storage chip does not respond to the target protocol command, the test device can continue to extract the protocol command arranged second from the preset protocol command set, determine it as the target protocol command, and continue to traverse.

[0124] In some embodiments, after the aforementioned generating the test result of the target storage chip containing the storage page size, the storage block size and the total number of storage blocks, the method further comprises:

[0125] Step S210, generating a test report according to the test result;

[0126] Step S211, sending the test report to the host computer, and / or saving the test report.

[0127] In the embodiment, with reference to Figure 8 After the test device executes step S151 or step S162, the test device can also generate a test report. The test device can generate a test report according to the test result. The test device can also be connected with the host computer, and the test device can send the test report to the host computer; at the same time, the test device can also save the test report. The test device can also not be connected with the host computer, at this time, the test device can directly save the test report. Of course, when the test device is connected with the host computer, the test report can also not be sent to the host computer, but directly saved.

[0128] The application sends a parameter reading command to the target storage chip based on the preset communication protocol, judges whether parameter data fed back by the target storage chip according to the parameter reading command is received; if the parameter data is received, the parameter data is analyzed to obtain a test result; if the parameter data is not received, read-write-erase testing is performed on the target storage chip to obtain a test result; when the parameter data cannot be directly read, the parameter data is determined by performing read-write-erase testing on the target storage chip, thereby obtaining the test result, and the flexibility of parameter testing is improved.

[0129] The application further provides a parameter testing system of the NAND FLASH, which comprises the NAND FLASH and a testing device.

[0130] In the embodiment, the parameter testing system of the NAND FLASH comprises the NAND FLASH and a testing device, and the testing device can comprise a communication interface. Figure 9

[0131] The parameter testing device of the NAND FLASH in the embodiment can be a controller capable of running the parameter testing method of the NAND FLASH, and the controller can be at least one. Figure 10 As shown in the figure, the parameter testing device of the NAND FLASH can comprise a controller 1001 (for example, a CPU), a network interface 1004, a user interface 1003, a memory 1005 and a communication bus 1002. The communication bus 1002 is used to realize the connection and communication among the components. The user interface 1003 can comprise a display screen (Display) and an input unit such as a keyboard (Keyboard), and the optional user interface 1003 can further comprise a standard wired interface and a wireless interface. The network interface 1004 can optionally comprise a standard wired interface and a wireless interface (for example, a WI-FI interface). The memory 1005 can be a high-speed RAM memory or a stable memory (non-volatile memory) such as a disk memory. The memory 1005 can optionally be a storage device independent of the aforementioned controller 1001.

[0132] Those skilled in the art can understand that the structure of the parameter testing device of the NAND FLASH shown in the figure does not constitute a limitation on the parameter testing device of the NAND FLASH, and can comprise more or fewer components than the figure, or combine certain components, or different component arrangements. Figure 10

[0133] As shown in the figure, the memory 1005 as a computer storage medium can comprise an operating system, a network communication module, a user interface module and a computer program. Figure 10 In the embodiment, the parameter testing system of the NAND FLASH comprises the NAND FLASH and a testing device, and the testing device can comprise a communication interface.

[0134] Figure 10 ​​​In the parameter testing device of the NAND FLASH shown, the network interface 1004 is mainly used for connecting a background server and communicating data with the background server; the user interface 1003 is mainly used for connecting a client (user end) and communicating data with the client; and the controller 1001 can be used for calling a computer program stored in the memory 1005, and the computer program is executed by the controller 1001 to realize the steps of the parameter testing method of the NAND FLASH.

[0135] The application further provides a storage medium, which stores a computer program configured to execute the parameter testing method of the NAND FLASH.

[0136] The above description is only some or preferred embodiments of the application, and neither the text nor the drawings can limit the scope of protection of the application. Any equivalent structural transformation, direct / indirect application in other related technical fields, or the like, which is made based on the content of the specification and drawings, is included in the scope of protection of the application.

Claims

1. A method for testing parameters of NAND FLASH, characterized in that, The parameter testing methods for the NAND FLASH include: A parameter read command is sent to the target memory chip based on a preset communication protocol. The target memory chip is the NAND FLASH chip to be tested. Determine whether parameter data has been received from the target storage chip in response to the command to read the parameters. If the parameter data is received, the parameter data is parsed to obtain the test result; If the parameter data is not received, a read-write-erase test is performed on the target memory chip to obtain the test results.

2. The parameter testing method for NAND FLASH according to claim 1, characterized in that, The process of parsing the parameter data to obtain test results includes: The page size, block size, and total number of blocks of the target memory chip are obtained by parsing the parameter data. Generate the test results for the target memory chip, which include the memory page size, the memory block size, and the total number of memory blocks.

3. The parameter testing method for NAND FLASH according to claim 1, characterized in that, The read-write-erase test performed on the target memory chip, and the resulting test results, include: Write tests are performed on the target memory chip to determine the memory page size, and erase tests are performed on the target memory chip to determine the memory block size; Obtain the total capacity of the target memory chip, and determine the total number of memory blocks based on the total capacity and the memory block size; Generate the test results for the target memory chip, which include the memory page size, the memory block size, and the total number of memory blocks.

4. The parameter testing method for NAND FLASH according to claim 3, characterized in that, The step of performing a write test on the target memory chip to determine the memory page size and performing an erase test on the target memory chip to determine the memory block size includes: Generate the first and second data; The target memory chip is written to based on the first data, and erased based on the second data. Determine whether the write test and the erase test were successful; If both the write test and the erase test are successful, the storage page size and storage block size are obtained. If the write test fails, the first data is updated, and the write test on the target memory chip is re-executed based on the first data. If the erase test fails, the second data is updated, and the erase test on the target memory chip is re-executed based on the second data.

5. The parameter testing method for NAND FLASH according to any one of claims 2 or 3, characterized in that, The generation of the test results for the target memory chip, which includes the memory page size, the memory block size, and the total number of memory blocks, includes: Feature data is obtained by extracting features from the storage page size, the storage block size, and the total number of storage blocks; The system queries a preset model database based on the feature data and determines whether the model corresponding to the feature data is found. When the model corresponding to the feature data is found, the model corresponding to the feature data is determined as the target model, and the test result is generated based on the target model, the storage page size, the storage block size, and the total number of storage blocks.

6. The parameter testing method for NAND FLASH according to claim 5, characterized in that, After determining whether the model corresponding to the feature data is found, the method further includes: If the model corresponding to the feature data is not found, the feature data is input into a preset model prediction model to obtain the predicted model. Obtain the memory page size, memory block size, and total number of memory blocks for the predicted model; Determine whether the memory page size, memory block size, and total number of memory blocks of the predicted model are consistent with the memory page size, memory block size, and total number of memory blocks of the target memory chip; When they match, the preset model is determined as the target model, and the test results are generated based on the target model, the storage page size, the storage block size, and the total number of storage blocks; In case of inconsistency, update the preset model prediction model and re-execute the process of inputting the feature data into the preset model prediction model to obtain the predicted model.

7. The parameter testing method for NAND FLASH according to claim 1, characterized in that, Before sending the parameter read command to the target memory chip based on the preset communication protocol, the method further includes: The target protocol command is obtained by traversing the preset protocol command set; Send the target protocol command to the target memory chip; When the target memory chip responds to the target protocol command, the protocol corresponding to the target protocol command is determined to be the preset communication protocol, and the execution of traversing the preset protocol command set to obtain the target protocol command is stopped; When the target memory chip does not respond to the target protocol command, the process continues to traverse the preset protocol command set to obtain the target protocol command.

8. The parameter testing method for NAND FLASH according to any one of claims 2 or 3, characterized in that, After generating the test results for the target memory chip, which include the memory page size, the memory block size, and the total number of memory blocks, the method further includes: A test report is generated based on the test results; Send the test report to the host computer and / or save the test report.

9. A parameter testing system for NAND FLASH, characterized in that, The parameter testing system for NAND FLASH includes NAND FLASH and testing equipment; the parameter testing system for NAND FLASH is capable of executing the parameter testing method for NAND FLASH according to any one of claims 1 to 8.

10. A parameter testing device for NAND FLASH, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that are executed by the at least one processor to enable the at least one processor to perform the parameter testing method for NAND FLASH according to any one of claims 1 to 8.

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