Method of depositing molybdenum nitride film and semiconductor device structure including molybdenum nitride film

Abstract

Methods for depositing a molybdenum nitride film on a substrate surface are disclosed. The method may include providing a substrate into a reaction chamber; and depositing the molybdenum nitride film directly on the surface of the substrate by performing one or more unit deposition cycles of the cyclic deposition process, where the unit deposition cycles may include contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor and contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor. Semiconductor device structures including molybdenum nitride films are also disclosed.

Description

[0001] This application is a divisional application of the application patent application with the application date of 2020-08-18, the application number of 202010830240.X, and the invention name of “Method of Depositing Molybdenum Nitride Film and Semiconductor Device Structure Including Molybdenum Nitride Film”.

[0002] Cross Reference to Related Applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 891,254, filed August 23, 2019, and titled “Method of Depositing Molybdenum Nitride Film on a Substrate Surface by a Cyclic Deposition Process and Related Semiconductor Device Structure Including Molybdenum Nitride Film,” which is incorporated herein by reference. This application is related to U.S. Provisional Patent Application No. 62 / 891,247, filed August 23, 2019, and titled “Method for Forming Polycrystalline Molybdenum Film on a Substrate Surface and Related Structure Including Polycrystalline Molybdenum Film,” the entirety of which is incorporated herein by reference. TECHNICAL FIELD

[0004] The present disclosure generally relates to methods for depositing molybdenum nitride films on a substrate surface, particularly methods of depositing molybdenum nitride films by a cyclic deposition process. The present disclosure also generally relates to semiconductor device structures including molybdenum nitride films. BACKGROUND

[0005] Complementary metal-oxide-semiconductor (CMOS) technology generally utilizes n-type and p-type polysilicon as gate electrode material. However, doped polysilicon can not be an ideal gate electrode material for advanced technology nodes. For example, although doped polysilicon is electrically conductive, there can be a surface region that can deplete carriers under bias. This region of depletion can appear as an additional gate insulator thickness, often referred to as gate depletion, and can affect the equivalent oxide thickness. Although the gate depletion region can be thin, on the order of a few angstroms (A), it can become significant in advanced technology nodes as gate oxide thickness is reduced. In addition, polysilicon does not exhibit an ideal effective work function (eWF) for both NMOS and PMOS devices. To overcome the non-ideal effective work function of doped polysilicon, threshold voltage adjustment implants can be utilized. However, as device geometry is reduced in advanced technology nodes, the threshold voltage adjustment implant process can become increasingly complex.

[0006] To overcome problems associated with doped polysilicon gate electrodes, non-ideal doped polysilicon gate materials can be replaced with alternative materials, such as metals, metal nitrides, and metal carbides. For example, the properties of a metal nitride film can be used to provide a more ideal effective work function for NMOS and PMOS devices, where the effective work function of the gate electrode, i.e., the energy requirement to extract an electron, can be compatible with the barrier height of the semiconductor material. For example, in the case of a PMOS device, the effective work function is approximately 5.0-5.2 eV, and in the case of an NMOS device, the effective work function is approximately 4.1-4.3 eV.

[0007] Accordingly, there is a need for a method for forming low resistivity gate electrodes for NMOS and PMOS devices with preferred effective work functions. SUMMARY

[0008] This Summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in greater detail below in the detailed description of example embodiments of the disclosure. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0009] In some embodiments, a method of depositing a molybdenum nitride film on a substrate surface by a cyclic deposition process is provided. The method can include providing a substrate into a reaction chamber; and depositing a molybdenum nitride film directly on a substrate surface by performing one or more unit deposition cycles of a cyclic deposition process, where a unit deposition cycle includes contacting the substrate with a first gas phase reactant including a molybdenum halide precursor; and contacting the substrate with a second gas phase reactant including a nitrogen precursor.

[0010] In some embodiments of the disclosure, a semiconductor device structure including a molybdenum nitride film is provided. The semiconductor device structure of the disclosure can include a semiconductor channel region; and a gate stack structure disposed directly on the semiconductor channel region, where the gate stack structure includes a gate dielectric disposed directly on the semiconductor channel region; and a molybdenum nitride film disposed directly on the gate dielectric.

[0011] For purposes of summarizing the application and the advantages achieved over the prior art, certain objects and advantages of the application are described herein in the foregoing description. It is to be understood, however, that not necessarily all such objects or advantages can be achieved in accordance with any particular embodiment of the application. Thus, for example, those skilled in the art will recognize that the application can be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as can be taught or suggested herein.

[0012] All of these embodiments are intended to be within the scope of the disclosed application. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description, wherein some embodiments of the application are set forth by reference to the drawings identified below. BRIEF DESCRIPTION OF DRAWINGS

[0013] While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the application, advantages of embodiments of the present disclosure can be provided in some examples by way of example and illustrative embodiments which can be learned by those of ordinary skill in the art by reading the descriptions of some examples of embodiments of the present disclosure when read in conjunction with the drawings in which:

[0014] Figure 1 An exemplary process flow is shown demonstrating a cyclic deposition process for depositing a molybdenum nitride film according to embodiments of the present disclosure;

[0015] Figure 2 An exemplary process flow is shown demonstrating another cyclic deposition process for depositing a molybdenum nitride film according to embodiments of the present disclosure;

[0016] Figure 3 An exemplary process flow is shown demonstrating yet another cyclic deposition process for depositing a molybdenum nitride film according to embodiments of the present disclosure;

[0017] Figure 4 Resistivities of various thicknesses of molybdenum nitride films deposited according to embodiments of the present disclosure are shown;

[0018] Figure 5 Resistivities of various thicknesses of molybdenum nitride films deposited directly on a dielectric are shown compared to resistivities of varying thicknesses of titanium nitride films deposited using a titanium tetrachloride precursor;

[0019] Figure 6 X-ray diffraction (XRD) data obtained from exemplary molybdenum nitride films deposited according to embodiments of the present disclosure are shown;

[0020] Figure 7 A cross-sectional schematic of an exemplary semiconductor device structure including a molybdenum nitride film deposited according to embodiments of the present disclosure is shown;

[0021] Figure 8 A cross-sectional schematic of another semiconductor device structure including a molybdenum nitride film according to embodiments of the present disclosure is shown;

[0022] Figure 9 Effective work functions of various gate stacks including various thicknesses of molybdenum nitride films deposited according to embodiments of the present disclosure are shown;

[0023] Figure 10Effective work functions for other molybdenum nitride films of various thicknesses deposited according to embodiments of the disclosure are shown;

[0024] Figure 11 A schematic diagram showing an exemplary semiconductor device structure including a molybdenum nitride film according to embodiments of the disclosure is shown;

[0025] Figure 12 Another schematic diagram showing an exemplary semiconductor device structure including a molybdenum nitride film according to embodiments of the disclosure is shown; and

[0026] Figure 13 A schematic diagram showing a reaction system configured to deposit a molybdenum nitride film according to embodiments of the disclosure is shown. DETAILED DESCRIPTION

[0027] While certain embodiments and examples are disclosed herein, one of ordinary skill in the art will understand that the invention extends beyond the specifically disclosed embodiments and / or uses and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed herein should not be limited by the particular disclosed embodiments described above.

[0028] In addition, the illustrations presented herein are not meant to be actual views of any particular material, structure or device, but are merely idealized representations that are used to describe the embodiments of the present disclosure.

[0029] As used herein, the term "substrate" can refer to any one or more underlying materials that can be used or upon which a device, circuit, or film can be formed.

[0030] As used herein, the term "cyclical deposition" can refer to the sequential introduction of two or more precursors (reactants) into a reaction chamber to deposit a film over a substrate and includes deposition techniques such as atomic layer deposition (ALD) and cyclical chemical vapor deposition (cyclical CVD).

[0031] As used herein, the term "cyclical chemical vapor deposition" can refer to any process that exposes a substrate sequentially to two or more volatile precursors that react and / or decompose on the substrate to deposit a film.

[0032] As used herein, the term "atomic layer deposition" (ALD) can refer to a vapor deposition process that is carried out in a reaction chamber, preferably a plurality of sequential deposition cycles. Typically, during each unit deposition cycle, a precursor chemisorbs to a deposition surface (e.g., a substrate surface or a previously deposited underlayer surface, such as material from a previous ALD cycle), thereby forming a monolayer or sub-monolayer that is not readily reactive with additional precursors (i.e., self-limiting reaction). Thereafter, if desired, a reactant (e.g., another precursor or a reactive gas) can be subsequently introduced into the reaction chamber for converting the chemisorbed precursor into a desired material on the deposition surface. Typically, this reactant is capable of further reacting with the precursor. Additionally, a purge step can also be utilized during each unit deposition cycle to remove excess precursor and / or excess reactant and / or reaction byproducts from the reaction chamber after conversion of the chemisorbed precursor. Furthermore, the term "atomic layer deposition" as used herein is also intended to include processes designated by related terms such as "chemical vapor atomic layer deposition," "atomic layer epitaxy (ALE)," molecular beam epitaxy (MBE), gas source MBE or organometallic MBE, and chemical beam epitaxy, when carried out using alternating pulses of precursor compositions, reactive gases, and purge (e.g., inert carrier gas) gases.

[0033] As used herein, the term "film" can refer to any physically continuous or discontinuous structure and material formed by the methods disclosed herein. For example, a "film" can include a 2D material, a nanolaminate, a nanorod, a nanotube, or a nanoparticle, or even a partial or complete molecular layer, or a partial or complete atomic layer, or a cluster of atoms and / or molecules. A "film" can also include a material or layer with pinholes, but is still at least partially physically continuous.

[0034] As used herein, the term "molybdenum nitride film" can refer to a film comprising at least a molybdenum component and a nitrogen component.

[0035] As used herein, the term "molybdenum halide precursor" can refer to a reactant comprising at least a molybdenum component and a halide component, where the halide component can include one or more of a chlorine component, an iodine component, or a bromine component.

[0036] As used herein, the term "chalcogen halide molybdenum" can refer to a reactant comprising at least a molybdenum component, a halide component, and a chalcogen component, where the chalcogen is an element from Group IV of the Periodic Table, including oxygen (O), sulfur (S), selenium (Se), and tellurium (Te).

[0037] As used herein, the term "oxygen halide molybdenum" can refer to a reactant comprising at least a molybdenum component, an oxygen component, and a halide component.

[0038] As used herein, the term "reducing agent" can refer to a reactant that donates electrons to another species in an oxidation-reduction chemical reaction.

[0039] As used herein, the term "crystalline film" can refer to a film that exhibits at least short-range order or even long-range order of crystalline structure, and includes single-crystalline films as well as polycrystalline films.

[0040] As used herein, the term "amorphous film" can refer to a film that does not substantially exhibit order of crystalline structure as observed in crystalline films.

[0041] As used herein, the term "gas" can refer to a vapor or a vaporized solid and / or a vaporized liquid, and can be composed of a single gas or a mixture of gases.

[0042] Embodiments of the present disclosure include methods that can be used to deposit molybdenum nitride films and related semiconductor device structures including molybdenum nitride films deposited according to embodiments of the present disclosure. In some embodiments of the present disclosure, the molybdenum nitride films can form part of a gate stack, such as a gate electrode to at least a portion of a transistor device structure. Gate electrodes based on the molybdenum nitride films can provide gate stacks with a preferred effective work function for both PMOS and NMOS devices.

[0043] Existing work function metals employed for gate electrode formation can have limitations due to their inappropriate effective work function values. For example, it is well known that the effective work function of a material can vary with its thickness. Thus, as device geometries decrease in advanced technology nodes, the thickness of corresponding device films such as work function metals for gate electrodes also decreases in thickness, causing the effective work function values of the total gate stack to vary. Such variations in the effective work function of the gate stack can result in non-ideal effective work functions for both NMOS and PMOS device structures.

[0044] In some embodiments of the present disclosure, the resistivity of the deposited molybdenum nitride films can be an important parameter in improving semiconductor device performance, such as in applications where the molybdenum nitride films can be utilized as part of a gate electrode, a liner material (such as for memory applications), a barrier material, a capping material, or a contact layer. As discussed above, next generation technology nodes can require continually decreasing film thicknesses. However, as the film thickness of a conductive film decreases, the resistivity of the conductive film can increase, resulting in a loss of efficiency in the related semiconductor device structure. As a non-limiting example, the molybdenum nitride films of the present disclosure can be utilized as a replacement for common titanium nitride films currently employed in semiconductor device structures. Thus, the resistivity of the molybdenum nitride films of the present disclosure can be lower as compared to the resistivity typically achieved in titanium nitride films having comparable thicknesses.

[0045] Accordingly, embodiments of the present disclosure can include methods of depositing a molybdenum nitride film directly on a substrate surface by a cyclic deposition process. The methods can include providing a substrate into a reaction chamber; and depositing a molybdenum nitride film directly on a substrate surface by performing one or more unit deposition cycles of a cyclic deposition process, wherein a unit deposition cycle includes contacting the substrate with a first gas phase reactant including a molybdenum halide precursor; and contacting the substrate with a second gas phase reactant including a nitrogen precursor.

[0046] The methods of depositing a molybdenum nitride film directly on a substrate surface disclosed herein can include a cyclic deposition process, such as atomic layer deposition (ALD) or cyclic chemical vapor deposition (cyclic CVD).

[0047] Non-limiting example embodiments of a cyclic deposition process can include atomic layer deposition (ALD), in which ALD is based on generally self-limiting reactions whereby about one atomic (or molecular) monolayer of a material is deposited per unit deposition cycle using sequential and alternating pulses of reactants. The deposition conditions and precursors are generally selected to provide a self-saturating reaction such that an adsorbed layer of one reactant leaves a surface termination state that is unreactive with gas phase reactants of the same reactant. The substrate is then contacted with a different reactant that reacts with the previous termination state to enable continued deposition. Thus, each cycle of alternating pulses generally leaves no more than about one monolayer of the desired material. However, as noted above, the skilled artisan will recognize that, for example, more than one monolayer of material can be deposited in one or more ALD cycles if some gas phase reactions occur, even though the process has alternating nature.

[0048] In an example ALD process for forming a molybdenum nitride film directly on a substrate surface, a unit deposition cycle can include exposing the substrate to a first gas phase reactant, removing any unreacted first reactant and reaction byproducts from the reaction chamber, and exposing the substrate to a second gas phase reactant, followed by a second removal step. In some embodiments of the present disclosure, the first gas phase reactant can include a molybdenum halide precursor, and the second gas phase reactant can include a nitrogen precursor.

[0049] The precursors can be separated by an inert gas such as argon (Ar) or nitrogen (N2) to prevent gas phase reactions between the reactants and to achieve a self-saturating surface reaction. In some embodiments, however, the substrate can be moved to contact the first and second gas phase reactants separately. Because the reaction is self-saturating, there is typically no need for strict temperature control of the substrate and precise dose control of the precursors. The substrate temperature is preferably such, however, that the accompanying gas species neither condense into monolayers nor decompose on the surface. Residual chemical species and reaction byproducts, if any, are removed from the substrate surface before contacting the substrate with the next reactive chemical, such as by purging the reaction space or by moving the substrate. Undesired gaseous molecules can be effectively expelled from the reaction space with the aid of an inert purge gas. A vacuum pump can be used to assist in purging.

[0050] Reactors capable of performing a cyclic deposition process can be used to deposit molybdenum nitride films as described herein. Such reactors include ALD reactors configured to provide the precursors as well as CVD reactors. According to some embodiments, a showerhead reactor can be used. According to some embodiments, a cross-flow, batch, small batch, or spatial ALD reactor can be used.

[0051] In some embodiments of the present disclosure, a batch reactor can be used. In some implementations, a vertical batch reactor can be used. For example, a vertical batch reactor can include a reaction chamber and an elevator structured and arranged to move boats configured to support a batch of 10 to 200 substrates in or out of the reaction chamber. In other embodiments, the batch reactor includes a small batch reactor configured to hold 10 or fewer wafers, 8 or fewer wafers, 6 or fewer wafers, 4 or fewer wafers, or 2 or fewer wafers. In some embodiments using a batch reactor, the wafer-to-wafer non-uniformity is less than 3% (1 sigma), less than 2%, less than 1%, or even less than 0.5%.

[0052] The exemplary cyclical deposition processes described herein can optionally be performed in a reactor and associated reaction chambers connected to a cluster tool. In a cluster tool, because each reaction chamber is dedicated to one process type, the temperature of the reaction chamber in each module can be kept constant, which will improve throughput as compared to reactors in which the substrate is heated up to process temperature before each run. Additionally, the time required to pump the reaction chamber down to the process pressure between substrates can be shortened in a cluster tool. In some embodiments of the disclosure, the exemplary cyclical deposition processes for depositing a molybdenum nitride film disclosed herein can be performed in a cluster tool comprising a plurality of reaction chambers, wherein each individual reaction chamber can be used to expose the substrate to an individual precursor gas and the substrate can be transferred between different reaction chambers to be exposed to multiple precursor gases, the transfer of the substrate being performed in a controlled environment to prevent contamination of the substrate. In some embodiments of the disclosure, the cyclical deposition processes described herein can be performed in a cluster tool comprising a plurality of reaction chambers, wherein each individual reaction chamber can be configured to heat the substrate to a different temperature.

[0053] A standalone reactor can be equipped with a load lock. In this case, it is not necessary to cool the reaction chamber between each run.

[0054] According to some non-limiting embodiments of the disclosure, an ALD process can be used to deposit a molybdenum nitride film directly on a substrate surface. In some embodiments of the disclosure, each ALD unit deposition cycle can comprise two different deposition steps or phases. In a first phase of the unit deposition cycle ("moly phase"), the substrate surface on which deposition is desired can be contacted with a first gas phase reactant comprising a molybdenum precursor, which chemisorbs onto the substrate surface, thereby forming at most about one monolayer of the reactant species on the substrate surface. In a second phase of the unit deposition cycle ("nitrogen phase"), the substrate surface on which deposition is desired can be contacted with a second gas phase reactant comprising a nitrogen precursor.

[0055] Reference can be made to Figure 1 An exemplary cyclical deposition process for depositing a molybdenum nitride film directly on a substrate surface is understood, and a diagram illustrating an exemplary atomic layer deposition process 100 for depositing a molybdenum nitride film on a substrate surface is shown.

[0056] In more detail, Figure 1 An exemplary molybdenum nitride deposition process 100 comprising a cyclical deposition phase 105 is shown. The exemplary atomic layer deposition process 100 can begin with a process block 110 comprising providing a substrate into a reaction chamber and heating the substrate to a desired deposition temperature.

[0057] In some embodiments of the disclosure, the substrate can include a planar substrate or a patterned substrate including high aspect ratio features, such as vertical trenches, horizontal trenches, vertical gap features, horizontal gap features, and / or fin structures. The substrate can include one or more materials, including but not limited to semiconductor materials, dielectric materials, and metallic materials. The substrate can also include one or more exposed surfaces, including (but not limited to) semiconductor surfaces, dielectric surfaces, and metallic surfaces.

[0058] In some embodiments, the substrate can include a semiconductor material, such as but not limited to silicon (Si), germanium (Ge), germanium tin (GeSn), silicon germanium (SiGe), silicon germanium tin (SiGeSn), silicon carbide (SiC), or a group III-V semiconductor material.

[0059] In some embodiments, the substrate can include a dielectric material, such as but not limited to a silicon-containing dielectric material and a metal oxide dielectric material. In some embodiments, the substrate can include one or more silicon-containing dielectric materials / surfaces, such as but not limited to silicon dioxide (Si02), silicon sub-oxide, silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon oxycarbide nitride (SiOCN), silicon carbonitride (SiCN). In some embodiments, the substrate can include one or more metal oxide materials / surfaces, such as but not limited to aluminum oxide (AI2O3), hafnium oxide (Hf02), tantalum oxide (Ta205), zirconium oxide (Zr02), titanium oxide (Ti02), hafnium silicon oxide (HfSi02), and lanthanum oxide (La203). x )and lanthanum oxide (La203).

[0060] In some embodiments, the substrate can include an engineered substrate, in which a surface semiconductor layer is disposed above a bulk support, with an intervening buried oxide (BOX) disposed therebetween.

[0061] The patterned substrate can include a substrate that can include semiconductor device structures formed into or on a surface of the substrate. For example, the semiconductor device structures can include partially fabricated semiconductor device structures, such as transistors and memory elements. In some embodiments, the substrate can contain a single crystalline surface and / or one or more subsurfaces, which can include non-single crystalline surfaces, such as polycrystalline surfaces and / or amorphous surfaces.

[0062] The reaction chamber for deposition can be an atomic layer deposition reaction chamber or a chemical vapor deposition reaction chamber or any of the reaction chambers as previously described herein.

[0063] At process block 110 (process 100 continues at process block 112. Figure 1In some embodiments of the cycle deposition phase 105, the substrate can be heated to a deposition temperature for a subsequent cycle deposition phase 105. For example, the substrate can be heated to a substrate temperature of less than about 700 °C, or less than about 600 °C, or less than about 500 °C, or less than about 400 °C, or less than about 300 °C, or even less than about 200 °C. In some embodiments, the substrate temperature during the cycle deposition process 100 can be between about 200 °C and 700 °C, or between about 350 °C and 600 °C, or between about 450 °C and 550 °C.

[0064] In addition to achieving a desired deposition temperature (i.e., a desired substrate temperature), the example cycle deposition process 100 can also regulate the pressure within the reaction chamber during film deposition. For example, in some embodiments, the example cycle deposition process 100 can be performed within a reaction chamber that is regulated to a pressure of less than 300 Torr, or less than 200 Torr, or less than 100 Torr, or less than 50 Torr, or less than 30 Torr, or less than 10 Torr, or less than 5 Torr, or even less than 2 Torr. In some embodiments, the pressure within the reaction chamber during deposition can be regulated to a pressure of between about 2 Torr and 300 Torr, or between 30 Torr and 80 Torr.

[0065] After heating the substrate to a desired deposition temperature and regulating the pressure within the reaction chamber, the example cycle deposition process 100 (e.g., an ALD process) can continue with a cycle deposition phase 105 by way of process block 120, which includes contacting the substrate with a first gas-phase reactant comprising a halogenated molybdenum precursor, i.e., a molybdenum precursor.

[0066] In some embodiments of the present disclosure, the halogenated molybdenum precursor can comprise a molybdenum chloride precursor, a molybdenum bromide precursor, or a molybdenum iodide precursor. For example, the molybdenum chloride can comprise one or more of: molybdenum pentachloride (MoCl5) or molybdenum hexachloride (MoCl6), as non-limiting examples.

[0067] In some embodiments, the halogenated molybdenum precursor can comprise a chalcogenide halogenated molybdenum precursor, such as a molybdenum oxyhalide precursor selected from the group comprising: a molybdenum oxychloride, a molybdenum oxyiodide, and / or a molybdenum oxybromide. In some embodiments, the molybdenum precursor can comprise a molybdenum oxychloride, comprising one of: molybdenum(V)oxychloride (MoOCl3), molybdenum(VI)oxychloride (MoOCl4), or molybdenum(IV)dichloride dioxide (MoO2Cl2).

[0068] In alternative embodiments, the first gas phase reactant, i.e., the molybdenum precursor, can comprise a metal-organic molybdenum precursor, such as Mo(NMe2)4, Mo(NEt2)4, Mo2(NMe2)6, Mo(tBuN)2(NMe2)2, Mo(tBuN)2(NEt2)2, Mo(NEtMe)4, Mo(NtBu)2(StBu)2, Mo(NtBu)2(iPr2AMD)2 Mo(thd)3, MoO2(acac), MoO2(thd)2, and / or MoO2(iPr2AMD)2. The first gas phase reactant can comprise an organometallic molybdenum compound, including but not limited to those containing cyclopentadienyl (Cp) ligands, η 6 - compounds of arene ligands and carbonyl ligands, such as Mo(CO) 6、 - Mo(Cp)2H2, Mo(iPrCp)2H2, Mo(η 6 - Mo(Cp)2H2, Mo(iPrCp)2H2, Mo(η 3 - Mo(Cp)2H2, Mo(iPrCp)2H2, Mo(η

[0069] In at least one embodiment of the present disclosure, the first gas phase reactant can comprise bis(tert-butylimido)bis(dimethylamino)molybdenum(VI). The first gas phase reactant can react with a second gas phase reactant, where the second gas phase reactant can comprise ammonia gas. The resulting molybdenum nitride film can have a work function value, resistivity, and flatband shift suitable for pMOS work function metal applications. This can be due in part to the higher electronegativity of molybdenum compared to titanium or vanadium, for example. Additionally, the lower resistivity of molybdenum nitride enables a higher effective work function.

[0070] In some embodiments of the present disclosure, contacting the substrate with the molybdenum halide precursor can comprise a time period of between about 0.1 seconds and about 60 seconds, between about 0.1 seconds and about 10 seconds, or even between about 0.5 seconds and about 5.0 seconds. Additionally, the flow rate of the molybdenum halide precursor can be less than 1000 seem, or less than 500 seem, or less than 100 seem, or less than 10 seem, or even less than 1 seem during the contacting of the substrate with the molybdenum halide precursor. Additionally, the flow rate of the molybdenum precursor can be in a range of about 1 to 2000 seem, about 5 to 1000 seem, or about 10 to about 500 seem during the contacting of the substrate with the molybdenum halide precursor.

[0071] As determined by Figure 1Exemplary cyclic deposition processes for depositing a molybdenum nitride film can continue with a process 100 illustrated by a purge of the reaction chamber. For example, excess molybdenum halide precursor and reaction byproducts, if any, can be removed from the substrate surface, e.g., by pumping with an inert gas. In some embodiments of the disclosure, the purge process can include a purge cycle in which the substrate surface is purged for a period of less than about 5 seconds, or less than about 3 seconds, or less than about 2 seconds, between about 2 seconds and 5 seconds. Excess molybdenum halide precursor and any possible reaction byproducts can be removed by means of a vacuum generated by a pumping system in fluid communication with the reaction chamber. In some embodiments of the disclosure, the purge cycle after contacting the substrate with the first gas phase reactant can be omitted.

[0072] The exemplary cyclic deposition process 100 can continue with a second stage of the cyclic deposition stage 105 by means of a process block 130, which includes contacting the substrate with a second gas phase reactant, in particular a second gas phase reactant comprising a nitrogen precursor (“nitrogen stage”).

[0073] In some embodiments of the disclosure, the nitrogen precursor can comprise at least one of: molecular nitrogen (N2), ammonia (NH3), hydrazine (N2H4), a hydrazine derivative, or a nitrogen plasma. In some embodiments, the hydrazine derivative can comprise an alkyl-hydrazine, including at least one of: tert-butylhydrazine (C4H9N2H3), methylhydrazine (CH3NHNH2), 1,1-dimethylhydrazine ((CH3)2N2H2), 1,2-dimethylhydrazine, ethylhydrazine, 1,1-diethylhydrazine, 1-ethyl-1-methylhydrazine, isopropylhydrazine, phenylhydrazine, 1,1-diphenylhydrazine, 1,2-diphenylhydrazine, N-amino piperidine, N-amino pyrrole, N-amino pyrrolidine, N-methyl-N-phenylhydrazine, 1-amino-1,2,3,4-tetrahydroquinoline, N-amino piperazine, 1,1-diphenylmethylhydrazine, 1,2-diphenylmethylhydrazine, 1-ethyl-1-phenylhydrazine, 1-aminoazepane, 1-methyl-1-(m-tolyl)hydrazine, 1-ethyl-1-(p-tolyl)hydrazine, 1-aminoimidazole, 1-amino-2,6-dimethylpiperidine, N-aminooxirane, or azo tert-butane. In some embodiments, the nitrogen plasma can be generated by applying RF power to a nitrogen-containing gas, and the nitrogen plasma can comprise atomic nitrogen (N), nitrogen ions, nitrogen radicals, and excited nitrogen species. In some embodiments, the nitrogen plasma can further comprise additional reactive species, e.g., by adding additional gases.

[0074] In some embodiments of the disclosure, contacting the substrate with the nitrogen precursor can include a contact period of between about 0.01 seconds and about 180 seconds, or between about 0.05 seconds and about 60 seconds, or even between about 0.1 seconds and about 10.0 seconds. In some embodiments, the substrate can be exposed to the nitrogen precursor for a period of less than 60 seconds, or less than 30 seconds, or less than 15 seconds, or even less than 5 seconds. In some embodiments, the substrate can be exposed to the nitrogen precursor for a period of between 5 seconds and 60 seconds, or between 5 seconds and 30 seconds. Additionally, during the contacting of the substrate with the nitrogen precursor, the flow rate of the nitrogen precursor can be less than 30 slm, or less than 15 slm, or less than 10 slm, or less than 5 slm, or less than 2 slm, or even less than 1 slm. Additionally, during the contacting of the substrate with the nitrogen precursor, the flow rate of the nitrogen precursor can be in a range of about 0.1 to 30 slm, about 2 to 15 slm, or equal to or greater than 2 slm.

[0075] Following the contacting of the substrate with the nitrogen precursor, the example cyclical deposition process 100 can proceed by purging the reaction chamber, as previously described herein. In some embodiments of the disclosure, the purging cycle following the contacting of the substrate with the nitrogen precursor can be omitted.

[0076] The cyclical deposition phase 105 of the example cyclical deposition process 100 can continue with a decision gate 140, where the decision gate 140 depends on the average film thickness of the deposited molybdenum nitride film. For example, if the deposited molybdenum nitride film is not thick enough for the desired device application, the cyclical deposition phase 105 can be repeated by returning to the process block 120 and continuing further unit deposition cycles, where the unit deposition cycles can include contacting the substrate with a molybdenum halide precursor (process block 120), purging the reaction chamber, contacting the substrate with a nitrogen precursor (process block 130), and again purging the reaction chamber. In some embodiments, the unit deposition cycles of the cyclical deposition phase 105 can omit the purging cycle following the introduction of the precursor.

[0077] The unit deposition cycles of the cyclical deposition phase 105 can be repeated one or more times until a desired average film thickness of the molybdenum nitride film is deposited on the substrate. Once the molybdenum nitride film has been deposited to the desired average film thickness, the example cyclical deposition process 100 can exit via the process block 150, and the substrate having the molybdenum nitride film deposited thereon can be subjected to further processing to form, for example, a semiconductor device structure.

[0078] It will be appreciated that in some embodiments of the disclosure, the order in which the substrate is contacted with the first gas phase reactant (e.g., a molybdenum precursor) and the second gas phase reactant (e.g., a nitrogen precursor) can be such that the substrate is first contacted with the second gas phase reactant and then contacted with the first gas phase reactant. Additionally, in some embodiments, the cycle deposition phase 105 of the example cyclical deposition process 100 can include contacting the substrate with the first gas phase reactant one or more times and then contacting the substrate with the second gas phase reactant one or more times. Additionally, in some embodiments, the cycle deposition phase 105 of the example cyclical deposition process 100 can include contacting the substrate with the second gas phase reactant one or more times and then contacting the substrate with the first gas phase reactant one or more times.

[0079] In some embodiments, the cyclical deposition processes as described herein can include a hybrid ALD / CVD or cyclical CVD process. For example, in some embodiments, the growth rate of an ALD process can be lower as compared to a CVD process. One method of increasing the growth rate can be to operate at a higher substrate temperature than is typically employed in an ALD process, resulting in a portion of a chemical vapor deposition process, but still utilizing the sequential introduction of precursors, such a process can be referred to as a cyclical CVD. In some embodiments, a cyclical CVD process can include the introduction of two or more precursors into a reaction chamber, where there can be an overlap in time between the two or more precursors in the reaction chamber, resulting in an ALD deposition component and a CVD deposition component. By way of example, a cyclical CVD process can include a continuous flow of a first precursor into a reaction chamber and a periodic pulsing of a second precursor into the reaction chamber.

[0080] In some embodiments, a cyclical deposition process for depositing a molybdenum nitride film can include a unit deposition further comprising contacting the substrate with a third gas phase reactant comprising a reducing agent. By way of non-limiting example, in some embodiments, the nitrogen precursor and the reducing agent can be co-flowed into the reaction chamber, i.e., the substrate is simultaneously contacted with the nitrogen precursor and the reducing agent. By way of another non-limiting example, in some embodiments, the nitrogen precursor and the reducing agent can be introduced into the reaction chamber as separate gas pulses, e.g., a purge cycle can be performed between the process of contacting the substrate with the nitrogen precursor and contacting the substrate with the reducing agent.

[0081] In more detail, Figure 2 An example cyclical deposition process 200 for molybdenum nitride deposition is shown. The example process 200 can include a cycle deposition phase 205 including a process block 230 in which the substrate is contacted with a gas comprising a nitrogen precursor and a reducing agent precursor, i.e., the nitrogen precursor and the reducing agent precursor are simultaneously exposed to the substrate.

[0082] An exemplary cyclic deposition process 200 may begin with process block 210, which includes providing a substrate into a reaction chamber and heating the substrate to a desired deposition temperature. Process block 210 may be associated with... Figure 1 The process frame 110 is basically the same, therefore, for the sake of brevity, the description of process frame 210 will not be repeated.

[0083] The exemplary cyclic deposition process 200 can be continued via a cyclic deposition stage 205 initiated by process block 220, which includes contacting the substrate with a molybdenum halide precursor. Process block 220 can be coupled with... Figure 1 The process frame 120 is basically the same, therefore, for the sake of brevity, the description of process frame 220 will not be repeated.

[0084] Exemplary cyclic deposition process 200 ( Figure 2 ) can be done as previously mentioned Figure 1 As described in exemplary process 100, the reaction chamber is purged to continue. In some embodiments of this disclosure, the purge cycle following contact of the substrate with the molybdenum halide precursor may be omitted.

[0085] The exemplary cyclic deposition process 200 can be continued in a second stage of cyclic deposition stage 205 by means of process block 230, which includes contacting the substrate with a gas containing a nitrogen precursor and a reducing agent. In other words, the substrate can be contacted with a gas containing both a nitrogen precursor and a reducing agent. In at least one embodiment of the invention, the single gas contacting the substrate can be both a nitrogen precursor and a reducing agent.

[0086] In some embodiments, the nitrogen precursor may contain previously mentioned... Figure 1 The process block 130 describes one or more of the nitrogen precursors, therefore, for the sake of brevity, the nitrogen precursors that may be used in the exemplary process 200 will not be described again.

[0087] In some embodiments of the disclosure, the substrate can be contacted with the gas comprising a nitrogen precursor and a reducing agent for a period of time between about 0.01 seconds and about 180 seconds, between about 0.05 seconds and about 60 seconds, or between about 0.1 seconds and about 10.0 seconds, or for a period of time less than 60 seconds, or less than 30 seconds, or less than 15 seconds, or even less than 5 seconds. In some embodiments, the substrate can be exposed to the gas comprising a nitrogen precursor and a reducing agent for a period of time between about 5 seconds and 60 seconds, or between about 5 seconds and 30 seconds. Additionally, during the contacting of the substrate with the gas comprising both a nitrogen precursor and a reducing agent, the flow rate of the nitrogen precursor can be less than 30 slm, or less than 15 slm, or less than 10 slm, or less than 5 slm, or less than 2 slm, or less than 1 slm, or even between about 1 slm and 30 slm. Additionally, the flow rate of the reducing agent can be less than 30 slm, or less than 15 slm, or less than 10 slm, or less than 5 slm, or less than 2 slm, or even between about 2 slm and 30 slm.

[0088] As previously described herein, the exemplary cyclical deposition process 200 can continue with a purge of the reaction chamber. In some embodiments of the disclosure, the purge cycle after contacting the substrate with the nitrogen precursor / reducing agent can be omitted.

[0089] The cyclical deposition phase 205 of the exemplary cyclical deposition process 200 can continue with a decision gate 240, where the decision gate 240 depends on the average film thickness of the deposited molybdenum nitride film. For example, if the deposited molybdenum nitride film is not of sufficient average film thickness for the desired device application, the cyclical deposition phase 205 can be repeated by returning to the process block 220 and continuing further unit deposition cycles, where the unit deposition cycles can include contacting the substrate with a molybdenum halide precursor (process block 220), purging the reaction chamber, contacting the substrate with a gas comprising a nitrogen precursor and a reducing agent (process block 230), and again purging the reaction chamber. In some embodiments, the unit deposition cycles of the cyclical deposition phase 205 can omit the purge cycle after introduction of the precursor.

[0090] The unit deposition cycles of the cyclical deposition phase 205 can be repeated one or more times until a molybdenum nitride film of a desired average film thickness is deposited on the substrate. Once the molybdenum nitride film has been deposited to the desired average film thickness, the exemplary cyclical deposition process 200 can exit via the process block 250, and the substrate having the molybdenum nitride film deposited thereon can be subjected to further processing to form, for example, a device structure.

[0091] It should be understood that in some embodiments of this disclosure, the contact sequence between the substrate and the molybdenum halide precursor and the gas containing the nitrogen precursor and the reducing agent may be as follows: first, the substrate is contacted with the gas containing the nitrogen precursor and the reducing agent, and then with the molybdenum halide precursor. Additionally, in some embodiments, the cyclic deposition stage 205 of the exemplary process 200 may include contacting the substrate with the molybdenum halide precursor once or multiple times, and then contacting the substrate with the gas containing the nitrogen precursor and the reducing agent once or multiple times. Furthermore, in some embodiments, the cyclic deposition stage 205 of the exemplary process 200 may include contacting the substrate with the gas containing the nitrogen precursor and the reducing agent once or multiple times, and then contacting the substrate with the molybdenum halide precursor once or multiple times.

[0092] In some embodiments, an exemplary cyclic deposition process for depositing a molybdenum nitride film may include separate pulses of a nitrogen precursor and a reducing agent, for example, a purge cycle may be performed between contacting the substrate with the nitrogen precursor and contacting the substrate with the reducing agent.

[0093] More in detail, Figure 3 An exemplary cyclic deposition process 300 including a cyclic deposition stage 305 is shown. In some embodiments, the cyclic deposition stage 305 may include a process block 330 for contacting the substrate with a nitrogen precursor and a process block 340 for contacting the substrate with a reducing agent, i.e., the substrate may be exposed to the nitrogen precursor and the reducing agent separately.

[0094] An exemplary cyclic deposition process 300 may begin with process block 310, which includes providing a substrate into a reaction chamber and heating the substrate to a desired deposition temperature. Process block 310 may be associated with... Figure 1 The process frame 310 is basically the same as that of process frame 110, therefore, for the sake of brevity, the description of process frame 310 will not be repeated.

[0095] An exemplary cyclic deposition process 300 can be continued via a cyclic deposition stage 305 initiated by process block 320, which includes contacting the substrate with a molybdenum halide precursor. Process block 320 can be coupled with... Figure 1 The process frame 120 is basically the same, therefore, for the sake of brevity, the description of process frame 220 will not be repeated.

[0096] Exemplary cyclic deposition stage 305 of exemplary cyclic deposition process 300 Figure 3 ) can be done as previously mentioned Figure 1 As described in exemplary process 100, the reaction chamber is purged to continue. In some embodiments of this disclosure, the purge cycle following contact of the substrate with the molybdenum halide precursor may be omitted.

[0097] Exemplary cyclic deposition process 300 ( Figure 3The process can be continued in a second stage of cyclic deposition stage 305 using process frame 330, which includes contacting the substrate with the nitrogen precursor. Process frame 330 can be used with... Figure 1 The process frame 130 is basically the same, therefore, for the sake of simplicity, the description of process frame 330 will not be repeated.

[0098] Exemplary cyclic deposition stage 300 of process 300 ( Figure 3 ) can be done as previously mentioned Figure 1 As described in exemplary process 100, the reaction chamber is purged to continue. In some embodiments of this disclosure, the purging cycle following contact of the substrate with the nitrogen precursor may be omitted.

[0099] The exemplary cyclic deposition process 300 can be continued by means of a third stage of cyclic deposition stage 305, which includes contacting the substrate with a reducing agent, via process frame 340. In some embodiments of this disclosure, the reducing agent precursor may be selected from those previously described with respect to process frame 230; therefore, for the sake of brevity, the reducing agent used in process 220 is not repeated.

[0100] In some embodiments of this disclosure, the substrate may be in contact with the reducing agent for a period of time between about 0.01 seconds and about 180 seconds, between about 0.05 seconds and about 60 seconds, or between about 0.1 seconds and about 10.0 seconds, or for a period of time less than 60 seconds, or less than 30 seconds, or less than 15 seconds, or even less than 5 seconds. In some embodiments, the substrate may be exposed to the reducing agent precursor for a period of time between 5 seconds and 60 seconds, or between 5 seconds and 30 seconds. Additionally, during the contact of the substrate with the reducing agent, the flow rate of the reducing agent precursor may be less than 100 slm, or less than 50 slm, or less than 25 slm, or less than 10 slm, or less than 5 slm, or even between about 5 slm and 100 slm.

[0101] Exemplary cyclic deposition process 300 ( Figure 3 ) can be done as previously mentioned Figure 3 As described in exemplary process 100, the reaction chamber is purged to continue. In some embodiments of this disclosure, the purging cycle following contact of the substrate with the reducing agent may be omitted.

[0102] Cyclic deposition stage 305 of exemplary process 300 ( Figure 4The decision gate 350 can continue, where the decision gate 350 depends on the average film thickness of the deposited molybdenum nitride film. For example, if the deposited molybdenum nitride film is not of sufficient average film thickness for the desired device application, the cycle deposition phase 305 can be repeated by returning to the process block 320 and continuing further unit deposition cycles, where the unit deposition cycles can include contacting the substrate with a molybdenum halide precursor (process block 320), purging the reaction chamber, contacting the substrate with a nitrogen precursor (process block 330), purging the reaction chamber, contacting the substrate with a reducing agent (process block 340), and again purging the reaction chamber. In some embodiments, the unit deposition cycles of the cycle deposition phase 305 can omit the purging cycles after introduction of the precursors.

[0103] The unit deposition cycles of the cycle deposition phase 305 can be repeated one or more times until a desired average film thickness of the molybdenum nitride film is deposited on the substrate. Once the molybdenum nitride film has been deposited to the desired average film thickness, the example cycle deposition process 300 can exit via the process block 360, and the substrate having the molybdenum nitride film deposited thereon can be subjected to further processing to form, for example, a device structure.

[0104] It should be appreciated that in some embodiments of the present disclosure, the order of contacting the substrate with the molybdenum halide precursor, the nitrogen precursor, and the reducing agent can be in any conceivable sequence order, and is not limited to the sequence order shown in FIG. 3. Additionally, the contacting of the substrate with a particular precursor, such as the molybdenum halide precursor, the nitrogen precursor, or the reducing agent, can be repeated one or more times prior to executing the subsequent process blocks of the cycle deposition phase 305. Figure 1

[0105] The example deposition processes disclosed herein can deposit a molybdenum nitride film on a substrate surface at a growth rate of about 0.05 A / cycle to about 10 A / cycle, about 0.5 A / cycle to about 5 A / cycle, or even about 0.5 A / cycle to about 2 A / cycle. In some embodiments, the molybdenum nitride film is grown on the substrate surface at a growth rate of more than about 0.5 A / cycle, more than about 1 A / cycle, or even more than about 2 A / cycle. In some embodiments of the present disclosure, the molybdenum nitride film can be deposited at a growth rate of between 0.5 A / cycle and 1 A / cycle or between 0.8 A / cycle and 1 A / cycle, or at a deposition temperature, i.e., substrate temperature, of between 300 °C and 700 °C, or between 400 °C and 500 °C, or even less than 450 °C.

[0106] The molybdenum nitride film deposited by the methods disclosed herein can be a physically continuous film. In some embodiments, the molybdenum nitride film can be physically continuous at an average film thickness of less than about 100 A, or less than about 60 A, or less than about 50 A, or less than about 40 A, or less than about 30 A, or about 20 A, or even between about 20 A and 100 A.​

[0107] In some embodiments, the film can be made physically continuous at an average film thickness that can be different than the average film thickness at which the film is made electrically continuous, or vice versa.

[0108] In some embodiments, a molybdenum nitride film deposited according to the methods disclosed herein can be physically continuous at an average film thickness of less than 40 A, or less than 30 A, or less than 20 A, or less than 10 A, or even between approximately 10 A and 40 A. In other words, the molybdenum nitride film can have an average film thickness of less than 40 A, or less than 30 A, or less than 20 A, less than 10 A, or even between approximately 10 A and 40 A. The thickness at which the film becomes physically continuous can be determined using low energy ion scattering (LEIS).

[0109] In some embodiments, a molybdenum nitride film of the present disclosure can have an average film thickness of between approximately 20 A and 250 A, or between approximately 50 A and 200 A, or even between approximately 100 A and 150 A. In some embodiments, a molybdenum nitride film of the present disclosure can have an average film thickness of greater than approximately 20 A, or greater than approximately 30 A, or greater than approximately 40 A, or greater than approximately 50 A, or greater than approximately 60 A, or greater than approximately 100 A, or greater than approximately 250 A, or greater than approximately 500 A, or even between approximately 20 A and 500 A. In some embodiments, a molybdenum nitride film of the present disclosure can have an average film thickness of less than approximately 250 A, or less than approximately 100 A, or less than approximately 50 A, or less than approximately 25 A, or less than approximately 10 A, or less than approximately 5 A, or even between approximately 5 A and 250 A.

[0110] In some embodiments, a molybdenum nitride film deposited according to the methods disclosed herein can comprise a low resistivity molybdenum nitride film. In more detail, Figure 2 The resistivity of a plurality of molybdenum nitride films of various thicknesses deposited according to embodiments of the present disclosure is shown, where the data labeled 400 comprises a molybdenum nitride film deposited by the cyclic deposition process 100 of Figure 3 , the data labeled 410 comprises a molybdenum nitride film deposited by the cyclic deposition process 200 of Figure 4 , and the data labeled 420 comprises a molybdenum nitride film deposited by the cyclic deposition process 300 of Figure 4 . Figure 5 An examination of the resistivity data of Figure 5Further examination of the data clearly shows that the pulsed introduction of the nitrogen precursor and reducing agent alone (process 300 / data labeled 420) further reduces the resistivity of the deposited molybdenum nitride film compared to the molybdenum nitride film deposited with the co-flow of the nitrogen precursor and reducing agent (process 200 / data labeled 410).

[0111] As a non-limiting example, a molybdenum nitride film deposited according to embodiments of the disclosure can have a resistivity of less than 750 μΩ-cm at an average film thickness of less than 200 Å, or less than 750 μΩ-cm at an average film thickness of less than 100 Å, or less than 1300 μΩ- cm at an average film thickness of less than 25 Å.

[0112] As another non-limiting example, a molybdenum nitride film deposited according to embodiments of the disclosure can have a resistivity of less than 550 μΩ-cm at an average film thickness of less than 200 Å, or less than 550 μΩ-cm at an average film thickness of less than 100 Å, or less than 950 μΩ-cm at an average film thickness of less than 25 Å.

[0113] As another non-limiting example, a molybdenum nitride film deposited according to embodiments of the disclosure can have a resistivity of less than 250 μΩ-cm at an average film thickness of less than 200 Å, or less than 250 μΩ-cm at an average film thickness of less than 100 Å, or less than 600 μΩ-cm at an average film thickness of less than 25 Å.

[0114] In some embodiments, for a molybdenum nitride film having an average film thickness between about 10 Å and 200 Å, or between about 20 Å and 100 Å, or even between about 20 Å and 50 Å, a molybdenum nitride film deposited according to embodiments of the disclosure can have a resistivity between 250 μΩ-cm and 1000 μΩ-cm, or between 250 μΩ-cm and 750 μΩ-cm, or even between 250 μΩ-cm and 500 μΩ-cm.

[0115] The superior resistivity of the molybdenum nitride films deposited by embodiments of the disclosure is further demonstrated in Figure 5 which shows the resistivity of a plurality of molybdenum nitride films of various thicknesses deposited on a dielectric substrate according to embodiments of the disclosure. Additionally, Figure 5 The molybdenum films of the present disclosure are also compared to the resistivity of prior art titanium nitride films of varying thicknesses deposited using a titanium tetrachloride precursor. Data labeled 500 corresponds to a titanium nitride film deposited with titanium tetrachloride (TiCl4). Figure 5 All films shown in FIG. 5 were deposited on an exposed surface of a dielectric material.

[0116] In more detail, the data labeled 510 corresponds to a molybdenum nitride film deposited on a silicon oxide substrate, and the data labeled 520 corresponds to a molybdenum nitride film deposited on a hafnium oxide (Hf02) substrate. Figure 6 The exemplary molybdenum nitride films shown were deposited at a deposition temperature, i.e., substrate temperature, of less than about 500 °C using molybdenum (IV) dioxide dichloride (M0O2CI2) as the molybdenum halide precursor, ammonia (NH3) as the nitrogen precursor, and hydrogen gas (H2) as the reducing agent.

[0117] Figure 1 An examination of the resistivity data in Table 1 clearly indicates that the molybdenum nitride films of the present disclosure have a reduced resistivity at a reduced average film thickness when compared to the resistivity of comparable thickness titanium nitride films of the prior art.

[0118] As non-limiting examples, the molybdenum nitride films of the present disclosure can have a resistivity of less than 250 μΩ-cm at an average film thickness of less than 50 Å, or a resistivity of less than 300 μΩ-cm at an average film thickness of less than 40 Å, or a resistivity of less than 400 μΩ-cm at an average film thickness of less than 25 Å. In some embodiments, the molybdenum nitride films of the present disclosure can have a resistivity of between about 250 μΩ-cm and 400 μΩ-cm at an average film thickness of less than 50 Å.

[0119] In some embodiments, the molybdenum nitride films deposited according to the embodiments disclosed herein can comprise a crystalline film or an amorphous film. In particular embodiments in which the molybdenum nitride film is crystalline, the molybdenum nitride film can comprise a MoN phase or a Mo2N phase. In some embodiments, the molybdenum nitride film can comprise both a MoN phase and a Mo2N phase.

[0120] In more detail, Figure 2 X-ray diffraction (XRD) data obtained from exemplary molybdenum nitride films deposited according to embodiments of the present disclosure are shown, wherein the XRD data labeled 600 comprises a molybdenum nitride film deposited by the cyclical deposition process 100 of Figure 3 the XRD data labeled 610 comprises a molybdenum nitride film deposited by the cyclical deposition process 200 of Figure 6 the data labeled 620 comprises a molybdenum nitride film deposited by the cyclical deposition process 300 of Figure 6 the data labeled 620 comprises a molybdenum nitride film deposited by the cyclical deposition process 300 of Figure 7 An examination of the XRD data of Table 2 indicates that there is no significant difference between the XRD data of the molybdenum nitride films deposited by processes 100, 200, or 300. However, Figure 7Further examination of the XRD data of Sample 1 shows four main peaks in the XRD data labeled 630, 640, 650, and 660. The XRD peak labeled 630 corresponds to a MoN phase with a (200) crystal orientation and a Mo2N phase with a (111) crystal orientation. The XRD peak labeled 640 corresponds to a Mo2N phase with a (200) crystal orientation. The XRD peak labeled 650 corresponds to a MoN phase with a (220) crystal orientation and a Mo2N phase with a (200) crystal orientation. The XRD peak labeled 660 corresponds to a MoN phase with a (222) crystal orientation and a Mo2N phase with a (311) crystal orientation.

[0121] In embodiments where the composition of the deposited molybdenum nitride film includes at least a MoN phase and a Mo2N phase, the ratio of the MoN phase present within the molybdenum nitride film to the Mo2N phase present within the molybdenum nitride film (MoN:Mo2) can be controlled during the cyclic deposition process of the present disclosure. For example, the MoN:Mo2N ratio can be varied by changing the cyclic deposition parameters of the molybdenum nitride deposition, including, but not limited to, deposition temperature, reaction chamber pressure, precursor concentration, or addition of other gas species.

[0122] In some embodiments, the MoN phase of molybdenum nitride can be preferred over the Mo2N phase of molybdenum nitride, i.e., the MoN:Mo2N ratio is increased. As a non-limiting example, the MoN phase can be preferentially deposited over the Mo2N phase by adding a reducing agent to the deposition process.

[0123] The exemplary cyclic deposition methods disclosed herein can also deposit molybdenum nitride films having improved average r.m.s. surface roughness. For example, in some embodiments, the molybdenum nitride film can have an average r.m.s. surface roughness (R a The average r.m.s. surface roughness (R a ) of the as-deposited molybdenum nitride film can be determined using an atomic force microscope (AFM), for example, by scanning a surface area of approximately 100 μm x 100 μm.

[0124] In some embodiments, the surface roughness of the molybdenum nitride film can be expressed as a percentage of the roughness to the average total thickness of the molybdenum nitride film. For example, the surface roughness percentage of the molybdenum nitride film of the present disclosure can be less than 10%, or less than 5%, or less than 3%, or less than 2%, or less than 1.5%, or even less than 1%. As a non-limiting example, a molybdenum nitride film deposited according to embodiments of the present disclosure can have an average film thickness of approximately 100 A, wherein the molybdenum nitride film has an r.m.s. surface roughness (Ra ) and less than 4% of a corresponding surface roughness percentage.

[0125] In some embodiments, the substrate can include at least one of a dielectric surface, a semiconductor surface, or a metal surface. As used herein, the term "dielectric surface" can refer to a surface of a dielectric material, including but not limited to, for example, silicon-containing dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and mixtures thereof, as well as metal oxides. As used herein, the term "metal surface" can refer to a surface that includes a metal component, including but not limited to metal surfaces, metal oxide surfaces, metal silicide surfaces, metal nitride surfaces, and metal carbide surfaces. In some embodiments, the substrate can include both a dielectric surface and a metal surface, and the cyclic deposition process of the present disclosure can be used to deposit a molybdenum nitride film directly on both the dielectric surface and the metal surface, i.e., without using an intermediate nucleation layer.

[0126] Molybdenum nitride films deposited according to embodiments of the present disclosure can be used for a variety of applications. For example, molybdenum nitride films can be used as a barrier layer material to prevent diffusion of metal species into interlayer dielectrics, or as a liner material, or as part of a gate stack formed on a semiconductor device structure.

[0127] As a non-limiting example embodiment, molybdenum nitride films deposited according to embodiments of the present disclosure can be used as a barrier layer in back end of line (BEOL) metallization applications, as shown in FIG. 1 of U.S. Patent No. 8,992, 1 1 1, the disclosure of which is incorporated herein by reference in its entirety. In more detail, FIG. 1 of U.S. Patent No. 8,992, 1 1 1 shows a partially fabricated semiconductor device structure 100, which includes a substrate 102 that can include a partially fabricated and / or fabricated semiconductor device structure, such as transistors and memory elements (not shown). The partially fabricated semiconductor device structure 100 can include a dielectric material 104 formed over the substrate 102, which can include a low dielectric constant material, i.e., a low-k dielectric, such as a silicon-containing dielectric or a metal oxide dielectric. A trench can be formed in the dielectric material 104, and a barrier layer 106 can be disposed on the surface of the trench, which prevents or substantially prevents diffusion of a metal interconnect material 108 into the surrounding dielectric material 104. In some embodiments of the present disclosure, the barrier layer 106 can include a molybdenum nitride film deposited by the deposition processes described herein. Figure 7 Figure 8 A partially fabricated semiconductor device structure 700 is shown, which includes a substrate 702 that can include a partially fabricated and / or fabricated semiconductor device structure, such as transistors and memory elements (not shown). The partially fabricated semiconductor device structure 700 can include a dielectric material 704 formed over the substrate 702, which can include a low dielectric constant material, i.e., a low-k dielectric, such as a silicon-containing dielectric or a metal oxide dielectric. A trench can be formed in the dielectric material 704, and a barrier layer 706 can be disposed on the surface of the trench, which prevents or substantially prevents diffusion of a metal interconnect material 708 into the surrounding dielectric material 704. In some embodiments of the present disclosure, the barrier layer 706 can include a molybdenum nitride film deposited by the deposition processes described herein.

[0128] The partially fabricated semiconductor structure 700 can also include a metal interconnect material 708 for electrically interconnecting a plurality of device structures disposed in / on the substrate 702. In some embodiments, the metal interconnect material 708 can include copper or cobalt. Additionally, a cap layer 710 can be disposed on the upper surface of the metal interconnect 708. Thus, with reference to FIG. 2 of U.S. Patent No. 8,992, 1 1 1, the metal interconnect material 708 can include a copper interconnect 720 and a cobalt cap layer 722 disposed on the copper interconnect 720. Figure 9 ​semiconductor device structure 700 can also include a capping layer 710 disposed directly on an upper surface of the metal interconnect material 708. The capping layer 710 can be utilized to prevent oxidation of the metal interconnect material 708, and importantly, to prevent diffusion of the metal interconnect material 708 into additional dielectric material formed over the partially fabricated semiconductor structure 700 in subsequent fabrication processes, i.e., for a multi-level interconnect structure. In some embodiments, the metal interconnect material 708, the molybdenum nitride barrier layer 706, and the capping layer 710 can collectively form an electrode for electrical interconnection of a plurality of semiconductor devices disposed in / on the substrate 702. In some embodiments, the capping layer 710 can comprise a molybdenum nitride film deposited in accordance with embodiments of the present disclosure.

[0129] As another non-limiting example, a molybdenum nitride film of the present disclosure can comprise at least a portion of a gate electrode in a gate stack formed on a semiconductor channel region. In more detail, Figure 9 A cross-sectional schematic of a semiconductor device structure is shown, including a molybdenum nitride film deposited in accordance with embodiments of the present disclosure. The semiconductor device structure 800 can comprise a transistor structure including a semiconductor body 816 including a source region 802, a drain region 804, and a semiconductor channel region 806 disposed between the source region 802 and the drain region 804.

[0130] In some embodiments, the semiconductor device structure 800 can comprise an NMOS device, and both the semiconductor body 816 and the semiconductor channel region 806 can be doped p-type, and both the source region 802 and the drain region 804 can be doped n-type. In alternative embodiments, the semiconductor device structure 800 can comprise a PMOS device, and both the semiconductor body 816 and the semiconductor channel region 806 can be doped n-type, and both the source region 802 and the drain region 804 can be doped p-type. In some embodiments, the semiconductor body 816 can comprise substantially single crystalline silicon.

[0131] Disposed on the semiconductor channel region 806 is a gate stack 808, which can include a gate dielectric 809 and a gate electrode 811. In some embodiments, the gate dielectric can include a silicon oxide interface layer 816 disposed directly on the semiconductor channel region 806, and a high-k dielectric layer 812 disposed directly on the interface layer 816. In some embodiments of the present disclosure, the high-k dielectric layer 812 can comprise at least one of hafnium oxide (Hf02), tantalum oxide (Ta205), zirconium oxide (Zr02), titanium oxide (Ti02), hafnium silicate (HfSi02), lanthanum oxide (La203), or mixtures / laminates thereof. x

[0132] ​A gate electrode 811 is disposed over a gate dielectric 809, and in some embodiments, directly on the gate dielectric 809, which can include a molybdenum nitride film 810 deposited according to embodiments of the disclosure. Another metal film 814 can be disposed directly over the molybdenum nitride film 810 to complete the gate electrode 811, for example, the other metal film 814 can include a transition metal carbide (e.g., titanium carbide) or a transition metal nitride (e.g., titanium nitride).

[0133] In some embodiments of the disclosure, the effective work function of the gate stack 808 disposed over the semiconductor channel region 806 can be adjusted by the deposition method used to deposit the molybdenum nitride film 810 and the average film thickness of the molybdenum nitride film 810. For example, the effective work function of a gate stack 808 including a molybdenum nitride film can be in the range of about 4 eV to about 5 eV, or greater than 4, or greater than 4.5 eV, or greater than 4.75 eV, at an average molybdenum nitride film thickness of less than 50 A, or less than 40 A, or less than 30 A, or less than 20 A, or less than 20 A, or less than 15 A, or between 15 A and 50 A.

[0134] Thus, in some embodiments, a molybdenum nitride film includes a portion of a gate stack formed on a semiconductor channel region, where the effective work function of the gate stack is greater than 4.0 eV, or greater than 4.5 eV, or greater than 4.75 eV, or even greater than 4.9 eV, or between 4 eV and 5 eV, at an average molybdenum nitride film thickness of less than 50 A, or less than 40 A, or less than 30 A, or less than 20 A, or less than 20 A, or less than 15 A, or between 15 A and 50 A.

[0135] As non-limiting examples, Figure 10 The effective work function of a gate stack (disposed on a semiconductor channel region) including a molybdenum nitride film deposited according to embodiments of the disclosure is shown for various average film thicknesses. Figure 3Inspection of the data in Table 1 indicates that as the average film thickness of the molybdenum nitride layer is reduced from about 50 A to 15 A, the corresponding effective work function of the gate stack including the molybdenum nitride film only slightly decreases from about 4.75 eV to about 4.6 eV. Thus, in some embodiments of the disclosure, the molybdenum nitride film of the disclosure can constitute a portion of a gate stack having an effective work function greater than 4 eV, or greater than 4.25 eV, or greater than 4.5 eV, or greater than 4.75 eV, or greater than 4.8 eV, or between 4 eV and 4.8 eV, or between 4.6 eV and 4.75 eV at an average molybdenum nitride film thickness less than 50 A, or less than 40 A, or less than 30 A, or less than 20 A, or less than 15 A, or between 15 A and 50 A. In some embodiments, the gate stack disposed on a semiconductor channel region and including a molybdenum nitride film has an effective work function greater than 4.75 eV at an average molybdenum nitride film thickness equal to or less than 50 A.

[0136] As another non-limiting example, Figure 10 effective work functions of gate stacks including molybdenum nitride films deposited utilizing the exemplary cyclical deposition process 300 Figure 11 ) of varying average film thickness are shown. Figure 11 Inspection of the data in Table 1 indicates that as the average film thickness of the molybdenum nitride layer is reduced from about 50 A to 15 A, the corresponding effective work function of the gate stack including the molybdenum nitride film only slightly decreases from about 4.75 eV to about 4.6 eV. Thus, in some embodiments of the disclosure, the molybdenum nitride film of the disclosure can constitute a portion of a gate stack having an effective work function greater than 4 eV, or greater than 4.25 eV, or greater than 4.5 eV, or greater than 4.75 eV, or greater than 4.8 eV, or between 4 eV and 4.8 eV, or between 4.6 eV and 4.75 eV at an average molybdenum nitride film thickness less than 50 A, or less than 40 A, or less than 30 A, or less than 20 A, or less than 15 A, or between 15 A and 50 A. In some embodiments, the gate stack disposed on a semiconductor channel region and including a molybdenum nitride film has an effective work function greater than 4.75 eV at an average molybdenum nitride film thickness equal to or less than 50 A.

[0137] In some device applications, such as PMOS device structures, the ability to form a gate stack including a molybdenum nitride film in which the effective work function of the gate stack is substantially independent of the average film thickness of the molybdenum nitride film can be desirable.

[0138] Accordingly, in some embodiments, a gate stack can include a molybdenum nitride film having an average film thickness between approximately 15 A and 45 A, where the effective work function of the gate stack can have an effective work function that is substantially independent of the average film thickness of the molybdenum nitride film. Additionally, a gate stack including a molybdenum nitride film can include an effective work function of substantially constant approximately 4.8 eV at an average film thickness of the molybdenum nitride film between approximately 15 A and 45 A. Moreover, the gate stack can include a molybdenum nitride film deposited by a cyclic deposition process including contacting a substrate sequentially with a molybdenum halide precursor, a nitrogen precursor, and a reducing agent, where the gate stack includes an effective work function of substantially constant approximately 4.8 eV at an average molybdenum nitride film thickness between approximately 15 A and 45 A.

[0139] As another non-limiting application of the molybdenum nitride films of the present disclosure, Figure 12 Another cross-sectional schematic of an exemplary semiconductor device structure is shown, including a molybdenum nitride film deposited according to embodiments of the present disclosure, and specifically a FinFet semiconductor device structure is shown.

[0140] In more detail, Figure 13 A non-limiting example of a semiconductor device structure 1100 including an exemplary FinFET device structure is shown. The semiconductor device structure 1100 can include a substrate 1102, which can include a bulk silicon (Si) substrate. The substrate 1102 can be doped with p-type dopants (for NMOS type FinFET devices) and / or with n-type dopants (for PMOS type FinFET devices).

[0141] The semiconductor device structure 1100 can also include an isolation region 1104, which can include a shallow trench isolation (STI) region. The semiconductor device structure 1100 can also include a fin structure 1106 extending above a top surface of the isolation region 1104, the fin structure 1106 partially buried below a gate stack 1108 including a semiconductor channel region. A gate dielectric 1110 can be disposed above sidewalls of the fin structure 1106 and the gate dielectric 1110 can include silicon oxide and / or a high-k dielectric material.

[0142] A gate electrode can be disposed on the gate dielectric 1110 to provide electrical contact with the semiconductor channel region, and the gate electrode can include a molybdenum nitride film 1112 deposited according to embodiments of the present disclosure, and an additional metal film 1114 that can include a transition metal carbide or a transition metal nitride. In some embodiments of the present disclosure, the semiconductor device structure 1100 can further include a source / drain region 1116 adjacent to the semiconductor channel region.

[0143] As another non-limiting application of the molybdenum nitride films of the present disclosure,Figure 13 Another schematic of an exemplary semiconductor device structure is shown, including a molybdenum nitride film deposited according to embodiments of the disclosure, and specifically a gate-all-around (GAA) semiconductor device structure is shown.

[0144] In more detail, the semiconductor device structure 1200 can include a semiconductor substrate 1202 and a dielectric film 1204 disposed above the substrate 1202. Further, the GAA device structure can include a semiconductor line 1206 (doped p-type or n-type) with a gate dielectric 1208 disposed around and encasing the semiconductor line 1206. A gate electrode can be disposed around a region of the semiconductor line 1206 and can include a molybdenum nitride film 1210 deposited according to embodiments of the disclosure. Additionally, the gate electrode can include another metal film 1212, such as a transition metal carbide or a transition metal nitride.

[0145] Embodiments of the disclosure also provide semiconductor device structures including a molybdenum nitride film. In some embodiments, a semiconductor device structure can include: a semiconductor channel region; and a gate stack disposed directly on the semiconductor channel region, wherein the gate stack includes: a gate dielectric disposed directly on the semiconductor channel region and a gate electrode including a molybdenum nitride film disposed directly on the gate dielectric.

[0146] In some embodiments, a semiconductor device structure can include a molybdenum nitride film that can have a resistivity of less than 1000 μΩ-cm, or less than 500 μΩ-cm, or less than 250 μΩ-cm, or between 250 μΩ-cm and 1000 μΩ-cm at an average molybdenum nitride film thickness of less than 100 Å, or between 10 Å and 50 Å, or less than 20 Å, or less than 10 Å. In some embodiments, a semiconductor device structure can include a molybdenum nitride film that can have a resistivity of less than 250 μΩ-cm at an average film thickness of less than 100 Å. In some embodiments, a semiconductor device structure can include a molybdenum nitride film that can have a resistivity of less than 500 μΩ-cm at an average film thickness of less than 25 Å.

[0147] In some embodiments, a semiconductor device structure including a molybdenum nitride film can include a MoN phase and a Mo2N phase. In some embodiments, a semiconductor device structure includes a physically continuous molybdenum nitride film having an average film thickness of less than 40 Å, or less than 30 Å, or less than 20 Å, or less than 15 Å, or between 15 Å and 40 Å. In some embodiments, a semiconductor device structure can include a molybdenum nitride film that can be amorphous or crystalline.

[0148] In some embodiments, semiconductor device structures including a molybdenum nitride film can include PMOS work function metal device structures, FinFET semiconductor device structures, or gate-all-around semiconductor device structures.

[0149] Embodiments of the present disclosure can also include a reaction system configured to deposit a molybdenum nitride film of the present disclosure. In more detail, ​ A reaction system 1300 including a reaction chamber 1302 is schematically shown, which further includes mechanisms for holding a substrate (not shown) under predetermined pressure, temperature, and environmental conditions and for selectively exposing the substrate to various gases. A precursor reactant source 1304 can be coupled to the reaction chamber 1302 by a conduit or other suitable member 1304A, and can be further coupled to a manifold, a valve control system, a mass flow control system, or mechanisms to control the gaseous precursors sourced from the precursor reactant source 1304. The precursors, reactants (not shown) supplied by the precursor reactant source 1304 can be liquid or solid at room temperature and standard atmospheric pressure conditions. Such precursors can be vaporized within a reactant source vacuum vessel, which can be maintained at or above the vaporization temperature within the precursor source chamber. In such embodiments, the vaporized precursors can be delivered with a carrier gas (e.g., an inert or noble gas), which is then fed into the reaction chamber 1302 through a conduit 1304AA. In other embodiments, the precursors can be vapors at standard conditions. In such embodiments, the precursors need not be vaporized, and a carrier gas can not be required. For example, in one embodiment, the precursors can be stored in gas cylinders. The reaction system 1300 can also include additional precursor reactant sources, such as precursor reactant sources 1306 and 1308, which can also be coupled to the reaction chamber as described above by conduits 1306A and 1306B. In some embodiments, the precursor reactant source 1304 can include a molybdenum halide, the precursor reactant source 1306 can include a nitrogen precursor, and the precursor reactant source 1308 can include a reducing agent.

[0150] A purge gas source 1310 can also be coupled to the reaction chamber 1302 via a conduit 1310A, and various inert or noble gases are selectively supplied to the reaction chamber 1302 to help remove precursor gases or exhaust gases from the reaction chamber. The various inert or noble gases that can be supplied can be sourced from solid, liquid, or stored gaseous forms.

[0151] ​The reaction system 1300 can also include system operation and control mechanisms 1312 that provide electronic circuitry and mechanical components to selectively operate the valves, manifolds, pumps, and other equipment included in the reaction system 1300. Such circuitry and components are used to introduce precursors, purge gases from the respective precursor sources 1304, 1306, 1308 and purge gas source 1310. The system operation and control mechanisms 1312 also control the timing of the gas pulse sequence, the temperature of the substrate and reaction chamber, and the pressure of the reaction chamber, as well as providing various other operations necessary for proper operation of the reaction system 1300. The operation and control mechanisms 1312 can include control software and electrically or pneumatically controlled valves to control the flow of precursors, reactants, and purge gases into and out of the reaction chamber 1302. The control system can include modules, such as software or hardware components, e.g., FPGAs or ASICs, that perform certain tasks. The modules can advantageously be configured to reside on an addressable storage medium of the control system and configured to perform one or more processes.

[0152] Those skilled in the relevant art will appreciate that other configurations of the reaction system of the present disclosure are possible, including different numbers and kinds of precursor reactant sources and purge gas sources. Moreover, those skilled in the relevant art will also appreciate that there are many arrangements of valves, conduits, precursor sources, purge gas sources that can be used to achieve the goal of selectively feeding gases into the reaction chamber 1302. Moreover, as a schematic illustration of a reaction system, many components have been omitted for simplicity of illustration, and such components can include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0153] The exemplary embodiments of the present disclosure described above do not limit the scope of the application, because such embodiments are merely examples of embodiments of the application and are given for illustrative purposes only, the application being defined only by the claims and their legal equivalents. Any equivalent embodiments are intended to fall within the scope of the application. Indeed, various modifications of the disclosure, in addition to those shown and described herein, will become apparent to those skilled in the art from the drawings, the specification and the claims. Such modifications are intended to fall within the scope of the appended claims.

Claims

1. A semiconductor device structure comprising: Semiconductor channel region; and A gate stack disposed on the semiconductor channel region, wherein the gate stack comprises: A gate dielectric disposed on the semiconductor channel region; and A gate electrode comprising a molybdenum nitride film disposed on the gate dielectric, wherein the molybdenum nitride film is a physically continuous molybdenum nitride film having an average film thickness of less than 40 Å.

2. The semiconductor device structure according to claim 1, wherein the molybdenum nitride film has a resistivity of less than 750 μΩ-cm with an average molybdenum nitride film thickness of less than 50 Å.

3. The semiconductor device structure according to claim 1, wherein the molybdenum nitride film has a resistivity of less than 250 μΩ-cm with an average molybdenum nitride film thickness of less than 100 Å.

4. The semiconductor device structure according to claim 1, wherein the molybdenum nitride film has a resistivity of less than 400 μΩ-cm with an average molybdenum nitride film thickness of less than 25 Å.

5. The semiconductor device structure according to claim 1, wherein the molybdenum nitride film comprises a MoN phase and a Mo2N phase.

6. The semiconductor device structure according to claim 1, wherein the gate dielectric is directly disposed on the semiconductor channel region.

7. The semiconductor device structure according to claim 1, wherein the molybdenum nitride film is directly disposed on the gate dielectric.

8. The semiconductor device structure according to claim 1, wherein the molybdenum nitride film is amorphous.

9. The semiconductor device structure according to claim 1, wherein the molybdenum nitride film is crystalline.

10. The semiconductor device structure of claim 1, wherein the gate stack has an effective work function greater than 4.6 eV with an average molybdenum nitride film thickness of less than 50 Å.

11. The semiconductor device structure of claim 1, wherein the gate stack has an effective work function between approximately 4.6 eV and 4.75 eV at an average molybdenum nitride film thickness between approximately 15 Å and 50 Å.

12. A semiconductor device structure comprising: Semiconductor channel region; and A gate stack disposed on the semiconductor channel region, wherein the gate stack comprises: A gate dielectric disposed on the semiconductor channel region; and A gate electrode comprising a molybdenum nitride film disposed on the gate dielectric, wherein the molybdenum nitride film has a resistivity of less than 750 μΩ-cm at an average molybdenum nitride film thickness of less than 100 Å.

13. The semiconductor device structure according to claim 12, wherein the gate dielectric is directly disposed on the semiconductor channel region.

14. The semiconductor device structure according to claim 12, wherein the molybdenum nitride film is directly disposed on the gate dielectric.

15. The semiconductor device structure according to claim 12, wherein the molybdenum nitride film comprises a MoN phase and a Mo2N phase.

16. A semiconductor device structure comprising: Semiconductor channel region; and A gate stack disposed on the semiconductor channel region, wherein the gate stack comprises: A gate dielectric disposed on the semiconductor channel region; and A gate electrode comprising a molybdenum nitride film disposed on the gate dielectric, wherein the molybdenum nitride film has a roughness percentage of less than 1.5%.

17. The semiconductor device structure of claim 16, wherein the semiconductor channel region includes a portion of a gate-around semiconductor device structure.

18. The semiconductor device structure of claim 16, wherein the molybdenum nitride film has a resistivity of less than 500 μΩ-cm at an average molybdenum nitride film thickness of less than 25 Å.

19. The semiconductor device structure according to claim 16, wherein the molybdenum nitride film is amorphous.

20. The semiconductor device structure of claim 16, wherein the molybdenum nitride film is crystalline.

21. A semiconductor device structure comprising: Substrate; A dielectric material formed on the surface of the substrate, wherein the dielectric material includes trenches formed therein; and A barrier layer disposed on the surface of the trench, wherein the barrier layer comprises a physically continuous molybdenum nitride film with an average film thickness of less than 40 Å.

22. The semiconductor device structure of claim 21, further comprising a metal interconnect material disposed in the trench such that the barrier layer is located between the metal interconnect material and the dielectric material.

23. The semiconductor device structure of claim 22, wherein the metal interconnect material comprises at least one of copper or cobalt.

24. The semiconductor device structure of claim 22, further comprising a cover layer disposed on the upper surface of the metal interconnect material.

25. The semiconductor device structure of claim 21, wherein the molybdenum nitride film has a roughness percentage of less than 1.5%.

26. The semiconductor device structure of claim 21, wherein the molybdenum nitride film has a resistivity of less than 750 μΩ-cm at an average molybdenum nitride film thickness of less than 100 Å.

27. A semiconductor device structure comprising: Substrate, which includes fin-like structures; A molybdenum nitride film disposed on at least a portion of the fin structure, wherein the molybdenum nitride film has a roughness percentage of less than 1.5%.

28. The semiconductor device structure of claim 27, wherein the molybdenum nitride film is included in a gate stack disposed over at least said portion of the fin structure, wherein the gate stack further includes a gate dielectric disposed on the surface of the fin structure between the fin structure and the molybdenum nitride film.

29. The semiconductor device structure of claim 28, wherein the gate stack has an effective work function greater than 4.6 eV at an average molybdenum nitride film thickness of less than 50 Å.

30. The semiconductor device structure of claim 28, wherein the gate stack further comprises an additional metal film disposed on the molybdenum nitride film.

31. The semiconductor device structure of claim 30, wherein the additional metal film comprises at least one of a transition metal carbide or a transition metal nitride.

32. The semiconductor device structure of claim 27, wherein the molybdenum nitride film is physically continuous and has an average film thickness of less than 40 Å.

33. The semiconductor device structure of claim 27, wherein the molybdenum nitride film has a resistivity of less than 750 μΩ-cm at an average molybdenum nitride film thickness of less than 100 Å.

34. A semiconductor device structure comprising: Substrate; A dielectric film disposed on the surface of the substrate; Semiconductor lines; as well as A molybdenum nitride film disposed around at least a portion of the semiconductor line, such that at least a portion of the molybdenum nitride film is located between the semiconductor line and the dielectric film, wherein the molybdenum nitride film is physically continuous and has an average film thickness of less than 40 Å.

35. The semiconductor device structure of claim 34, further comprising a gate dielectric disposed around at least a second portion of the semiconductor line, such that the gate dielectric is disposed between the semiconductor line and the molybdenum nitride film.

36. The semiconductor device structure according to claim 35, further comprising another metal film disposed on the molybdenum nitride film.

37. The semiconductor device structure of claim 36, wherein the other metal film comprises at least one of a transition metal carbide or a transition metal nitride.

38. The semiconductor device structure of claim 34, wherein the molybdenum nitride film has a roughness percentage of less than 1.5%.

39. The semiconductor device structure of claim 34, wherein the molybdenum nitride film has a resistivity of less than 750 μΩ-cm at an average molybdenum nitride film thickness of less than 100 Å.

40. The semiconductor device structure according to claim 34, wherein the molybdenum nitride film comprises a MoN phase and a Mo2N phase.

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