Driving system and driving method of digital sound chip

Abstract

The application discloses a driving system and a driving method of a digital sound production chip, and relates to the technical field of digital sound production, to solve the problems of poor universality and high use cost of a special driving chip for the digital sound production chip in the prior art. The driving system of the digital sound production chip comprises at least a processor, a serial-parallel converter and the digital sound production chip. A first number of output pins in the processor are connected with corresponding pins in the serial-parallel converter, and the processor is used at least for converting one total serial data received into multiple sub serial data. The serial-parallel converter is used for receiving the multiple sub serial data and a control signal output by the processor, dynamically adjusting working parameters based on the control signal, and converting the multiple sub serial data into a second number of parallel high-voltage driving signals to drive a second number of sound production units to be driven in the digital sound production chip. The first number is less than the second number. The application improves the universality of the driving system of the digital sound production chip and reduces the use cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital sound production, in particular to a driving system and a driving method of a digital sound production chip. BACKGROUND

[0002] A digital sound production chip is an array sound production device composed of pixel units. For example, the array of the digital sound production chip can be composed of two groups of individually controllable single pixels and one group of controllably arranged column pixels. Each pixel has a diaphragm, which is controlled by upper and lower electrodes. When there is a voltage difference, the diaphragm is attracted; when there is no voltage difference, the diaphragm is released. To make the pixel produce sound, vibration needs to be triggered. To vibrate, the diaphragm needs to be attracted and released according to a certain frequency to achieve the effect of vibration. For example, a low level is applied to the lower electrode of all pixels, and when the upper electrode is applied with a high level, the diaphragm is attracted. After a period of time, the upper electrode is applied with a low level, and the diaphragm is released back to the original position, which is a vibration. By controlling the vibration of multiple pixels, different frequency sounds can be synthesized, and finally complete sound production is achieved. The present application needs to realize a driving system for controlling the vibration and sound production of the digital sound production chip with many pixels according to the corresponding logic.

[0003] To meet the demand for multi-channel (for example, 128 channels) parallel driving of the digital sound production chip, a corresponding application-specific integrated circuit (ASIC) is currently mainly used. The ASIC fixes the driving logic by a hardware circuit (rather than programmable software), integrates at least a plurality of output pins and corresponding driving circuits (for example, a circuit structure for fixing 128 channels of parallel output internally), and can directly drive a plurality of pixel units of the digital sound production chip without an external conversion module.

[0004] The ASIC has the following disadvantages: long design cycle, high cost, and fixed function (the hardware logic is not programmable, and parameters such as driving frequency and duty cycle cannot be modified). Therefore, once the demand for the digital sound production chip changes (such as driving voltage adjustment, pixel quantity increase or decrease), the fixed circuit of the ASIC cannot be adapted, and the ASIC must be redesigned and taped out. The ASIC has poor versatility and cannot be compatible with different models or iterative upgrades of the digital sound production chip. SUMMARY

[0005] The present application aims to provide a driving system and a driving method of a digital sound production chip, to improve the versatility of the driving system of the digital sound production chip and reduce the use cost.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a driving system of a digital sound production chip, which at least includes a processor, a serial-parallel converter, and a digital sound production chip.

[0008] The first number of output pins in the processor are connected with corresponding pins in the serial-parallel converter, and the processor is used at least for converting one received total serial data into multiple sub serial data;

[0009] The serial-parallel converter is used for receiving the multiple sub serial data and control signals output by the processor, dynamically adjusting working parameters based on the control signals, and converting the multiple sub serial data into second number of parallel high-voltage driving signals to drive second number of to-be-driven sound units in the digital sound chip; wherein the first number is less than the second number.

[0010] Optionally, the serial-parallel converter comprises a shift register group, a latch, a logic gate control circuit and a high-voltage output buffer circuit.

[0011] The data input end of the shift register group receives the multiple sub serial data; the shift register group is composed of N groups of M-bit shift registers, each group of M-bit shift registers in the N groups of M-bit shift registers corresponds to receive one sub serial data in the multiple sub serial data; the product of N and M is the second number; N and M are both positive integers, and M is the number of bits of each group of M-bit shift registers.

[0012] The data output end of the shift register group is connected with the data input end of the latch; the latch is a second number of bit latches, the data input end of the latch corresponds to the data output end of the shift register group, and the total number of bits of the shift register group and the latch is the second number.

[0013] The data output end of the latch is connected with the input end of the logic gate control circuit, and the output end of the logic gate control circuit is connected with the input end of the high-voltage output buffer circuit.

[0014] Optionally, the high-voltage output buffer circuit comprises second number of high-voltage output buffers, each high-voltage output buffer in the second number of high-voltage output buffers is built-in push-pull output circuit, and the push-pull output circuit is used for converting the low-voltage signal output by the logic gate control circuit into a high-voltage driving signal.

[0015] Optionally, the logic gate control circuit comprises second number of groups of logic gates; each group of logic gates in the second number of groups of logic gates is connected with one output end of the second number of bit latches.

[0016] Each group of logic gates comprises an NAND gate and an AND gate.

[0017] The first input end of the NAND gate is connected with a corresponding output end of the latch, and the second input end of the NAND gate is connected with a forced high-voltage signal.

[0018] an output terminal of the NAND gate is connected to a first input terminal of the AND gate; a second input terminal of the AND gate is connected to a forced low signal;

[0019] an output terminal of the AND gate is connected to a level signal input terminal of the corresponding high-voltage output buffer; an enable signal input terminal of the high-voltage output buffer is connected to an enable signal.

[0020] Optionally, the high-voltage output buffer circuit is built-in push-pull output circuit, and the push-pull output circuit is used for converting the low-level signal output by the logic gate control circuit into a high-voltage driving signal.

[0021] Optionally, the control signal at least includes a clock signal and a latch signal; and the working parameter at least includes a playing frequency.

[0022] The processor periodically pulls up the latch signal, so that each time the latch signal generates a rising edge, the serial-parallel converter performs output according to the data in the current M-bit shift register, and the playing frequency is consistent with the pull-up frequency of the latch signal.

[0023] The clock signal completes M-bit data transmission in a single latch period.

[0024] Optionally, the control signal further includes a forced low signal.

[0025] The processor controls the serial-parallel converter to output parallel high-voltage driving signals to the digital sound chip and maintain a first time length according to a preset duty cycle, then pulls down the forced low signal to make all the parallel high-voltage driving signals low to interrupt the output and maintain a second time length; wherein the ratio of the first time length to the second time length matches the preset duty cycle.

[0026] Optionally, the control signal further includes a reset signal.

[0027] When resetting, the processor pulls up the reset signal, and at the same time triggers a rising edge of the clock signal and the latch signal to clear the data in the shift register group and the latch to realize resetting.

[0028] Optionally, the control signal further includes an enable signal and a forced high signal.

[0029] When the enable signal is high, the AND gate is turned on, and the data output by the latch enters the high-voltage output buffer after logical processing by the AND gate; when the enable signal is low, the output of the high-voltage output buffer is in a high-impedance state.

[0030] The output signal of the latch is input to the first input end of the AND gate after being processed by the NAND gate logic with the forced high level signal; and the forced low level signal is input to the second input end of the AND gate.

[0031] When the driving system detects an abnormality or needs to control the duty cycle, the forced low level signal is an effective level, the AND gate is closed, the data transmission is cut off, and a low level is forced to be output; when the forced high level signal is an effective level, the NAND gate outputs a high level, the AND gate is turned on, and a high level is output.

[0032] When the driving system is working normally, the forced low level signal and the forced high level signal are both invalid levels, and the AND gate outputs the signal processed by the NAND gate.

[0033] Optionally, the second number is 128.

[0034] The shift register group comprises four groups of 32-bit shift registers; the four groups of 32-bit shift registers share one clock signal input end, one reset signal input end and one direction signal input end, and each group of 32-bit shift registers has one data input end and 32 data output ends.

[0035] The latch is a 128-bit latch; the 128 data input ends of the 128-bit latch correspond to the 128 data output ends of the shift register group one by one.

[0036] Compared with the prior art, the driving system of the digital sound chip provided by the application can dynamically adjust the working parameters based on the control signal output by the processor, and when the working parameters of the digital sound chip need to be adjusted, the hardware circuit does not need to be modified as in the traditional technology, thereby breaking through the limitation that the parameters of an ASIC cannot be adjusted.

[0037] The serial-parallel converter can convert the multiple sub-serial data output by the processor into a second number of parallel high-voltage driving signals, and the first number is less than the second number; when the number of pixels of the digital sound chip increases or decreases, only the configuration of the shift register group of the serial-parallel converter needs to be adjusted to adapt, without the need to replace the driving chip; at the same time, the serial-parallel converter supports high-voltage output and can match the different driving voltage requirements of the digital sound chip, thereby solving the problem that an ASIC cannot adapt to parameter changes. Moreover, the system uses a combination of a processor and a serial-parallel converter, without the need to redesign and tape out as in an ASIC, thereby greatly shortening the development cycle and reducing the design and use costs.

[0038] In a second aspect, the application further provides a driving method of a digital sound chip, applied to the driving system of the digital sound chip according to any one of the above-mentioned aspects, and characterized in that the method comprises:

[0039] The processor receives audio data, outputs multiple sub-serial data and control signals to the serial-parallel converter through a first number of output pins of the processor;

[0040] The serial-parallel converter receives the multiple sub-serial data and the control signals, dynamically adjusts working parameters based on the control signals, and converts the multiple sub-serial data into a second number of parallel high-voltage driving signals to drive a second number of to-be-driven sound units in the digital sound chip; wherein the first number is less than the second number. BRIEF DESCRIPTION OF DRAWINGS

[0041] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the principles of the application. In the drawings:

[0042] Figure 1 Structure schematic diagram of a driving system of a digital sound chip provided for an embodiment of the application;

[0043] Figure 2 Structure schematic diagram of a driving system of a digital sound chip provided for an embodiment of the application;

[0044] Figure 3 Circuit structure schematic diagram of a serial-parallel converter provided for an embodiment of the application;

[0045] Figure 4 Structure schematic diagram of a digital sound chip provided for an embodiment of the application;

[0046] Figure 5 Circuit structure schematic diagram of a corresponding serial-parallel converter; Figure 4 Circuit structure schematic diagram of a corresponding serial-parallel converter;

[0047] Figure 6 Flowchart of a driving method of a digital sound chip provided for an embodiment of the application.

[0048] Reference signs: 1-processor; 2-serial-parallel converter; 21-shift register group; 210-M-bit shift register; 211-32-bit shift register; 22-latch; 220-128-bit latch; 23-logic gate control circuit; 230-NAND gate; 231-AND gate; 24-high-voltage output buffer circuit; 240-high-voltage output buffer; 3-digital sound chip; 4-upper computer; 5-power supply. DETAILED DESCRIPTION

[0049] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms of "first", "second", etc. are used to distinguish the same or similar items with basically the same function and role. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and the order is not limited. Those skilled in the art can understand that the terms of "first", "second", etc. do not limit the quantity and execution order, and the terms of "first", "second", etc. also do not necessarily mean different.

[0050] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or superior to other embodiments or design solutions. Rather, the use of the words "exemplary" or "for example" is intended to present related concepts in a specific manner.

[0051] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, indicating that there can be three relationships.

[0052] In the current digital sound chip driving technology field, the corresponding special chip, namely ASIC, is currently used to drive the digital sound chip. The circuit structure of the ASIC is realized by hardwiring according to fixed functional requirements. Once the design is completed, the circuit connection and logic function inside the ASIC are fixed. For example, when designing the ASIC for driving the digital sound chip, the control logic of the driving frequency and the duty cycle is designed and wired according to the established parameters, and it is difficult to modify it later, because modifying these functions means re-designing the entire circuit layout of the ASIC.

[0053] In the development process of the digital sound chip, its driving voltage, pixel quantity and other parameters will be constantly changed and improved. Since the ASIC is designed for specific parameters of the digital sound chip, when the parameters of the digital sound chip change, the original ASIC cannot adapt. For example, if an ASIC is designed according to a specific driving voltage, when the digital sound chip needs a higher or lower driving voltage, the ASIC cannot be used directly and must be redesigned to match the new voltage requirement.

[0054] From the design principle of the ASIC, most special ASICs will have similar problems. Because the customization nature of the ASIC determines its inherent deficiency in flexibility and versatility. The specific reasons are as follows:

[0055] 1) Hardware circuit is not programmable: the driving logic of ASIC (such as frequency control, duty cycle adjustment circuit) is fixed in hardware at the chip design stage through processes such as photolithography, and cannot be modified by software code like programmable chips. For example, if the driving frequency is fixed at 50KHz during design, the parameters of the internal clock circuit and timing control circuit have been fixed and cannot be adjusted to 100KHz through external instructions.

[0056] 2) No flexible configuration interface: ASIC usually only retains simple control pins such as enable and reset, and does not have configurable registers or communication interfaces (such as I2C, SPI) to receive external parameter instructions. Therefore, the driving frequency, duty cycle and other parameters are fixed after the chip production is completed, and cannot be adjusted according to the different needs of digital sound chip (such as different models of pixel vibration frequency requirements).

[0057] 3) Design target limitation: The advantage of ASIC is high integration and low cost (in mass production), but its design intention is to optimize for a single scenario without considering generality. If you want to support parameter modification, you need to add programmable circuits, which will increase the design complexity and cost, violating the design goal of ASIC.

[0058] Therefore, when the driving needs of the digital sound chip change (such as driving voltage increase, pixel number increase, frequency parameter adjustment), ASIC cannot be adapted and must be reflow designed, resulting in poor generality.

[0059] The prior art also has a parallel driving mode of multi-chip cascade, for example, a plurality of general GPIO expansion chips (General Purpose Input / Output, a general-purpose pin on a chip, which can be configured as an input or output mode through software, used for transmitting digital signals, and realizing communication or control with external devices such as sensors, actuators, other chips, etc.) are cascaded, and 128-way output is realized through the combination of multiple chips. The disadvantages are: 1. The pin occupation is still high: each 16-way expander needs at least 4-5 control pins (I2C / SPI bus), 128-way needs 8 chips, and the total control pin is 32-40, which requires the core processor to reserve 32-40 dedicated pins, limiting its ability to handle other functions (such as human-computer interaction, sensor data acquisition) at the same time, especially when multiple digital sound chip cascades, the number of pins will be doubled, leading to difficulties in processor selection; 2. It cannot meet the high-voltage requirement: the output voltage of the general GPIO expander is mostly 3.3V / 5V, while the digital sound chip needs higher driving voltage due to process limitations, and the existing expansion chip cannot be directly adapted, and needs to be additionally matched with a complex boost circuit, increasing the system complexity and failure rate; 3. Multi-chip cascade will introduce signal delay difference (clock offset of different chips), and the pixel vibration of the digital sound chip needs to be strictly synchronized (otherwise the synthesized sound will be distorted), and the existing scheme cannot guarantee the microsecond-level synchronization accuracy.

[0060] Therefore, whether it is a dedicated ASIC or a multi-chip general GPIO expansion chip cascade, it does not essentially break through the logic of parallel driving requiring an equal number of control pins, and cannot meet the core requirements of high-voltage output, flexible configuration parameters, and high pin occupation of the core processor. The existing technology either has too strong speciality and too high cost, or is limited in function and cannot adapt to the special requirements of the digital sound chip, resulting in the difficulty of multi-way simultaneous driving as a common technical pain point in the industry.

[0061] To solve the above problems, see Figure 1 The embodiment of the present application provides a driving system of a digital sound chip, at least comprising: a processor, a serial-parallel converter and a digital sound chip;

[0062] A first number of output pins in the processor are connected with corresponding pins in the serial-parallel converter, and the processor is used at least for converting a received one-way total serial data into a plurality of sub-serial data;

[0063] The serial-parallel converter is used for receiving the plurality of sub-serial data and control signals output by the processor, dynamically adjusting the working parameters based on the control signals, and converting the plurality of sub-serial data into a second number of parallel high-voltage driving signals to drive a second number of to-be-driven sound units in the digital sound chip; wherein the first number is less than the second number.

[0064] Specifically, the processor is a processing unit with programmable logic function, the internal logic of which can be dynamically configured through programming, can flexibly output serial data and control signals, and can adjust the output timing and logic relationship according to the driving requirements of the digital sound chip; the processor is connected with the serial-parallel converter through a small number of output pins, and adapts to different scene serial data transmission protocols by virtue of its programmable characteristics, and supports dynamic control of the working parameters of the serial-parallel converter. For example, the processor can be an FPGA (Field-Programmable Gate Array, programmable gate array).

[0065] It can be understood that, referring to Figure 2 , the driving system can further include a host computer 4 and a power supply 5, the host computer 4 and the processor 1 are connected through TCP for communication, the host computer 4 is used to send audio data and control instructions, the audio data is converted into multiple sub-serial data for parallel transmission after being processed by the processor 1 and is transmitted to the serial-parallel converter, each sub-serial data contains multiple bits (for example, 32 bits). The power supply 5 can provide a voltage of, for example, 5V for the processor 1, can provide a voltage of, for example, 5V for the low-voltage area in the serial-parallel converter 2, and can provide high voltage HVDD for the high-voltage area of the serial-parallel converter 2.

[0066] For example, in a specific implementation, the data received by the PS end of the processor FPGA through TCP is often in 32-bit frames, and then these data are stored in the DDR according to the addresses in Table 1 below.

[0067] Table 1: Address table

[0068]

[0069] The data in the base address (i.e. the command address) are read in real time at the PL end of the FPGA to execute the corresponding commands, and the correspondence relationship table is as shown in Table 2 below.

[0070] Table 2: Correspondence relationship table

[0071]

[0072] The audio data sent from the host computer through TCP will exist in the corresponding address of the DDR, when the command to start playing is received, the PL end of the FPGA will read the data of the DDR at a rate of 100M and store them in the FIFO buffer unit, and read the data from the FIFO buffer unit at a rate matching the actual playing frequency.

[0073] Next, the audio data mapping rule is explained. The audio data is sent by the upper computer, the data format is 32 bits as a group, arranged in the order of T1-T32, T33-L30, B1-B32, B33-R29, 4 groups of 32-bit data constitute a frame, the frame sequence is looped until the audio ends.

[0074] Combined with the total number of T, B, L, R control signals (T: 34, B: 34, L: 30, R: 30, total 128), because the shift register group needs 32-bit input, the T / B type signals more than 32 bits are split and spliced, 128 control signals are mapped through 4 groups of 32-bit data, assuming that the 4 groups of 32-bit data are D1A, D2A, D3A, D4A, the rules are as follows:

[0075] (1) Data group D4A (corresponding to the first 32 control signals of T type).

[0076] Bit sequence range: D4A[0]~D4A

[31] .

[0077] Mapping relationship: T1~T32 (covering the first 32 signals of T type) in turn.

[0078] Example: D4A[0]→T1, D4A[1]→T2, …, D4A

[31] →T32

[0079] (2) Data group D3A (corresponding to the remaining signals of T type + L type signals).

[0080] Bit sequence range: D3A[0]~D3A

[31] .

[0081] Mapping relationship: T33, T34 (remaining 2 signals of T type) + L1~L30 (all 30 signals of L type), a total of 32 bits.

[0082] Example: D3A[0]→T33, D3A[1]→T34, D3A[2]→L1, …, D3A

[31] →L30.

[0083] (3) Data group D2A (corresponding to the first 32 control signals of B type).

[0084] Bit sequence range: D2A[0]~D2A

[31] .

[0085] Mapping relationship: B1~B32 (covering the first 32 signals of B type) in turn.

[0086] Example: D2A[0]→B1, D2A[1]→B2, …, D2A

[31] →B32.

[0087] (4) Data group D1A (corresponding to the remaining signals of B type + R type signals).

[0088] Bit sequence range: D1A[0]~D1A

[31] .

[0089] Mapping relationship: B33, B34 (the remaining 2 signals of the B type) + R1~R30 (all 30 signals of the R type), a total of 32 bits.

[0090] Example: D1A[0]→B33, D1A[1]→B34, D1A[2]→R1... D1A

[31] →R30

[0091] Mapping logic summary: Grouping logic: 34 signals of the T / B type (more than 32 bits), splitting the remaining 2 signals and splicing 30 signals of the L / R type, adapting the 32-bit input requirement of the shift register group. Total number of signals: 34 (T) + 34 (B) + 30 (L) + 30 (R) = 128, which exactly fills 4 groups x 32 bits = 128 bits.

[0092] Core sequence: The T type takes the first 32 (D4A), and the remaining 2 (T33, T34) are spliced with the L type (D3A); the B type takes the first 32 (D2A), and the remaining 2 (B33, B34) are spliced with the R type (D1A);

[0093] The bit sequence in each group starts from 0 and is filled in order according to “T / B remaining signals→L / R signals”.

[0094] Through the above rules, the mapping relationship of 128-way control signals→4 groups of 32-bit data is clearly defined, solving the problem of ambiguous splitting of group pixel bit sequence.

[0095] Technical effect analysis of the embodiment:

[0096] I. The core problem of existing ASICs is that the circuit is fixed, the parameters cannot be changed, and the versatility is poor. This embodiment first uses FPGA as a processor, and FPGA has the feature of field programmable, and its logic function can be modified by programming without the need to redesign the hardware circuit. For example, the driving frequency, duty cycle and other parameters can be flexibly adjusted by updating the program, without the need to reflow like ASIC; secondly, this embodiment also uses a serial-parallel converter for dynamic adaptation, which can dynamically adjust the working parameters based on the control signal, and efficiently convert the multi-channel parallel high-voltage drive signal by receiving the multi-channel sub-serial data output by the processor (split from one total serial data). When the number of pixels (the second number) of the digital sound chip changes, only the output channel number configuration of the serial-parallel converter needs to be adjusted, without the need to replace the hardware; the high-voltage drive characteristics can also be adapted to different voltage requirements through the converter, avoiding the adaptation problem caused by the fixed voltage design of ASIC.

[0097] The existing multi-chip cascade has the problems of high pin occupation, poor signal synchronization, and inability to directly output high voltage. It can be understood that the existing ASIC also has the problem of high pin occupation. When the pins in the chip also need to be controlled in other aspects, the function cannot be expanded. However, 1) the first number of output pins of the processor FPGA in the embodiment are connected to the serial-parallel converter, a large number of parallel outputs are controlled through parallel transmission of a small number of multi-sub-serial data, and the first number is less than the second number, for example, 10 pins are used to realize 128-way driving, which is much lower than the 32-40 pin of the multi-chip cascade, solving the problem of high pin occupation. 2) The multi-sub-serial data are synchronously converted into parallel signals by the single converter, avoiding the signal delay difference of the multi-chip cascade, which is beneficial to guarantee the timing accuracy of pixel vibration. 3) The serial-parallel converter directly outputs the parallel high-voltage driving signal, without the need for an additional voltage boosting circuit, simplifying the system structure and solving the problem that the ordinary GPIO expander cannot adapt to high voltage.

[0098] In summary, the embodiment breaks through the limitations of ASIC and the defects of multi-chip cascade by the transmission design of splitting one total serial data into multiple sub-serial data by the processor, combining the programmability and the dynamic adaptation of the serial-parallel converter, while meeting the needs of low pin occupation, high voltage output, and flexible parameter configuration, and solving the common pain points of the existing technology.

[0099] In an optional embodiment, referring to Figure 3 , the serial-parallel converter 2 can include a shift register group 21, a latch 22, a logic gate control circuit 23, and a high-voltage output buffer circuit 24; the data input end of the shift register group 21 receives the multi-sub-serial data; the shift register group 21 is composed of N groups of M-bit shift registers 210, each group of M-bit shift registers 210 in the N groups of M-bit shift registers corresponds to receiving one sub-serial data in the multi-sub-serial data; the product of N and M is the second number; N and M are positive integers, and M is the number of bits of each group of M-bit shift registers; the data output end of the shift register group 21 is connected to the data input end of the latch 22; the latch 22 is a second number of bit latches, the data input end of the latch 22 corresponds to the data output end of the shift register group 21, and the total number of bits of the shift register group 21 and the latch 22 is the second number; the data output end of the latch 22 is connected to the input end of the logic gate control circuit 23, the output end of the logic gate control circuit 23 is connected to the input end of the high-voltage output buffer circuit 24, and the output end of the high-voltage output buffer circuit 24 is used to output the high-voltage driving signal.

[0100] Referring to Figure 4For example, the digital sound chip is composed of 34 top-layer single-pixel T, 34 columns of whole-column pixels B, 30 spare pixels L and 30 lower electrode groups R. If the digital sound chip is to be driven, at least 34+34+30+30=128 effective controllable signals are needed, and the second quantity is 128. The shift register group includes 4 groups of 32-bit shift registers. The 4 groups of 32-bit shift registers share 1 clock signal input end, 1 reset signal input end and 1 direction signal input end, and each group of 32-bit shift registers has 1 data input end and 32 data output ends. The latch is a 128-bit latch, and the 128 data input ends of the 128-bit latch correspond to the 128 data output ends of the shift register group one by one. Correspondingly, the 11 (i.e. the first quantity) output pins in the processor include: 4 sub-serial data output pins, 1 clock signal output pin, 1 latch signal output pin, 1 reset signal output pin, 1 direction signal output pin, 1 enable signal output pin, 1 forced high-level signal output pin, and 1 forced low-level signal output pin. Among them, the 4 sub-serial data output pins correspond to the 4 data input ends of the shift register group one by one; the clock signal output pin is connected to the clock signal input end shared by the serial-parallel converter; the reset signal output pin is connected to the reset signal input end shared by the serial-parallel converter; and the direction signal output pin is connected to the direction signal input end shared by the serial-parallel converter.

[0101] For the direction signal (DIR signal) shared by the above-mentioned 4 groups of 32-bit shift registers, in the actual application scenario of driving the digital sound chip, the DIR signal does not need to be dynamically switched and adjusted: only need to set the DIR signal to 1 to ensure that the data transmission direction of the shift register group is “D1A→D1B” (i.e. from the data input end of each group of 32-bit shift registers to its 32 data output ends); and in the actual circuit design, the D1B end of the shift register is not physically connected, and the DIR signal is not set to 0 at all, which can completely avoid the abnormality of circuit data transmission or hardware failure caused by the misoperation of the direction signal. D1A is the data input end of the M-bit shift register, and D1B is the data output end corresponding to D1A of the M-bit shift register.

[0102] Beneficial effect analysis of the embodiment:

[0103] I. From the perspective of data processing, 1) a shift register group composed of N groups of M-bit shift registers is used to receive the parallel sub-serial data of the serial data segment output by the processor through N data input terminals (i.e., the processor splits one total serial data into N parallel transmitted sub-data segments, and each group of shift registers corresponds to receive one sub-serial data), and converts the multi-channel sub-serial data into N times M parallel high-voltage driving signals. This design can effectively resolve the contradiction between the limited number of processor pins and the large number of sound generating units to be driven. By parallel splitting and converting a small amount of sub-serial data, a small number of pins can realize multi-channel driving, breaking the strong binding between the number of ASIC pins and the number of driving channels, and significantly improving the flexibility of the processor in adapting to different numbers of sound generating units. For example, when using 4 groups of 32-bit shift registers, the serial data output by the processor can be split into 4 parallel sub-data segments, and finally converted into 128 parallel signals (4x32=128). The key is that only 11 output pins of the processor are needed to control the 128 driving signals, effectively resolving the contradiction between the small number of processor pins (first quantity) and the large number of sound generating units to be driven (second quantity), allowing the processor with limited pins to drive multiple sound generating units, breaking the strong binding between ASIC pins and driving channels, and improving the flexibility of the processor in adapting to different numbers of sound generating units. 2) With the help of the second number of D-type flip-flops, the dynamic serial data transmitted by the shift register is converted into static parallel data form, avoiding data jitter in the conversion link. For example, a 128-bit latch can convert the dynamic data output by the shift register into stable 128-channel static parallel data. Digital sound chips have strict requirements for timing synchronization (pixel vibration of sound generating units needs to be accurately aligned), and the latch can ensure the synchronous effect of the corresponding second number of signals, solving the problem of inconsistent signal delay in the traditional multi-chip cascade scheme and improving the consistency of signal output.

[0104] II. From the perspective of cost reduction and efficiency improvement, 1) the N groups of shift registers share the clock signal input end, the reset signal input end, and the direction signal input end, only 1 set of control pins is needed, and no control pins need to be configured for each group of shift registers. Taking 4 groups of shift registers as an example, 1 clock signal, 1 reset signal and 1 direction signal output by the processor are connected to the clock signal input end, the reset signal input end and the direction signal input end shared by the 4 groups of shift registers, that is, the processor includes at least 1 clock signal output pin, 1 reset signal output pin, 1 direction signal output pin, combined with 4 sub-serial data output pins of the processor, 1 latch signal output pin, 1 enable signal output pin, 1 forced high level signal output pin and 1 forced low level signal output pin, a total of only 11 output pins, which can realize the cooperative control of the 4 groups of shift registers, instead of configuring independent control pins for the 4 groups of shift registers. Compared with the multi-chip cascade scheme in the prior art which needs to occupy more control pins (for example, 32-40 channels), the embodiment greatly reduces the occupation of hardware resources, makes the system hardware architecture more simple, and reduces the hardware cost and design complexity. 2) Through the cooperation of the shift register group and the latch, the number of parallel signals output can accurately match the actual driving channel number required by the digital sound chip. For example, for a digital sound chip composed of 34 top single-pixel T, 34 columns of whole-pixel B, 30 spare pixels L and 30 lower electrode groups R, the 34+34+30+30=128 effective controllable signals required can be accurately matched by the 128 parallel signals output by the shift register group and the latch of the embodiment, and the control is realized through only 11 processor output pins throughout the process, avoiding the problems of redundant or insufficient driving channels. The customized parallel conversion mechanism adapts to the chip structure, and compared with the general GPIO expander in the prior art, the embodiment has more advantages in channel adaptation and conversion efficiency, and improves the adaptability of the driving system and the chip.

[0105] III. From the perspective of signal stability, 1) The transmission mode of multi-channel parallel receiving multi-path sub-serial data is adopted (the shift register group synchronously receives N sub-serial data through N data input terminals), for example, under the precise control of 11 output pins, this transmission stage belongs to the transmission of weak signal and high frequency control signal (low signal amplitude, such as 3.3V / 5V, and high frequency driving demand needs to be matched), which is more sensitive to electromagnetic interference. At this time, through a small number of signal lines (for example, 4 sub-serial data correspond to 4 lines), compared with the parallel transmission in the ASIC in the prior art which needs to use a large number of signal lines (such as 128 lines are needed for 128-way driving), the embodiment can greatly reduce the probability of electromagnetic coupling (crosstalk) between lines. Even if the transmission process is disturbed, it usually only affects 1 sub-serial data, and does not cause multiple baseband signals to be wrong at the same time due to the dense arrangement of multiple lines, which is caused by the traditional parallel transmission. This design effectively solves the crosstalk problem that is prone to occur in long-distance parallel transmission, and is especially suitable for high-frequency driving scenes such as high-speed vibration control of digital sound chip, and can reliably guarantee the accuracy of signal transmission and significantly improve the stability of the driving system in high-frequency scenes. 2) The latch converts the 128 parallel signals output by the shift register group into stable parallel signals and temporarily stores them, on the one hand, it realizes the signal isolation between the processor and the high-voltage driving link, avoids the reverse interference of the high-voltage output buffer circuit on the weak signal output by the processor when it is working, and guarantees the stable operation of the processor; on the other hand, the 128 parallel signals after latching are strong signals (high amplitude, up to 80V) and have static output characteristics (the signal state remains unchanged within the latching period), and the anti-interference ability is much stronger than that of the weak signal in the transmission stage. At the same time, the latch and the high-voltage output buffer circuit are isolated by the logic gate control circuit, and the high-voltage output buffer circuit has a built-in push-pull output circuit, which can further enhance the signal driving ability and suppress noise. Therefore, even if 128 parallel transmission is used after latching, the probability of error caused by crosstalk is much lower than that of the weak signal in the transmission stage, and it is complementary to the anti-interference design in the transmission stage, which improves the overall reliability of the system.

[0106] IV. From the perspective of high-voltage driving, 1) Compared with the ordinary GPIO expander in the prior art, the output voltage is mostly 3.3V / 5V, which is difficult to drive directly. The high-voltage output buffer circuit in the embodiment can convert the low-voltage control signal output by the logic gate into the high-voltage driving signal required by the digital sound chip, without the need for additional boost circuit, simplifying the system structure.

[0107] In addition, the first number of output pins of the processor are connected with the first number of input pins of the shift register group in a one-to-one correspondence, for example, through 11-pin control of 128-way driving, which ensures the orderly transmission of control signals and data signals, further strengthens the stability and reliability of the serial-parallel conversion process, and ensures that the driving system operates efficiently according to the preset logic.

[0108] In an alternative embodiment, the high-voltage output buffer circuit includes a second number of high-voltage output buffers, each of the second number of high-voltage output buffers having a push-pull output circuit built-in, which is used to convert the low-voltage signal (e.g. 3.3V / 5V) output by the logic gate control circuit into a high-voltage driving signal (e.g. up to 80V). The circuit structure of the push-pull output circuit can refer to related technologies, and this embodiment will not be described again.

[0109] The push-pull output circuit realizes efficient conversion from low voltage to high voltage (e.g. 3.3V / 5V→up to 80V), directly adapts to the high-voltage driving requirements of the digital sound chip, without the need for additional voltage boosting circuits, simplifying the system structure and reducing the failure rate.

[0110] For example, the high-voltage output buffer can include: a level isolation circuit, a timing buffer unit, a push-pull output circuit (including a high-power push-pull enhancement stage), an overcurrent protection circuit, a high-voltage low-dropout regulator (HV-LDO) + energy storage capacitor network, and a 128-way current equalization distribution circuit, a total of 6 types of core modules.

[0111] The signal transmission link is: the low-voltage output end of the logic gate control circuit (3.3V / 5V)→the input end of the level isolation circuit (optocoupler / isolation amplifier)→the output end of the level isolation circuit→the input end of the timing buffer unit (RC filter+delay calibration sub-circuit)→the output end of the timing buffer unit→the control signal input end of the push-pull output circuit (including a high-power enhancement stage)→the high-voltage output end of the push-pull output circuit→the input end of the 128-way current equalization distribution circuit→the output end of the 128-way current equalization distribution circuit→the digital sound chip.

[0112] The safety and voltage stabilization link is: the high-voltage output end of the push-pull output circuit→the current sampling end of the overcurrent protection circuit (with a series of milliohm sampling resistors)→the protection signal end of the overcurrent protection circuit, one way is fed back to the shutdown control end of the push-pull output circuit, and the other way is fed back to the abnormality detection pin of the processor. The high-voltage power supply→the input end of the high-voltage low-dropout regulator→the output end of the HV-LDO→the power supply end Vpp of the push-pull output circuit.

[0113] Power supply and ground: 1) Level isolation circuit, timing buffer unit: powered by 5V low voltage power supply (share low voltage with logic gate control circuit), ground terminal connects digital ground DGND; 2) Push-pull output circuit, overcurrent protection circuit, HV-LDO, current equalization distribution circuit: high voltage side is powered by Vpp, ground terminal connects power ground PGND, bottom DGND and PGND share ground.

[0114] The functions of each circuit module in the high-voltage output buffer: 1) Level isolation: high and low voltage circuit electrical isolation is realized through optocoupler / isolation amplifier to prevent high voltage side (80V) large current / high voltage from interfering with low voltage side logic circuit (processor, logic gate); 2) Timing synchronization and noise reduction: RC filter sub-circuit of timing buffer unit filters out high-frequency noise, and delay calibration sub-circuit compensates for 128-way signal timing deviation, ensuring synchronization of driving signals and avoiding vibration of sound generating units out of sync; 3) High voltage conversion and high power driving: push-pull output circuit converts low voltage signal to 80V high voltage signal, combined with high-power push-pull enhancement stage (such as using 4-6 groups of STP80NF70MOS transistors in parallel with IR2110 driving IC), to improve single channel filling / pulling current and total driving capacity, meeting the large current demand of 128-way simultaneous driving; 4) Overcurrent protection: overcurrent protection circuit samples output current in real time, cuts off the push-pull circuit when the threshold is exceeded, and feeds back to the processor to prevent electrode overcurrent breakdown of the sound generating unit; 5) Power stabilization: HV-LDO compensates for load current changes to ensure Vpp≥76V (voltage drop≤5%) when fully loaded, and energy storage capacitor network suppresses high and low frequency ripple to stabilize power voltage; 6) Current equalization: 128-way current equalization distribution circuit (series high-precision resistors or constant current loop) balances the load current of each way to avoid impedance deviation of the sound generating unit.

[0115] In an alternative embodiment, the logic gate control circuit comprises a second number of groups of logic gates; each group of logic gates in the second number of groups of logic gates is connected to an output terminal of a second number of flip-flops; each group of logic gates comprises a NAND gate and an AND gate; a first input terminal of the NAND gate is connected to a corresponding output terminal of the latch, and a second input terminal of the NAND gate is connected to a forced high level signal; an output terminal of the NAND gate is connected to a first input terminal of the AND gate; a second input terminal of the AND gate is connected to a forced low level signal; an output terminal of the AND gate is connected to a level signal input terminal of a high voltage output buffer in the high voltage output buffer circuit; an enable signal input terminal of the high voltage output buffer is connected to an enable signal.

[0116] and Figure 4 Correspondingly, see Figure 5 , Figure 5 for Figure 3In one embodiment, the shift register group 21 includes four groups of 32-bit shift registers 211, the latch 22 is a 128-bit latch 220, the logic gate control circuit 23 includes 128 groups of logic gates, each group of logic gates includes a NAND gate 230 and an AND gate 231, and the high-voltage output buffer circuit 24 includes 128 groups of high-voltage output buffers 240.

[0117] Referring to Figure 5 In the embodiment, the logic gate control circuit 23 includes 128 groups of logic gates; each group of logic gates in the 128 groups of logic gates is connected to an output terminal of the 128-bit latch 220, and the 128-bit latch 220 includes 128 data input terminals D0 to D127 and 128 data output terminals Q0 to Q127. Each group of 32-bit shift registers includes 32 data output terminals. For example, the first data output terminal of the first 32-bit shift register is connected to the first data input terminal D0 of the 128-bit latch 220, and so on, the 32nd data output terminal of the first 32-bit shift register is connected to the 125th data input terminal D124 of the 128-bit latch 220; the first data output terminal of the second 32-bit shift register is connected to the second data input terminal D1 of the 128-bit latch 220, and so on, the 32nd data output terminal of the second 32-bit shift register is connected to the 126th data input terminal D125 of the 128-bit latch 220; the first data output terminal of the third 32-bit shift register is connected to the third data input terminal D2 of the 128-bit latch 220, and so on, the 32nd data output terminal of the third 32-bit shift register is connected to the 127th data input terminal D126 of the 128-bit latch 220; the first data output terminal of the fourth 32-bit shift register is connected to the fourth data input terminal D3 of the 128-bit latch 220, and so on, the 32nd data output terminal of the fourth 32-bit shift register is connected to the 128th data input terminal D127 of the 128-bit latch 220.

[0118] In Figure 5 In the embodiment, the input terminal of the first NAND gate 230 is connected to the first data output terminal Q0 of the 128-bit latch 220, and so on, the input terminal of the 128th NAND gate 230 is connected to the 128th data output terminal Q127 of the 128-bit latch 220.

[0119] The second input terminal of the NAND gate 230 is connected to a forced high-level signal OH; the output terminal of the NAND gate 230 and the first input terminal of the AND gate 231 are connected; the second input terminal of the AND gate 231 is connected to a forced low-level signal OL; the output terminal of the AND gate 231 is connected to the level signal input terminal of the corresponding high-voltage output buffer 240 in the high-voltage output buffer circuit 24; and the enable signal input terminal of the high-voltage output buffer 240 is connected to the enable signal OE.

[0120] It should be noted that the first input end of the NOT gate is equivalent to a NOT gate, which has the function of reversing the input signal.

[0121] The embodiment has the following technical effects: 1) accurate signal screening and transmission. Each set of logic gates realizes dynamic screening of the latch output signal through the combination logic of the forced high-level signal OH, the forced low-level signal OL, and the enable signal OE: only when the signal meets the preset logic (for example, OL=1, OH=1, and OE=1 during normal operation), is allowed to enter the high-voltage output buffer circuit, ensuring the accuracy of the driving signal. 2) has multi-scene adaptation ability. Through the level switching of OL and OH signals, forced low-level (interrupt output) and forced high-level (continuous driving) special modes can be quickly realized, which not only meets the dynamic demand of duty cycle adjustment, but also can cut off the output in system exception, protecting the digital sound chip from damage by abnormal signals. 3) has isolation and synergistic effect. The logic gate control circuit acts as an intermediate layer between the latch and the high-voltage output buffer circuit, which not only isolates the direct interaction between low-voltage logic signals and high-voltage driving signals, but also realizes the synchronous control of 128 signals through unified logic rules, ensuring the action consistency of multiple sound emitting units.

[0122] The control logic of the driving system is described as follows.

[0123] The control signals include clock signal CLK, latch signal LE, forced low-level signal OL, enable signal OE, forced high-level signal OH, reset signal RST, and direction signal. The core working parameters include at least playing frequency and duty cycle.

[0124] (1) Data transmission: the processor controls N sets of M-bit shift registers to receive serial data synchronously based on the rising edge of the clock signal CLK; every time the processor inputs 1-bit data to the M-bit shift register, the data in the M-bit shift register is shifted left by 1 bit, and the highest bit overflows when it exceeds M bits (for example, when M=32, the 33rd bit input will squeeze out the 1st bit).

[0125] (2) Output control: when the latch signal LE is high, the second number of bit latches transmit the second number of parallel data output by the N sets of M-bit shift registers to the logic gate control circuit; when the latch signal LE is low, the second number of bit latches maintain the current output state, ensuring signal stability.

[0126] (3) Play frequency adjustment: the processor pulls up the latch signal LE periodically, so that the serial-parallel converter performs an output according to the current data in the M-bit shift register every time the latch signal generates a rising edge, and the play frequency is consistent with the pull-up frequency of the latch signal. For example, when a play frequency of 50K is required, the processor controls the LE signal to be pulled up once every 20us, that is, the pull-up frequency of LE is 50K.

[0127] The clock signal needs to meet the following conditions: the clock signal completes M-bit (for example, 32-bit) data transmission within a single latch period (the time interval between two adjacent LE pull-ups). For example, when the play frequency is 200K, the single LE period is 5us, and the CLK frequency needs to be ≥6M to ensure that M-bit data is input within 5us.

[0128] (4) Duty cycle adjustment: the processor controls the serial-parallel converter to output parallel high-voltage drive signals to the digital sound chip and maintain the first duration according to the preset duty cycle, and then pulls down the forced low signal OL to make all parallel high-voltage drive signals low to interrupt the output and maintain the second duration. The ratio of the first duration to the second duration matches the preset duty cycle to form a cycle of "output-interrupt". For example, a 50% duty cycle means that the first duration=the second duration.

[0129] It should be noted that the OL signal line of the serial-parallel converter has the function of forcibly pulling down all outputs. By pulling down the OL signal, all current outputs can be interrupted, thereby realizing duty cycle control (for example, a 50% duty cycle corresponds to half the time with drive signal output and half the time without drive signal output). The OL signal needs to be pulled down after the xth clock cycle according to the set duty cycle. Here, x is the key clock cycle count parameter required to achieve the target duty cycle.

[0130] Further, in the FPGA, the main clock of the drive system is 100M, and the preset frequency duty cycle is all frequency division according to the 100M main clock. When the host computer sends the required frequency duty cycle, for example, 50KHz, 50% duty cycle, it can be calculated that under the condition of 100M main clock, every 2000 main clock cycles is a single output of 50KHz. The duty cycle is calculated after frequency division, and 50% is 1000 main clock cycles. This 1000 is the x of the xth clock cycle in the above duty cycle control, and x is an integer.

[0131] It should be noted that the adjustment of the play frequency in this embodiment is completely dependent on the timing dynamic change of the control signal LE, which conforms to the core logic of "serial-parallel converter dynamically adjusts working parameters based on control signal":

[0132] From the parameter adjustment principle, the essence of the playing frequency is the frequency of the serial-parallel converter outputting the driving signal to the digital sound chip, which does not need to modify the hardware circuit and only needs to change the pull-up timing of the LE signal: for example, if the playing frequency needs to be raised from 50KHz to 200KHz, only the pull-up period of the LE signal needs to be shortened from 20μs to 5μs, so that the LE pull-up frequency can be synchronized with the target playing frequency.

[0133] From the hardware support, the driving system adopts FPGA as the processor, the main clock is 100M, and the playing frequency parameter is calculated based on the main clock division: 50KHz playing frequency corresponds to “pulling up LE once every 2000 100M main clock periods”, and 200KHz playing frequency corresponds to “pulling up LE once every 500 100M main clock periods”, and the processor only needs to modify the main clock division coefficient through programming, so as to realize the dynamic adjustment of the LE signal pull-up frequency and further change the playing frequency.

[0134] Compared with the prior art ASIC, the playing frequency of the ASIC is fixed by the internal clock circuit, timing control circuit and other hardware parameters, and if the frequency needs to be adjusted (such as from 50KHz to 200KHz), the flow must be redesigned; and in this embodiment, the playing frequency can be flexibly switched by modifying the LE signal pull-up timing (control signal) combined with FPGA division programming, which completely solves the defect that the parameters of the ASIC cannot be changed.

[0135] The adjustment of the duty cycle is also realized by the dynamic change of the timing of the control signal (OL), which completely fits the logic of “dynamic adjustment of working parameters based on control signal”:

[0136] From the parameter adjustment principle, the essence of the duty cycle is the ratio of the effective driving time (first time) to the interruption time (second time), and its adjustment follows the core link of “preset duty cycle (target) → calculation of OL pull-down opportunity (control signal modulation) → OL signal pull-down (control signal change) → output of the duty cycle meeting the target”: for 30% duty cycle, only the OL pull-down opportunity needs to be adjusted: at 50KHz frequency (corresponding to 2000 main clock periods), the control serial-parallel converter outputs the driving signal for 600 main clock periods (first time) and then pulls down the OL, and the output is interrupted for 1400 main clock periods (second time), so that the ratio of “30%:70%” can be realized without modifying the hardware circuit.

[0137] From the accuracy guarantee, the value of x clock periods in the duty cycle adjustment can be dynamically calculated by “preset duty cycle multiplied by the total period number corresponding to the frequency” (such as 50KHz frequency total period number is 2000, and 30% duty cycle corresponds to x=2000x30%=600), and the calculation process only needs software programming without hardware intervention, which ensures the accuracy of the duty cycle adjustment.

[0138] Compared with the prior art ASIC, the duty cycle of the ASIC is fixed by internal hardware logic such as AND gate and OR gate, and if the duty cycle needs to be adjusted from 50% to 30%, the driving logic circuit must be redesigned; and the present application can realize dynamic switching of the duty cycle through "modification of OL pull-down timing (control signal) combined with x value calculation", which highlights the superiority of adjusting the working parameters based on the control signal and solves the pain points of fixed function and unchangeable working parameters of the traditional technology ASIC.

[0139] It should be noted that in the present driving system, the DDR reading rate can be 100M, the clock frequency of the serial-parallel converter corresponds to 30M, and the LE signal frequency is obtained by frequency division according to the setting value of the upper computer; the PL end of the FPGA realizes data reading and writing rate matching through the FIFO buffer unit, the FIFO is designed with 32-bit width and 16384 depth, data is written from the DDR using a fixed 100M clock, data is read to the serial-parallel converter using a 30M clock, and after each reading of 32-bit data, the LE signal output is completed, and the next reading is performed. When the playing frequency changes, the FPGA dynamically controls the data taking speed of the FIFO according to the playing frequency (i.e. the LE signal frequency), to ensure that the data output rhythm is consistent with the storage rhythm of the shift register group.

[0140] (5) Reset of the driving system: when resetting, the processor pulls up the reset signal RST, and at the same time triggers the rising edges of the clock signal CLK and the latch signal LE, to clear the data in the shift register group and the latch, so as to realize the reset and make the system return to the initial state.

[0141] (6) Signal logic screening and output state control: when the enable signal OE is high, the AND gate is turned on, and the data output by the latch is processed by the AND gate and then enters the high-voltage output buffer; when the enable signal OE is low, the output of the high-voltage output buffer is in a high-impedance state; the output signal of the latch and the forced high-level signal OH are processed by the NAND gate and then input to the first input end of the AND gate; the forced low-level signal OL is connected to the second input end of the AND gate; when the driving system detects an abnormality or needs to control the duty cycle, the forced low-level signal OL is at an effective level OL=0, the AND gate is closed, the data transmission is cut off, and a low level is forced to be output; when the forced high-level signal OH is at an effective level (OH=0), the NAND gate outputs a high level, the AND gate is turned on and outputs a high level; when the driving system works normally, the forced low-level signal and the forced high-level signal are both at an ineffective level (OL=1, OH=1), and the AND gate outputs the signal processed by the NAND gate.

[0142] Specifically, the high resistance state (high impedance state) is that the switch in the circuit is off: at this time, the output end of the high voltage output buffer neither outputs a high level (such as 80V) nor a low level (such as 0V), but presents an open circuit state, which is equivalent to being disconnected from the sound unit of the digital sound chip, and will not have any voltage or current effect on it.

[0143] In a specific embodiment, taking a serial-parallel converter containing 4 groups of 32-bit shift registers and 128-bit latches as an example, the signal configuration rules, initial working state, and driving timing logic are further described.

[0144] Table 3: 16 key signals required for normal operation of the serial-parallel converter

[0145]

[0146] (1) Signal initialization before playing (after receiving the start playing command).

[0147] The FPGA needs to adjust 3 key signals first, so that the serial-parallel converter switches from the initial state to the standby playing state:

[0148] Release forced high / low level: OH=1, OL=1 (release the lock of "forced high level" and "forced low level", allowing the high voltage output to change with data);

[0149] Turn on the output enable: OE=1 (switch the high voltage output end of HV583 from the high resistance state to the effective output state, and the subsequent high voltage driving signal can be output).

[0150] (2) Data transmission and timing control during playing.

[0151] The FPGA transmits data to the serial-parallel converter according to the fixed timing to ensure the synchronous output of 128 high voltage signals:

[0152] Data storage: on the rising edge of each CLK (clock signal), DnA (D1A~D4A) stores 1-bit data into the corresponding 32-bit shift register;

[0153] Data latching output: every 32-bit data (corresponding to 1 group of complete subserial data) is stored, the FPGA pulls up LE (latch signal) for 1 clock cycle, and then pulls it down. When LE is pulled up, the 32-bit data in the 32-bit shift register is transmitted synchronously to the 128-bit latch, and finally output to the digital sound chip through the high voltage buffer, realizing 1-time pixel vibration driving.

[0154] (3) Duty cycle control output interrupt logic.

[0155] The duty cycle adjustment is realized by an OL (forced low level) signal, and the high voltage output is interrupted to match the preset duty cycle: when the FPGA counts the "duty cycle stop playing part" (such as the no output period of 50% duty cycle), OL=0 (force all high voltage outputs to low level); at this time, whether there is data in the shift register or not, the HVOUT (output of the serial-parallel converter) outputs low level, realizes output interruption, and after the stop period ends, OL=1 is restored to normal output, forming a cycle of "output-interruption" (i.e. duty cycle control).

[0156] The embodiment has the following technical effects: 1) The multiple serial-parallel converters are independent and controlled by independent GPIO of the FPGA, without the need of designing a complex chip cascade circuit, reducing the number of hardware interfaces and wiring difficulty, and reducing the system failure rate. 2) The same CLK, LE and OE signals are shared by the serial-parallel converters, ensuring that all serial-parallel converters complete data reception, latching and high voltage output at the same timing, avoiding the synchronization difference of pixel vibration caused by the delay difference of control signals of multiple digital sound generation chips, and preventing audio distortion. 3) The FPGA controls each serial-parallel converter by independent GPIO, and can individually configure the data distribution logic of each serial-parallel converter (such as the difference of pixel driving requirements of different digital sound generation chips); at the same time, the unified control signal ensures synchronization, supports flexible expansion of multiple chips, and does not need to sacrifice driving consistency, solving the contradiction between difficult expansion and synchronization difference of traditional multiple chip driving.

[0157] The serial-parallel converter designed in the embodiment of the application needs to be distinguished from other types of serial-parallel converters in the field of digital sound generation, and the following is described.

[0158] For example, in the traditional technology, a multi-channel digital loudspeaker system also includes a serial-parallel converter, the front end of the system is connected to a sound field controller, the multi-channel parallel PCM signal is first converted into a single-channel high-speed serial data (the sampling rate is increased to L times) by the serial-parallel converter, then processed by a generalized encoder (converting PCM encoding to binary state encoding) and an extraction selector (selecting a single-channel encoded signal), and converted back to L parallel data by the serial-parallel converter; the back end is connected to a multi-channel digital power amplifier, and outputs a 1-bit wide, low voltage (such as 3.3V) parallel binary encoded signal to the power amplifier, which is finally amplified by the power amplifier to drive the loudspeaker array. The core function of this type of serial-parallel conversion unit is to reduce the number of transmission lines and reduce multi-channel signal interference through parallel-serial-parallel format conversion, and to realize beam directivity optimization and frequency response flatness correction with the sound field controller. The circuit structure takes data selector, clock frequency division and clock frequency multiplication unit as the core, without high voltage driving hardware and multi-channel synchronization control capability.

[0159] The serial-parallel converter is specially adapted to the high-voltage driving requirement of the digital sound chip, front-end connection of the FPGA receives multi-channel sub-serial data and control signals output by 11 control pins, and rear-end direct connection of the digital sound chip outputs 128 channels of 80V high-voltage parallel driving signals. The core function is not only format conversion, but also integration of 4 groups of 32-bit shift registers + 128-bit latches, to realize few-pin control of multiple channels (for example, 11 control pins control 128 channels) and synchronous output of high-voltage signals, and to support dynamic adjustment of playing frequency and duty cycle through LE / OL signals, to directly drive pixel diaphragm vibration sound.

[0160] In an alternative embodiment, when the driving system drives multiple digital sound chips, the FPGA controls multiple serial-parallel converters through different GPIO pins by hardware circuits; meanwhile, the FPGA outputs the same clock signal (CLK), latch signal (LE) and enable signal (OE) to each serial-parallel converter to ensure timing synchronization, and the data end distributes sub-serial data according to timing, to finally realize synchronous output of parallel high-voltage driving signals.

[0161] Referring to Figure 6 The embodiment of the present application also provides a driving method of the digital sound chip, which is applied to the driving system of the digital sound chip in any of the above embodiments, and can include the following steps.

[0162] Step 610: The processor receives audio data, and outputs multi-channel sub-serial data and control signals to the serial-parallel converter through a first number of output pins of the processor;

[0163] Step 620: The serial-parallel converter receives the multi-channel sub-serial data and control signals, dynamically adjusts working parameters based on the control signals, and converts the multi-channel sub-serial data into a second number of parallel high-voltage driving signals, to drive a second number of to-be-driven sound units in the digital sound chip; wherein the first number is less than the second number.

[0164] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the attached drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. Some measures described in mutually different dependent claims can be combined and produce a good result.

[0165] Although the present application has been described in connection with the preferred embodiments thereof with reference to the specific content thereof, it will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. Accordingly, it is intended that the present application cover all such modifications and changes as fall within the scope of the application, along with all equivalents thereof. It will be understood by those within the art that, in general, terms used herein, and especially to the immediately preceding description and claims attached hereto, are intended to be given their broadest interpretation consistent with the specification and the patent statutes.

Claims

1. A driving system for a digital sound chip, characterized in that, At least including: Processors, serial-to-parallel converters, and digital sound chips; The first number of output pins in the processor are connected to the corresponding pins in the serial-to-parallel converter, and the processor is used at least to convert one received total serial data into multiple sub-serial data. The serial-to-parallel converter is used to receive multiple sub-serial data and control signals output by the processor, dynamically adjust the operating parameters based on the control signals, and convert the multiple sub-serial data into a second number of parallel high-voltage drive signals to drive a second number of sound-generating units to be driven in the digital sound-generating chip; wherein, the first number is less than the second number; The control signals include at least a clock signal and a latch signal; the operating parameters include at least a playback frequency. The processor periodically pulls the latch signal high, so that each time the latch signal generates a rising edge, the serial-to-parallel converter performs an output based on the data in the current M-bit shift register, and the playback frequency is consistent with the high frequency of the latch signal. The clock signal completes M-bit data transmission within a single latch cycle.

2. The driving system for the digital sound chip according to claim 1, characterized in that, The serial-to-parallel converter includes: a shift register group, a latch, a logic gate control circuit, and a high-voltage output buffer circuit; The data input terminal of the shift register group receives the multi-channel sub-serial data; the shift register group consists of N groups of M-shift registers, and each of the N groups of M-shift registers receives one sub-serial data from the multi-channel sub-serial data; the product of N and M is the second quantity; N and M are both positive integers, and M is the number of bits in each group of M-shift registers; The data output terminal of the shift register group is connected to the data input terminal of the latch; the latch is a second-quantity bit latch, the data input terminal of the latch corresponds one-to-one with the data output terminal of the shift register group, and the total number of bits of the shift register group and the latch is the second quantity; The data output terminal of the latch is connected to the input terminal of the logic gate control circuit, and the output terminal of the logic gate control circuit is connected to the input terminal of the high-voltage output buffer circuit.

3. The driving system for the digital sound chip according to claim 2, characterized in that, The high-voltage output buffer circuit includes a second number of high-voltage output buffers, each of which has a built-in push-pull output circuit. The push-pull output circuit is used to convert the low-level signal output by the logic gate control circuit into a high-voltage drive signal.

4. The driving system for the digital sound chip according to claim 3, characterized in that, The logic gate control circuit includes a second set of logic gates; each set of logic gates in the second set of logic gates is connected to one output terminal of the second set of bit latches. Each group of logic gates includes NAND gates and AND gates; The first input terminal of the NAND gate is connected to a corresponding output terminal of the latch, and the second input terminal of the NAND gate is connected to a forced high-level signal; The output of the NAND gate is connected to the first input of the AND gate; the second input of the AND gate is connected to a forced low-level signal. The output terminal of the AND gate is connected to the level signal input terminal of the corresponding high-voltage output buffer; the enable signal input terminal of the high-voltage output buffer is connected to an enable signal.

5. The driving system for the digital sound chip according to claim 4, characterized in that, The control signal also includes a forced low-level signal; The processor controls the serial-to-parallel converter to output parallel high-voltage drive signals to the digital sound chip according to a preset duty cycle and maintains the output for a first duration. Then, it pulls the forced low-level signal low to make all parallel high-voltage drive signals low to interrupt the output and maintain the output for a second duration. The ratio of the first duration to the second duration matches the preset duty cycle.

6. The driving system for the digital sound chip according to claim 4, characterized in that, The control signal also includes a reset signal; During reset, the processor pulls the reset signal high and simultaneously triggers the rising edge of the clock signal and the latch signal to clear the data in the shift register group and the latch to achieve reset.

7. The driving system for the digital sound chip according to claim 4, characterized in that, The control signals also include an enable signal and a forced high-level signal; When the enable signal is high, the AND gate is turned on, and the data output by the latch enters the high-voltage output buffer after being processed by the AND gate; when the enable signal is low, the output of the high-voltage output buffer is in a high-impedance state. The output signal of the latch and the forced high-level signal are processed by a NAND gate and then input to the first input terminal of the AND gate; the forced low-level signal is connected to the second input terminal of the AND gate. When the drive system detects an anomaly or needs to control the duty cycle, the forced low-level signal is active, the AND gate is closed, data transmission is cut off, and a forced low-level output is forced; when the forced high-level signal is active, the NAND gate outputs a high level, the AND gate is turned on, and a high-level output is forced. When the drive system is working normally, both the forced low-level signal and the forced high-level signal are invalid levels, and the AND gate output is the signal processed by the NAND gate.

8. The driving system for the digital sound chip according to claim 2, characterized in that, The second number is 128; The shift register group includes four groups of 32-bit shift registers; the four groups of 32-bit shift registers share one clock signal input terminal, one reset signal input terminal, and one direction signal input terminal, and each of the four groups of 32-bit shift registers has one data input terminal and 32 data output terminals; The latch is a 128-bit latch; the 128 data input terminals of the 128-bit latch correspond one-to-one with the 128 data output terminals of the shift register group.

9. A driving method for a digital sound-generating chip, applied to the driving system of the digital sound-generating chip as described in claim 1, characterized in that, The method includes: The processor receives audio data and outputs multiple sub-serial data and control signals to the serial-to-parallel converter through its first number of output pins. The serial-to-parallel converter receives the multi-channel sub-serial data and the control signal, dynamically adjusts the operating parameters based on the control signal, and converts the multi-channel sub-serial data into a second number of parallel high-voltage drive signals to drive a second number of sound-generating units to be driven in the digital sound-generating chip; wherein the first number is less than the second number.

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