Memory device and forming method thereof

Abstract

A memory device includes a plurality of first memory cells formed in a first region of a substrate, a plurality of first via structures formed in a second region of the substrate, the second region being disposed alongside the first region along a first lateral direction, a first front-side interconnect structure of a plurality of front-side interconnect structures formed on a first side of the substrate, and a second front-side interconnect structure of a plurality of second memory cells formed on a second side of the substrate. Wherein the first front-side interconnect structure is coupled to gate terminals of access transistors of the plurality of first memory cells, and a first back-side interconnect structure of a plurality of back-side interconnect structures formed on a second side of the substrate vertically opposite the first side, wherein the first backside interconnect structure is coupled to the first front side interconnect structure through one or more first vias of the plurality of first vias. The embodiment of the invention also discloses a method for forming the memory device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. As the IC industry continues to evolve, there is an ongoing need to improve the performance of integrated circuits. One way to improve performance is to increase the number of devices that are integrated into a single chip. This process of increasing the number of devices integrated into a single chip is often referred to as device scaling. Device scaling typically provides benefits by improving production efficiency and reducing associated costs. SUMMARY

[0003] According to one aspect of embodiments of the present application, a memory device is provided, comprising: a plurality of first memory cells formed in a first region of a substrate; a plurality of first via structures formed in a second region of the substrate, the second region disposed alongside the first region along a first lateral direction; a first front-side interconnect structure of a plurality of front-side interconnect structures formed on a first side of the substrate, wherein the first front-side interconnect structure is coupled to gate terminals of access transistors of the plurality of first memory cells; and a first back-side interconnect structure of a plurality of back-side interconnect structures formed on a second side of the substrate that is vertically opposite the first side, wherein the first back-side interconnect structure is coupled to the first front-side interconnect structure through one or more first via structures of the plurality of first via structures.

[0004] According to another aspect of embodiments of the present application, a memory device is provided, comprising: a memory array comprising a plurality of memory cells, wherein the plurality of memory cells are formed in a first region of a substrate; a first interconnect structure formed on a first side of the substrate, wherein the first interconnect structure is operable as a first portion of word lines of the plurality of memory cells; a second interconnect structure formed on a second side of the substrate that is opposite the first side, wherein the second interconnect structure is operable as a second portion of the word lines of the plurality of memory cells; and one or more via structures formed in a second region of the substrate, the second region located alongside the first region along a lateral direction, wherein the one or more via structures are configured to couple the first interconnect structure to the second interconnect structure; wherein the first interconnect structure and the second interconnect structure each extend along the lateral direction to pass through both the first region and the second region.

[0005] According to yet another aspect of the embodiments of the application, a method of forming a memory device is provided, including: forming a plurality of memory cells on a first region and a first side of a substrate; forming a first interconnect structure on the first side of the substrate and over the plurality of memory cells, wherein the first interconnect structure is coupled to corresponding gate terminals of the plurality of memory cells; flipping the substrate; forming a via structure in a second region of the substrate and on a second side, wherein the second region is positioned alongside the first region along a lateral direction; and forming a second interconnect structure on the second side of the substrate, wherein the second interconnect structure is coupled to the first interconnect structure through the via structure; wherein the first interconnect structure and the second interconnect structure both extend along the lateral direction to pass through both the first region and the second region. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be emphasized that numerous variations and modifications can be made to the embodiments described and illustrated herein, and that industrial applicability exists in the embodiments in their various permutations and incantations. Accordingly, the application is not intended to be limited to the embodiments described but is to be accorded with the broadest scope allowable by the discipline.

[0007] Figure 1 A block diagram of an example memory device is shown in accordance with some embodiments.

[0008] Figure 2 A schematic diagram of an example circuit that can be included in a memory device in accordance with some embodiments is shown. Figure 1

[0009] Figure 3A And Figure 3B An example layout associated with the example circuit in accordance with some embodiments is shown.

[0010] Figure 4 A schematic diagram of an example circuit that can be included in a memory device in accordance with some embodiments is shown. Figure 1

[0011] Figure 5A And Figure 5B An example layout associated with the example circuit in accordance with some embodiments is shown.

[0012] Figure 6A And Figure 6B A schematic diagram of an example circuit that can be included in a memory device in accordance with some embodiments is shown. Figure 1

[0013] A schematic diagram of an example circuit that can be included in a memory device in accordance with some embodiments is shown. Figure 7 Figure 1 An example layout associated with the example circuit in accordance with some embodiments is shown.

[0014] Figure 8 ​​​An example layout associated with an example circuit is shown in accordance with some embodiments.

[0015] Figure 9 A flowchart of an example method for forming a memory device is shown.

[0016] Figure 10 A flowchart of an example method for forming a memory device is shown. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific embodiments or examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and second component are directly contacted formed, and can also include embodiments where additional components can be formed between the first component and second component such that the first component and second component can not be directly contacted. Furthermore, the application can be repeated with variations and / or modifications to the various examples. This repetition is for simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.

[0018] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] Generally, word line (WL) delay is one of the factors that significantly impacts the overall speed of a memory device, such as a static random access memory (SRAM). SRAM devices retain data when powered, providing faster access speed and better reliability for high performance applications. However, as semiconductor technology shrinks, the poly pitch (spacing between poly lines) also decreases, which causes the WL to narrow, increasing resistance and capacitance, which in turn reduces WL delay and slows down memory access speed. Additionally, in memory devices that use backside metal lines, the backside metal lines cannot be directly connected to the frontside device gate, which requires indirect connections, resulting in higher resistance and capacitance, while also increasing design complexity. The present disclosure can effectively improve WL delay by utilizing a via structure to implement a backside WL scheme, addressing these challenges.

[0020] The present disclosure provides various embodiments of a memory device (or integrated circuit). The memory device can include a memory array formed in a first region of a substrate, a first interconnect structure formed on a first side of the substrate, a second interconnect structure formed on a second side of the substrate, and a via structure formed in a second region of the substrate such that the via structure can couple the first interconnect structure to the second interconnect structure. This can enable a backside WL scheme while improving WL latency issues without significantly impacting device area.

[0021] Figure 1 A block diagram of an example memory device 100 is shown in accordance with some embodiments. The memory device 100 includes a memory controller 105 and a memory array 120. In one aspect, the memory array 120 includes a plurality of storage circuits or memory cells 125. The memory array 120 also includes word lines WL0, WL1... WL J and bit lines BL0, BL1... BL K each extending in a second direction (e.g., Y direction). The word lines WL and the bit lines BL can each be a conductive metal or a conductive track. In some embodiments, each memory cell 125 is coupled to a respective word line WL and a respective bit line BL, and can be operated according to a voltage or current through the respective word line WL and the respective bit line BL. In some embodiments, each bit line includes a bit line BL, BLB coupled to one or more memory cells 125 in a set of memory cells 125 arranged along the second direction (e.g., Y direction). The bit lines BL, BLB can receive and / or provide a differential signal.

[0022] Each memory cell 125 can include a volatile memory cell, a non-volatile memory cell, or a combination thereof. For example, each memory cell 125 is implemented as a static random access memory (SRAM) cell. However, it should be appreciated that the memory cells 125 can be implemented as any of a variety of other non-volatile memory cells, such as resistive random access memory (RRAM) cells, magnetoresistive random access memory (MRAM) cells, phase change random access memory (PCRAM) cells, electrical fuses, anti-fuses, etc., while still being within the scope of the present disclosure. In some embodiments, the memory array 120 includes additional lines (e.g., select lines, reference lines, reference control lines, power rails, etc.).

[0023] Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes bit line (BL) controller 112, word line (WL) controller 114, and voltage provision circuit 110. BL controller 112, WL controller 114, and voltage provision circuit 110 can be embodied as logic circuits, analog circuits, or a combination thereof. In one configuration, WL controller 114 is a circuit that provides a voltage or current through one or more word lines WL of memory array 120, and BL controller 112 is a circuit that provides or senses a voltage or current through one or more bit lines BL of memory array 120. In one configuration, voltage provision circuit 110 is a circuit that provides a voltage signal to BL controller 112 and / or WL controller 114. BL controller 112 can be coupled to bit lines BL of memory array 120, and WL controller 114 can be coupled to word lines WL of memory array 120. In some embodiments, memory controller 105 includes more, fewer, or different components than shown. Figure 1

[0024] In various embodiments, memory array 120 can include a plurality of memory cells 125 formed in a first region of a substrate. Memory array 120 can include a first interconnect structure formed on a first side of the substrate and operable as a first portion of word lines of the plurality of memory cells 125. Memory array 120 can include a second interconnect structure formed on a second side of the substrate opposite the first side and operable as a second portion of the word lines of the plurality of memory cells 125. Memory array 120 can include one or more via structures formed in a second region of the substrate adjacent to the first region along a lateral direction and configured to couple the first interconnect structure to the second interconnect structure. The first interconnect structure and the second interconnect structure can each extend along the lateral direction to pass through both the first region and the second region.

[0025] In some embodiments, memory device 100 can include a plurality of first memory cells 125 formed in a first region of a substrate. Memory device 100 can include a plurality of first via structures formed in a second region of the substrate, the second region disposed alongside the first region along a first lateral direction. Memory device 100 can include a first front-side interconnect structure of a plurality of front-side interconnect structures formed on a first side of the substrate. The first front-side interconnect structure can be coupled to gate terminals of access transistors of the plurality of first memory cells 125. Memory device 100 can include a first back-side interconnect structure of a plurality of back-side interconnect structures formed on a second side of the substrate perpendicular to the first side. The first back-side interconnect structure can be connected to the first front-side interconnect structure through one or more first via structures of the plurality of first via structures.​

[0026] Figure 2 The illustration shows that, according to some embodiments, it may include in Figure 1 A schematic diagram of an example circuit 200 in a memory device. Circuit 200 may include a plurality of memory cells (e.g., memory cells 225, 226), a first word line 210, a second word line 220, first interconnect structures 230, 231, 232, 233, 234, 235, second interconnect structures 240, 241, one or more through-hole structures 250, and one or more through-hole structures 251. It should be understood that, for illustrative purposes, Figure 2 The schematic diagram is simplified, therefore, circuit 200 can be implemented in any of a variety of other configurations while still remaining within the scope of this disclosure.

[0027] Multiple memory cells may be a memory array 120. In some embodiments, the multiple memory cells may be arranged along rows of the memory array and span multiple columns (e.g., M columns). In some embodiments, the multiple memory cells may be formed in a first region of a substrate. The multiple memory cells (e.g., memory cells 225, 226) may include or be coupled to access transistors (e.g., access transistors 225T, 226T). Access transistors 225T, 226T may connect memory cells 225, 226 to corresponding bit lines BL / BLB. In some embodiments, memory cell 225 may include multiple first memory cells, and memory cell 226 may include multiple second memory cells. In some embodiments, each of the multiple memory cells (e.g., memory cells 225, memory cells 226, etc.) may include a static random access memory (SRAM) cell.

[0028] The first word line 210 and the second word line 220 can be a memory array 120. In some embodiments, the first word line 210 can be a front-side word line. In some embodiments, the second word line 220 can be a back-side word line. The first word line 210 and the second word line 220 can be connected in various ways. In some embodiments, the first word line 210 and the second word line 220 can be connected by a first interconnect structure 230, a second interconnect structure 240, and one or more via structures 250. In some embodiments, the one or more via structures 250 can be feed-through via structures. In some embodiments, the first interconnect structure 230 can be formed on a first side (e.g., a front side) of a substrate. For example, the first interconnect structure 230 can be a front-side interconnect structure. In some embodiments, the first interconnect structure 230 can be configured to be operable as part of the first word line 210 for the memory cell 225. In some embodiments, the second interconnect structure 240 can be formed on a second side (e.g., a back side) of the substrate opposite the first side. For example, the second interconnect structure 240 can be a back-side interconnect structure. In some embodiments, the second interconnect structure 240 can be configured to be operable as part of the word line 220 for the memory cell 225.

[0029] In some embodiments, the circuit 200 can include a plurality of front-side interconnect structures (e.g., the first interconnect structure 230, interconnect structures 231, 232, 233, 234, etc.). The interconnect structures 231, 232, 233, 234 can be formed on a front side of a substrate. In some embodiments, the interconnect structures 231, 232 can be coupled to gate terminals of the memory cell 225. For example, the interconnect structures 231, 232 can be coupled to gate terminals of access transistors 225T of the memory cell 225. In some embodiments, the interconnect structures 231, 232 can be configured to be operable as part of the first word line 210 for the memory cell 225 while being coupled to the memory cell 225 through the gate terminals of the access transistors 225T. In some embodiments, the circuit 200 can include a plurality of back-side interconnect structures (e.g., the second interconnect structure 240, interconnect structures 241, etc.). As shown, the interconnect structures 240, 241 can be formed on a back side of a substrate perpendicular to the front side. In some embodiments, the interconnect structures 233, 234 can be coupled to gate terminals of the memory cell 226. For example, the interconnect structures 233, 234 can be coupled to gate terminals of access transistors 226T of the memory cell 226. In some embodiments, the interconnect structures 233, 234 can be configured to be operable as part of the first word line 210 for the memory cell 226 while being coupled to the memory cell 226 through the gate terminals of the access transistors 226T.

[0030] One or more via structures 250 can be formed in a second region of the substrate. For example, the second region can be located alongside the first region (e.g., a plurality of memory cells can be formed in the first region). In some embodiments, as shown, the one or more via structures 250 can be configured to couple the first interconnect structure 230 (e.g., a front-side interconnect structure) to the second interconnect structure 240 (e.g., a back-side interconnect structure).

[0031] In some embodiments, the first word line 210 and the second word line 220 can be connected by a first interconnect structure 235, a second interconnect structure 241, and one or more via structures 251. In some embodiments, the first interconnect structure 235 can be formed on a first side (e.g., a front side) of the substrate. For example, the first interconnect structure 235 can be a front-side interconnect structure. In some embodiments, the first interconnect structure 235 can be configured to be operable as part of the first word line 210 of the memory cell 226. In some embodiments, the second interconnect structure 241 can be formed on a second side (e.g., a back side) of the substrate opposite the first side. For example, the second interconnect structure 241 can be a back-side interconnect structure. In some embodiments, the second interconnect structure 241 can be configured to be operable as part of the word line 220 of the memory cell 226.

[0032] In some embodiments, the circuit 200 can include a plurality of front-side interconnect structures (e.g., the first interconnect structure 235, the interconnect structures 233, 234, etc.) associated with a second memory cell (e.g., the memory cell 226). The interconnect structures 233, 234 can be formed on a front side of the substrate. In some embodiments, the interconnect structures 233, 234 can be coupled to a gate terminal of an access transistor 226T of the memory cell 226. For example, the interconnect structures 233, 234 can be coupled to a gate terminal of an access transistor 226T of the memory cell 226. In some embodiments, the interconnect structures 233, 234 can be configured to be operable as part of the first word line 210 of the memory cell 226 while being coupled to the memory cell 226 through the gate terminal of the access transistor 226T. In some embodiments, the circuit 200 can include a plurality of back-side interconnect structures (e.g., the second interconnect structure 240, the interconnect structures 241, etc.). As shown, the interconnect structures 240, 241 can be formed on a back side of the substrate vertically opposite the front side.

[0033] One or more via structures 251 can be formed in a second region of the substrate. For example, the second region can be located alongside the first region (e.g., a plurality of memory cells can be formed in the first region). In some embodiments, as shown, the one or more via structures 251 can be configured to couple the first interconnect structures 235 (e.g., front side interconnect structures) to the second interconnect structures 241 (e.g., back side interconnect structures). In some embodiments, the one or more via structures 251 can be formed in an opposite portion of the second region of the substrate (e.g., opposite the one or more via structures 250 with respect to the memory cells 225, 226, etc.).

[0034] Figure 3A and Figure 3B An example layout 300 associated with an example circuit is shown in accordance with some embodiments. More specifically, Figure 3A A cross-sectional view of the layout 300 is shown, in particular Figure 3B A cross-section of portion Y in Figure 3B A top view of the layout 300 is shown in. In some embodiments, the layout 300 can be associated with the circuit 200. Figure 3A and Figure 3B The layout 300 shown in

[0035] Referring to Figure 3A In some embodiments, on a front side of the substrate, the circuit can include active regions (e.g., a plurality of transistors, gate structures, source / drain structures, etc.) and at least a portion of the via structures 350. Above the front side, the circuit can include a plurality of source / drain interconnect structures (sometimes referred to as MD 301), some of which are coupled with gate via structures (sometimes also referred to as VD 302) and the via structures 350 formed thereon. Above the gate structures of the transistors in the active regions, the circuit can include a plurality of gate via structures (sometimes referred to as VG) (not shown).

[0036] VD 302 can couple MD 301 to first metal lines (sometimes referred to as M0 tracks 303) in a first (e.g., bottom-most) front-side metallization layer. Above the first metal lines (e.g., M0 tracks 303) (and various other metal lines in the bottom-most front-side metallization layer), the circuitry can include a plurality of via structures (sometimes referred to as V0 304) to couple the first metal lines (e.g., M0 tracks 303) to corresponding one or more metal lines (sometimes referred to as Ml tracks 330) in a next front-side metallization layer further from the substrate. Further, above the Ml tracks 330 (and various other metal lines in the same front-side metallization layer), the circuitry can include a plurality of via structures (not shown) to couple the Ml tracks 330 to respective one or more metal lines in a next front-side metal layer further from the substrate. Although two front-side metallization layers are shown, it will be appreciated that the circuitry can include any number of front-side metallization layers. According to various embodiments, metal tracks formed across such front-side metallization layers can be configured to electrically couple different components of the circuitry (in order to route signals and / or deliver power).

[0037] Referring to Figure 3A On the backside of the substrate, the circuitry can include a plurality of backside via structures (sometimes referred to as BV) that can couple source / drain structures and gate structures of transistors in the active region to a plurality of metal lines (sometimes also referred to as BM0 tracks 306) in a first (e.g., top-most) backside metallization layer. In some embodiments, on the backside of the substrate, the circuitry can include at least a portion of the via structures 350. In some embodiments, above the BM0 tracks 306, the circuitry can include a plurality of via structures (sometimes referred to as BV0 305) that can couple the BM0 tracks 306 to a plurality of metal lines (e.g., BMl tracks 340) in a next backside metallization layer further from the substrate. Further, above the BMl tracks 340, the circuitry can include a plurality of via structures (sometimes referred to as BVl) (not shown) that can couple the BMl tracks 340 to a plurality of metal lines (sometimes referred to as BM2 tracks) (not shown) in a next backside metallization layer further from the substrate.

[0038] Figure 3B Shown in FIG. 3 is a layout 300 in a top-down view. In a first region of a substrate, circuitry (e.g., circuitry 200) associated with the layout 300 can include a plurality of memory cells (e.g., first memory cell 325, second memory cell 326, etc.). The circuitry can include a plurality of via structures in a second region of the substrate (e.g., including portion Y). The second region can be alongside the first region along a lateral direction (e.g., the x-axis as shown). Figure 3B

[0039] ​In some embodiments, the circuit may include a plurality of memory cells arranged along rows of a memory array formed in a first region and spanning a plurality of columns. In some embodiments, a second memory cell 326 may be aligned with a first memory cell 325 along the x-axis. In some embodiments, although not shown, the second memory cell 326 may be aligned with the first memory cell 325 along the y-axis.

[0040] In some embodiments, the circuit may include via structures and interconnect structures (e.g., BMO 306, M0 303, etc.) formed in various portions of the second region. For example, as Figure 3B As shown, the circuit may include a first set of via structures (e.g., via structures 304A, 305A, etc.) and a first set of interconnect structures (e.g., BMO 306A, M0 303A, etc.) in a first portion of the second region; and a second set of via structures (e.g., via structures 304B, 305B, etc.) and a second set of interconnect structures (e.g., BMO 306B, M0 303B, etc.) in a second portion of the second region. In some embodiments, such as Figure 3B As shown, the via structure assembly and the interconnect structure assembly can be arranged along the x-axis and / or y-axis. In some embodiments, such as Figure 3B As shown, a set of through-hole structures (e.g., through-hole structures 304B, 305B, 304C, 305C, etc.) can be shifted along the x and y axes from another set of through-hole structures (e.g., through-hole structures 304A, 305A, etc.). In some embodiments, such as Figure 3B As shown, interconnect sets (e.g., BMO 306A, M0 303A, etc.) can be shifted along the x and y axes from another interconnect set (e.g., BMO 306B, M0303B, BMO 306C, M0 303C, etc.). In some embodiments, the circuit may include a plurality of M1 tracks (e.g., M1 track 330A, M1 track 330B, etc.) arranged along the y-axis. Figure 3B As shown, M1 track 330B can be shifted from M1 track 330A along the x and y axes. In some embodiments, the circuit may include multiple BM1 tracks (e.g., BM1 track 340A, BM1 track 340B, etc.) arranged along the y-axis. Figure 3B As shown, BM1 track 340B can be shifted from BM1 track 340A on the x and y axes.

[0041] In some embodiments, the M1 track 330 may extend along the x-axis (e.g., as shown in the figure). Figure 3BM0 tracks 303A, 303B in FIG. 3B). In some embodiments, the M0 tracks 303 can pass through the M1 tracks 330, the BM1 tracks 340, and / or the like. In some embodiments, the MD 301 can extend along the x-axis (e.g., as shown in FIG. 3A, FIG. 3B, and / or the like). Figure 3B M0 tracks 303A, 303B in FIG. 3B). In some embodiments, the M0 tracks 303 can pass through the M1 tracks 330, the BM1 tracks 340, and / or the like. In some embodiments, the MD 301 can extend along the x-axis (e.g., as shown in FIG. 3A, FIG. 3B, and / or the like). Figure 3B MD 301A, MD 301B in FIG. 3B). In some embodiments, the MD 301 can pass through the M0 tracks 303, the BM0 tracks 306, and / or the like. In some embodiments, the BM0 tracks 306 can extend along the y-axis (e.g., as shown in FIG. 3A, FIG. 3B, and / or the like). Figure 3A BM0 tracks 306A, 306B in FIG. 3B). In some embodiments, the BM0 tracks 306 can pass through the M1 tracks 330, the BM1 tracks 340, and / or the like. In some embodiments, the BM1 tracks 340 can extend along the x-axis (e.g., as shown in FIG. 3A, FIG. 3B, and / or the like). Figure 3B BM1 tracks 340A, 340B in FIG. 3B). In some embodiments, the BM1 tracks 340 can pass through the first memory cells 325, the second memory cells 326, and / or the like.

[0042] In some embodiments, the via structures (e.g., V0 304, VD 302, via structures 350, BV0 305, and / or the like) can extend along the z-axis to connect at least one of the M1 330, the M0 303, the MD 301, the BM0 306, and the BM1 340 to another.

[0043] In some embodiments, one or more via structures can each extend through the substrate (e.g., through the z-axis). For example, the via structures 350 can extend through the substrate to connect a first interconnect structure on a front side to a second interconnect structure on a back side. In some embodiments, one or more via structures can be configured to couple a first interconnect structure to a second interconnect structure. For example, as shown in FIG. 3A, FIG. 3B, and / or the like, a via structure (e.g., via structures 350, VD 302, V0 304, BV0 305, and / or the like) can couple a first interconnect structure (which can be the M1 tracks 330 or a portion thereof) and a second interconnect structure (which can be the BM1 tracks 340 or a portion thereof). In some embodiments, the via structures can each extend through the substrate to connect a first side (e.g., a front side) of the substrate to a second side (e.g., a back side). Figure 3B

[0044] Reference is made to Figure 3A ​In some embodiments, circuitry associated with the layout 300 (e.g., circuitry 200) can include a first interconnect structure formed on a first side (e.g., a front side) of the substrate. In some embodiments, the first interconnect structure can be a front side interconnect structure or a portion thereof. For example, the first interconnect structure can be the Ml tracks 330 or a portion of the Ml tracks 330. In some embodiments, the first interconnect structure can be configured to be operable as a first portion of word lines (e.g., of the front side) for a plurality of memory cells (e.g., the first memory cell 325, the second memory cell 326, etc.). In some embodiments, the circuitry can include a second interconnect structure formed on a second side (e.g., a back side) of the substrate opposite the first side. In some embodiments, the second interconnect structure can be a back side interconnect structure or a portion thereof. For example, the second interconnect structure can be the BMl tracks 340 or a portion thereof. In some embodiments, the second interconnect structure can be configured to be operable as a second portion of word lines (e.g., of the back side) for a plurality of memory cells (e.g., the first memory cell 325, the second memory cell 326, etc.).

[0045] In some embodiments, circuitry associated with the layout 300 (e.g., circuitry 200) can include a plurality of first interconnect structures formed on a first side (e.g., a front side) of the substrate. For example, the circuitry can include a first interconnect structure, which can be the M0 tracks 303 or a portion thereof. In some embodiments, the circuitry can include a plurality of back side interconnect structures formed on a second side (e.g., a back side) of the substrate perpendicular to the first side. For example, the circuitry can include a second interconnect structure, which can be the BM0 tracks 306 or a portion thereof. In some embodiments, at least one first interconnect structure (e.g., a front side interconnect structure) can be coupled to gate terminals of access transistors of a plurality of memory cells (e.g., the first memory cell 325, the second memory cell 326, etc.). In some embodiments, at least one second interconnect structure (e.g., a back side interconnect structure) can be coupled to the at least one first interconnect structure through one or more of a plurality of via structures (e.g., the via structures 350).

[0046] In some embodiments, with reference to Figure 3A Circuitry associated with the layout 300 (e.g., circuitry 200) can include a first interconnect structure (which can be the Ml tracks 330 or a portion thereof) and a second interconnect structure (which can be the BMl tracks 340 or a portion thereof), each extending along a lateral direction (e.g., the x-axis) to pass through both the first region and the second region.

[0047] In some embodiments, with reference to Figure 4The circuit associated with layout 300 (e.g., circuit 200) may include multiple first interconnect structures (e.g., front-side interconnect structures). For example, the circuit may include a second interconnect structure (e.g., a second front-side interconnect structure) vertically disposed between the substrate and the first interconnect structure in the first front-side interconnect structure. For example, the first interconnect structure may be an M1 track 330 or a portion thereof, and the second interconnect structure may be an MD301 or a portion thereof. Thus, the second interconnect structure may be vertically disposed between the substrate and the first interconnect structure. In some embodiments, the circuit associated with layout 300 (e.g., circuit 200) may include multiple second interconnect structures (e.g., back-side interconnect structures). For example, the circuit may include a second interconnect structure vertically disposed between the substrate and the first interconnect structure in the second interconnect structure. For example, the first interconnect structure may be a BM1 track 340 or a portion thereof, and the second interconnect structure may be a BM0 track 306 or a portion thereof, such that the second interconnect structure may be vertically disposed between the substrate and the first interconnect structure in the second interconnect structure. In some embodiments, such as Figure 1 As shown, the via structure 350 can directly contact the second in the first interconnect structure (e.g., MD 301) and the second in the second interconnect structure (e.g., BMO 306).

[0048] Figure 4 The illustration shows that, according to some embodiments, it may include in Figure 4 A schematic diagram of an example circuit 400 in a memory device. Circuit 400 may include a plurality of memory cells (e.g., memory cells 425, 426), a first word line 410, a second word line 420, first interconnect structures 431, 432, 433, 434, transistors 450, 451, one or more through-hole structures 460 and one or more through-hole structures 461. It should be understood that, for illustrative purposes, Figure 5A The schematic diagram is simplified, therefore, circuit 400 can be implemented in any of a variety of other configurations, while still remaining within the scope of this disclosure.

[0049] In some embodiments, circuit 400 may be substantially similar to or include features of circuit 200. In some embodiments, in contrast to circuit 200, which includes via structures 250, 251 and interconnect structures 230, 240, 235, 241, circuit 400 may optionally include transistors 450, 451 and via structures 460, 461.

[0050] In some embodiments, at least one of the transistors 450, 451 can be formed in a second region of the substrate. For example, the transistors 450, 451 can be formed in a second region that is alongside a first region in which the memory cells 425, 426 are formed. In some embodiments, as shown, the gate terminals and first source / drain terminals of the transistors 450, 451 can be coupled to a first interconnect structure (which can be part of the word line 410), and the second source / drain terminals of the transistors 450, 451 can be coupled to a second interconnect structure (which can be part of the word line 420) through one or more via structures 460, 461. Figure 5B

[0051] Figure 5A and Figure 5B An example layout 500 associated with an example circuit is shown in accordance with some embodiments. More specifically, Figure 5B A cross-sectional view of the layout 500 is shown, in particular Figure 5A of the portion Y. Figure 5B A top view of the layout 500 is shown in Figure 5A and Figure 5A The layout 500 shown in

[0052] Referring to Figure 5B In some embodiments, on a front side of the substrate, the circuit can include active regions (e.g., multiple transistors, gate structures, source / drain structures, etc.) in a first region and at least a portion of a dissipative element 550 (e.g., a dummy element formed in a transistor) in a second region that is alongside the first region. Above the front side, the circuit can include multiple source / drain interconnect structures (sometimes referred to as MD 500R), some of which are coupled with gate via structures (sometimes also referred to as VD 502) and the dissipative element 550 formed thereon. Above the gate structures of the transistors in the active regions of the first region, the circuit can include multiple gate via structures (sometimes referred to as VG) (not shown).

[0053] ​VD 502 can couple MD 501 to a first metal line (sometimes referred to as M0 track 503) in a first (e.g., bottom-most) frontside metallization layer. Above the first metal line (e.g., M0 track 503) (and various other metal lines in the bottom-most frontside metallization layer), the circuit can include a plurality of via structures (sometimes referred to as V0 504) to couple the first metal line (e.g., M0 track 503) to a corresponding one or more metal lines (sometimes referred to as M1 track 530) in a next frontside metallization layer further from the substrate. Further, above the M1 track 530 (and various other metal lines in the same frontside metallization layer), the circuit can include a plurality of via structures (not shown) to couple the M1 track 530 to a respective one or more metal lines in a next frontside metal layer further from the substrate. Although two frontside metallization layers are shown, it will be appreciated that the circuit can include any number of frontside metallization layers. According to various embodiments, metal tracks formed across such frontside metallization layers can be configured to electrically couple different components of the circuit (in order to route signals and / or deliver power).

[0054] Referring to Figure 5B On the backside of the substrate, the circuit can include a plurality of backside via structures (sometimes referred to as BV), which can couple source / drain structures and gate structures of transistors in the active region of the first region to a plurality of metal lines (sometimes also referred to as BM0 track 506) in a first (e.g., top-most) backside metallization layer. In some embodiments, on the backside of the substrate, in a second region next to the first region, the circuit can include a via structure 560. In some embodiments, above the BM0 track 506, the circuit can include a plurality of via structures (sometimes referred to as BV0 505), which can couple the BM0 track 506 to a plurality of metal lines (e.g., BM1 track 540) in a next backside metallization layer further from the substrate. Further, above the BM1 track 540, the circuit can include a plurality of via structures (sometimes referred to as BV1) (not shown), which can couple the BM1 track 540 to a plurality of metal lines (sometimes referred to as BM2 track) (not shown) in a next backside metallization layer further from the substrate.

[0055] As shown, in connecting the M1 track 530 and the BM1 track 540, the dissipative element 550 and the via structure 560 can be connected. In some embodiments, a gate terminal and a first source / drain terminal of a transistor (e.g., transistor 450) in the dissipative element 550 can be coupled to the M1 track 530, and a second source / drain terminal of the transistor in the dissipative element 505 can be coupled to the BM1 track 540 through one or more via structures (e.g., via structure 560, BV0, etc.).

[0056] Figure 5B The diagram shows a top view of layout 500. In a first region of the substrate, circuitry associated with layout 500 (e.g., circuitry 400) may include multiple memory cells (e.g., first memory cell 525, second memory cell 526, etc.). The circuitry may include multiple via structures in a second region of the substrate (e.g., portion Y). The second region may extend along a lateral direction (e.g., as shown in the diagram). Figure 5B The x-axis shown is located next to the first region.

[0057] In some embodiments, the circuit may include a plurality of memory cells arranged along rows of a memory array formed in a first region and spanning a plurality of columns. In some embodiments, a second memory cell 526 may be aligned with a first memory cell 525 along the x-axis. In some embodiments, although not shown, the second memory cell 526 may be aligned with the first memory cell 525 along the y-axis.

[0058] In some embodiments, the circuit may include transistors, via structures, and interconnect structures (e.g., BMO 506, M0 503, etc.) formed in various portions of the second region. For example, as Figure 5B As shown, the circuit may include a first set of via structures (e.g., via structures 504A, 505A, 560A, etc.), a dissipative element 550A, and a first set of interconnect structures (e.g., BMO 506A, M0 503A, etc.) in a first portion of the second region; and a second set of via structures (e.g., via structures 504B, 505B, etc.), a dissipative element 550B, and a second set of interconnect structures (e.g., BMO 506B, M0 503B, etc.) in a second portion of the second region. In some embodiments, such as Figure 5B As shown, the via structures, transistors, and interconnect structures can be arranged along the x-axis and / or y-axis. In some embodiments, such as Figure 5B As shown, a set of through-hole structures (e.g., through-hole structures 504B, 505B, 560B, 504C, 505C, 560C, etc.) can be shifted from another set of through-hole structures (e.g., through-hole structures 504A, 505A, 560A, etc.) on both the x-axis and y-axis. In some embodiments, such as Figure 5B As shown, interconnect sets (e.g., BM0 506B, M0 503B, BM0 506C, M0 503C, etc.) can be shifted along both the x-axis and y-axis from another interconnect set (e.g., BM0506A, M0 503A, etc.). In some embodiments, the circuit may include a plurality of M1 tracks (e.g., M1 track 530A, M1 track 530B, etc.) arranged along the y-axis. Figure 5BAs shown, Ml track 530B can be displaced from Ml track 530A in both the x-axis and the y-axis. In some embodiments, the circuit can include a plurality of BMl tracks (e.g., BMl track 540A, BMl track 540B, etc.) arranged along the y-axis. As shown, BMl track 540B can be displaced from BMl track 540A in both the x-axis and the y-axis. Figure 5B

[0059] In some embodiments, Ml track 530 can extend along the x-axis (e.g., as Ml track 530A, 530B in FIG. 5A). In some embodiments, Ml track 530 can pass through first memory cell 525, second memory cell 526, etc. In some embodiments, M0 track 503 can extend along the y-axis (e.g., as M0 track 503A, 503B in FIG. 5A). In some embodiments, M0 track 503 can pass through Ml track 530, BMl track 540, etc. In some embodiments, MD 501 can extend along the x-axis (e.g., as MD 501A, 501B in FIG. 5A). In some embodiments, MD 501 can pass through M0 track 503, BM0 track 506, etc. In some embodiments, BM0 track 506 can extend along the y-axis (e.g., as BM0 track 506A, 506B in FIG. 5A). In some embodiments, BM0 track 506 can pass through Ml track 530, BMl track 540, etc. In some embodiments, BMl track 540 can extend along the x-axis (e.g., as BMl track 540A, 540B in FIG. 5A). In some embodiments, BMl track 540 can pass through first memory cell 525, second memory cell 526, etc. Figure 5B Figure 5B Figure 5B Figure 5A Figure 5A

[0060] In some embodiments, via structures (e.g., V0 504, VD 502, BV0 505, etc.) can extend along the z-axis to connect at least one of Ml 530, M0 503, MD 501, BM0 506, and BMl 540 with another. In some embodiments, dissipative element 550 can extend along the y-axis (e.g., as dissipative element 550A, 550B in FIG. 5A). In some embodiments, dissipative element 550 can pass through Ml track 530, BMl track 540, etc. Figure 5B

[0061] ​​​​​​​In some embodiments, one or more of the via structures and / or transistors may each extend through the substrate (e.g., through the z-axis). For example, dissipative element 550 and via structure 560 may extend through the substrate to connect a first interconnect structure on the front side to a second interconnect structure on the back side. In some embodiments, one or more of the via structures may be configured to couple the first interconnect structure to the second interconnect structure. For example, as... Figure 5B As shown, the transistors formed in the dissipative element 550 and the via structure 560 can couple a first interconnect structure (which may be M1 track 530 or a portion thereof) and a second interconnect structure (which may be BM1 track 540 or a portion thereof). In some embodiments, the dissipative element 550 and the via structure 560 can each extend through the substrate, such that the transistors in the dissipative element 550 and the via structure 560 can connect a first side (e.g., the front side) of the substrate to a second side (e.g., the back side). Figure 5A As shown, the transistors in the dissipation element 550 and the via structure 560 can connect a first side (e.g., the front side) of the substrate to a second side (e.g., the back side).

[0062] refer to Figure 5A In some embodiments, the circuitry associated with layout 500 (e.g., circuitry 400) may include a first interconnect structure formed on a first side (e.g., front side) of the substrate. In some embodiments, the first interconnect structure may be a front-side interconnect structure or a portion thereof. For example, the first interconnect structure may be an M1 track 530 or a portion thereof. In some embodiments, the first interconnect structure may be configured to be operatively used as a first portion of word lines (e.g., front-side word lines) for a plurality of memory cells (e.g., first memory cell 525, second memory cell 526, etc.). In some embodiments, the circuitry may include a second interconnect structure formed on a second side (e.g., back side) of the substrate opposite to the first side. In some embodiments, the second interconnect structure may be a back-side interconnect structure or a portion thereof. For example, the second interconnect structure may be a BM1 track 540 or a portion thereof. In some embodiments, the second interconnect structure may be configured to be operatively used as a second portion of word lines (e.g., back-side word lines) for a plurality of memory cells (e.g., first memory cell 525, second memory cell 526, etc.).

[0063] In some embodiments, a circuit (e.g., circuit 400) associated with the layout 500 can include a plurality of first interconnect structures formed on a first side (e.g., a front side) of a substrate. For example, the circuit can include a first interconnect structure, which can be the M0 track 503 or a portion thereof. In some embodiments, the circuit can include a plurality of backside interconnect structures formed on a second side (e.g., a backside) of the substrate that is vertically opposite the first side. For example, the circuit can include a second interconnect structure, which can be the BM0 track 506 or a portion thereof. In some embodiments, at least one first interconnect structure (e.g., a frontside interconnect structure) can be coupled to a gate terminal of an access transistor of a plurality of memory cells (e.g., the first memory cell 525, the second memory cell 526, etc.). In some embodiments, at least one second interconnect structure (e.g., a backside interconnect structure) can be coupled to the at least one first interconnect structure through one or more of a plurality of via structures and transistors (e.g., the transistors in the dissipative element 550 and the via structure 560).

[0064] In some embodiments, referring to Figure 6A A circuit (e.g., circuit 400) associated with the layout 500 can include a first interconnect structure (which can be the M1 track 530 or a portion thereof) and a second interconnect structure (which can be the BM1 track 540 or a portion thereof), each of which extends along a lateral direction (e.g., the x-axis) to pass through both the first region and the second region.

[0065] In some embodiments, referring to Figure 1 A circuit (e.g., circuit 400) associated with the layout 500 can include a plurality of first interconnect structures (e.g., frontside interconnect structures). For example, the circuit can include a second one of the first interconnect structures (e.g., a second frontside interconnect structure) vertically disposed between the substrate and a first one of the first frontside interconnect structures. For example, the first one of the first interconnect structures can be the M1 track 530 or a portion thereof, and the second one of the first interconnect structures can be the MD 501 or a portion thereof, such that the second one of the first interconnect structures can be vertically disposed between the substrate and the first one of the first interconnect structures. In some embodiments, a circuit (e.g., circuit 400) associated with the layout 500 can include a plurality of second interconnect structures (e.g., backside interconnect structures). For example, the circuit can include a second one of the second interconnect structures vertically disposed between the substrate and a first one of the second interconnect structures. For example, the first one of the second interconnect structures can be the BM1 track 540 or a portion thereof, and the second one of the second interconnect structures can be the BM0 track 506 or a portion thereof, such that the second one of the second interconnect structures can be vertically disposed between the substrate and the first one of the second interconnect structures. In some embodiments, as Figure 6AAs shown, the dissipative element 550 and / or the via structure 560 can be in direct contact with the second in the first interconnect structure (e.g., MD401) and the second in the second interconnect structure (e.g., BM0 506).

[0066] Figure 6A The illustration shows that, according to some embodiments, it may include in Figure 6B A schematic diagram of an example circuit 600 in a memory device. Circuit 600 may include multiple memory cells (e.g., memory cells 625, 626, 627, 628), a first word line 610, a second word line 620, etc. It should be understood that, for illustrative purposes, Figure 1 The schematic diagram is simplified, therefore, circuit 600 can be implemented in any of a variety of other configurations while still remaining within the scope of this disclosure.

[0067] In some embodiments, circuit 600 may be substantially similar to or include features of circuit 200. In some embodiments, unlike circuit 200 which includes word lines 220 connected to columns associated with multiple memory cells (e.g., memory cells 225, 226, etc.), circuit 600 may optionally include word lines 620 connected to a portion of columns associated with multiple memory cells (e.g., memory cells 625, 626, etc.) but not connected to another portion of columns associated with other multiple memory cells (e.g., memory cells 627, 628, etc.). For example, as... Figure 6B As shown, circuit 600 may include M columns. Word line 620 may be connected to N columns associated with a plurality of memory cells (e.g., memory cells 625, 626, etc.), but not to MN columns associated with other plurality of memory cells (e.g., memory cells 627, 628, etc.). In some embodiments, memory cells 627, 628 may be connected to word line 610, but not to word line 620.

[0068] Figure 6B The illustration shows that, according to some embodiments, it may include in Figure 7 A schematic diagram of example circuit 650 in a memory device. Circuit 650 may include multiple memory cells (e.g., memory cells 675, 676, 677, 678), a first word line 660, and a second word line 670. It should be understood that, for illustrative purposes, Figure 1 The schematic diagram is simplified, therefore, circuit 650 can be implemented in any of a variety of other configurations while still remaining within the scope of this disclosure.

[0069] In some embodiments, circuit 650 may be substantially similar to or include features of circuit 400. In some embodiments, in contrast to circuit 400, which includes word lines 420 connected to the entire memory cell (e.g., memory cells 425, 426, etc.), circuit 650 may optionally include word lines 670 connected to a portion of a column associated with a plurality of memory cells (e.g., memory cells 675, 676, etc.), but not connected to another portion of a column associated with other plurality of memory cells (e.g., memory cells 677, 678, etc.). For example, as... Figure 7 As shown, circuit 650 may include M columns. Word line 670 may be connected to N columns associated with a plurality of memory cells (e.g., memory cells 675, 676, etc.), but not to MN columns associated with other plurality of memory cells (e.g., memory cells 677, 678, etc.). In some embodiments, memory cells 677, 678 may be connected to word line 660, but not to word line 670.

[0070] Figure 8 The illustration shows that, according to some embodiments, it may include in Figure 8 A schematic diagram of an example circuit 700 in a memory device. Circuit 700 may include row 200R of circuit 200 and row 700R of the circuit. Row 700R may include a first word line 710, a second word line 720, multiple memory cells (e.g., memory cells 725, 726), interconnect structures 731, 732, 733, 734, etc. It should be understood that, for illustrative purposes, Figure 8 The schematic diagram is simplified, therefore, circuit 700 can be implemented in any of a variety of other configurations while still remaining within the scope of this disclosure.

[0071] In some embodiments, circuit 700 may be substantially similar to or include features of circuit 200. In some embodiments, unlike circuit 200, which may include multiple rows 200R, circuit 700 may optionally include rows 700R. In some embodiments, circuit 700 may include multiple rows, which may be any arrangement of rows 200R and rows 700R. For example, rows 200R and rows 700R may be arranged alternately.

[0072] The plurality of memory cells may be a memory array 120. In some embodiments, the plurality of memory cells (e.g., memory cells 725, 726) may be arranged along rows of the memory array and across multiple columns (e.g., M columns). In some embodiments, the plurality of memory cells may be arranged such that each of the plurality of memory cells can be aligned with a corresponding memory cell in a plurality of memory cells in row 200R. For example, memory cells 725, 726 may correspond to memory cells 225, 226, etc.

[0073] In some embodiments, the plurality of memory cells (e.g., memory cells 725, 726) can include or be coupled with access transistors (e.g., access transistors 725T, 726T). The access transistors 725T, 726T can connect the memory cells 725, 726 with respective bit lines BL / BLB. In some embodiments, the memory cells 725 can include a plurality of first memory cells, and the memory cells 726 can include a plurality of second memory cells. In some embodiments, each of the plurality of memory cells (e.g., memory cells 725, memory cells 726, etc.) can include a static random access memory (SRAM) cell.

[0074] The first word line 710 and the second word line 720 can be a memory array 120. In some embodiments, the first word line 710 can be a word line associated with a first metallization layer at a front side. In some embodiments, the second word line 720 can be a word line associated with a second metallization layer at the front side. For example, the first word line 710 can be associated with one or more metallization layers formed at a top of the front side. The second word line 720 can be associated with one or more metallization layers formed at a bottom of the front side. In some embodiments, the row 700R can include interconnect structures 731, 732, 733, 734, etc. The interconnect structures 731, 732, 733, 734 can be coupled to gate terminals of the memory cells 725, 726. For example, the interconnect structures 731, 732 and the interconnect structures 733, 734 can be coupled to respective gate terminals of the access transistors 725T and 726T, respectively.

[0075] In some embodiments, the word line 710 can be connected to a metallization layer (e.g., M5 track) of a first row (e.g., Row[0] or even row) at the front side, while the word line 720 can be connected to one or more metallization layers (e.g., M1 and M3 tracks) at the first row at the front side. In some embodiments, the word line 210 of the row 200R can be connected to one or more metallization layers (e.g., M1 and M3 tracks) of a second row (e.g., Row[1] or odd row) at the front side, while the word line 220 of the row 200R can be connected to a metallization layer (e.g., M5 track) at the second row at the back side.

[0076] Figure 8 An example layout 800 associated with an example circuit is shown in accordance with some embodiments. More specifically, Figure 8 A top view of the layout 800 is shown in FIG. 8B. In some embodiments, the layout 800 can be associated with the circuit 700. Figure 8The layout 800 shown is a non-limiting example and has been simplified for illustrative purposes. It should be understood that layout 800 can be implemented in any of a variety of other configurations while still remaining within the scope of this disclosure.

[0077] In some embodiments, layout 800 may be substantially similar to or include features of layout 500. In some embodiments, unlike layout 500 which may include multiple rows 500R, layout 800 may optionally include row 801. In some embodiments, layout 800 may include multiple rows, which may be any arrangement of rows 801 and rows 500R. For example, rows 801 and rows 500R may be arranged alternately.

[0078] In a first region of the substrate, the circuitry associated with layout 800 (e.g., circuitry 700) may include multiple memory cells (e.g., first memory cell 825, second memory cell 826, etc.). The circuitry may include multiple via structures in a second region of the substrate. The second region may be along a lateral direction (e.g., as shown in the image). Figure 8 The x-axis shown is located next to the first region.

[0079] In some embodiments, the circuit may include a plurality of memory cells arranged along rows of a memory array formed in a first region and spanning multiple columns. In some embodiments, a plurality of memory cells may be formed such that rows 500R and 801 pass through the plurality of memory cells.

[0080] In some embodiments, the circuit may include via structures (e.g., V1 805, V2 804, V3 803, V4 802, etc.) and interconnect structures (e.g., M5 810, M4 820, M3 830, M2 840, etc.) formed in various portions of the second region. For example, as Figure 8 As shown, the circuit may include a first set of via structures (e.g., V1805A, V2 804A, V3 803A, V4 802A, etc.) and a first set of interconnect structures (e.g., M5 810A, M4 820A, M3 830A, M2 840A, etc.) in a first portion of the second region; and a second set of via structures (e.g., V1 805B, V2 804B, V3 803B, V4 802B, etc.) and a second set of interconnect structures (e.g., M5 810B, M4 820B, M3 830B, M2 840B, etc.) in a second portion of the second region. In some embodiments, such as Figure 8 As shown, the via structure assembly and interconnect structure assembly can be arranged along the x-axis (and / or y-axis (not shown)). In some embodiments, such as Figure 8As shown, the via structure set (e.g., V1 805A, V2 804A, V3 803A, V4 802A, etc.) can be shifted along the x and y axes from another via structure set (e.g., via structures 504A, 505A, 560A, etc.). In some embodiments, such as Figure 8 As shown, interconnect sets (e.g., M5 810A, M4 820A, M3830A, M2 840A, etc.) can be shifted along the x and y axes from other interconnect sets (e.g., BMO 506C, M0 503C, etc.). In some embodiments, the circuitry may include multiple rows arranged along the y-axis (e.g., row 801, row 500R, etc.). Figure 8 As shown, row 801 can be shifted from row 500R on both the x and y axes.

[0081] In some embodiments, the M2 track 840 may extend along the y-axis (e.g., as shown in the figure). Figure 8 (As shown in M2 tracks 840A and 840B). In some embodiments, M2 track 840 may pass through M1 track 530, M3 track 830, etc. In some embodiments, M3 track 830 may extend along the x-axis (e.g., as shown in the diagram). Figure 9 (As shown in M3 tracks 830A and 830B). In some embodiments, M3 track 830 may pass through M2 track 840, M4 track 820, etc. In some embodiments, M4 track 820 may extend along the y-axis (e.g., as shown in the diagram). Figure 3A (As shown in M4 tracks 820A and 820B). In some embodiments, M4 track 820 may pass through M1 track 530, M3 track 830, etc. In some embodiments, M5 track 810 may extend along the x-axis (e.g., as shown in the diagram). Figure 3B (As shown in M5 tracks 810A and 810B). In some embodiments, M5 track 810 may pass through M4 track 820, M2 track 840, memory cells 825 and 826, etc.

[0082] In some embodiments, the through-hole structure (e.g., V1 805A, V2 804A, V3 803A, V4 802A, etc.) may extend along the z-axis to connect at least one of M5 810, M4 820, M3 830, M2 840, etc. to another.

[0083] Figure 5A A flowchart of an example method 900 for forming a memory device is shown. In some embodiments, method 900 may be performed based on information about... Figure 5B , Figure 8 , Figure 9 , Figure 10 and Figure 3AThe layout discussed above to form a memory device, so some of the reference signs used above can be reused in the discussion of the method 900 below. It should be noted that the method 900 is merely an example and is not intended to limit the disclosure. Therefore, it should be understood that additional operations can be provided before, during, and after the method 900, and some of the described operations can be modified or eliminated, in accordance with the principles of the present disclosure. Figure 3B

[0084] Briefly, the method 900 can start with operation 910, forming a plurality of memory cells in a first region of a substrate and on a first side of the substrate. The method 900 can continue to operation 920, forming a first interconnect structure on the first side of the substrate and over the plurality of memory cells. The method 900 can continue to operation 930, flipping the substrate. The method 900 can continue to operation 940, forming a via structure in a second region of the substrate and on the second region. The method 900 can continue to operation 950, forming a second interconnect structure on a second side of the substrate.

[0085] In operation 910, a plurality of memory cells (e.g., memory cells 225, 226) can be formed in a first region of a substrate and on a first side (e.g., a front side). In some embodiments, the plurality of memory cells can be formed such that the plurality of memory cells are arranged along rows of a memory array and across a plurality of columns. In some embodiments, the plurality of memory cells can include first memory cells and second memory cells arranged along a lateral direction. In some embodiments, the plurality of memory cells can include static random access memory (SRAM) cells.

[0086] In operation 920, a first interconnect structure (e.g., Ml tracks 330) can be formed on the first side of the substrate and over the plurality of memory cells. In some embodiments, the first interconnect structure can be coupled to corresponding gate terminals of the plurality of memory cells. For example, the first interconnect structure can be coupled to corresponding gate terminals of access transistors (e.g., access transistors 225T) of the plurality of memory cells. In operation 930, the substrate can be flipped.

[0087] ​In operation 940, a via structure (e.g., via structure 350) can be formed in a second region of the substrate and on a second side (e.g., a backside) of the substrate. In some embodiments, the second region can be alongside the first region along the lateral direction. In operation 950, a second interconnect structure (e.g., BM1 track 340) can be formed on the second side of the substrate. In some embodiments, the second interconnect structure can be coupled to the first interconnect structure through the via structure. In some embodiments, the first and second interconnect structures can each extend along the lateral direction to pass through both the first and second regions. In some embodiments, the via structure can extend through the substrate to connect the first side to the second side of the substrate. In some embodiments, the via structure can be formed on the second side of the substrate.

[0088] Figure 5A A flowchart showing an example method 1000 for forming a memory device is shown. In some embodiments, the method 1000 can be performed to form a memory device based on the layouts discussed with respect to Figure 5B 、 Figure 8 、 Figure 10 、 ​ and ​ , so some reference signs used above can be reused in the following discussion of the method 1000. It should be noted that the method 1000 is merely an example and is not intended to limit the disclosure. Therefore, it should be understood that additional operations can be provided before, during, and after the method 1000, and some other operations described herein can be omitted. ​

[0089] Briefly, the method 1000 can start with operation 1010, forming a plurality of memory cells in a first region of a substrate and on a first side. The method 1000 can continue to operation 1020, forming a first interconnect structure on the first side of the substrate and over the plurality of memory cells. The method 1000 can continue to operation 1030, flipping the substrate. The method 1000 can continue to operation 1040, forming a via structure in a second region of the substrate and on a second side of the substrate. The method 1000 can continue to operation 1050, forming a second interconnect structure on the second side of the substrate.

[0090] In operation 1010, a plurality of memory cells (e.g., memory cells 425, 426) can be formed in a first region of a substrate and on a first side (e.g., a front side). In some embodiments, the plurality of memory cells can be formed such that the plurality of memory cells are arranged along rows of a memory array and across a plurality of columns. In some embodiments, the plurality of memory cells can include a first memory cell and a second memory cell arranged along a lateral direction. In some embodiments, the plurality of memory cells can include static random access memory (SRAM) cells.​

[0091] In operation 1020, a first interconnect structure (e.g., Ml track 530) can be formed on a first side of the substrate and over the plurality of memory cells. In some embodiments, the first interconnect structure can be coupled to corresponding gate terminals of the plurality of memory cells. For example, the first interconnect structure can be coupled to corresponding gate terminals of access transistors (e.g., access transistors 425T) of the plurality of memory cells. In operation 1030, the substrate can be flipped.

[0092] In operation 1040, a via structure (e.g., via structure 560) and a transistor (e.g., transistor 450) coupled to the via structure can be formed in a second region of the substrate and on a second side (e.g., backside). In some embodiments, a gate terminal and a first source / drain terminal of the transistor can be coupled to the first interconnect structure, a second source / drain terminal of the transistor can be coupled to a second interconnect structure through the via structure. In some embodiments, the transistor can be formed in a dissipative element (e.g., dissipative element 550). For example, the dissipative element can be a dummy element in which the transistor is formed. In some embodiments, the second region can be located alongside the first region along the lateral direction. In operation 1050, a second interconnect structure (e.g., BMl track 540) can be formed on the second side of the substrate. In some embodiments, the second interconnect structure can be coupled to the first interconnect structure through the via structure. In some embodiments, the first interconnect structure and the second interconnect structure can each extend along the lateral direction to pass through both the first and second regions. In some embodiments, the via structure can extend through the substrate to connect the first side to the second side of the substrate. In some embodiments, the via structure can be formed on the second side of the substrate.

[0093] In one aspect of the disclosure, a memory device is disclosed. The memory device includes: a plurality of first memory cells formed in a first region of a substrate; a plurality of first via structures formed in a second region of the substrate, the second region disposed alongside the first region along a first lateral direction; a first front-side interconnect structure of a plurality of front-side interconnect structures formed on a first side of the substrate, wherein the first front-side interconnect structure is coupled to gate terminals of access transistors of the plurality of first memory cells; and a first back-side interconnect structure of a plurality of back-side interconnect structures formed on a second side of the substrate that is perpendicular opposite to the first side, wherein the first back-side interconnect structure is coupled to the first front-side interconnect structure through one or more first via structures of the plurality of first via structures.

[0094] In some embodiments, the first front-side interconnect structure and the first back-side interconnect structure each extend along the first lateral direction.

[0095] In some embodiments, the memory device further includes: a plurality of second memory cells formed in the first region of the substrate; a plurality of second via structures formed in the second region of the substrate; a second front-side interconnect structure of the plurality of front-side interconnect structures coupled to a gate terminal of an access transistor of the plurality of second memory cells; and a second back-side interconnect structure of the plurality of back-side interconnect structures coupled to the second front-side interconnect structure through one or more second via structures of the plurality of second via structures; wherein the second front-side interconnect structure and the second back-side interconnect structure each extend along the first lateral direction.

[0096] In some embodiments, each of the plurality of first memory cells and the plurality of second memory cells comprises a static random access memory (SRAM) cell.

[0097] In some embodiments, the second memory cells are aligned with the first memory cells along a second lateral direction that is perpendicular to the first lateral direction, and the one or more first via structures are displaced from the one or more second via structures in both the first lateral direction and the second lateral direction.

[0098] In some embodiments, the one or more first via structures each extend through the substrate.

[0099] In some embodiments, the memory device further includes: a second front-side interconnect structure of the plurality of front-side interconnect structures, wherein the second front-side interconnect structure is disposed vertically between the substrate and the first front-side interconnect structure; and a second back-side interconnect structure of the plurality of back-side interconnect structures, wherein the second back-side interconnect structure is disposed vertically between the substrate and the first back-side interconnect structure.

[0100] In some embodiments, the one or more first via structures each directly contact the second front-side interconnect structure and the second back-side interconnect structure.

[0101] In some embodiments, the first interconnect structure, the second front-side interconnect structure, and the first back-side interconnect structure each extend in the first lateral direction, and the second back-side interconnect structure extends in a second lateral direction that is perpendicular to the first lateral direction.

[0102] In some embodiments, the first front-side interconnect structure and the first back-side interconnect structure are operable as portions of a word line for the first memory cells.

[0103] In some embodiments, the first memory cells are configured to be arranged along rows of the memory array and across a plurality of columns, and wherein the memory array is formed in the first region.

[0104] In another aspect of the disclosure, a memory device is disclosed. The memory device includes: a memory array including a plurality of memory cells, wherein the plurality of memory cells are formed in a first region of a substrate; a first interconnect structure formed on a first side of the substrate, wherein the first interconnect structure is operable as a first portion of word lines of the plurality of memory cells; a second interconnect structure formed on a second side of the substrate opposite the first side, wherein the second interconnect structure is operable as a second portion of the word lines of the plurality of memory cells; and one or more via structures formed in a second region of the substrate alongside the first region along a lateral direction, wherein the one or more via structures are configured to couple the first interconnect structure to the second interconnect structure; wherein the first interconnect structure and the second interconnect structure each extend along the lateral direction to pass through both the first region and the second region.

[0105] In some embodiments, the one or more via structures each extend through the substrate to connect the first side to the second side of the substrate.

[0106] In some embodiments, the one or more via structures are each formed on the second side of the substrate.

[0107] In some embodiments, the memory device further includes: at least one transistor formed in the second region of the substrate; wherein a gate terminal and a first source / drain terminal of the at least one transistor are coupled to the first interconnect structure, and a second source / drain terminal of the at least one transistor is coupled to the second interconnect structure through the one or more via structures.

[0108] In some embodiments, each of the plurality of memory cells includes a static random access memory (SRAM) cell.

[0109] In some embodiments, the first interconnect structure and the second interconnect structure are each coupled to corresponding gate terminals of the plurality of memory cells.

[0110] In another aspect of the disclosure, a method for forming a memory device is disclosed. The method includes: forming a plurality of memory cells on a first region and a first side of a substrate; forming a first interconnect structure on the first side of the substrate and over the plurality of memory cells, wherein the first interconnect structure is coupled to corresponding gate terminals of the plurality of memory cells; flipping the substrate; forming a via structure in a second region of the substrate and on a second side, wherein the second region is positioned alongside the first region along a lateral direction; and forming a second interconnect structure on the second side of the substrate, wherein the second interconnect structure is coupled to the first interconnect structure through the via structure; wherein the first interconnect structure and the second interconnect structure each extend along the lateral direction to pass through both the first region and the second region.

[0111] In some embodiments, the via structure extends through the substrate to connect the first side to the second side of the substrate.

[0112] In some embodiments, the via structure is formed on the second side of the substrate.

[0113] As used herein, the terms "about" and "approximately" generally mean values that can vary depending on the particular technical node associated with the subject semiconductor device. Based on the particular technical node, the term "about" can mean a value of a given quantity that varies, for example, within a range of 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0114] The foregoing summarizes features of several embodiments in order that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily apply the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will recognize that such equivalent constructions do not depart from the spirit and scope of the present application, and that they can make various changes, substitutions and alterations within the scope of the application without departing from the spirit and scope of the present application.

Claims

1. A memory device, comprising: Multiple first memory cells are formed in a first region of the substrate; Multiple first through-hole structures are formed in a second region of the substrate, the second region being disposed adjacent to the first region along a first lateral direction; A first front-side interconnect structure, one of a plurality of front-side interconnect structures, is formed on a first side of the substrate, wherein the first front-side interconnect structure is coupled to the gate terminal of the access transistor of the plurality of first memory cells; and A first back-side interconnect structure of a plurality of back-side interconnect structures is formed on a second side of the substrate perpendicular to the first side, wherein the first back-side interconnect structure is coupled to the first front-side interconnect structure through one or more of the plurality of first via structures.

2. The memory device according to claim 1, further comprising: Multiple second memory cells are formed in the first region of the substrate; Multiple second via structures are formed in the second region of the substrate; The second front interconnect structure in the plurality of front interconnect structures is coupled to the gate terminal of the access transistor of the plurality of second memory cells. as well as The second back-side interconnect structure in the plurality of back-side interconnect structures is coupled to the second front-side interconnect structure through one or more of the plurality of second through-hole structures. Both the second front interconnect structure and the second back interconnect structure extend along the first lateral direction.

3. The memory device according to claim 2, wherein, Each of the plurality of first memory units and the plurality of second memory units includes a static random access memory unit.

4. The memory device according to claim 2, wherein, The second memory cell is aligned with the first memory cell along a second lateral direction perpendicular to the first lateral direction, while the one or more first through-hole structures are displaced from the one or more second through-hole structures in both the first lateral direction and the second lateral direction.

5. The memory device according to claim 1, wherein, The one or more first via structures extend through the substrate.

6. The memory device according to claim 5, further comprising: The second front-side interconnect structure among the plurality of front-side interconnect structures, wherein the second front-side interconnect structure is vertically disposed between the substrate and the first front-side interconnect structure; and The second back-side interconnect structure is one of the plurality of back-side interconnect structures, wherein the second back-side interconnect structure is vertically disposed between the substrate and the first back-side interconnect structure.

7. A memory device, comprising: A memory array comprising a plurality of memory cells, wherein the plurality of memory cells are formed in a first region of a substrate; A first interconnect structure is formed on a first side of the substrate, wherein the first interconnect structure is operatively used as a first portion of a word line of the plurality of memory cells; A second interconnect structure is formed on a second side of the substrate opposite to the first side, wherein the second interconnect structure is operatively configured as a second portion of the word lines of the plurality of memory cells; and One or more via structures are formed in a second region of the substrate, the second region being located adjacent to the first region in a lateral direction, wherein the one or more via structures are configured to couple the first interconnect structure to the second interconnect structure; Both the first interconnect structure and the second interconnect structure extend along the lateral direction to pass through both the first region and the second region.

8. The memory device according to claim 7, wherein, The one or more through-hole structures are formed on the second side of the substrate.

9. The memory device according to claim 8, further comprising: At least one transistor is formed in the second region of the substrate; The gate terminal and the first source / drain terminal of the at least one transistor are coupled to the first interconnect structure, and the second source / drain terminal of the at least one transistor is coupled to the second interconnect structure through the one or more via structures.

10. A method of forming a memory device, comprising: Multiple memory cells are formed on a first region and a first side of the substrate; A first interconnect structure is formed on the first side of the substrate and above the plurality of memory cells, wherein the first interconnect structure is coupled to the corresponding gate terminals of the plurality of memory cells; Flip the substrate; A through-hole structure is formed in a second region and on a second side of the substrate, wherein the second region is positioned laterally adjacent to the first region; and A second interconnect structure is formed on the second side of the substrate, wherein the second interconnect structure is coupled to the first interconnect structure through the through-hole structure; Both the first interconnect structure and the second interconnect structure extend along the lateral direction to pass through both the first region and the second region.

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