Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes: a substrate layer; a first transistor and a second transistor over the substrate layer; a first memory cell over the substrate layer; a first word line over the substrate layer and electrically connected to the first memory cell, where the first word line is at a first height, and a first transistor electrically connected to the first word line; a second memory cell over the substrate layer; and a second word line over the substrate layer and electrically connected to the second memory cell, where the second word line is at a second height higher than the first height, and the second transistor is electrically connected to the second word line. Based on this configuration, the stability and efficiency of the semiconductor device may be improved.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a memory cell. DRAM is known for its high speed, high density, and scalability. However, as DRAM production scales up, DRAM manufacturing becomes more challenging and more prone to defects. For example, certain designs may limit the pace of chip size reduction. Therefore, there is a need for an efficient semiconductor device and its manufacturing method. Summary of the Invention

[0003] Embodiments of the present invention provide a semiconductor device, comprising: a substrate layer; a first transistor and a second transistor located above the substrate layer; a first memory cell located above the substrate layer; a first word line located above the substrate layer and electrically connected to the first memory cell, wherein the first word line is located at a first height and the first transistor is electrically connected to the first word line; a second memory cell located above the substrate layer; and a second word line located above the substrate layer and electrically connected to the second memory cell, wherein the second word line is located at a second height higher than the first height and the second transistor is electrically connected to the second word line.

[0004] In some embodiments, the height of the second memory cell is greater than the height of the first memory cell.

[0005] In some embodiments, the first memory cell includes a first access transistor and a first capacitor, with the first access transistor located above the first capacitor.

[0006] In some embodiments, the second memory cell includes a second access transistor and a second capacitor, the second capacitor being located above the second access transistor.

[0007] In some embodiments, a bottom dielectric layer is further included between the substrate layer and the first capacitor of the first memory cell.

[0008] In some embodiments, the device further includes: a first conductive via located above the substrate layer and electrically connected to the first transistor and the first character line; and a second conductive via located above the substrate layer and electrically connected to the second transistor and the second character line.

[0009] In some embodiments, the top surface of the first conductive via is lower than the top surface of the second conductive via.

[0010] In some embodiments, the bottom surface of the first conductive via and the bottom surface of the second conductive via are located on the top surface of the substrate layer.

[0011] In some embodiments, a bit line located between and electrically connected to the first memory cell and the second memory cell is also included.

[0012] In some embodiments, the bit line is located at a third height between the first height and the second height.

[0013] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a substrate layer; forming a first transistor and a second transistor above the substrate layer; forming a first word line and a first memory cell electrically connected to each other above the substrate layer, wherein the first word line is located at a first height and the first transistor is electrically connected to the first word line; and forming a second word line and a second memory cell electrically connected to each other above the substrate layer, wherein the second word line is located at a second height above the first height and the second transistor is electrically connected to the second word line.

[0014] In some embodiments, the second memory cell is formed at a higher height than the first memory cell.

[0015] In some embodiments, the first memory cell includes a first capacitor and a first access transistor located above the first capacitor.

[0016] In some embodiments, the second memory cell includes a second capacitor and a second access transistor located below the second capacitor.

[0017] In some embodiments, the method further includes forming a bottom dielectric layer over a substrate layer before forming the first memory cell, wherein the first memory cell is formed on the bottom dielectric layer.

[0018] In some embodiments, the method further includes: forming a first conductive via above a substrate layer and electrically connecting it to a first transistor, wherein a first word line is electrically connected to the first conductive via.

[0019] In some embodiments, the method further includes: forming a second conductive via above the substrate layer and electrically connecting it to the second transistor, wherein the second word line is electrically connected to the second conductive via.

[0020] In some embodiments, the method further includes: forming a bit line electrically connected to the first memory cell, wherein the second memory cell is formed on the bit line and electrically connected thereto.

[0021] In some embodiments, the method further includes: forming a first contact above the first memory cell and electrically connecting it to the first memory cell before forming the bit line, wherein the bit line is formed above the first contact; and forming a second contact to the bit line and electrically connecting it to the bit line after forming the bit line.

[0022] In some embodiments, the bit line is formed at a third height between the first height and the second height. Attached Figure Description

[0023] The best understanding of this disclosure is achieved by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0024] Figure 1 This is a schematic diagram of a memory array according to some embodiments of the present invention.

[0025] Figure 2 This is a schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0026] Figure 3A and Figure 3B This is a flowchart illustrating a method for manufacturing a semiconductor device according to a partial embodiment of the present invention.

[0027] Figures 4A to 28C This is a method for manufacturing a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0028] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, some of which illustrate exemplary embodiments. However, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0029] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0030] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms are used to describe the relationship of one element or feature to another, as illustrated in the figure. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation beyond those shown in the figure. For example, if the device in the figure is flipped, an element described as “below” or “below” other elements or features would be positioned “above” other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0031] As used herein, “approximately,” “about,” “roughly,” or “substantially” can generally mean within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that the terms “approximately,” “about,” “roughly,” or “substantially” can be inferred unless explicitly stated otherwise. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and can decrease or vary as integrated circuits shrink in size.

[0032] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including” as used in this specification designate the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence of said features, integrals, steps, operations, elements, and / or components.

[0033] This document describes exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized exemplary embodiments (and intermediate structures). Therefore, variations in the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Thus, the exemplary embodiments should not be construed as limited to the specific shapes of the regions shown herein, but rather include, for example, shape deviations due to manufacturing processes. For example, an injection region illustrated as rectangular will typically have circular or curved features and / or an injection concentration gradient at its edges, rather than a binary variation from the injection region to the non-injection region. Similarly, a buried region formed by injection can result in some injection in the region between the buried region and the surface through which injection is carried out. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0034] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms, such as those defined in common dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0035] The exemplary embodiments will now be explained in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic diagram of a memory array according to a partial embodiment of the present invention. A semiconductor device 10 is shown in the figure. The semiconductor device 10 includes a plurality of memory cells 11 arranged in a rectangular matrix. Figure 1 This illustrates a simple example of a 4x4 cell matrix. Other storage matrices may have a height and width of thousands of cells. In some embodiments, the semiconductor device 10 may be a dynamic random access memory (dynamic RAM or DRAM).

[0037] Each row of memory cells 11 is connected by word lines 20, and each column of memory cells 11 is connected by bit lines 30. Multiple word lines 20 can extend horizontally. The word lines 20 are parallel to each other. Furthermore, the word lines 20 can be separated from each other at substantially equal intervals. On the other side, multiple bit lines 30 can extend vertically. Similar to the word lines 20, the bit lines 30 are parallel to each other and can be separated from each other at substantially equal intervals.

[0038] Figure 2 This is a schematic diagram of a memory cell according to some embodiments of the present invention. Specifically, Figure 2 yes Figure 1 A close-up. In some embodiments, memory cell 11 includes access transistor 11T and storage capacitor 11C electrically connected to access transistor 11T.

[0039] In some embodiments, the access transistor 11T is an NMOS transistor and is configured to control the channel to the memory cell 11 by turning the gate of the access transistor 11T on or off. In some embodiments, the storage capacitor 11C is configured to store information according to the state of the charge stored therein. The storage capacitor 11C in an empty state (i.e., no charge) is represented by a logic value of 0. The storage capacitor 11C in a fully charged state is represented by a logic value of 1. The memory cell 11 uses the two extreme charge states stored in the storage capacitor 11C to store one bit of data.

[0040] In some embodiments, word line 20 connected to access transistor 11T is used to control the gate of access transistor 11T by applying a voltage to the gate of access transistor 11T. In some embodiments, bit line 30 is arranged perpendicular to word line 20 and is also connected to access transistor 11T. When the gate of access transistor 11T is turned on, access transistor 11T connects storage capacitor 11C to bit line 30, such that the logic value stored in storage capacitor 11C is read onto bit line 30.

[0041] Figure 3A and Figure 3B This is a flowchart illustrating a method for manufacturing a semiconductor device according to a partial embodiment of the present invention. Figures 4A to 28C This is a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0042] Specifically, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A They are Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B A top view of the cross-section along line B-B'. Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A They are Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B A top view of the cross-section along line A-A'. Figure 14C yes Figure 14B A top view of the cross-section along line B-B'. Figure 17C yes Figure 17B A top view of the cross-section along line B-B'. Figure 18A yes Figure 18B A top view of the cross-section along line B-B'. Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A They are Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B A top view of the cross-section along line A-A'. Figure 24C yes Figure 24B A top view of the cross-section along line B-B'. Figure 28C yes Figure 28B A top view of the cross-section along line B-B'.

[0043] Combining Figures 4A to 28C Discuss semiconductor devices and their manufacturing methods (M50). For example... Figure 3A and Figure 3B As shown, manufacturing method M50 may include the following operations: operation S100, operation S200, operation S300, operation S400, operation S500, operation S600, operation S700, operation S800, operation S900, operation S1000, operation S1100, operation S1200, operation S1300, operation S1400, operation S1500, operation S1600, operation S1700, operation S1800, operation S1900, operation S2000, operation S2100, operation S2200, operation S2300, operation S2400 and operation S2500.

[0044] This document provides various operations of the embodiments. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. The benefits of alternative ordering can be understood through this description. Furthermore, it should be understood that not all operations must exist in every embodiment provided herein. Moreover, it should be understood that not all operations are necessary in some embodiments.

[0045] Method M50 begins with operation S100, forming transistors on the substrate layer. (Reference) Figure 4A and Figure 4B Transistors TR1 and TR2 are formed on substrate layer 100.

[0046] In some embodiments, the substrate layer 100 is made of silicon (Si). In some embodiments, the substrate layer 100 is configured as a substrate structure supporting N-type metal-oxide-semiconductor (NMOS) devices and / or P-type metal-oxide-semiconductor (PMOS) devices formed in subsequent processes.

[0047] A first gate structure 200A and a second gate structure 200B are formed above the substrate layer 100. In some embodiments, the first gate structure 200A and the second gate structure 200B may each include a gate dielectric layer 201, a first conductive layer 202, a second conductive layer 203, a third conductive layer 204, and a dielectric capping layer 205.

[0048] Appropriate deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flow chemical vapor deposition (FCVD), or other suitable deposition processes, can be used to deposit a gate dielectric layer 201, a first conductive layer 202, a second conductive layer 203, a third conductive layer 204, and a dielectric capping layer 205 on the substrate layer 100. Subsequently, the gate dielectric layer 201, the first conductive layer 202, the second conductive layer 203, the third conductive layer 204, and the dielectric capping layer 205 can be patterned according to a predetermined pattern.

[0049] In some embodiments, the gate dielectric layer 201 may be made of a dielectric material. In some embodiments, the gate dielectric layer 201 may be made of an oxide. In some embodiments, the gate dielectric layer 201 may include silicon oxide (SiO2) or aluminum oxide (Al2O3).

[0050] In some embodiments, the first conductive layer 202, the second conductive layer 203, and the third conductive layer 204 may be made of conductive materials. In some embodiments, the first conductive layer 202 may be made of polycrystalline silicon. In some embodiments, the second conductive layer 203 may be made of titanium nitride (TiN). In some embodiments, the third conductive layer 204 may be made of tungsten (W).

[0051] In some embodiments, the first conductive layer 202, the second conductive layer 203, and the third conductive layer 204 can be used as gate electrodes for corresponding transistors TR1 and TR2.

[0052] In some embodiments, the width W1 of the gate dielectric layer 201, the width W2 of the first conductive layer 202, the width W3 of the second conductive layer 203, and the width W4 of the third conductive layer 204 can satisfy the following condition: width W1 > width W2 > width W3 > width W4.

[0053] Next, a dielectric capping layer 205 can be deposited over the third conductive layer 204 and along the sidewalls of the gate dielectric layer 201, the first conductive layer 202, the second conductive layer 203 and the third conductive layer 204.

[0054] In some embodiments, the dielectric capping layer 205 may be made of a dielectric material. In some embodiments, the dielectric capping layer 205 may be made of silicon nitride (SiN). In some embodiments, the dielectric capping layer 205 may be formed in a generally trapezoidal cross-sectional profile.

[0055] The dielectric capping layer 205 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the dielectric capping layer 205 is configured such that the gate structures 200A and 200B are laterally canceled out by their corresponding source / drain regions.

[0056] Next, source / drain regions 300A and 300B are formed in the substrate layer 100, adjacent to the gate structures 200A and 200B, respectively. Specifically, the first source / drain region 300A is formed in the substrate layer 100 and is located on both sides of the first gate structure 200A. On the other hand, the second source / drain region 300B is formed in the substrate layer 100 and is located on both sides of the second gate structure 200B.

[0057] In some embodiments, source / drain regions 300A and 300B are formed via one or more ion implantation processes. In some embodiments, source / drain regions 300A and 300B are implanted with substances that alter the conductivity type of the thin film.

[0058] In some embodiments, the first source / drain region 300A may be implanted with an N-type dopant. In some embodiments, the first source / drain region 300A may be implanted with phosphorus (P) and / or arsenic (As).

[0059] In some embodiments, the second source / drain region 300B may be implanted with a P-type dopant. In some embodiments, the second source / drain region 300B may be implanted with boron (B), gallium (Ga), and / or indium (In).

[0060] After the source / drain regions 300A and 300B are formed, the first transistor TR1 and the second transistor TR2 are formed.

[0061] Regarding the first transistor TR1, the first transistor TR1 includes a substrate layer 100, a first gate structure 200A above the substrate layer 100, and a source / drain region 300A located on the opposite side of the first gate structure 200A.

[0062] Regarding the second transistor TR2, the second transistor TR2 includes a substrate layer 100, a second gate structure 200B above the substrate layer 100, and a source / drain region 300B located on the opposite side of the second gate structure 200B.

[0063] Method M50 continues to operation S200, forming a bottom dielectric layer on the substrate layer. (Reference) Figure 5A and Figure 5B A bottom dielectric layer 400 is deposited on the substrate layer 100.

[0064] Specifically, the bottom dielectric layer 400 is deposited on the substrate layer 100 through a mask pattern (not shown), and may not cover the first transistor TR1, the second transistor TR2, or their respective source / drain regions 300A and 300B. The bottom dielectric layer 400 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0065] The bottom dielectric layer 400 is made of a dielectric material. In some embodiments, the bottom dielectric layer 400 is made of a nitride, such as silicon nitride (SiN).

[0066] In some embodiments, the bottom dielectric layer 400 is configured on the substrate layer 100 and the conductive structure to be formed in subsequent steps (e.g., Figure 7A Electrical isolation is provided between capacitors 1200 in the middle.

[0067] Method M50 continues to operation S300, where a first dielectric layer is formed on the substrate layer. (Reference) Figure 6A and Figure 6B A first dielectric layer 1100 is deposited on the substrate layer 100.

[0068] Specifically, a first dielectric layer 1100 is deposited on a substrate layer 100 and may cover a first transistor TR1, a second transistor TR2, their respective source / drain regions 300A and 300B, and a bottom dielectric layer 400. The first dielectric layer 1100 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0069] In some embodiments, the first dielectric layer 1100 is used for conductive structures formed in subsequent steps (e.g., Figure 7A Electrical isolation is provided between capacitors 1200 in the capacitor. The first dielectric layer 1100 is made of a dielectric material. In some embodiments, the first dielectric layer 1100 is made of an oxide, such as silicon dioxide (SiO2).

[0070] Method M50 continues to operation S400, where the first dielectric layer is patterned to form a capacitor. (See reference) Figure 7A and Figure 7B The first dielectric layer 1100 is patterned to form an opening, and a capacitor 1200 is formed in the opening.

[0071] First, a mask pattern (not shown) is formed on the first dielectric layer 1100. Then, the first dielectric layer 1100 is etched through this mask pattern to form an opening (not shown). In some embodiments, this opening exposes the bottom dielectric layer 400.

[0072] Then, capacitors 1200 are formed in the openings. In other words, each opening corresponds to one capacitor 1200. The capacitors 1200 can be planarized to make them flush with the first dielectric layer 1100. Therefore, the planarized capacitors 1200 and the first dielectric layer 1100 are coplanar and thus share the same top surface. That is, the top surface of the planarized capacitors 1200 and the top surface of the first dielectric layer 1100 can be connected to each other. The planarization process can employ a chemical mechanical polishing (CMP) process. The CMP process can be stopped when the first dielectric layer 1100 is exposed.

[0073] In some embodiments, the capacitors 1200 are parallel to each other and can be arranged regularly at substantially equal intervals.

[0074] The capacitor 1200 may include a bottom electrode, a capacitor dielectric layer above the bottom electrode, and a top electrode above the capacitor dielectric layer. In some embodiments, the bottom electrode and the top electrode of the capacitor 1200 may include a conductive material.

[0075] In some embodiments, the bottom electrode and the top electrode may comprise metal. In some embodiments, the bottom electrode and the top electrode may comprise titanium nitride (TiN). In some embodiments, the capacitor dielectric layer of capacitor 1200 may comprise a dielectric material. The bottom electrode, capacitor dielectric layer, and top electrode of capacitor 1200 may be deposited sequentially using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0076] Method M50 continues to operation S500, where a first conductive via is formed in the first dielectric layer, wherein the first conductive via is electrically connected to the first transistor. (Reference) Figure 8A and Figure 8B A first conductive via 500A is formed in the first dielectric layer 1100, and the first conductive via is electrically connected to the first transistor TR1.

[0077] Specifically, a first conductive via 500A is formed between the first transistor TR1 and the bottom dielectric layer 400, and can be electrically connected to the first source / drain region 300A of the first transistor TR1.

[0078] In some embodiments, the method for forming the first conductive via 500A is as follows: patterning the first dielectric layer 1100 to form an opening (not shown) in the first dielectric layer 1100 to expose the first source / drain region 300A; depositing conductive material in the opening; and then performing a planarization process (e.g., CMP) to remove excess conductive material until the first dielectric layer 1100 is exposed. The deposition method for the first conductive via 500A can employ CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0079] The first conductive via 500A may be made of a conductive material. In some embodiments, the width of the first conductive via 500A may be smaller than the width of the capacitor 1200.

[0080] Method M50 continues to operation S600, where a second dielectric layer is deposited on the capacitor and the first dielectric layer. (See reference) Figure 8A and Figure 8B A second dielectric layer 1300 is deposited on capacitor 1200 and first dielectric layer 1100. To facilitate viewing the various components formed in this cross-section, the viewpoint of the following figures will move along A-A'. Figures 9A to 17A They are Figures 9B to 17B A top view of the cross-section along line A-A'.

[0081] A second dielectric layer 1300 may be deposited on the capacitor 1200 and the first dielectric layer 1100. In some embodiments, the second dielectric layer 1300 covers the capacitor 1200. The second dielectric layer 1300 is configured to provide electrical isolation between conductive structures (e.g., character line structures) formed in subsequent steps.

[0082] The second dielectric layer 1300 is made of a dielectric material. In some embodiments, the second dielectric layer 1300 and the first dielectric layer 1100 may be made of the same material. In some embodiments, the second dielectric layer 1300 is made of an oxide, such as silicon dioxide (SiO2). The second dielectric layer 1300 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the vertical thickness of the second dielectric layer 1300 may be slightly less than the vertical thickness of the first dielectric layer 1100.

[0083] Method M50 enters operation S700 to pattern the second dielectric layer to expose the capacitor. (Reference) Figure 10A and Figure 10B The second dielectric layer 1300 can be patterned to form openings 1400 that expose the capacitor 1200. A mask pattern (not shown) can be formed on the second dielectric layer 1300. Subsequently, the second dielectric layer 1300 is etched through this mask pattern.

[0084] In some embodiments, operation S700 may include a photolithography process. In some embodiments, the location of the opening 1400 may be defined by a mask pattern. For example, a mask pattern is formed on a vertical portion of a second dielectric layer 1300 on a first dielectric layer 1100, which does not cover the capacitor 1200. Therefore, the portion of the second dielectric layer 1300 on the first dielectric layer 1100 that does not cover the capacitor 1200 is not etched during the etching process and defines the opening 1400 after the etching process. In some embodiments, the width of the opening 1400 is greater than the width of the capacitor 1200. In some embodiments, each opening 1400 may extend along a first direction (e.g., the Y direction), and the openings 1400 are arranged along a second direction (e.g., the X direction) that is different from the first direction and substantially perpendicular to the first direction.

[0085] Method M50 continues to operation S800, forming word lines and gate dielectrics along the sidewalls of the opening. (Reference) Figure 11A and Figure 11B Word lines 1500 and gate dielectric 1600 are sequentially formed along the sidewall of opening 1400. In some embodiments, word line material (not shown) may be formed over an underlying structure (e.g., a first dielectric layer 1100, a capacitor 1200, and a second dielectric layer 1300). The word line material can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The word line material is then subjected to an anisotropic etching process to remove the horizontal portions of the word line material, leaving only the vertical portions. The remaining vertical portions are referred to as word lines 1500.

[0086] In some embodiments, the word line 1500 may extend upward from the first dielectric layer 1100 and along the sidewall of the opening 1400. In some embodiments, the word line 1500 is made of a conductive material. In some embodiments, the word line 1500 may include a metal. In some embodiments, the word line 1500 may include tungsten (W). In some embodiments, the word line 1500 may serve as a gate electrode to control... Figure 13A The channel structure 1700 is included. In some embodiments, the character line 1500 has a strip-shaped top profile.

[0087] Subsequently, a gate dielectric 1600 is formed on the sidewall of the opening 1400. Specifically, a gate dielectric 1600 is formed that extends upward from the first dielectric layer 1100 and along the sidewall of the opening 1400.

[0088] In some embodiments, a gate dielectric material blanket (not shown) may be formed over an underlying structure (e.g., a first dielectric layer 1100, a second dielectric layer 1300, a capacitor 1200, and a word line 1500). The gate dielectric material blanket may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0089] Then, an anisotropic etching process is performed on the gate dielectric material blanket to remove the horizontal portion of the gate dielectric material blanket, leaving only the vertical portion of the gate dielectric material along the sidewall of opening 1400. The remaining vertical portion is called gate dielectric 1600.

[0090] In some embodiments, the gate dielectric 1600 is made of a dielectric material. In some embodiments, the gate dielectric 1600 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. In some embodiments, the gate dielectric 1600 is configured to electrically isolate the word line 1500 from conductive structures (e.g., channel structures) formed in subsequent steps. In some embodiments, the width of the gate dielectric 1600 is substantially the same as the width of the word line 1500. In some embodiments, the gate dielectric 1600 has a striped top profile.

[0091] In some embodiments, the top of the gate dielectric 1600 may be substantially flush with the top surface of the second dielectric layer 1300 and the word line 1500. In some embodiments, the word line 1500 and the gate dielectric 1600 do not cover the top of the capacitor 1200. In other words, the capacitor 1200 remains exposed in the opening 1400.

[0092] Method M50 continues to operation S900, forming a channel structure material within the opening. (Reference) Figure 12A and Figure 12B A channel structure material 1700M is formed in the opening 1400. Specifically, the channel structure material 1700M is formed on the capacitor 1200 and surrounded by the gate dielectric 1600. In some embodiments, the channel structure material 1700M is formed on the first dielectric layer 1100 and surrounded by the gate dielectric 1600.

[0093] In some embodiments, a channel layer (not shown) may be formed to cover the opening 1400. The channel layer may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The channel layer may then be planarized (e.g., a CMP process) to remove excess channel layer portions on top of the second dielectric layer 1300 and flush the channel layer with the second dielectric layer 1300. In some embodiments, planarization may be stopped when the second dielectric layer 1300 is exposed. The remaining portion of the channel layer is referred to as the channel structure material 1700M.

[0094] Method M50 continues to operation S1000, where part of the channel structure material is removed to re-expose the opening. (See reference...) Figure 13A and Figure 13B Remove the portion of the channel structure material 1700M that does not cover the capacitor 1200 and re-expose the opening 1400.

[0095] First, a masking pattern (not shown) can be formed on the second dielectric layer 1300, the word line 1500, the gate dielectric 1600, and the channel structure material 1700M covering the capacitor 1200. Subsequently, the portion of the channel structure material 1700M not covered by the masking pattern is etched, and the opening 1400 is re-exposed.

[0096] The remaining portion of the channel structure material 1700M is referred to as channel structure 1700. In some embodiments, each channel structure 1700 extends vertically from a corresponding capacitor 1200. In some embodiments, the vertical length of the channel structure 1700 is substantially the same as that of the word line 1500 and / or the gate dielectric 1600. In some embodiments, the channel structure 1700 may be electrically connected to the capacitor 1200 below. In some embodiments, the channel structure 1700 has a square top profile.

[0097] In some embodiments, channel structure 1700 may include an oxide semiconductor (OS) material. In some embodiments, channel structure 1700 may include indium gallium zinc oxide (IGZO). Vertical channel structure 1700 may increase memory cell density in semiconductor device 10.

[0098] In some embodiments, the channel structure 1700 may be wrapped by the word line 1500 through the gate dielectric 1600. In other words, the word line 1500 (which can be used as a gate electrode), the gate dielectric 1600, and the channel structure 1700 may form a transistor (e.g., Figure 2 The access transistor 11T in the channel structure 1700 has a gate dielectric 1600 covering opposite sides of the channel structure 1700. This configuration provides a larger contact surface for the channel structure 1700, thereby increasing the current flowing through the gate dielectric 1600 and the word line 1500. Therefore, compared to a planar channel structure, the word line 1500 can achieve a higher switching speed and allows for better control of the channel structure 1700.

[0099] Method M50 continues to operation S1100, where the insulating layer is refilled into the re-exposed opening. (See reference) Figure 14A , Figure 14B and Figure 14C The isolation layer 1800 is deposited and refilled in the re-exposed opening 1400.

[0100] In some embodiments, the isolation layer 1800 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The isolation layer 1800 may then undergo a planarization process (e.g., CMP) to remove excess portions of the isolation layer 1800 on top of the second dielectric layer 1300, thereby making the isolation layer 1800 flush with the second dielectric layer 1300. In some embodiments, the planarization process may be stopped when the second dielectric layer 1300 is exposed.

[0101] In some embodiments, the isolation layer 1800 is made of a dielectric material. In some embodiments, the isolation layer 1800 is made of a dielectric material having a low dielectric constant (low k), such as silicon oxide (SiO2). In some embodiments, the isolation layer 1800 is configured to provide electrical isolation between channel structures 1700.

[0102] Method M50 continues to operation S1200, forming a third dielectric layer and contacts on the channel structure. (See reference) Figure 15A and Figure 15B A third dielectric layer 1900 is deposited on the second dielectric layer 1300, and a contact 1910 is formed in the third dielectric layer 1900, the contact 1910 being electrically connected to the corresponding channel structure 1700.

[0103] First, a third dielectric layer 1900 is deposited on the second dielectric layer 1300, word line 1500, gate dielectric 1600, and isolation layer 1800. In some embodiments, the third dielectric layer 1900 is configured to provide electrical isolation between the word line 1500 and the bit line structure to be formed in subsequent steps.

[0104] The third dielectric layer 1900 is made of a dielectric material. In some embodiments, the third dielectric layer 1900 may be made of the same dielectric material as the first dielectric layer 1100 and / or the second dielectric layer 1300. In some embodiments, the third dielectric layer 1900 is made of an oxide, such as silicon dioxide (SiO2). The third dielectric layer 1900 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the vertical thickness of the third dielectric layer 1900 is less than the vertical thickness of the second dielectric layer 1300.

[0105] In some embodiments, the third dielectric layer 1900 may be patterned to form an opening. A mask pattern (not shown) may be formed on the third dielectric layer 1900. Subsequently, the third dielectric layer 1900 is etched through the mask pattern to form the opening (not shown). In some embodiments, the opening exposes the channel structure 1700.

[0106] Next, a contact 1910 can be formed in the opening. In other words, each opening is replaced by a contact 1910. In some embodiments, the contact 1910 may be located at the top of the channel structure 1700.

[0107] The contact 1910 can be planarized so that it is flush with the third dielectric layer 1900. Therefore, the planarized contact 1910 can be coplanar with the third dielectric layer 1900, thus sharing the same top surface. In other words, the top surface of the planarized contact 1910 and the top surface of the third dielectric layer 1900 can be adjacent to each other. The planarization process can employ chemical mechanical polishing (CMP). The CMP process can be stopped when the third dielectric layer 1900 is exposed.

[0108] In some embodiments, contact 1910 is configured to provide an electrical connection between channel structure 1700 and bitline structure formed in subsequent steps. Contact 1910 is made of a conductive material. Contact 1910 may contact channel structure 1700. In some embodiments, the widths of contact 1910, channel structure 1700, and capacitor 1200 are substantially the same. In some embodiments, contact 1910, channel structure 1700, and capacitor 1200 are substantially vertically aligned. In some embodiments, contact 1910 has a square top profile.

[0109] Figure 14C A method for manufacturing a semiconductor device along line B-B' is illustrated according to certain embodiments of the present invention. Specifically, Figure 14C It is along Figure 14B A cross-sectional view of line B-B' in the top view. Note that the position of line B-B' has been slightly adjusted so that character line 1500, capacitor 1200, and the components above them are visible.

[0110] exist Figure 14C In the cross-sectional view, at least one word line 1500 is in contact with and electrically connected to the top surface of the first conductive via 500A. Therefore, the first transistor TR1 is electrically connected to the word line 1500. With this configuration, the first transistor TR1 can act as a word line driver for the word line 1500.

[0111] Method M50 continues to operation S1300, forming a bitline structure on the third dielectric layer and the contact. (Reference) Figure 16A and Figure 16B A bit line structure 1950 is formed on the third dielectric layer 1900 and the contact 1910. In some embodiments, the bit line structure 1950 may extend along a second direction (e.g., the X direction), which is different from the first direction and substantially perpendicular to the extension direction of the word line 1500.

[0112] The bit line structure 1950 may be deposited on the third dielectric layer 1900 and the contact 1910. The bit line structure 1950 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD or other suitable deposition processes. In some embodiments, the bit line structure 1950 covers the contact 1910.

[0113] In some embodiments, the bit line structure 1950 is made of a conductive material. In some embodiments, the bit line structure 1950 is made of a metal. In some embodiments, the bit line structure 1950 may include metal nitrides, metal silicides, doped polysilicon, tungsten, tungsten nitride, titanium nitride, and / or combinations thereof.

[0114] Method M50 continues to operation S1400, forming a fourth dielectric layer and contacts on the bitline structure. (Reference) Figure 17A , Figure 17B and Figure 17C A fourth dielectric layer 2900 and a contact 2910 are formed on the bit line structure 1950. Operation S1400 is similar to operation S1200, therefore similar components will use similar numbering.

[0115] First, a fourth dielectric layer 2900 is deposited on the bit line structure 1950. In some embodiments, the fourth dielectric layer 2900 is configured to provide electrical isolation between the bit line structure 1950 and the conductive material formed in subsequent steps. The fourth dielectric layer 2900 is made of a dielectric material. In some embodiments, the fourth dielectric layer 2900 and the third dielectric layer 1900 contain the same material. In some embodiments, the fourth dielectric layer 2900 is made of an oxide (e.g., silicon dioxide (SiO2)). The fourth dielectric layer 2900 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0116] In some embodiments, the fourth dielectric layer 2900 may be patterned to form an opening. A mask pattern (not shown) may be formed on the fourth dielectric layer 2900. Subsequently, the fourth dielectric layer 2900 is etched through the mask pattern to form the opening (not shown). In some embodiments, the opening is located above the channel structure 1700 and the contact 1910.

[0117] Next, a contact 2910 can be formed in the opening. In other words, each opening corresponds to one contact 2910. In some embodiments, the contact 2910 is located above the channel structure 1700 and the contact 1910.

[0118] The contact 2910 can be planarized to make it flush with the fourth dielectric layer 2900. Therefore, the planarized contact 2910 can be coplanar with the fourth dielectric layer 2900, thus sharing the same top surface. That is, the top surface of the planarized contact 2910 and the top surface of the fourth dielectric layer 2900 can be adjacent to each other. The planarization process can employ chemical mechanical polishing (CMP). The CMP process can be stopped when the fourth dielectric layer 2900 is exposed.

[0119] In some embodiments, contact 2910 has a square top profile. In some embodiments, contact 2910 is configured to provide an electrical connection between the underlying bitline structure 1950 and the channel structure formed in a subsequent step. Contact 2910 is made of a conductive material. Contact 2910 may contain the same material as contact 1910.

[0120] Figure 17C A method for manufacturing a semiconductor device along line B-B' according to some embodiments of the present invention is shown. Specifically, Figure 17C It is along Figure 17B A cross-sectional view of line B-B' in the top view.

[0121] refer to Figure 17C The character line 1500 can be located above, in contact with and electrically connected to the first conductive via 500A, and can be covered by the third dielectric layer 1900 and the fourth dielectric layer 2900.

[0122] Method M50 continues to operation S1500, forming a second conductive via that passes through the fourth dielectric layer, the third dielectric layer, the isolation layer, and the first dielectric layer and is electrically connected to the second transistor. (Reference) Figure 18A and Figure 18B A second conductive via 500B is formed, passing through the fourth dielectric layer 2900, the third dielectric layer 1900, the isolation layer 1800 and the first dielectric layer 1100, and electrically connected to the second transistor TR2.

[0123] Specifically, the second conductive via 500B is formed between the second transistor TR2 and the bottom dielectric layer 400, and can be electrically connected to the second source / drain region 300B of the second transistor TR2.

[0124] In some embodiments, the formation steps of the second conductive via 500B are as follows: First, an opening (not shown) is formed penetrating the fourth dielectric layer 2900, the third dielectric layer 1900, the isolation layer 1800, and the second dielectric layer 1300, exposing the second source / drain region 300B; then, conductive material is deposited in the opening; finally, a planarization process (e.g., CMP) is performed to remove excess conductive material until the fourth dielectric layer 2900 is exposed. The deposition of the second conductive via 500B can be performed using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0125] The second conductive via 500B may be made of a conductive material. In some embodiments, the width of the second conductive via 500B may be smaller than the width of the capacitor 1200. In some embodiments, the width of the second conductive via 500B may be substantially the same as the width of the first conductive via 500A.

[0126] In some embodiments, after the second conductive via 500B is formed, the bottom dielectric layer 400 is vertically located between the substrate layer 100 and the capacitor 1200, and laterally located between the first conductive via 500A and the second conductive via 500B.

[0127] Method M50 continues to operation S1600, where a fifth dielectric layer is formed on the fourth dielectric layer and the contact. (See reference) Figure 19A and Figure 19B A fifth dielectric layer 2300 is formed on the fourth dielectric layer 2900 and the contact 2910. Operation S1600 is similar to the formation of the second dielectric layer 1300 in operation S600, therefore similar components will use similar numbering.

[0128] First, a fifth dielectric layer 2300 is deposited on the fourth dielectric layer 2900 and the contact 2910. The fifth dielectric layer 2300 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the fifth dielectric layer 2300 covers the contact 2910. The fifth dielectric layer 2300 serves to provide electrical isolation between the contact 2910 and conductive structures (e.g., channel structures) formed in subsequent steps.

[0129] The fifth dielectric layer 2300 is made of a dielectric material. In some embodiments, the fifth dielectric layer 2300 and the second dielectric layer 1300 may be made of the same material. In some embodiments, the fifth dielectric layer 2300 is made of an oxide (e.g., silicon dioxide (SiO2)). In some embodiments, the vertical thicknesses of the second dielectric layer 1300 and the fifth dielectric layer 2300 may be substantially the same. In some embodiments, the vertical thickness of the fifth dielectric layer 2300 is greater than the vertical thickness of the fourth dielectric layer 2900.

[0130] Method M50 continues to operation S1700, where the fifth dielectric layer is patterned to expose the contacts. (See reference) Figure 20A and Figure 20B The fifth dielectric layer 2300 can be patterned to form openings 2400 for exposing contacts 2910. Operation S1700 is similar to operation S700, therefore similar components will use similar numbering.

[0131] First, a mask pattern (not shown) can be formed on the fifth dielectric layer 2300. Then, the fifth dielectric layer 2300 is etched through the mask pattern.

[0132] In some embodiments, operation S1700 may include photolithography. In some embodiments, the location of the opening 2400 may be defined by a mask pattern. For example, the mask pattern is formed in a portion of the fifth dielectric layer 2300 that is not covered and does not surround the contact 2910. Therefore, the portion of the fifth dielectric layer 2300 that is not covered and does not surround the contact 2910 is not etched during the etching process and defines the opening 2400 after the etching process. In some embodiments, the width of the opening 2400 is greater than the width of the contact 2910. In some embodiments, the opening 2400 may expose the contact 2910 and a portion of the fourth dielectric layer 2900.

[0133] Method M50 continues to operation S1800, forming word lines and gate dielectrics along the sidewall of the opening. (Reference) Figure 21A and Figure 21B Character lines 2500 and gate dielectric 2600 are sequentially formed along the sidewall of opening 2400. Operation S1800 is similar to operation S800, therefore similar components will use similar numbering.

[0134] In some embodiments, character line material (not shown) may be formed over an underlying structure (e.g., a fifth dielectric layer 2300, contact 2910, and a fourth dielectric layer 2900). The character line material may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The character line material is then subjected to an anisotropic etching process to remove the horizontal portions of the character line material, leaving only the vertical portions. The remaining vertical portions are referred to as character lines 2500.

[0135] In some embodiments, the character line 2500 may extend upward from the fourth dielectric layer 2900 and along the sidewall of the opening 2400. In some embodiments, the character line 2500 is made of a conductive material. In some embodiments, the character line 2500 may include a metal. In some embodiments, the character line 2500 is made of the same material as the character line 1500. In some embodiments, the character line 2500 may include tungsten (W). In some embodiments, the character line 2500 may serve as a gate electrode to control the channel structure formed in subsequent steps. In some embodiments, the character line 2500 has a striped top profile. In some embodiments, the character line 2500 may contact and be electrically connected to the second conductive via 500B (e.g., ...). Figure 28C (As shown).

[0136] In some embodiments, word line 1500 and word line 2500 above it can be used to receive different control voltages during a write operation.

[0137] Subsequently, a gate dielectric 2600 is formed on the sidewall of the opening 2400. Specifically, the gate dielectric 2600 is formed extending upward from the fourth dielectric layer 2900 and along the sidewall of the opening 2400.

[0138] In some embodiments, a gate dielectric material blanket (not shown) may be formed over an underlying structure (e.g., a fifth dielectric layer 2300, a contact 2910, a fourth dielectric layer 2900, and a word line 1500). The gate dielectric material blanket may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0139] Then, an anisotropic etching process is performed on the gate dielectric material blanket to remove the horizontal portion of the gate dielectric material blanket, leaving only the vertical portion of the gate dielectric material retained along the sidewall of opening 2400. The remaining vertical portion is referred to as gate dielectric 2600.

[0140] In some embodiments, gate dielectric 2600 is made of a dielectric material. In some embodiments, gate dielectric 2600 is made of the same material as gate dielectric 1600. In some embodiments, gate dielectric 2600 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. In some embodiments, gate dielectric 2600 is configured to electrically isolate word line 2500 from conductive structures (e.g., channel structures) formed in subsequent steps. In some embodiments, the width of gate dielectric 2600 is substantially the same as the width of word line 2500. In some embodiments, gate dielectric 2600 has a striped top profile.

[0141] In some embodiments, the top of the gate dielectric 2600 may be substantially flush with the top surface of the fifth dielectric layer 2300 and the word line 2500. In some embodiments, the word line 2500 and the gate dielectric 2600 do not cover the top of the contact 2910. In other words, the contact 2910 remains exposed in the opening 2400.

[0142] Method M50 continues to operation S1900, forming a channel structure material within the opening. (Reference) Figure 22A and Figure 22B A channel structure material 2700M is formed in the opening 2400. Specifically, the channel structure material 2700M is formed on the contact 2910 and surrounded by the gate dielectric 2600. In some embodiments, the channel structure material 2700M is formed on the fifth dielectric layer 2300 and surrounded by the gate dielectric 2600. Operation S1900 is similar to operation S900, therefore similar elements will be numbered similarly.

[0143] In some embodiments, a channel layer (not shown) may be formed to cover the opening 2400. The channel layer may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The channel layer may then be planarized (e.g., using a CMP process) to remove excess channel layer portions on top of the fifth dielectric layer 2300 and flush the channel layer with the fifth dielectric layer 2300. In some embodiments, planarization may be stopped when the fifth dielectric layer 2300 is exposed. The remaining portion of the channel layer is referred to as channel structure material 2700M.

[0144] Method M50 continues with operation S2000, removing a portion of the channel structure material to re-expose the opening. (See reference...) Figure 23A and Figure 23B Remove the portion of the channel structure material 2700M that does not cover the contact 2910, and re-expose the opening 2400. Operation S2000 is similar to operation S1000, therefore similar components will be numbered similarly.

[0145] First, a masking pattern (not shown) is formed on the fifth dielectric layer 2300, word line 2500, gate dielectric 2600, and channel structure material 2700M covering contact 2910. Subsequently, the portion of channel structure material 2700M not covered by the masking pattern is etched, and the opening 2400 is re-exposed.

[0146] The remaining portion of the channel structure material 2700M is referred to as channel structure 2700. In some embodiments, each channel structure 2700 extends vertically from a corresponding contact 2910. In some embodiments, the vertical length of the channel structure 2700 is substantially the same as that of the word line 2500 and / or the gate dielectric 2600. In some embodiments, the channel structure 2700 may be electrically connected to the contact 2910 below. In some embodiments, the channel structure 2700 has a square top profile.

[0147] In some embodiments, channel structure 2700 may be made of the same material as channel structure 1700. In some embodiments, channel structure 2700 may include an oxide semiconductor (OS) material. In some embodiments, channel structure 2700 may include indium gallium zinc oxide (IGZO). The vertical channel structure 2700 may increase the memory cell density in semiconductor device 10.

[0148] In some embodiments, the channel structure 2700 may be covered by the word line 2500 passing through the gate dielectric 2600. In other words, the word line 2500 (which may serve as a gate electrode), the gate dielectric 2600, and the channel structure 2700 may form a transistor (e.g., Figure 2 The access transistor 11T in the channel structure 2700 has a gate dielectric 2600 covering opposite sides of the channel structure 2700. This configuration provides a larger contact surface for the channel structure 2700, thereby increasing the current flowing through the gate dielectric 2600 and the word line 2500. Therefore, compared to a planar channel structure, the word line 2500 can achieve a higher switching speed and allows for better control of the channel structure 2700.

[0149] Method M50 continues with operation S2100, refilling the insulating layer into the re-exposed opening. (See reference) Figure 24A , Figure 24B and Figure 24C The isolation layer 2800 is deposited and refilled in the re-exposed opening 2400. Operation S2100 is similar to operation S1100, so similar elements will be numbered similarly.

[0150] In some embodiments, the isolation layer 2800 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The isolation layer 2800 may then undergo a planarization process (e.g., CMP) to remove excess portions of the isolation layer 2800 on top of the fifth dielectric layer 2300, thereby flush the isolation layer 2800 with the fifth dielectric layer 2300. In some embodiments, the planarization process may be stopped when the fifth dielectric layer 2300 is exposed.

[0151] In some embodiments, the isolation layer 2800 is made of a dielectric material. In some embodiments, the isolation layer 2800 is made of the same material as the isolation layer 1800. In some embodiments, the isolation layer 2800 is made of a dielectric material having a low dielectric constant (low k), such as silicon oxide (SiO2). In some embodiments, the isolation layer 2800 is configured to provide electrical isolation between the channel structures 2700.

[0152] exist Figure 24C In the cross-sectional view, at least one word line 2500 is in contact with and electrically connected to the top surface of the second conductive via 500B. Therefore, the second transistor TR2 is electrically connected to the word line 2500. With this configuration, the second transistor TR2 can act as a word line driver for the word line 2500.

[0153] Method M50 continues to operation S2200, forming a sixth dielectric layer on the channel structure. (See reference) Figure 25A and Figure 25B A sixth dielectric layer 2100 is deposited on the channel structure 2700.

[0154] Specifically, a sixth dielectric layer 2100 is deposited on the channel structure 2700, the fifth dielectric layer 2300, the word line 2500, the gate dielectric 2600, and the isolation layer 2800. The sixth dielectric layer 2100 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0155] The sixth dielectric layer 2100 is made of a dielectric material. The sixth dielectric layer 2100 may be made of a different dielectric material than the fourth dielectric layer 2900 or the fifth dielectric layer 2300. In some embodiments, the sixth dielectric layer 2100 is made of a nitride, such as silicon nitride (SiN).

[0156] In some embodiments, the sixth dielectric layer 2100 is configured to provide electrical isolation between the character line 2500 and the conductive structure formed in subsequent steps.

[0157] Method M50 continues to operation S2300, patterning the sixth dielectric layer to expose the channel structure. (See reference) Figure 26A and Figure 26B The sixth dielectric layer 2100 is patterned to form an opening in the exposed channel structure 2700.

[0158] First, a mask pattern (not shown) may be formed on the sixth dielectric layer 2100. Then, the sixth dielectric layer 2100 is etched through the mask pattern to form an opening 2150. In some embodiments, the opening 2150 exposes the top surface of the channel structure 2700.

[0159] Method M50 continues to operation S2400, forming a capacitor on the channel structure. (Reference) Figure 27A and Figure 27B A capacitor 2200 is formed on the channel structure 2700.

[0160] Specifically, capacitors 2200 may be formed in openings 2150. In other words, capacitors 2200 replace each opening 2150. In some embodiments, capacitors 2200 are parallel to each other and may be arranged regularly at substantially equal intervals.

[0161] Capacitor 2200 may be substantially the same as capacitor 1200. That is, capacitor 2200 may include a bottom electrode, a capacitor dielectric layer above the bottom electrode, and a top electrode above the capacitor dielectric layer. In some embodiments, the bottom electrode and top electrode of capacitor 2200 may include conductive materials.

[0162] Capacitor 2200 may comprise substantially the same material as capacitor 1200. In some embodiments, the bottom electrode and top electrode may comprise metal. In some embodiments, the bottom electrode and top electrode may comprise titanium nitride (TiN). In some embodiments, the capacitor dielectric layer of capacitor 2200 may comprise a dielectric material. The bottom electrode, capacitor dielectric layer, and top electrode of capacitor 2200 may be deposited sequentially using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0163] Method M50 continues to operation S2500, etching back the sixth dielectric layer. (Reference) Figure 28A , Figure 28B and Figure 28C , Etch back the sixth dielectric layer 2100.

[0164] First, the sixth dielectric layer 2100 is etched back so that the top surface of the sixth dielectric layer 2100 is lower than the top surface of the capacitor 2200. As a result, the capacitor 2200 can protrude from the etched top surface of the sixth dielectric layer 2100.

[0165] In some embodiments, the vertical thickness of capacitor 2200 is greater than the vertical thickness of sixth dielectric layer 2100. In some embodiments, the vertical thickness of sixth dielectric layer 2100 is less than the vertical thickness of fourth dielectric layer 2900 and / or fifth dielectric layer 2300.

[0166] Figure 28C For along Figure 28B A cross-sectional view of line B-B' from a top view. (See diagram below.) Figure 28C As shown, word line 1500 and word line 2500 can be electrically connected to their respective transistors TR1 and TR2 through their respective conductive vias 500A and 500B.

[0167] In summary, the present invention provides a method for manufacturing a structure with dual memory arrays, wherein a first memory array is located at a bottom layer and a second memory array is located at a top layer above the bottom layer. The first memory array may include a plurality of first memory cells, wherein each first memory cell includes a capacitor 1200, a first access transistor (e.g., a channel structure 1700, a gate dielectric 1600, and a word line 1500). At least one word line 1500 is disposed at the bottom layer and electrically connected to the first memory cell.

[0168] On the other hand, the second memory array may include a plurality of second memory cells, each of which includes a capacitor 2200, a second access transistor (e.g., a channel structure 2700, a gate dielectric 2600, and a word line 2500). At least one word line 2500 is disposed on the top layer and electrically connected to the second memory cell. Furthermore, at least one bit line structure 1950 is vertically disposed between the first and second memory arrays and electrically connected thereto. This dual-layout design facilitates increased cell capacitance (potentially doubling) and enhanced signal margin.

[0169] Furthermore, word line 1500 and word line 2500 can be electrically connected to their respective transistors TR1 and TR2 through their respective conductive vias 500A and 500B, thus enabling them to receive different control voltages during write operations.

[0170] Although this disclosure has been described in considerable detail with reference to certain embodiments of the invention, other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.

[0171] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of this disclosure. In view of the foregoing, the present invention is intended to cover modifications and variations thereof, provided they fall within the scope of the following claims.

[0172] [Symbol Explanation]

[0173] 10: Semiconductor devices

[0174] 11: Memory Unit

[0175] 11C: Storage capacitor

[0176] 11T: Access Transistor

[0177] 20: Character Line

[0178] 30: Bit line

[0179] TR1: Transistor

[0180] TR2: Transistor

[0181] 100: Substrate layer

[0182] 200A: Gate structure

[0183] 200B: Gate structure

[0184] 300A: Source / Drain Region

[0185] 300B: Source / Drain Region

[0186] 201: Gate dielectric layer

[0187] 202: First conductive layer

[0188] 203: Second conductive layer

[0189] 204: Third conductive layer

[0190] 205: Dielectric capping layer

[0191] 400: Bottom dielectric layer

[0192] 500A: Conductive Through Hole

[0193] 500B: Conductive via

[0194] 1100: First dielectric layer

[0195] 1200: Capacitor

[0196] 1300: Second dielectric layer

[0197] 1400: Opening

[0198] 1500: Character Line

[0199] 1600: Gate Dielectric

[0200] 1700: Channel Structure

[0201] 1700M: Channel structural material

[0202] 1800: Isolation layer

[0203] 1900: Third dielectric layer

[0204] 1910: Contact element

[0205] 1950: Bitline Structure

[0206] 2150: Opening

[0207] 2100: Sixth dielectric layer

[0208] 2200: Capacitor

[0209] 2300: Fifth dielectric layer

[0210] 2400: Opening

[0211] 2500: Character Line

[0212] 2600: Gate Dielectric

[0213] 2700: Channel Structure

[0214] 2700M: Channel structural material

[0215] 2800: Isolation layer

[0216] 2900: Fourth dielectric layer

[0217] 2910: Contact element

[0218] A-A': line

[0219] B-B': line

[0220] M50: Method

[0221] S100: Operation

[0222] S200: Operation

[0223] S300: Operation

[0224] S400: Operation

[0225] S500: Operation

[0226] S600: Operation

[0227] S700: Operation

[0228] S800: Operation

[0229] S900: Operation

[0230] S1000: Operation

[0231] S1100: Operation

[0232] S1200: Operation

[0233] S1300: Operation

[0234] S1400: Operation

[0235] S1500: Operation

[0236] S1600: Operation

[0237] S1700: Operation

[0238] S1800: Operation

[0239] S1900: Operation

[0240] S2000: Operation

[0241] S2100: Operation

[0242] S2200: Operation

[0243] S2300: Operation

[0244] S2400: Operation

[0245] S2500: Operation.

Claims

1. A semiconductor device, characterized in that, include: Substrate layer; The first transistor and the second transistor are located above the substrate layer; The first memory cell located above the substrate layer; A first word line located above the substrate layer and electrically connected to the first memory cell, wherein the first word line is located at a first height, and the first transistor is electrically connected to the first word line; The second memory cell is located above the substrate layer; as well as A second word line is located above the substrate layer and electrically connected to the second memory cell, wherein the second word line is located at a second height above the first height, and the second transistor is electrically connected to the second word line.

2. The apparatus of claim 1, wherein the height of the second memory unit is greater than the height of the first memory unit.

3. The apparatus of claim 1, wherein the first memory cell includes a first access transistor and a first capacitor, the first access transistor being located above the first capacitor.

4. The apparatus of claim 3, wherein the second memory cell includes a second access transistor and a second capacitor, the second capacitor being located above the second access transistor.

5. The apparatus according to claim 3, wherein, It also includes a bottom dielectric layer located between the substrate layer and the first capacitor of the first memory cell.

6. The apparatus according to claim 1, wherein, Also includes: A first conductive via is located above the substrate layer and electrically connected to the first transistor and the first character line; as well as A second conductive via is located above the substrate layer and electrically connected to the second transistor and the second character line.

7. The apparatus of claim 6, wherein the top surface of the first conductive via is lower than the top surface of the second conductive via.

8. The apparatus of claim 7, wherein the bottom surface of the first conductive via and the bottom surface of the second conductive via are located on the top surface of the substrate layer.

9. The apparatus according to claim 1, wherein, It also includes bit lines that are located between the first memory cell and the second memory cell and are electrically connected.

10. The apparatus of claim 9, wherein the bit line is located at a third height between the first height and the second height.

11. A method for manufacturing a semiconductor device, characterized in that, include: Forming a substrate layer; A first transistor and a second transistor are formed on the substrate layer; A first word line and a first memory cell electrically connected to each other are formed above the substrate layer, wherein the first word line is located at a first height, and the first transistor is electrically connected to the first word line; as well as A second word line and a second memory cell electrically connected to each other are formed above the substrate layer, wherein the second word line is located at a second height above the first height, and the second transistor is electrically connected to the second word line.

12. The method of claim 11, wherein the second memory cell is formed at a higher height than the first memory cell.

13. The method of claim 11, wherein the first memory cell includes a first capacitor and a first access transistor located above the first capacitor.

14. The method of claim 13, wherein the second memory cell includes a second capacitor and a second access transistor located below the second capacitor.

15. The method according to claim 11, wherein, Also includes: Before forming the first memory cell, a bottom dielectric layer is formed above the substrate layer, wherein the first memory cell is formed on the bottom dielectric layer.

16. The method according to claim 11, wherein, Also includes: A first conductive via is formed above the substrate layer and electrically connected to the first transistor, wherein the first word line is electrically connected to the first conductive via.

17. The method according to claim 11, wherein, Also includes: A second conductive via is formed above the substrate layer and electrically connected to the second transistor, wherein the second word line is electrically connected to the second conductive via.

18. The method according to claim 11, wherein, Also includes: A bit line is formed that is electrically connected to the first memory cell, wherein the second memory cell is formed on the bit line and electrically connected to it.

19. The method according to claim 18, wherein, Also includes: Before the bit line is formed, a first contact is formed above the first memory cell and electrically connected to the first memory cell, wherein the bit line is formed above the first contact; as well as After the bit line is formed, a second contact is formed on the bit line and electrically connected to the bit line.

20. The method of claim 18, wherein the bit line is formed at a third height between the first height and the second height.

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