Resistive random access memory element and manufacturing method thereof

Abstract

The invention discloses a resistive random access memory element and a manufacturing method thereof. The resistive random access memory element comprises a substrate; a first interlayer dielectric layer disposed on the substrate; the first interconnection structure is arranged in the first interlayer dielectric layer; a cap layer disposed on the first interconnect structure and the first interlayer dielectric layer; an intermediate dielectric layer disposed on the cap layer; a conductive via disposed in the cap layer and the intermediate dielectric layer, where the conductive via includes a grinding stop layer, a barrier layer on the grinding stop layer, and a tungsten layer on the barrier layer; and the resistance switching structure is arranged on the conductive through hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular, to a resistive random access memory (RRAM) element and a method for fabricating the same. BACKGROUND

[0002] A resistive random access memory (RRAM) is a memory structure that includes an array of RRAM cells, each of which stores a bit of data using resistance values rather than charge. In particular, each RRAM cell includes a layer of resistance-switching material whose resistance can be adjusted to represent a logical "0" or a logical "1".

[0003] At advanced technology nodes, feature sizes are scaled down, and the size of memory elements is also scaled down accordingly. However, the scaling down of RRAM elements is limited due to a "forming" operation. During the "forming" process, a high voltage is applied to the RRAM element to generate a conductive path in the layer of resistance-switching material.

[0004] When integrating RRAM elements into a 12-nanometer node fabrication process, a short via design must be used, and because a tungsten metal grinding fabrication process consumes a large amount of silicon oxide layer, a step height required for photolithography fabrication process alignment is insufficient. Although an additional photomask can solve the alignment problem, it increases the fabrication process cost. SUMMARY

[0005] The main purpose of the present application is to provide an improved resistive random access memory element and a method for fabricating the same to solve the problems of the prior art.

[0006] One aspect of the present application provides a resistive random access memory element, comprising: a substrate; a first interlayer dielectric layer disposed on the substrate; a first interconnect structure disposed in the first interlayer dielectric layer; a cap layer disposed on the first interconnect structure and the first interlayer dielectric layer; an intermediate dielectric layer disposed on the cap layer; a conductive via disposed in the cap layer and the intermediate dielectric layer, wherein the conductive via comprises a stop layer, a barrier layer on the stop layer, and a tungsten layer on the barrier layer; and a resistance-switching structure disposed on the conductive via.

[0007] According to an embodiment of the present application, the conductive via comprises an upper portion protruding from a top surface of the intermediate dielectric layer.

[0008] According to an embodiment of the present application, the resistive random access memory element further comprises: a spacer disposed around the upper portion of the conductive via and the resistance-switching structure.

[0009] According to an embodiment of the present invention, the gap wall covers the sidewall of the resistive switch structure, the upper sidewall of the conductive via, and the top surface of the intermediate dielectric layer, wherein the gap wall directly contacts the grinding stop layer.

[0010] According to an embodiment of the present invention, the spacer wall comprises a silicon nitride layer and a silicon oxide layer.

[0011] According to an embodiment of the present invention, the capping layer comprises a nitrogen-doped silicon carbide layer.

[0012] According to an embodiment of the present invention, the intermediate dielectric layer comprises a TEOS silicon oxide layer.

[0013] According to an embodiment of the present invention, the grinding stop layer comprises tantalum nitride.

[0014] According to an embodiment of the present invention, the barrier layer comprises titanium nitride.

[0015] According to an embodiment of the present invention, the resistive random access memory element further includes: a second interlayer dielectric layer covering the gap wall; and a second interconnect structure disposed in the second interlayer dielectric layer.

[0016] Another aspect of the present invention provides a method for forming a resistive random access memory element, comprising: providing a substrate; forming a first interlayer dielectric layer on the substrate; forming a first interconnect structure in the first interlayer dielectric layer; forming a capping layer on the first interconnect structure and the first interlayer dielectric layer; forming an intermediate dielectric layer on the capping layer; forming a conductive via in the capping layer and the intermediate dielectric layer, wherein the conductive via includes a polishing stop layer, a barrier layer on the polishing stop layer, and a tungsten layer on the barrier layer; and forming a resistance switching structure on the conductive via.

[0017] According to an embodiment of the present invention, the conductive via includes an upper portion protruding from the top surface of the intermediate dielectric layer.

[0018] According to an embodiment of the present invention, the method further includes: forming a gap wall around the upper part of the conductive via and the resistance switching structure.

[0019] According to an embodiment of the present invention, the gap wall covers the sidewall of the resistance switching structure, the upper sidewall of the conductive via, and the top surface of the intermediate dielectric layer, wherein the gap wall directly contacts the grinding stop layer.

[0020] According to an embodiment of the present invention, the spacer wall comprises a silicon nitride layer and a silicon oxide layer.

[0021] According to an embodiment of the present invention, the capping layer comprises a nitrogen-doped silicon carbide layer.

[0022] According to an embodiment of the present invention, the intermediate dielectric layer comprises a TEOS silicon oxide layer.

[0023] According to an embodiment of the present invention, the grinding stop layer comprises tantalum nitride.

[0024] According to an embodiment of the present invention, the barrier layer comprises titanium nitride.

[0025] According to an embodiment of the present invention, the method further includes: forming a second interlayer dielectric layer on the gap wall; and forming a second interconnect structure in the second interlayer dielectric layer. Attached Figure Description

[0026] Figure 1 This is a cross-sectional schematic diagram of a portion of a memory element region of a resistive random access memory element according to an embodiment of the present invention;

[0027] Figures 2 to 5 This is a schematic diagram illustrating a method for forming a resistive random access memory element according to an embodiment of the present invention.

[0028] Symbol Explanation

[0029] 1 Resistive Random Access Memory Element

[0030] 100 base

[0031] 106 Etching Stop Layer

[0032] 110 First interlayer dielectric layer

[0033] 120 cap layer

[0034] 130 Intermediate Dielectric Layer

[0035] 130a Top surface

[0036] 160 Second interlayer dielectric layer

[0037] 200 conductive via

[0038] 200a upper part

[0039] 201 Grinding Stop Layer

[0040] 202 Barrier Layer

[0041] 203 Tungsten layer

[0042] 300 resistor switching structure

[0043] 310 Hard mask layer

[0044] 400 gap wall

[0045] 410 silicon nitride layer

[0046] 420 silicon oxide layer

[0047] AM Alignment Marker Area

[0048] M1 First Interconnection Structure

[0049] M2 Second Interconnection Structure

[0050] MR storage cell area

[0051] S1 and S2 sidewalls

[0052] SH trench step height

[0053] SV through hole

[0054] T aligned with the groove

[0055] V1 Conductive Through Hole Detailed Implementation

[0056] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0057] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0058] Please see Figure 1 This is a cross-sectional schematic diagram of a portion of a memory element region of a resistive random access memory element according to an embodiment of the present invention. Figure 1 As shown, the resistive random access memory element 1 includes a substrate 100 and a first interlayer dielectric layer 110 disposed on the substrate 100. According to embodiments of the present invention, the substrate 100 may be a semiconductor substrate, such as a silicon substrate, but is not limited thereto. According to embodiments of the present invention, for example, the first interlayer dielectric layer 110 may comprise a low dielectric constant material layer or an ultra-low dielectric constant material layer. According to embodiments of the present invention, the thickness of the first interlayer dielectric layer 110 is, for example, about 800 to 900 angstroms.

[0059] According to an embodiment of the present invention, a first interconnect structure M1 is formed in the first interlayer dielectric layer 110. According to an embodiment of the present invention, the first interconnect structure M1 may be a copper damascene structure, for example. According to an embodiment of the present invention, a capping layer 120 is formed on the first interconnect structure M1 and the first interlayer dielectric layer 110. According to an embodiment of the present invention, the capping layer 120 may comprise, for example, a nitrogen-doped silicon carbide layer, but is not limited thereto. According to an embodiment of the present invention, the thickness of the capping layer 120 is, for example, about 100 angstroms.

[0060] According to an embodiment of the present invention, an intermediate dielectric layer 130 is formed on the capping layer 120. According to an embodiment of the present invention, the intermediate dielectric layer 130 may, for example, comprise a TEOS silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, the thickness of the intermediate dielectric layer 130 is, for example, about 100 angstroms.

[0061] According to an embodiment of the present invention, the resistive random access memory element 1 further includes a conductive via 200 disposed in the capping layer 120 and the intermediate dielectric layer 130. According to an embodiment of the present invention, for example, the conductive via 200 includes an outermost polish stop layer 201, a barrier layer 202 located on the polish stop layer 201, and a tungsten layer 203 located on the barrier layer 202. According to an embodiment of the present invention, the polish stop layer 201 includes, for example, a material with a high polishing selectivity relative to the tungsten layer 203, such as tantalum nitride. According to an embodiment of the present invention, the barrier layer 202 includes, for example, titanium nitride, but is not limited thereto.

[0062] According to an embodiment of the present invention, the height of the conductive via 200 is approximately between 200 and 600 angstroms, for example, between 400 and 500 angstroms. According to an embodiment of the present invention, the conductive via 200 includes an upper portion 200a protruding from the top surface 130a of the intermediate dielectric layer 130. The resistive random access memory element 1 further includes a resistance switching structure 300 disposed on the conductive via 200. According to an embodiment of the present invention, the sidewall S1 of the resistance switching structure 300 may be flush with the sidewall S2 of the upper portion 200a of the conductive via 200. According to an embodiment of the present invention, the top surface of the resistance switching structure 300 may be covered by a hard mask layer 310.

[0063] According to an embodiment of the present invention, the resistance switching structure 300 may include a stacked structure such as a bottom electrode layer, a resistance switching layer and a top electrode layer. For example, the bottom electrode layer may include TaN, TiN, Pt, Ir, Ru or W, the resistance switching layer may include hafnium oxide, tantalum oxide, titanium, titanium oxide or a combination thereof, and the top electrode layer may include TiN, TaN, Pt, Ir or W, but is not limited thereto.

[0064] According to an embodiment of the present invention, a spacer wall 400 is provided around the upper portion 200a of the conductive via 200 and the resistor switching structure 300. According to an embodiment of the present invention, the spacer wall 400 may, for example, comprise a silicon nitride layer 410 and a silicon oxide layer 420, but is not limited thereto. According to an embodiment of the present invention, the silicon nitride layer 410 conformally covers the sidewall S1 of the resistor switching structure 300, the sidewall S2 of the upper portion 200a of the conductive via 200, and the top surface 130a of the intermediate dielectric layer 130. According to an embodiment of the present invention, the silicon nitride layer 410 directly contacts the polishing stop layer 201, but does not directly contact the barrier layer 202 and the tungsten layer 203.

[0065] According to an embodiment of the present invention, the resistive random access memory element 1 further includes a second interlayer dielectric layer 160, a cover gap wall 400, and a resistance switching structure 300. According to an embodiment of the present invention, a second interconnect structure M2 is formed in the second interlayer dielectric layer 160. According to an embodiment of the present invention, for example, the second interconnect structure M2 may be disposed between two adjacent resistance switching structures 300. The second interconnect structure M2 may be electrically connected to the first interconnect structure M1 through a conductive via V1.

[0066] Please see Figures 2 to 5 This is a schematic diagram illustrating a method for forming a resistive random access memory element according to an embodiment of the present invention, wherein the same layers, materials, or regions are still represented by the same symbols. Figure 2 As shown, a substrate 100, such as a silicon substrate, is first provided. According to an embodiment of the present invention, the substrate 100 includes a memory cell region MR and an alignment mark region AM. According to an embodiment of the present invention, an etch stop layer 106, a first interlayer dielectric layer 110, a capping layer 120, and an intermediate dielectric layer 130 are formed on the substrate 100.

[0067] For example, the etch stop layer 106 may comprise a nitrogen-doped silicon carbide layer, but is not limited thereto. The first interlayer dielectric layer 110 may comprise a low-dielectric-constant material layer or an ultra-low-dielectric-constant material layer. According to an embodiment of the invention, the thickness of the first interlayer dielectric layer 110 is, for example, about 800 to 900 angstroms. According to an embodiment of the invention, for example, the capping layer 120 comprises a nitrogen-doped silicon carbide layer, but is not limited thereto. According to an embodiment of the invention, the thickness of the capping layer 120 is, for example, about 100 angstroms. According to an embodiment of the invention, for example, the intermediate dielectric layer 130 may comprise a TEOS silicon oxide layer, but is not limited thereto. According to an embodiment of the invention, the thickness of the intermediate dielectric layer 130 is, for example, about 300 angstroms.

[0068] According to an embodiment of the present invention, a first interconnect structure M1 is formed in the first interlayer dielectric layer 110 within the memory cell region MR. According to an embodiment of the present invention, for example, the first interconnect structure M1 may be a copper damascene structure. According to an embodiment of the present invention, an alignment trench T is formed within the alignment mark region AM using photolithography and etching processes. According to an embodiment of the present invention, the alignment trench T may extend deep into the alignment trench T, exposing the etch stop layer 106 at its bottom. For example, the depth of the alignment trench T is approximately 1200–1300 angstroms.

[0069] like Figure 3As shown, photolithography and etching processes are then performed to form vias SV in the intermediate dielectric layer 130 and capping layer 120 above the first interconnect structure M1 in the memory cell region MR, exposing a portion of the first interconnect structure M1. Next, a chemical vapor deposition process is performed to deposit a polishing stop layer 201, a barrier layer 202, and a tungsten layer 203 over the substrate 100. The polishing stop layer 201 and the barrier layer 202 are conformally filled into the vias SV. Finally, the tungsten layer 203 fills the remaining space within the vias SV. In the alignment mark region AM, the polishing stop layer 201, the barrier layer 202, and the tungsten layer 203 are conformally filled into the alignment trench T.

[0070] Subsequently, a tungsten chemical mechanical polishing (WCMP) process is performed to remove the barrier layer 202 and tungsten layer 203 in the memory cell region MR and the alignment mark region AM. Because the polishing stop layer 201 has a high selectivity relative to the tungsten layer 203, polishing stops at the polishing stop layer 201, leaving the barrier layer 202 and tungsten layer 203 in the via SV, forming a conductive via 200. At this time, residual barrier layer 202 and tungsten layer 203 will also remain in the alignment trench T. Because of the polishing stop layer 201, the thickness of the intermediate dielectric layer 130 in the alignment mark region AM and the intermediate dielectric layer 130 in the memory cell region MR can be approximately the same. Therefore, the intermediate dielectric layer 130 is not consumed in the WCMP process, allowing the trench step height SH in the alignment mark region AM to reach approximately 920 angstroms, improving the alignment accuracy of subsequent photolithography processes.

[0071] like Figure 4 As shown, subsequent deposition, photolithography, and etching processes are performed to form a resistance switching structure 300 on the conductive via 200 within the memory cell region MR. During the formation of the resistance switching structure 300, the polishing stop layer 201 and part of the intermediate dielectric layer 130 not covered by the resistance switching structure 300 are etched away. At this point, the conductive via 200 includes an upper portion 200a protruding from the top surface 130a of the intermediate dielectric layer 130, and the remaining thickness of the intermediate dielectric layer 130 is approximately 100 angstroms.

[0072] like Figure 5As shown, a chemical vapor deposition and etching process is then performed to form a spacer wall 400 around the upper portion 200a of the conductive via 200 and the resistance switching structure 300. According to an embodiment of the invention, the spacer wall 400 may, for example, comprise a silicon nitride layer 410 and a silicon oxide layer 420, but is not limited thereto. According to an embodiment of the invention, the silicon nitride layer 410 conformally covers the sidewall S1 of the resistance switching structure 300, the sidewall S2 of the upper portion 200a of the conductive via 200, and the top surface 130a of the intermediate dielectric layer 130. According to an embodiment of the invention, the silicon nitride layer 410 directly contacts the polishing stop layer 201, but does not directly contact the barrier layer 202 and the tungsten layer 203. According to an embodiment of the invention, a second interlayer dielectric layer 160 is then formed on the spacer wall 400 and the resistance switching structure 300. Subsequently, a metallization process can be performed to form a second interconnect structure M2 in the second interlayer dielectric layer 160.

[0073] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A resistive random access memory element, comprising: Base; The first interlayer dielectric layer is disposed on the substrate; A first interconnect structure is disposed in the first interlayer dielectric layer; A capping layer is disposed on the first interconnect structure and the first interlayer dielectric layer; An intermediate dielectric layer is disposed on the cover layer; A conductive via is disposed in the capping layer and the intermediate dielectric layer, wherein the conductive via includes a polishing stop layer, a barrier layer located on the polishing stop layer, and a tungsten layer located on the barrier layer; as well as A resistance switching structure is disposed on the conductive via.

2. The resistive random access memory element as described in claim 1, wherein, The conductive via includes an upper portion that protrudes from the top surface of the intermediate dielectric layer.

3. The resistive random access memory element as described in claim 2, wherein, Also includes: A gap wall is provided on the upper part of the conductive via and around the resistive switch structure.

4. The resistive random access memory element as described in claim 3, wherein, The gap wall covers the sidewall of the resistive switch structure, the upper sidewall of the conductive via, and the top surface of the intermediate dielectric layer, wherein the gap wall directly contacts the grinding stop layer.

5. The resistive random access memory element as described in claim 3, wherein, The spacer wall contains a silicon nitride layer and a silicon oxide layer.

6. The resistive random access memory element as claimed in claim 1, wherein, The capping layer contains a nitrogen-doped silicon carbide layer.

7. The resistive random access memory element as claimed in claim 1, wherein, The intermediate dielectric layer contains a TEOS silicon oxide layer.

8. The resistive random access memory element as claimed in claim 1, wherein, The grinding stop layer contains tantalum nitride.

9. The resistive random access memory element as claimed in claim 1, wherein, The barrier layer contains titanium nitride.

10. The resistive random access memory element as claimed in claim 3, wherein, Also includes: A second interlayer dielectric layer covers the spacer wall; and The second interconnect structure is disposed in the second interlayer dielectric layer.

11. A method for forming a resistive random access memory element, comprising: Provide a base; A first interlayer dielectric layer is formed on the substrate; A first interconnect structure is formed in the first interlayer dielectric layer; A capping layer is formed on the first interconnect structure and the first interlayer dielectric layer; An intermediate dielectric layer is formed on this capping layer; Conductive vias are formed in the capping layer and the intermediate dielectric layer, wherein, The conductive via includes a grinding stop layer, a barrier layer on the grinding stop layer, and a tungsten layer on the barrier layer; as well as A resistance switching structure is formed on the conductive via.

12. The method of claim 11, wherein, The conductive via includes an upper portion that protrudes from the top surface of the intermediate dielectric layer.

13. The method of claim 12, wherein, Also includes: A gap wall is formed at the top of the conductive via and around the resistor switching structure.

14. The method of claim 13, wherein, The gap wall covers the sidewall of the resistance switching structure, the upper sidewall of the conductive via, and the top surface of the intermediate dielectric layer, wherein the gap wall directly contacts the grinding stop layer.

15. The method of claim 13, wherein, The spacer wall contains a silicon nitride layer and a silicon oxide layer.

16. The method of claim 11, wherein, The capping layer contains a nitrogen-doped silicon carbide layer.

17. The method of claim 11, wherein, The intermediate dielectric layer contains a TEOS silicon oxide layer.

18. The method of claim 11, wherein, The grinding stop layer contains tantalum nitride.

19. The method of claim 11, wherein, The barrier layer contains titanium nitride.

20. The method of claim 12, wherein, Also includes: A second interlayer dielectric layer is formed on the gap wall; and A second interconnect structure is formed in the second interlayer dielectric layer.

Images