Multi-chip parallel half-bridge IGBT device

Abstract

The invention discloses a multi-chip parallel half-bridge IGBT (Insulated Gate Bipolar Translator) device, which comprises a substrate, a first ceramic copper-clad substrate and a second ceramic copper-clad substrate are arranged on the substrate in parallel, an upper bridge circuit is arranged on the first ceramic copper-clad substrate, a lower bridge circuit is arranged on the second ceramic copper-clad substrate, and each of the upper bridge circuit and the lower bridge circuit comprises a plurality of groups of chips which are connected in parallel. Each group of chips comprises an IGBT chip and an FRD chip. The utilization rate of the internal space of the device can be improved.

Description

Technical Field

[0001] This invention relates to power semiconductor devices, and more specifically to a multi-chip parallel half-bridge IGBT device. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) power devices are core components of photovoltaic inverters and energy storage converters, performing functions such as voltage transformation, frequency conversion, and AC / DC conversion. Their performance plays a decisive role in the performance of photovoltaic inverters and energy storage converters. As the power of single units continues to increase, the power rating requirements for IGBT power devices are also becoming increasingly stringent. Currently, high-power IGBT devices are mostly multi-chip parallel IGBT power modules. The parallel connection of multiple chips within the module expands the current rating of the device to ensure that the power output capability meets requirements. Within the IGBT power device, due to the inconsistent conduction paths of each chip, dynamic and static current imbalances occur between the parallel chips. Each chip, due to its own turn-on and turn-off, power handling fluctuations, and changes in the external operating environment, is subjected to unbalanced electrothermal stress over a long period, making it prone to thermal fatigue during operation and reducing its reliability. Meanwhile, the junction temperature of the chip has a significant impact on the fatigue life of the device. The higher the maximum junction temperature, the greater the junction temperature difference, and the lower the power cycle life. Under the same electrical parameters, the junction temperature of the chip is related to the chip area. When the thickness is the same, the smaller the chip area, the greater its thermal resistance, and the higher the temperature rise and junction temperature under the same loss. On the other hand, when chips are connected in parallel and operate simultaneously, thermal coupling will form. The closer the chips are, the stronger the thermal coupling effect, which will further reduce the module's heat dissipation capacity and increase the chip junction temperature. Therefore, ensuring the consistency of current sharing among multiple chips connected in parallel within the device and reducing the chip junction temperature during operation are of great significance for ensuring the long-term stable operation of the device.

[0003] like Figure 1 and Figure 2As shown, in the prior art, both the upper bridge circuit and the lower bridge circuit contain two ceramic copper-clad substrates. Taking the upper bridge as an example, two sets of chips are soldered on the two ceramic copper-clad substrates respectively, and the collectors and emitters of the chips on the two ceramic copper-clad substrates are connected through power terminals to achieve the parallel connection of four sets of chips. However, existing technologies have the following drawbacks: Firstly, due to the limited space of the ceramic copper-clad substrate, the internal space utilization of the device is low, resulting in smaller IGBT and FRD chip areas (IGBT chips are generally 10*10mm at most, and FRD chips are approximately 10*9mm), leading to higher chip thermal resistance and higher chip temperature rise at the same power. Secondly, due to the limited space of the ceramic copper-clad substrate, multiple parallel IGBT and FRD chips are located close together (in traditional high-current designs, the distance between two adjacent IGBT chips is 1.5mm to 5mm, and the distance between two adjacent FRD chips is around 6mm). In high-power applications, there is high thermal coupling between IGBT chips and FRD chips, resulting in significant chip overheating. Thirdly, since both the upper and lower bridge circuits consist of four sets of chips connected in parallel, the chip paths are highly inconsistent, and the parasitic parameters of each chip circuit differ significantly, leading to differences in the turn-on speed of each chip and significant differences in the electrical stress experienced by the chips during device operation. Summary of the Invention

[0004] Purpose of the invention: The purpose of this invention is to provide a multi-chip parallel half-bridge IGBT device that can improve the utilization rate of the internal space of the device.

[0005] Technical solution: The present invention provides a multi-chip parallel half-bridge IGBT device, comprising a substrate, wherein a first ceramic copper-clad substrate and a second ceramic copper-clad substrate are arranged in parallel on the substrate, an upper bridge circuit is disposed on the first ceramic copper-clad substrate, and a lower bridge circuit is disposed on the second ceramic copper-clad substrate, both the upper bridge circuit and the lower bridge circuit comprising multiple sets of chips connected in parallel, each set of chips comprising an IGBT chip and an FRD chip.

[0006] Furthermore, both the upper bridge circuit and the lower bridge circuit include three sets of chips, and the current path of each set of chips is the same.

[0007] Furthermore, the bridge circuit includes a first bridge IGBT chip, a second bridge IGBT chip, a third bridge IGBT chip, a first bridge FRD chip, a second bridge FRD chip, and a third bridge FRD chip; the collectors of the first bridge IGBT chip, the second bridge IGBT chip, and the third bridge IGBT chip are connected to the cathodes of the first bridge FRD chip, the second bridge FRD chip, and the third bridge FRD chip through the upper copper layer of the first ceramic copper-clad substrate;

[0008] The emitters of the first, second, and third upper-bridge IGBT chips are connected to the anodes of the corresponding first, second, and third upper-bridge FRD chips.

[0009] Furthermore, the emitter of the first upper-bridge IGBT chip is connected to the anode of the first upper-bridge FRD chip via a first bonding wire cluster; the emitter of the second upper-bridge IGBT chip is connected to the anode of the second upper-bridge FRD chip via a second bonding wire cluster; and the emitter of the third upper-bridge IGBT chip is connected to the anode of the third upper-bridge FRD chip via a third bonding wire cluster.

[0010] Furthermore, the upper bridge circuit has a gate signal and a gate signal return line. The gate signal lead of the upper bridge circuit is connected to the upper bridge gate signal terminal of the upper bridge circuit through a bonding wire and the upper copper layer of the first ceramic copper-clad substrate. The gate signal return line of the upper bridge circuit is connected to the upper bridge gate return line terminal of the upper bridge circuit.

[0011] Furthermore, a voltage signal is applied between the upper bridge gate signal terminal and the upper bridge gate return terminal to control the upper bridge circuit to turn on or off.

[0012] Furthermore, the gate signal return line of the upper bridge circuit is connected to the upper bridge gate return line terminal through the upper copper layer of the first ceramic copper-clad substrate and bonding wires; or the gate signal return line of the upper bridge circuit is directly led out from the emitter of the third upper bridge IGBT chip of the upper bridge circuit and connected to the upper bridge gate return line terminal.

[0013] Furthermore, the downbridge circuit includes a first downbridge IGBT chip, a second downbridge IGBT chip, a third downbridge IGBT chip, a first downbridge FRD chip, a second downbridge FRD chip, and a third downbridge FRD chip; the collectors of the first downbridge IGBT chip, the second downbridge IGBT chip, and the third downbridge IGBT chip are connected to the cathodes of the first downbridge FRD chip, the second downbridge FRD chip, and the third downbridge FRD chip through the upper copper layer of the second ceramic copper-clad substrate;

[0014] The emitters of the first, second, and third lower-bridge IGBT chips are connected to the anodes of the corresponding first, second, and third lower-bridge FRD chips.

[0015] Furthermore, the emitter of the first lower-bridge IGBT chip is connected to the anode of the first lower-bridge FRD chip via a fourth bonding wire cluster; the emitter of the second lower-bridge IGBT chip is connected to the anode of the second lower-bridge FRD chip via a fifth bonding wire cluster; and the emitter of the third lower-bridge IGBT chip is connected to the anode of the third lower-bridge FRD chip via a sixth bonding wire cluster.

[0016] Furthermore, the lower bridge circuit has a gate signal and a gate signal return line. The gate signal lead of the lower bridge circuit is connected to the lower bridge gate signal terminal of the lower bridge circuit through a bonding wire and the upper copper layer of the second ceramic copper-clad substrate. The gate signal return line of the lower bridge circuit is connected to the lower bridge gate return line terminal of the lower bridge circuit through the upper copper layer of the second ceramic copper-clad substrate and the bonding wire. A voltage signal is applied between the lower bridge gate signal terminal and the lower bridge gate return line terminal to control the lower bridge circuit to turn on or off.

[0017] Beneficial effects: Compared with the prior art, the significant effects of the present invention are as follows: (1) By adjusting the welding of four ceramic copper-clad substrates on one substrate to welding two ceramic copper-clad substrates on one substrate, and correspondingly adjusting the position of the power terminal solder pins, the traditional parallel connection of four small chips is transformed into the parallel connection of three large chips; (2) The distance between parallel chips is greater (the distance between IGBT chips can reach more than 8mm; the distance between FRD chips can reach more than 8mm), the thermal coupling between chips is smaller, which is beneficial to chip heat dissipation; (3) Through the above layout, the upper bridge or lower bridge circuit is changed from being set on two small ceramic copper-clad substrates to being set on one large ceramic copper-clad substrate, the internal space utilization of the device is higher, and the area of ​​IGBT chip and FRD chip is larger (the area of ​​IGBT chip in the traditional design is 100mm²). 2 The FRD chip area is approximately 90mm². 2 Left and right, the total area of ​​the IGBT after the four chips are connected in parallel is 400mm². 2 This solution supports IGBT chips exceeding 200mm². 2 The total area of ​​the IGBT after the three chips are connected in parallel is 600 mm². 2 The FRD chip area exceeds 360mm². 2 Overall, the IGBT chip area increased more, while the FRD chip area increased less or slightly. The IGBT chip size reached 16.5*12mm, and the FRD chip size reached 10*12mm. The chip thermal resistance was lower, and the chip temperature rise was lower under the same power. (4) Through the circuit design on the ceramic copper-clad substrate, the current path of the three chips was more consistent. When the chips were turned on or off, the electrical stress borne by each chip was more consistent, which was conducive to improving the reliability of the module. (5) Increasing the area of ​​a single chip also increased the distance between the chips. Both of these measures can reduce heat generation. Attached Figure Description

[0018] Figure 1 A 3D structural diagram of an existing multi-chip parallel half-bridge IGBT device;

[0019] Figure 2 for Figure 1 Layout diagram of the chip;

[0020] Figure 3 This is a schematic diagram of the structure of Embodiment 1 of the present invention;

[0021] Figure 4 This is a schematic diagram of the structure of Embodiment 2 of the present invention. Detailed Implementation

[0022] The technical solution of the present invention will now be described in detail with reference to specific embodiments and accompanying drawings.

[0023] Example 1

[0024] like Figure 3 As shown, a multi-chip parallel half-bridge IGBT device of the present invention includes the following components: common emitter C2E1 power terminal 1, lower bridge emitter E2 power terminal 2, upper bridge collector C1 power terminal 3, upper bridge gate signal terminal 4, upper bridge gate return terminal 5, lower bridge gate signal terminal 6, lower bridge gate return terminal 7, first ceramic copper-clad substrate 81, second ceramic copper-clad substrate 82, substrate 9, first upper bridge IGBT chip 101, second upper bridge IGBT chip 102, third upper bridge IGBT chip 103, and so on. First upper bridge FRD chip 111, second upper bridge FRD chip 112, third upper bridge FRD chip 113, first bonding wire cluster 121, second bonding wire cluster 122, third bonding wire cluster 123, first lower bridge IGBT chip 131, second lower bridge IGBT chip 132, third lower bridge IGBT chip 133, first lower bridge FRD chip 141, second lower bridge FRD chip 142, third lower bridge FRD chip 143, fourth bonding wire cluster 151, fifth bonding wire cluster 152, sixth bonding wire cluster 153.

[0025] A first ceramic copper-clad substrate 81 and a second ceramic copper-clad substrate 82 are arranged side-by-side in the center of substrate 9, and are soldered to substrate 9. An upper bridge circuit is disposed on the first ceramic copper-clad substrate 81, and a lower bridge circuit is disposed on the second ceramic copper-clad substrate 82. Both the upper and lower bridge circuits include three sets of chips connected in parallel, each set including one IGBT chip and one FRD chip. The current-carrying paths of each set of chips in the upper and lower bridge circuits are identical, resulting in more consistent electrical stress on each chip during turn-on or turn-off, which improves module reliability.

[0026] The upper-bridge circuit includes a first upper-bridge IGBT chip 101, a second upper-bridge IGBT chip 102, a third upper-bridge IGBT chip 103, a first upper-bridge FRD chip 111, a second upper-bridge FRD chip 112, and a third upper-bridge FRD chip 113 soldered onto a first ceramic copper-clad substrate 81. The collectors of the first upper-bridge IGBT chips 101, 102, and 103 are connected to the cathodes of the first upper-bridge FRD chips 111, 112, and 113 through the upper copper layer of the first ceramic copper-clad substrate 81. The emitters of the first upper-bridge IGBT chip 101, the second upper-bridge IGBT chip 102, and the third upper-bridge IGBT chip 103 are connected to the anodes of the corresponding first upper-bridge FRD chips 111, 112, and 113. In this embodiment, the emitter of the first upper-bridge IGBT chip 101 is connected to the anode of the first upper-bridge FRD chip 111 via a first bonding wire bundle 121. The emitter of the second upper-bridge IGBT chip 102 is connected to the anode of the second upper-bridge FRD chip 112 via a second bonding wire bundle 122. The emitter of the third upper-bridge IGBT chip 103 is connected to the anode of the third upper-bridge FRD chip 113 via a third bonding wire bundle 123. This method achieves anti-parallel connection between the upper-bridge IGBT chips and the upper-bridge FRD chips.

[0027] The upper bridge circuit has a gate signal and a gate signal return line. The gate signal lead of the upper bridge circuit is connected to the upper bridge gate signal terminal 4 of the upper bridge circuit via a bonding wire and the upper copper layer of the first ceramic copper-clad substrate 81. The gate signal return line of the upper bridge circuit is connected to the upper bridge gate return line terminal 5 of the upper bridge circuit via the upper copper layer of the first ceramic copper-clad substrate 81 and a bonding wire. The upper bridge circuit is turned on or off by applying a voltage signal between the upper bridge gate signal terminal 4 and the upper bridge gate return line terminal 5.

[0028] Similarly, the lower-bridge circuit includes a first lower-bridge IGBT chip 131, a second lower-bridge IGBT chip 132, a third lower-bridge IGBT chip 133, a first lower-bridge FRD chip 141, a second lower-bridge FRD chip 142, and a third lower-bridge FRD chip 143 soldered onto the second ceramic copper-clad substrate 83. The collectors of the first lower-bridge IGBT chip 131, the second lower-bridge IGBT chip 132, and the third lower-bridge IGBT chip 133 are connected to the cathodes of the first lower-bridge FRD chip 141, the second lower-bridge FRD chip 142, and the third lower-bridge FRD chip 143 through the upper copper layer of the second ceramic copper-clad substrate 82. The emitters of the first lower-bridge IGBT chip 131, the second lower-bridge IGBT chip 132, and the third lower-bridge IGBT chip 133 are connected to the anodes of the corresponding first lower-bridge FRD chips 141, 142, and 143, respectively. In this embodiment, the emitter of the first lower-bridge IGBT chip 131 is connected to the anode of the first lower-bridge FRD chip 141 via a fourth bonding wire bundle 151. The emitter of the second lower-bridge IGBT chip 132 is connected to the anode of the second lower-bridge FRD chip 142 via a fifth bonding wire bundle 152. The emitter of the third lower-bridge IGBT chip 133 is connected to the anode of the third lower-bridge FRD chip 143 via a sixth bonding wire bundle 153. This method achieves anti-parallel connection of the lower-bridge IGBT chips and lower-bridge FRD chips.

[0029] The lower-bridge circuit has a gate signal and a gate signal return line. The gate signal lead of the lower-bridge circuit is connected to the lower-bridge gate signal terminal 6 of the lower-bridge circuit via a bonding wire and the upper copper layer of the second ceramic copper-clad substrate 82. The gate signal return line of the lower-bridge circuit is connected to the lower-bridge gate return line terminal 7 of the lower-bridge circuit via the upper copper layer of the second ceramic copper-clad substrate 82 and a bonding wire. The lower-bridge circuit is turned on or off by applying a voltage signal between the lower-bridge gate signal terminal 6 and the lower-bridge gate return line terminal 7.

[0030] Taking the bridge as an example, after the ceramic copper-clad substrate is reflow soldered to the substrate, it will undergo a certain offset and rotation. In traditional layouts, a certain distance needs to be maintained between the ceramic copper-clad substrates 81 and 82 to meet manufacturability requirements, such as... Figure 2 As shown; the present invention combines the above-mentioned ceramic copper-clad substrates 81 and 82 into a single ceramic copper-clad substrate, resulting in higher space utilization, as shown. Figure 3 As shown.

[0031] In this invention, the traditional method of soldering four ceramic copper-clad substrates onto one substrate is changed to soldering two ceramic copper-clad substrates onto one substrate. The upper bridge circuit and the lower bridge circuit are each arranged on one ceramic copper-clad substrate. The positions of the power terminals are adjusted, and the distance between parallel chips is increased, changing the traditional four-chip parallel connection to a three-chip parallel connection. At the same time, through the circuit design on the ceramic copper-clad substrate, the current path of the three chips is more consistent.

[0032] Example 2

[0033] like Figure 4 As shown, the difference between this embodiment and embodiment 1 is that in this embodiment, the gate signal loop of the upper bridge circuit is directly led out from the emitter of the third upper bridge IGBT chip 103 of the upper bridge circuit, and then connected to the upper bridge gate loop terminal 5, thereby shortening the gate signal loop path length, which is beneficial to reduce the parasitic inductance of the signal loop, and further accelerates the turn-on speed of the upper bridge circuit, thereby reducing the switching loss of the chip turn-on and improving the working efficiency of the device.

Claims

1. A multi-chip parallel half-bridge IGBT device, characterized in that: The system includes a substrate (9), on which a first ceramic copper-clad substrate (81) and a second ceramic copper-clad substrate (82) are arranged in parallel. An upper bridge circuit is arranged on the first ceramic copper-clad substrate (81), and a lower bridge circuit is arranged on the second ceramic copper-clad substrate (82). Both the upper bridge circuit and the lower bridge circuit include multiple sets of chips connected in parallel. Each set of chips includes an IGBT chip and an FRD chip.

2. The multi-chip parallel half-bridge IGBT device according to claim 1, characterized in that: Both the upper bridge circuit and the lower bridge circuit include three sets of chips, and the current path of each set of chips is the same.

3. The multi-chip parallel half-bridge IGBT device according to claim 1, characterized in that: The bridge circuit includes a first bridge IGBT chip (101), a second bridge IGBT chip (102), a third bridge IGBT chip (103), a first bridge FRD chip (111), a second bridge FRD chip (112), and a third bridge FRD chip (113); The collectors of the first upper-bridge IGBT chip (101), the second upper-bridge IGBT chip (102), and the third upper-bridge IGBT chip (103) are connected to the cathodes of the first upper-bridge FRD chip (111), the second upper-bridge FRD chip (112), and the third upper-bridge FRD chip (113) through the upper copper layer of the first ceramic copper-clad substrate (81). The emitters of the first upper-bridge IGBT chip (101), the second upper-bridge IGBT chip (102), and the third upper-bridge IGBT chip (103) are connected to the anodes of the corresponding first upper-bridge FRD chip (111), the second upper-bridge FRD chip (112), and the third upper-bridge FRD chip (113).

4. The multi-chip parallel half-bridge IGBT device according to claim 3, characterized in that: The emitter of the first upper-bridge IGBT chip (101) is connected to the anode of the first upper-bridge FRD chip (111) through a first bonding wire cluster (121); The emitter of the second upper-bridge IGBT chip (102) and the anode of the second upper-bridge FRD chip (112) are connected by a second bonding wire cluster (122); The emitter of the third upper-bridge IGBT chip (103) and the anode of the third upper-bridge FRD chip (113) are connected by a third bonding wire cluster (123).

5. The multi-chip parallel half-bridge IGBT device according to claim 1, characterized in that: The upper bridge circuit has a gate signal and a gate signal return line. The gate signal lead of the upper bridge circuit is connected to the upper bridge gate level signal terminal (4) of the upper bridge circuit through a bonding wire and the upper copper layer of the first ceramic copper-clad substrate (81). The gate signal return line of the upper bridge circuit is connected to the upper bridge gate level return line terminal (5) of the upper bridge circuit.

6. The multi-chip parallel half-bridge IGBT device according to claim 5, characterized in that: A voltage signal is applied between the upper bridge gate signal terminal (4) and the upper bridge gate return terminal (5) to control the upper bridge circuit to turn on or off.

7. The multi-chip parallel half-bridge IGBT device according to claim 5, characterized in that: The gate signal return line of the upper bridge circuit is connected to the upper bridge gate level return line terminal (5) through the upper copper layer and bonding wire of the first ceramic copper-clad substrate (81); or the gate signal return line of the upper bridge circuit is directly led out from the emitter of the third upper bridge IGBT chip (103) of the upper bridge circuit and connected to the upper bridge gate level return line terminal (5).

8. The multi-chip parallel half-bridge IGBT device according to claim 1, characterized in that: The downbridge circuit includes a first downbridge IGBT chip (131), a second downbridge IGBT chip (132), a third downbridge IGBT chip (133), a first downbridge FRD chip (141), a second downbridge FRD chip (142), and a third downbridge FRD chip (143); The collectors of the first lower-bridge IGBT chip (131), the second lower-bridge IGBT chip (132), and the third lower-bridge IGBT chip (133) are connected to the cathodes of the first lower-bridge FRD chip (141), the second lower-bridge FRD chip (142), and the third lower-bridge FRD chip (143) through the upper copper layer of the second ceramic copper-clad substrate (82). The emitters of the first lower-bridge IGBT chip (131), the second lower-bridge IGBT chip (132), and the third lower-bridge IGBT chip (133) are connected to the anodes of the corresponding first lower-bridge FRD chip (141), the second lower-bridge FRD chip (142), and the third lower-bridge FRD chip (143).

9. The multi-chip parallel half-bridge IGBT device according to claim 8, characterized in that: The emitter of the first lower-bridge IGBT chip (131) is connected to the anode of the first lower-bridge FRD chip (141) through a fourth bonding wire cluster (151); The emitter of the second lower-bridge IGBT chip (132) is connected to the anode of the second lower-bridge FRD chip (142) through a fifth bonding wire cluster (152); The emitter of the third lower-bridge IGBT chip (133) and the anode of the third lower-bridge FRD chip (143) are connected by a sixth bonding wire cluster (153).

10. The multi-chip parallel half-bridge IGBT device according to claim 1, characterized in that: The lower bridge circuit has a gate signal and a gate signal return line. The gate signal lead of the lower bridge circuit is connected to the lower bridge gate signal terminal (6) of the lower bridge circuit through a bonding wire and the upper copper layer of the second ceramic copper-clad substrate (82). The gate signal return line of the lower bridge circuit is connected to the lower bridge gate return line terminal (7) of the lower bridge circuit through the upper copper layer of the second ceramic copper-clad substrate (82) and a bonding wire. A voltage signal is applied between the lower bridge gate signal terminal (6) and the lower bridge gate return terminal (7) to control the lower bridge circuit to turn on or off.

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