Super-junction MOSFET electrostatic protection device, super-junction MOSFET and preparation method of super-junction MOSFET

Abstract

The invention discloses a super-junction MOSFET electrostatic protection device, a super-junction MOSFET and a preparation method of the super-junction MOSFET. The electrostatic protection device comprises a leading unit and a breakdown drainage unit, the breakdown drainage unit comprises a gate-drain breakdown drainage unit and a gate-source breakdown drainage unit; the leading unit is used for leading in impact current; the gate-drain breakdown drainage unit is used for introducing the introduced impact current into the epitaxial region and enabling the impact current to flow to the drain end through the substrate; and the gate-source breakdown drainage unit is used for introducing the introduced impact current into the source end injection region and enabling the introduced impact current to flow to the source end, so that the connection unit and the breakdown drainage unit form current discharge channels between the gate end and the drain end and between the gate end and the source end. The method can be implemented in the preparation process of the super-junction MOSFET, an extra ESD single tube is not needed, the implementation cost of ESD protection is reduced, any modification on a drain terminal is avoided, the self voltage resistance characteristic is not influenced, and the original high breakdown voltage is maintained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and particularly relates to a super-junction MOSFET electrostatic protection device, a super-junction MOSFET and a preparation method. BACKGROUND

[0002] A super-junction MOSFET (Super Junction MOSFET) is a high-voltage power semiconductor device based on the principle of charge compensation. The core structure of the super-junction MOSFET is composed of P-type and N-type doped columns arranged alternately. Compared with a traditional planar MOSFET, the structure realizes the coordinated improvement of on-resistance R_DS (on) and breakdown voltage (BV) through the optimization of a lateral electric field, and breaks through the theoretical limit between on-resistance and voltage resistance capability of a traditional silicon-based device. Although the super-junction MOSFET has excellent performance, the reliability of the super-junction MOSFET still faces great challenges, and the reliability problem still restricts high-end applications. For example, dynamic avalanche failure, hot carrier injection (HCI), packaging thermal resistance and electrostatic damage in the packaging storage and transportation assembly process.

[0003] The super-junction MOSFET static damage problem widely exists in packaging, storage, transportation and assembly processes. For example, due to the high-density doping column structure and the thin gate oxide layer (usually 50-100 nm) characteristics of the super-junction MOSFET, the device is at risk of ESD (electrostatic discharge) during packaging. The friction between the packaging equipment and the metal frame can generate an electrostatic voltage of >8kV, which can cause the gate oxide layer to break down if directly acting on the device pin (the breakdown voltage is usually 15-30V, which is much lower than the ESD transient voltage). Experimental data show that the ESD damage rate of the packaging process can reach 0.5%-1.2% without protective measures. In addition, the super-junction MOSFET is prone to accumulate static electricity during storage and transportation due to environmental humidity fluctuations (such as the probability of static electricity generation increases by 3 times when the humidity is <40%) and the friction of packaging materials. Tests show that the friction of ordinary plastic transport boxes can generate 6-12kV static electricity, increasing the risk of failure of unshielded devices. Finally, ESD events are easily caused by human operation and equipment contact during the assembly process. Data show that the human body static voltage can reach 3-5kV when the operator is not grounded, and a peak discharge current of >10A can be generated when the device pin is contacted, which can cause the gate-source short circuit of the super-junction MOSFET. Since the super-junction MOSFET is generally expensive, the protective measures of the formal installation product must meet the high-level requirements of IEC61340-5-1 (electrostatic control standard) and JEDEC JESD625-A (device handling specification). However, the gate of the natural super-junction MOSFET is an oxide or composite oxide medium layer, even if a high-k gate medium (such as Al2O3 / HfO2 stack) is prepared by atomic layer deposition (ALD) process, the breakdown field strength is increased from 1.0V / nm of traditional SiO2 to 1.5V / nm, which can also easily cause the gate oxide layer to break down (the ESD transient voltage is 8kV, and the gate medium breakdown voltage is in the tens of volts).

[0004] Currently, for the above-mentioned static damage problem of the super-junction MOSFET, the ESD single tube is added at the chip port during packaging to prevent static electricity; or a diode is constructed in the polycrystalline structure in the same wafer to realize the ESD protection function; or the drain end is improved.

[0005] For the above-mentioned way to overcome static damage, additional packaging processes and costs are required, which affects the performance of the device, and also cannot avoid the static damage in the subsequent packaging stage, storage, transportation and assembly processes. SUMMARY

[0006] The purpose of the present application is to provide a super-junction MOSFET static protection device, a super-junction MOSFET and a preparation method, so as to solve the high cost and performance damage problem caused by additional process overhead in the prior art super-junction MOSFET static protection measures.

[0007] To achieve the above object, the application provides the following scheme.

[0008] In a first aspect, the application provides a super-junction MOSFET electrostatic protection device, which is integrated in a super-junction MOSFET and comprises:

[0009] a lead-in unit and a breakdown current lead-in unit;

[0010] The breakdown current lead-in unit comprises a gate-drain breakdown current lead-in unit integrated between the gate end and the drain end of the super-junction MOSFET and a gate-source breakdown current lead-in unit integrated between the gate end and the source end of the super-junction MOSFET, one end of the lead-in unit is electrically connected to the gate end of the super-junction MOSFET, and the other end is connected in series with the gate-drain breakdown current lead-in unit and the gate-source breakdown current lead-in unit, respectively.

[0011] The lead-in unit is used to lead in the impact current of the gate end of the super-junction MOSFET, the gate-drain breakdown current lead-in unit is used to lead in the impact current led in by the lead-in unit into the epitaxial region of the super-junction MOSFET and flow to the drain end through the substrate, and the gate-source breakdown current lead-in unit is used to lead in the impact current led in by the lead-in unit into the source end implantation region of the super-junction MOSFET and flow to the source end, so that the lead-in unit and the breakdown current lead-in unit form a current discharge channel between the gate end and the drain end and between the gate end and the source end.

[0012] In some implementations of the first aspect, the discharge unit comprises a gate-drain charge discharge unit integrated between the gate end and the drain end of the super-junction MOSFET and a gate-source charge discharge unit integrated between the gate end and the source end of the super-junction MOSFET.

[0013] The gate-drain charge discharge unit is connected in parallel with the series circuit of the gate-drain breakdown current lead-in unit and the lead-in unit, and the gate-source charge discharge unit is connected in parallel with the series circuit of the gate-source breakdown current lead-in unit and the lead-in unit.

[0014] The gate-drain charge discharge unit is used to discharge large current between the gate end and the drain end, and the gate-source charge discharge unit is used to discharge large current between the gate end and the source end.

[0015] In some implementations of the first aspect, the diffusion region of the super-junction MOSFET is provided with an implantation region, and the implantation region and a functional region of the super-junction MOSFET constitute the lead-in unit, the breakdown current lead-in unit and the discharge unit.

[0016] In some implementations of the first aspect, the implantation region comprises a lead-in implantation region and a breakdown current lead-in implantation region, the lead-in implantation region is in contact with the gate polysilicon 010 of the super-junction MOSFET, and the breakdown current lead-in implantation region is in an electrically floating state.

[0017] The punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the epitaxial region of the super-junction MOSFET constitute the gate-drain breakdown current drain unit;

[0018] The punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the epitaxial region of the super-junction MOSFET constitute the gate-drain breakdown current drain unit;

[0019] The punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the source injection region of the super-junction MOSFET constitute the gate-source breakdown current drain unit;

[0020] The punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the epitaxial region of the super-junction MOSFET constitute the gate-drain charge drain unit;

[0021] The punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the source injection region of the super-junction MOSFET constitute the gate-source charge drain unit.

[0022] In some implementations of the first aspect, the punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the source injection region of the super-junction MOSFET constitute the gate-source breakdown current drain unit;

[0023] The projection area of the punchthrough drain injection region is located between the punchthrough drain injection region and the source injection region, and the punchthrough drain injection region, the punchthrough drain injection region, and the source injection region are not in contact with each other.

[0024] In some implementations of the first aspect, the punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the source injection region of the super-junction MOSFET constitute the gate-source breakdown current drain unit;

[0025] The drain of the punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the source injection region of the super-junction MOSFET constitute the gate-source breakdown current drain unit;

[0026] The drain of the punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the source injection region of the super-junction MOSFET constitute the gate-source breakdown current drain unit;

[0027] The drain of the punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the source injection region of the super-junction MOSFET constitute the gate-source breakdown current drain unit.

[0028] In some implementations of the first aspect, the punchthrough drain injection region, the diffusion region of the super-junction MOSFET, and the source injection region of the super-junction MOSFET constitute the gate-source breakdown current drain unit;

[0029] The drain of the gate-drain high current charge leakage transistor is connected to the gate of the super junction MOSFET, and the source of the gate-drain high current charge leakage transistor is connected to the drain of the super junction MOSFET.

[0030] The drain of the gate-source auxiliary current charge leakage transistor is connected to the gate of the super junction MOSFET, and the source of the gate-drain high current charge leakage transistor is connected to the source of the super junction MOSFET.

[0031] In some implementations of the first aspect, the injection region, the breakdown current injection region, and the diffusion region of the super junction MOSFET constitute the injection transistor.

[0032] The breakdown current injection region, the diffusion region of the super junction MOSFET, and the epitaxial region of the super junction MOSFET constitute the gate-drain breakdown current injection transistor.

[0033] The breakdown current injection region, the diffusion region of the super junction MOSFET, and the source injection region of the super junction MOSFET constitute the gate-source breakdown current injection transistor.

[0034] The injection region, the diffusion region of the super junction MOSFET, and the source injection region of the super junction MOSFET constitute the gate-source auxiliary current charge leakage transistor.

[0035] In the second aspect, the application provides a super junction MOSFET, comprising:

[0036] A semiconductor substrate, an epitaxial layer, a gate structure layer, and a metal electrode layer.

[0037] The epitaxial layer is provided with a columnar region, and an injection region is provided in a diffusion region on the columnar region, which cooperates with each functional region of the super junction MOSFET to constitute the super junction MOSFET electrostatic protection device as described in the first aspect.

[0038] In the third aspect, the application provides a manufacturing method of a super junction MOSFET, comprising:

[0039] Generating an epitaxial layer on a substrate;

[0040] Forming a columnar region on the epitaxial layer;

[0041] Forming a gate structure on the epitaxial layer and the columnar region of the super structure;

[0042] Forming a shallow doped drain on the other side of the substrate;

[0043] Contacting and heavily doping the diffusion region in the epitaxial layer between the gate structures to form an injection region;

[0044] Packaging the above structure.

[0045] According to the specific embodiments provided in the present application, the following technical effects are disclosed:

[0046] The present application provides a super-junction MOSFET electrostatic protection device, a super-junction MOSFET and a preparation method. A gate-drain breakdown current leading unit is integrated between the gate end and the drain end of the super-junction MOSFET, and a gate-source breakdown current leading unit is integrated between the gate end and the source end of the super-junction MOSFET, so as to build a discharge channel between the gate end and the source end and between the gate end and the drain end of the super-junction MOSFET, and form a full-terminal electrostatic protection device integrated in the super-junction MOSFET. The discharge channel remains silent when there is no ESD impact, and forms an effective discharge channel to discharge ESD charges when ESD impact occurs. That is, the leading unit is used to introduce impact current to the gate end of the super-junction MOSFET; the gate-drain breakdown current leading unit is used to introduce the impact current introduced by the leading unit into the epitaxial region of the super-junction MOSFET, and flow to the drain end through the substrate; and the gate-source breakdown current leading unit is used to introduce the impact current introduced by the leading unit into the source end injection region of the super-junction MOSFET, and flow to the source end. The leading unit and the breakdown current leading unit form a current discharge channel between the gate end and the drain end and between the gate end and the source end in the super-junction MOSFET. The leading unit and the breakdown current leading unit are integrated in the super-junction MOSFET, that is, a discharge channel is built between the gate end and the source end and between the gate end and the drain end of the super-junction MOSFET. Compared with the prior art method of adding an ESD single tube at the chip port during packaging, the electrostatic protection device can be implemented simultaneously during the preparation of the super-junction MOSFET, without the need for additional ESD single tubes, thereby reducing the implementation cost of ESD protection. Compared with the prior art method of implementing ESD function in the same wafer in the polycrystal, the present application is compatible with the super-junction MOSFET process, does not require additional process overhead, and ensures process yield. Finally, compared with the prior art method of modifying the drain end, the present application avoids any modification of the drain end, does not affect the withstand voltage characteristics of the super-junction MOSFET, and maintains the original high breakdown voltage of the super-junction MOSFET. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creating any inventive labor.

[0048] Figure 1 It is a structural schematic diagram of a classic super-junction MOSFET.

[0049] Figure 2 It is a three-dimensional structural schematic diagram of a classic super-junction MOSFET.

[0050] Figure 3 Three-dimensional view of the top of a classic super-junction MOSFET;

[0051] Figure 4 Three-dimensional view of the bottom of a classic super-junction MOSFET;

[0052] Figure 5 Three-dimensional view of the structure of a super-junction MOSFET according to some embodiments of the application;

[0053] Figure 6 Three-dimensional view of the top of a super-junction MOSFET according to embodiments of the application;

[0054] Figure 7 Three-dimensional view of the bottom of a super-junction MOSFET according to embodiments of the application;

[0055] Figure 8 Designation of the section C1 and two-dimensional view (YZ plane) of the section C1 according to embodiments of the application;

[0056] Figure 9 Designation of the sections C2, C3, C4, C5 according to embodiments of the application;

[0057] Figure 10 Two-dimensional view (XZ plane) of the section C2 according to embodiments of the application;

[0058] Figure 11 Two-dimensional view (XZ plane) of the section C3 according to embodiments of the application;

[0059] Figure 12 Two-dimensional view (XY plane) of the section C4 according to embodiments of the application;

[0060] Figure 13 Two-dimensional view (XY plane) of the section C5 according to embodiments of the application;

[0061] Figure 14 Equivalent circuit diagram according to embodiments of the application;

[0062] Figure 15 Schematic view of the implementation of the full-terminal protection according to embodiments of the application;

[0063] Figure 16 Transfer curve of a super-junction MOSFET according to embodiments of the application compared with a classic super-junction MOSFET;

[0064] Figure 17 IDVD curve of a super-junction MOSFET according to embodiments of the application compared with a classic super-junction MOSFET;

[0065] Figure 18 Breakdown curves for embodiments of the present application as compared to a classical super-junction MOSFET;

[0066] Figure 19 Breakdown phase electric field distribution for some embodiments of the present application;

[0067] Figure 20 Breakdown phase potential distribution for some embodiments of the present application;

[0068] Figure 21 Current distribution during the discharge process for embodiments of the present application;

[0069] Figure 22 Discharge curve for embodiments of the present application;

[0070] Figure 23 Process flow for embodiments of the present application.

[0071] BRIEF DESCRIPTION OF DRAWINGS

[0072] 001 - N-type epitaxial substrate boundary;

[0073] 002 - N-type epitaxial P-type pillar junction;

[0074] 003 - P-type pillar region;

[0075] 004 - N-type epitaxial region;

[0076] 005 - N-type access implant region;

[0077] 006 - N-type source end implant region;

[0078] 007 - N-type breakdown access implant region;

[0079] 008 - gate isolation dielectric;

[0080] 009 - sidewall isolation dielectric;

[0081] 010 - gate polysilicon;

[0082] 011 - P-type diffusion region;

[0083] 012 - N-type epitaxial P-type diffusion junction;

[0084] 021 - access transistor;

[0085] 022 - gate-drain breakdown access transistor;

[0086] 023 - gate-drain high current charge discharge flow transistor;

[0087] 024 - gate-drain terminal to terminal electrostatic protection unit;

[0088] 025 - Gate-source breakdown induced drain transistor;

[0089] 026 - Gate-source auxiliary current charge drain transistor;

[0090] 027 - Gate-source terminal electrostatic protection unit;

[0091] 028 - Protected super-junction MOSFET;

[0092] 029 - Intrinsic parasitic transistor of protected super-junction MOSFET;

[0093] 031 - Gate-drain terminal electrostatic shock path;

[0094] 032 - Gate-source terminal electrostatic shock path;

[0095] 033 - Drain-source terminal electrostatic shock path;

[0096] 041 - First equipotential line characterizing the potential distribution;

[0097] 042 - Second equipotential line characterizing the potential distribution;

[0098] 043 - Third equipotential line characterizing the potential distribution;

[0099] 051 - Equipotential line characterizing the electric field distribution;

[0100] 052 - First extreme high value position of the electric field distribution;

[0101] 053 - Second extreme high value position of the electric field distribution;

[0102] 061 - First equipotential current density line characterizing the current distribution;

[0103] 062 - Second equipotential current density line characterizing the current distribution;

[0104] 063 - Third equipotential current density line characterizing the current distribution;

[0105] 064 - Current path during the discharge process. DETAILED DESCRIPTION

[0106] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0107] The above objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings and specific embodiments.

[0108] It can be understood that, Figure 1 The structure of the super-junction MOSFET of N-type conductivity is shown in the schematic diagram. Figure 2 The structure of the classic super-junction MOSFET is shown in the three-dimensional schematic diagram, Figure 3 The structure of the classic super-junction MOSFET is shown in the three-dimensional schematic diagram, Figure 4 The structure of the classic super-junction MOSFET is shown in the three-dimensional schematic diagram.

[0109] The following will be described in conjunction with Figures 1 to 4 The structure of the classic super-junction MOSFET will be described in conjunction with the N-type conductivity.

[0110] As shown in Figures 1 to 4 001 is the N-type epitaxial substrate boundary. Below the N-type epitaxial substrate boundary 001 is a low or ultra-low resistivity <100> crystal direction N-type substrate, which serves as a drain conductive and mechanical support; above the N-type epitaxial substrate boundary 001 is an electrical functional area.

[0111] The N-type epitaxial P-type column junction, i.e. the N-type epitaxial P-type column junction 002, is formed by a gradually changing PN junction, one side of which is a P-type column region 003 and the other side is an N-type epitaxial region 004.

[0112] The P-type column region 003 has a doping concentration in the range of 2E15 to 1E16 (a typical value is 8E15), and is prepared by a multi-layer epitaxial repeated implantation or a deep trench filling process. In the classic super-junction MOSFET, it serves as a charge balancing function to achieve high conductivity and high voltage resistance.

[0113] The N-type epitaxial region 004 has a doping concentration in the range of 2E15 to 1E16 (a typical value is 4E15), and can be grown from a low or ultra-low resistivity <100> crystal direction N-type substrate, which is also <100>. In the classic super-junction MOSFET, it is a longitudinal conductive channel, and in a high voltage state, it is depleted to achieve high conductivity and high voltage resistance.

[0114] The N-type source end implantation region 006 has a doping concentration in the range of 5E18 to 1E20 (a typical value is 1E19), and in the classic super-junction MOSFET, it serves as a source and as one end of an electrical path.

[0115] The gate isolation medium 008 is located below the gate polysilicon 010, and in the classic super-junction MOSFET, it controls the opening and closing of the lateral conductive channel together with the gate polysilicon 010 by using the MIS effect.

[0116] Side wall isolation medium 009. Located at the side of gate polysilicon 010, used to suppress hot carrier effect in classic super junction MOSFET, to enhance the classic super junction MOSFET hot carrier reliability function.

[0117] Gate polysilicon 010, formed by self-aligned process using highly doped N-type polysilicon (typical value is 1E20). In classic super junction MOSFET as a gate, using MIS effect to control the opening and closing of the lateral conduction channel. Finally through two or more than two layers of metal lead to form the entire chip gate control terminal.

[0118] P-type diffusion region 011 is formed by implantation diffusion or active diffusion process, which is distributed in the top P-type region of the epitaxial layer. In classic super junction MOSFET as a channel region doping modulation threshold voltage. N-type epitaxial P-type diffusion region junction 012 is a gradual PN junction formed by 004 and 011.

[0119] In Figures 1 to 7 The three-dimensional schematic diagram, P-type diffusion region 011 and N-type epitaxial P-type diffusion region junction 012 are not convenient to mark in the figure, which will be further marked and explained in the subsequent cross-sectional schematic diagram.

[0120] It can be understood that the N-type epitaxial substrate boundary 001, the N-type epitaxial P-type column junction 002, the P-type column region 003, the N-type epitaxial region 004, the N-type source end implantation region 006, the gate isolation medium 008, the side wall isolation medium 009, and the gate polysilicon 010 in the above-mentioned figures all belong to the structural features of the classic super junction MOSFET, and are used to build the classic super junction MOSFET structure and complete the basic functions of the classic super junction MOSFET.

[0121] It can be understood that, in the embodiment of the present application, in order to overcome the disadvantages and limitations of the electrostatic protection structure of the super junction MOSFET in the related art, a corresponding unit structure is integrated in the super junction MOSFET to construct a discharge channel between the gate end-source end and the gate end-drain end, that is, the lead-in unit and the breakdown current lead-in unit are integrated in the super junction MOSFET, thereby forming a full-terminal electrostatic protection device integrated in the super junction MOSFET. The discharge channel remains silent when there is no ESD impact, and forms an effective discharge channel to discharge ESD charge when ESD impact occurs.

[0122] In order to better understand the super junction MOSFET electrostatic protection device provided by the embodiment of the present application, the structure schematic diagram of the above-mentioned electrostatic super junction MOSFET will be compared and described in detail below in conjunction with the drawings.

[0123] As illustrated by the cross-sectional view, how to form the unique lead-in unit, breakdown current lead-in unit, and charge discharge unit of the present application, as well as the connection mode between the related units, is illustrated.

[0124] That is, in the embodiments of the present application, a discharge channel is constructed between the gate end-source end and the gate end-drain end, which remains silent when there is no ESD impact and forms an effective discharge channel to discharge ESD charges when ESD impact occurs.

[0125] The constructed discharge channel can include a lead-in unit and a breakdown drainage unit.

[0126] The breakdown drainage unit includes a gate-drain breakdown drainage unit integrated between the gate end-drain end of the super-junction MOSFET, and a gate-source breakdown drainage unit integrated between the gate end-source end of the super-junction MOSFET, one end of the lead-in unit is electrically connected to the gate end of the super-junction MOSFET, and the other end is connected in series with the gate-drain breakdown drainage unit and the gate-source breakdown drainage unit, respectively.

[0127] The lead-in unit is used to introduce the impact current at the gate end of the super-junction MOSFET; the gate-drain breakdown drainage unit is used to introduce the impact current introduced by the lead-in unit into the epitaxial region of the super-junction MOSFET, and flow to the drain end through the substrate; and the gate-source breakdown drainage unit is used to introduce the impact current introduced by the lead-in unit into the source end injection region of the super-junction MOSFET, and flow to the source end, so that the lead-in unit and the breakdown drainage unit form a current discharge channel between the gate end-drain end and the gate end-source end.

[0128] It can be understood that when the electrostatic impact is small and the electrostatic charge is small, the lead-in unit and the breakdown drainage unit described above can discharge all the electrostatic charges.

[0129] In some other embodiments of the present application, in order to improve the electrostatic protection effect, the discharge channel constructed by the present application, i.e., the electrostatic protection device, further includes a discharge unit, which includes a gate-drain charge discharge unit integrated between the gate end-drain end of the super-junction MOSFET, and a gate-source charge discharge unit integrated between the gate end-source end of the super-junction MOSFET.

[0130] The gate-drain charge discharge unit is connected in parallel with the series circuit of the gate-drain breakdown drainage unit and the lead-in unit, and the gate-source charge discharge unit is connected in parallel with the series circuit of the gate-source breakdown drainage unit and the lead-in unit.

[0131] The gate-drain charge discharge unit is used to discharge large current between the gate end-drain end, and the gate-source charge discharge unit is used to discharge large current between the gate end-source end.

[0132] That is, even when the electrostatic impact is large and the electrostatic charge is large, the constructed discharge unit is turned on to complete the large current charge discharge function.

[0133] It can be understood that the discharge channel constructed by the application can not only complete the ESD charge discharge function between the gate and source, but also can construct a complete device for static protection between all terminals of the gate, source and drain in cooperation with the structure of the super-junction MOSFET.

[0134] Compared with the existing method of adding an ESD single tube at the chip port during packaging, the application is implemented simultaneously with the preparation process of the super-junction MOSFET, does not require additional ESD single tubes, and reduces the implementation cost of ESD protection.

[0135] Compared with the existing method of implementing ESD function in the same wafer in the polycrystal, the application is compatible with the super-junction MOSFET process, does not require additional process overhead, and ensures the process yield.

[0136] Finally, compared with the existing method of modifying the drain, the application avoids any modification of the drain, does not affect the withstand voltage characteristics of the super-junction MOSFET itself, and maintains the original high breakdown voltage of the super-junction MOSFET.

[0137] That is, by the implementation method disclosed in the application, an effective static discharge mechanism can be formed at the gate-drain and gate-source of the super-junction MOSFET. And by the implementation method disclosed in the application, a good full-terminal static protection discharge path is provided for the entire super-junction MOSFET, and the full-terminal static protection function of the super-junction MOSFET is realized.

[0138] Optionally, in some embodiments of the application, in order to integrate various protection units in the super-junction MOSFET and realize the full-terminal static protection function of the super-junction MOSFET, in some embodiments, an injection region can be provided in the P-type diffusion region 011 in the N-type conductive structure of the super-junction MOSFET, so that the injection region and the functional region of the super-junction MOSFET constitute the lead unit, the breakdown current lead unit and the discharge unit.

[0139] For example, as shown in FIGS. 1 and 2, the injection region can include a lead injection region and a breakdown current lead injection region. Figure 5 and Figure 6 The lead injection region is in contact with the gate polysilicon 010 of the super-junction MOSFET, and the breakdown current lead injection region 007 is in an electrically suspended state.

[0140] The lead injection region, the breakdown current lead injection region and the diffusion region of the super-junction MOSFET constitute the lead unit.

[0141] The breakdown current lead injection region, the diffusion region of the super-junction MOSFET and the epitaxial region 004 of the super-junction MOSFET constitute the gate-drain breakdown current lead unit.

[0142] The breakdown drain injection region, the diffusion region of the super junction MOSFET, and the source injection region of the super junction MOSFET constitute the gate-source breakdown drain injection unit.

[0143] The breakdown drain injection region, the diffusion region of the super junction MOSFET, and the source injection region of the super junction MOSFET constitute the gate-source breakdown drain injection unit.

[0144] The breakdown drain injection region, the diffusion region of the super junction MOSFET, and the source injection region of the super junction MOSFET constitute the gate-source breakdown drain injection unit.

[0145] Specifically, in combination with the N-type conductive structure as an example, the top enlarged three-dimensional schematic view of the super junction MOSFET of the embodiment of the present application, and the bottom enlarged three-dimensional schematic view are shown in FIGS. 1 and 2. Figure 5 Figure 6 Specifically, in combination with the N-type conductive structure as an example, the top enlarged three-dimensional schematic view of the super junction MOSFET of the embodiment of the present application, and the bottom enlarged three-dimensional schematic view are shown in FIGS. 1 and 2.

[0146] That is, in the N-type conductive structure, the injection region can include an N-type breakdown drain injection region 007 and an N-type gate injection region 005.

[0147] The N-type breakdown drain injection region 007 has a doping concentration in the range of 5E18 to 1E20 (a typical value is 1E19), and is prepared by a contact injection process together with the N-type gate injection region 005 and the N-type source injection region 006. The N-type breakdown drain injection region 007 is not connected to any electrical terminal and is completely floating in an electrical sense.

[0148] The N-type breakdown drain injection region 007 has a doping concentration in the range of 5E18 to 1E20 (a typical value is 1E19), and is prepared by a contact injection process together with the N-type gate injection region 005 and the N-type source injection region 006. The N-type breakdown drain injection region 007 is not connected to any electrical terminal and is completely floating in an electrical sense.

[0149] The N-type breakdown drain injection region 007 has a doping concentration in the range of 5E18 to 1E20 (a typical value is 1E19), and is prepared by a contact injection process together with the N-type gate injection region 005 and the N-type source injection region 006. The N-type breakdown drain injection region 007 is not connected to any electrical terminal and is completely floating in an electrical sense.

[0150] Optionally, the projection of the injection region and the breakdown drain injection region on the substrate and the projection of the source injection region on the substrate form a T-shaped distribution; the projection region of the breakdown drain injection region is located between the injection region and the source injection region, and the breakdown drain injection region, the injection region, and the source injection region do not contact each other.

[0151] Specifically, in combination with the N-type conductive structure as an example, the top enlarged three-dimensional schematic view of the super junction MOSFET of the embodiment of the present application, and the bottom enlarged three-dimensional schematic view are shown in FIGS. 1 and 2. Figures 5 to 13 Specifically, in combination with the N-type conductive structure as an example, the top enlarged three-dimensional schematic view of the super junction MOSFET of the embodiment of the present application, and the bottom enlarged three-dimensional schematic view are shown in FIGS. 1 and 2.​

[0152] The N-type breakdown drainage injection 007 and the N-type source injection area 006 are arranged in a T-shape and are arranged parallel to the N-type lead injection area 005. The N-type breakdown drainage injection 007 is electrically completely floating and is not directly electrically connected to the N-type lead injection area 005 or the N-type source injection area 006.

[0153] It is understood that in this application, the N-type lead injection area 005 and the N-type breakdown current injection area 007 are cleverly designed to form a lead unit, a breakdown current injection unit, and a charge discharge unit, thereby completing the electrostatic protection function of all terminals.

[0154] For example, in the embodiments of this application, a two-dimensional cross-section C1 is constructed at the top, forming a YZ plane, such as... Figure 8 As shown in the left figure. A schematic diagram of the cross-section formed at section C1 provided by the embodiment of the invention, as shown... Figure 8 As shown in the right figure, it includes an N-type epitaxial region 004, an N-type lead-in injection region 005, an N-type source-end injection region 006, an N-type breakdown-drain injection region 007, and a P-type diffusion region 011.

[0155] As can be seen from the cross-sectional view, the YZ plane provided in the embodiments of this application is characterized by:

[0156] The N-type lead-in injection area 005, the N-type source-end injection area 006, and the N-type breakdown drainage injection area 007 do not contact each other; secondly, the span of the length of the N-type breakdown drainage injection area 007 in the Z direction is smaller than that of the N-type lead-in injection area 005 and smaller than the distance between the upper and lower N-type source-end injection areas 006.

[0157] In the embodiments provided in this application, the minimum distance SP_S between the edge of the N-type breakdown injection region 007 and the edge of the N-type source injection region 006 in the Z direction; and the distance LS_G between the N-type breakdown injection region 007 and the N-type lead injection region 005, and the distance LS_S between the N-type breakdown injection region 007 and the N-type source injection region 006 in the Y direction. The length and width of the N-type breakdown injection region 007 vary depending on the design values ​​of SP_S, LS_G, and LS_S, as long as the minimum lithographic accuracy requirement is met.

[0158] Based on an understanding of the following explanation of principles, designers applying the embodiments of this application can verify the parameters of SP_S, LS_G, and LS_S in order to obtain a suitable discharge turn-on voltage and minimum back-break-back voltage.

[0159] Figure 9 The schematic diagram of the positions of specified cross sections C2, C3, C4, and C5 provided in the embodiments of this application indicates the positions of cross sections C2 and C3 in the XZ section and the positions of cross sections C4 and C5 in the XY section.

[0160] Figure 10The cross section C2 two-dimensional schematic diagram (XZ plane) provided by the embodiment of the present application is consistent with the cross section of the classic super-junction MOSFET, and includes the N-type epitaxial region 004, the N-type source end injection region 006, the gate isolation medium 008, the side wall isolation medium 009, the gate polysilicon 010, the P-type diffusion region 011, the N-type epitaxial P-type diffusion region junction 012, and continues the function of the classic super-junction MOSFET.

[0161] It is particularly pointed out that the PN gradual junction at the junction of the N-type epitaxial P-type diffusion region junction 012, i.e., the N-type epitaxial P-type diffusion region, can be seen in this interface. On one side of the N-type epitaxial P-type diffusion region junction 012 close to the N-type source end injection region 006 is the P-type diffusion region 010, and on the other side is the N-type epitaxial region 004.

[0162] Figure 11 The cross section C3 two-dimensional schematic diagram (XZ plane) provided by the embodiment of the present application is completely inconsistent with the cross section of the classic super-junction MOSFET, and is a structure unique to the embodiment of the present application. In particular, Figure 11 The N-type breakdown current injection region 007 is completely separated from the gate polysilicon 010 by the gate isolation medium 008 without any contact and connection, in combination with the foregoing Figure 7 In the right cross section C1 schematic diagram, the N-type breakdown current injection region 007 is also not connected with other structures in the YZ plane, and it can be known that the N-type breakdown current injection region 007 is completely floating in an electrical sense. Since the P-type column region 003 and the P-type diffusion region 011 are both P-type doped regions, there is no obvious PN junction; at the same time, since the P-type diffusion region 011 is a diffusion doped region, there is also no obvious doping concentration boundary between the P-type column region 003 and the P-type diffusion region 011, Figure 10 The approximate boundary line of the P-type column region 003 and the P-type diffusion region 011 and the approximate distribution of the P-type diffusion region 011 are indicated by the dashed line.

[0163] Figure 12 The cross section C4 two-dimensional schematic diagram (XY plane) provided by the embodiment of the present application is completely inconsistent with the cross section of the classic super-junction MOSFET, and is a structure unique to the embodiment of the present application. Figure 11 The P-type column region 003, the N-type epitaxial region 004, the N-type injection region 005, the N-type breakdown current injection region 007, the gate isolation medium 008, the side wall isolation medium 009, the gate polysilicon 010, the P-type diffusion region 011, and the foregoing are consistent.

[0164] Similarly, Figure 12 The approximate boundary line of the P-type column region 003 and the P-type diffusion region 011 and the approximate distribution of the P-type diffusion region 011 are indicated by the dashed line.

[0165] In particular, the N-type trigger implant region 005 and the N-type breakdown current sink implant region 007 are structurally completely contained in the P-type diffusion region 011, and the diffusion doping of the P-type diffusion region 011 prevents ESD premature breakdown. There is a break between the sidewall isolation medium 009 above the gate polysilicon 010 and the sidewall isolation medium 009 to the right of the gate polysilicon 010, and a via is selectively and optionally opened above the gate polysilicon 010 at this location, and then connected to the interconnection metal.

[0166] Figure 13 The two-dimensional schematic diagram (XY plane) of the cross section C5 provided by the embodiments of the present application is completely inconsistent with the cross section of the classic super-junction MOSFET at this location, and is a unique structure of the embodiments of the present application. Figure 12 The P-type pillar region 003, the N-type epitaxial region 004, the N-type trigger implant region 005, the N-type source implant region 006, and the P-type diffusion region 011 are consistent with the above description, and similarly, Figure 12 The approximate boundary line of the P-type pillar region 003 and the P-type diffusion region 011 and the approximate distribution of the P-type diffusion region 011 are indicated by the dashed line in the middle.

[0167] Optionally, in some embodiments of the present application, the discharge channel constructed by the implant region, in combination with the functional regions of the super-junction MOSFET, can be equivalent to a corresponding transistor.

[0168] Correspondingly, in combination with Figure 14 and Figure 15 as shown, in some embodiments, the trigger unit is a trigger transistor 021, the gate-drain breakdown current sink unit is a gate-drain breakdown current sink transistor 022, and the gate-source breakdown current sink unit includes a gate-source breakdown current sink transistor 025. Similarly, the gate-drain charge discharge unit is a gate-drain large-current charge discharge transistor 023, and the gate-source charge discharge unit is a gate-source auxiliary current charge discharge transistor 026.

[0169] Correspondingly, the trigger implant region, the breakdown current sink implant region, and the diffusion region of the super-junction MOSFET constitute the trigger transistor 021; the breakdown current sink implant region, the diffusion region of the super-junction MOSFET, and the epitaxial region 004 of the super-junction MOSFET constitute the gate-drain breakdown current sink transistor 022; the breakdown current sink implant region, the diffusion region 011 of the super-junction MOSFET, and the source implant region of the super-junction MOSFET constitute the gate-source breakdown current sink transistor 025; the trigger implant region, the diffusion region of the super-junction MOSFET, and the source implant region of the super-junction MOSFET constitute the gate-source auxiliary current charge discharge transistor 026.

[0170] The drain of the gate-drain breakdown current induction transistor 022 is connected to the source of the interface transistor 021, and the source of the gate-drain breakdown current induction transistor 022 is connected to the drain of the super-junction MOSFET.

[0171] The drain of the gate-drain large current charge discharge transistor 023 is connected to the gate of the super-junction MOSFET, and the source of the gate-drain large current charge discharge transistor 023 is connected to the drain of the super-junction MOSFET.

[0172] The drain of the gate-source auxiliary current charge discharge transistor 026 is connected to the gate of the super-junction MOSFET, and the source of the gate-drain large current charge discharge transistor 023 is connected to the source of the super-junction MOSFET.

[0173] Specifically, in order to better understand the protection unit, each injection region and each functional region of the super-junction MOSFET correspond to the equivalent circuit as shown in Figure 14 and Figure 15 .

[0174] As shown in Figure 14 , the entire active end S, drain D, and gate G terminals are drawn by the N-type epitaxial substrate boundary 001, N-type source injection region 006, and gate polysilicon 010, respectively.

[0175] The interface transistor 021 is composed of N-type interface injection region 005, P-type diffusion region 011, and N-type breakdown current induction injection region 007, which is an NPN transistor. Its main functions are: 1) connecting the G terminal to introduce the impact current of the G terminal, and 2) controlling the opening voltage Vtr of the G terminal when receiving an electrostatic shock (Vtr is strongly related to LS_G).

[0176] The gate-drain breakdown current induction transistor 022 is composed of N-type breakdown current induction injection region 007, P-type diffusion region 011, and N-type epitaxial region 004, which is an NPN transistor. Its main function is to induce the current of the interface transistor 021 to the N-type epitaxial region 004, and then flow through the N-type epitaxial substrate boundary 001 to the bottom drain terminal.

[0177] It can be understood that when the electrostatic shock is small and the electrostatic charge is small, the drain D to the gate G only relies on the interface transistor 021 and the gate-drain breakdown current induction transistor 022 to discharge all the electrostatic charge.

[0178] When the electrostatic impact is large and the electrostatic charge is more, the NPN gate-drain large current charge discharge transistor 023 composed of the N-type injection area 005, the N-type epitaxial substrate boundary 011 and the N-type epitaxial area 004 is opened to complete the large current charge discharge function. Since the N-type epitaxial area 004 is far beyond the N-type injection area 005 and the N-type breakdown current injection area 007 in the X direction depth, it can be equivalent to consider that the emission junction area of the gate-drain large current charge discharge transistor 023 is much larger than the injection transistor 021 and the gate-drain breakdown current discharge transistor 022.

[0179] Therefore, the electrostatic charge discharge capacity of the gate-drain large current charge discharge transistor 023 is much larger than the injection transistor 021 and the gate-drain breakdown current discharge transistor 022. The opening of the gate-drain large current charge discharge transistor 023 under large current further enhances the electrostatic protection capability provided by the embodiment of the application. Finally, the injection transistor 021, the gate-drain breakdown current discharge transistor 022 and the gate-drain large current charge discharge transistor 023 form the gate-drain terminal electrostatic protection unit 024.

[0180] The gate-source breakdown current discharge transistor 025, that is, the NPN transistor composed of the breakdown current injection area 007, the P-type diffusion area 011 and the N-type source end injection area 006, mainly functions to guide the current of the injection transistor 021 to the injection transistor 006 and then to the source terminal.

[0181] The gate-source auxiliary current charge discharge transistor 026, when the electrostatic impact comes, the source end S to the gate end G can discharge the electrostatic charge through the path of the injection transistor 021 and the gate-drain breakdown current discharge transistor 022, and can also complete the current charge discharge function through the NPN gate-drain large current charge discharge transistor 023 composed of the N-type injection area 005, the P-type diffusion area 011 and the N-type source end injection area 006. Finally, the injection transistor 021, the gate-source breakdown current discharge transistor 025 and the gate-source auxiliary current charge discharge transistor 026 form the gate-source terminal electrostatic protection unit 027.

[0182] Figure 15 The full-terminal protection implementation manner provided by the embodiment of the application is shown in the figure. Complete electrostatic protection should be able to play a perfect electrostatic protection role between all terminals, which is usually called full-chip protection or full-terminal protection in the electrostatic reliability field. For the classic super-junction MOSFET application, full-terminal protection means that the source end S, the drain end D and the gate end G form effective electrostatic protection between each other.

[0183] The protected super-junction MOSFET, whose source end S, drain end D and gate end G are exposed outside the package, can be impacted by static electricity. The intrinsic parasitic transistor 029 of the protected super-junction MOSFET is composed of the N-type source end injection region 006, the P-type diffusion region 011 and the N-type epitaxial region 004, and is an NPN-type transistor. The longitudinal area of the super-junction MOSFET is huge, that is, the emission junction area of the intrinsic parasitic transistor 029 of the protected super-junction MOSFET composed of the N-type source end injection region 006 and the P-type diffusion region 011 is huge. Even if static electricity occurs between DS, the excellent charge discharge capability of the intrinsic parasitic transistor 029 of the protected super-junction MOSFET can completely discharge the static electricity suddenly accumulated between DS through the gate-drain terminal static electricity impact path 031.

[0184] The most threatening static electricity impact on the super-junction MOSFET comes from the G gate end. At present, the gate of all super-junction MOSFETs is an oxide or composite oxide dielectric layer, even if a high-k gate dielectric (such as an Al2O3 / HfO2 stack) is prepared by an atomic layer deposition (ALD) process, the breakdown field strength is increased from 1.0 V / nm of traditional SiO2 to 1.5 V / nm, which can easily cause the gate oxide layer to break down. Without additional static electricity protection measures, the G gate end will be irreversibly damaged or burned at a voltage of tens of volts, and the static electricity transient voltage is as high as thousands of volts.

[0185] In the embodiments of the present application, the technology disclosed in the present patent forms a gate-drain terminal static electricity protection unit 024 between GD, so that when static electricity occurs between GD, the static electricity is discharged in time through the gate-drain terminal static electricity impact path 031, and the gate dielectric of the protected super-junction MOSFET 028 is prevented from being damaged. Similarly, the technology disclosed in the present patent forms a gate-source terminal static electricity protection unit 027 between GS, so that when static electricity occurs between GS, the static electricity is discharged in time through the gate-drain terminal static electricity impact path 032, and the gate dielectric of the protected super-junction MOSFET 028 is prevented from being damaged.

[0186] Figure 16 The transfer curve of the super-junction MOSFET provided in the embodiments of the present application, that is, the drain current and gate voltage (IDVG) curve, is provided as a contrast to the classical super-junction MOSFET. The present application demonstrates by a TCAD experiment that the basic function of the classical super-junction MOSFET, especially the opening characteristic, is not affected by the super-junction MOSFET provided in the embodiments of the present application. Figure 16 The dashed line is the IDVG curve of the classical super-junction MOSFET, and the solid line is the IDVG curve of the super-junction MOSFET provided in the embodiments of the present application.

[0187] As can be seen from the figure, the IDVG curve of the embodiment provided by the application is basically consistent with that of the classic super-junction MOSFET. The maximum slope method is used to calculate the on-voltage Vth of the embodiment provided by the application, which is 4.1 V, and the on-voltage Vth of the classic super-junction MOSFET is 4.0 V, and the two are basically consistent.

[0188] Figure 17 The drain current and drain voltage (IDVD) curve of the classic super-junction MOSFET for comparison is provided for the embodiment of the application. The TCAD experiment demonstrates that the embodiment provided by the application does not affect the basic functions of the classic super-junction MOSFET, especially the conduction characteristics.

[0189] Figure 17 The IDVD curve of the classic super-junction MOSFET is a dashed line when Vg=10, and the improved IDVD curve of the embodiment provided by the application is a solid line. As can be seen from the figure, the IDVD curve of the embodiment provided by the application is basically consistent with that of the classic super-junction MOSFET. The method of selecting the linear region of the Id-Vds curve to calculate the slope is the on-resistance Rdson. The on-resistance Rdson of the embodiment provided by the application is 4.9E -2 ohmcm -2 , the on-resistance Rdson of the classic super-junction MOSFET is 4.5E -2 ohmcm -2 , and the two are basically consistent.

[0190] Figure 18 The breakdown curve of the classic super-junction MOSFET for comparison is provided for the embodiment of the application. The TCAD experiment demonstrates that the embodiment provided by the application does not affect the basic functions of the classic super-junction MOSFET, especially the breakdown characteristics. Figure 18 The breakdown curve of the classic super-junction MOSFET is a dashed line, and the breakdown curve of the embodiment provided by the application is a solid line.

[0191] As can be seen from the figure, the breakdown curve of the embodiment provided by the application is basically consistent with that of the classic super-junction MOSFET. The method of taking the maximum value of the slope change of the breakdown curve is used to calculate the breakdown voltage BV of the embodiment provided by the application, which is 651.4 V, and the breakdown voltage BV of the classic super-junction MOSFET is 642.5 V, and the two are basically consistent.

[0192] Figure 19The breakdown stage potential distribution schematic diagram provided by the embodiment of the present application. The first equipotential line 041 representing the potential distribution, the second equipotential line 042 representing the potential distribution, and the third equipotential line 043 representing the potential distribution are all equipotential lines representing the potential distribution, and the potential values of the first equipotential line 041 representing the potential distribution, the second equipotential line 042 representing the potential distribution, and the third equipotential line 043 representing the potential distribution are arranged from large to small. As can be seen from the potential distribution, the upper half of the low-doped P-type pillar region 003 has no potential line distribution, and most of the potential line distribution is in the N-type epitaxial region 004.

[0193] It is illustrated that the design of the present application does not affect the withstand voltage of the super-junction MOSFET, and the P-type pillar region 003 does not break down prematurely and still plays a role in balancing the charge.

[0194] Figure 20 The breakdown stage electric field distribution schematic diagram provided by the embodiment of the present application. The equipotential line 051 representing the electric field distribution, the first extreme high value position 052 of the electric field distribution, and the second extreme high value position 053 of the electric field distribution are all extreme high value positions of the electric field distribution. The concentration of the electric field illustrates the position of the breakdown point in the device.

[0195] As can be seen, the design of the present application does not shift the breakdown point of the super-junction MOSFET to the surface, so the good withstand voltage of the original super-junction MOSFET can be maintained.

[0196] Figure 21 The current distribution schematic diagram during the discharge process provided by the embodiment of the present application. The first equal current density line 061 representing the current distribution, the second equal current density line 062 representing the current distribution, and the third equal current density line 063 representing the current distribution are all equal current density lines representing the current distribution, and the current density values of the first equal current density line 061 representing the current distribution, the second equal current density line 062 representing the current distribution, and the third equal current density line 063 representing the current distribution are arranged from small to large.

[0197] As can be seen from the potential distribution, during the discharge process, the static charge at the G terminal first reaches the N-type contact injection region 005, passes through the current path 064 during the discharge process, and then reaches 001 and flows to the D terminal. It can be seen that the present application avoids the G gate dielectric directly bearing the static impact, greatly enhancing the static protection capability of the G terminal.

[0198] Figure 22 The discharge curve provided by the embodiment of the present application. According to the classical oxide layer breakdown theory, the ideal breakdown field strength of silicon oxide is about 10E7V / cm, corresponding to 22nm silicon oxide used in the classical super-junction MOSFET, the maximum ESD withstand voltage between the gate-source and the gate-drain does not exceed 30V.

[0199] This application demonstrates, through TCAD experiments, the improvement in ESD protection performance between the gate and source, and between the gate and drain. Figure 22 The dashed line represents the gate-drain discharge curve provided in the embodiments of this application, and the dashed line represents the gate-source discharge curve provided in the embodiments of this application. The superjunction MOSFET reinforced by this application quickly enters the walkback mode at 732.3V when an ESD impact occurs between the gate and drain, and the walkback voltage drops rapidly to below 10V, ensuring that the gate oxide layer is not prematurely broken down.

[0200] Similarly, the superjunction MOSFET reinforced by this application rapidly enters the walkback mode at 16.9V when an ESD event occurs between the gate and source, and the walkback voltage quickly drops to below 10V, ensuring that the gate oxide layer is not prematurely broken down. This achieves full-chip protection between the gate and source, and between the gate and drain.

[0201] Figure 23 This is a flowchart illustrating the preparation process for embodiments of this application. Besides disclosing a novel structure and a unique working mechanism, this application also discloses a preparation method. The preparation method disclosed in this application extensively utilizes well-known and mature processes to achieve the structure disclosed in this application, and does not limit the parameters of the general process steps used.

[0202] On the other hand, this application also provides a superjunction MOSFET, which may include a semiconductor substrate, an epitaxial layer, a gate structure layer and a metal electrode layer.

[0203] The epitaxial layer has a cylindrical region of superstructure, and an injection region is provided in the diffusion region of the cylindrical region. The injection region cooperates with the functional regions of the superjunction MOSFET to form a superjunction MOSFET electrostatic protection device as described in the above embodiments.

[0204] Specifically, in combination Figures 1 to 13 As shown, the superjunction MOSFET provided in this embodiment, based on the classic superjunction MOSFET structure, has an injection region provided in the diffusion region on the cylindrical region, so that the injection region cooperates with the functional regions of the superjunction MOSFET to form a superjunction MOSFET electrostatic protection device as described in the above embodiments.

[0205] On the other hand, this application provides a method for fabricating a superjunction MOSFET, which is used for fabricating the superjunction MOSFET described in the above embodiments.

[0206] Taking the N-type conductive structure as an example, the fabrication method of this superjunction MOSFET will be explained. The method specifically includes the following steps:

[0207] S1: Silicon substrate and epitaxial layer fabrication: An epitaxial layer is formed on the substrate.

[0208] Specifically, high-purity n-type <100> single crystal silicon wafer can be selected as the substrate, with resistivity of 0.005-0.02 Ωcm and thickness of 650-800 μm.

[0209] S2: epitaxial growth.

[0210] Specifically, N-type epitaxial layer 004 is grown on 001 by low pressure chemical vapor deposition (LPCVD). The epitaxial layer has a thickness of 5-50 μm and a doping concentration of 1E14-5E15 cm -3 .

[0211] S3: superstructure preparation.

[0212] Specifically, the columnar region of the superstructure is formed on the epitaxial layer, i.e. the P column region of the superstructure is defined by photolithography.

[0213] For example, deep reactive ion etching (DRIE) can be used to form vertical trenches, with etching depth of 5-50 μm, sidewall angle of 88-89 degrees, trench width of 0.5-2 μm, and etching gas SF / CF alternated pulse process, pressure of 10-50 mTorr. When the P column region of the superstructure is patterned, the difference between the gate polysilicon 010 of the present application and the super-junction MOSFET should be noted.

[0214] S4: P-type filling and epitaxy.

[0215] Specifically, boron-doped epitaxial growth P-type silicon can be filled by chemical vapor deposition (CVD), with doping concentration of 1E16-5E17 cm -3 . The above process is repeated multiple times, and finally the 003 structure is formed, achieving charge balance with the N-type epitaxial layer 004

[0216] S5: gate structure preparation.

[0217] Specifically, the gate structure is formed on the epitaxial layer and the columnar region, i.e. it includes gate oxide layer growth (dry oxidation process: temperature of 900-1000 degrees Celsius, oxygen flow of 5-20 L / min, thickness of 20-100 nm), polysilicon gate deposition (phosphorus-doped polysilicon by low pressure chemical vapor deposition, thickness of 200-400 nm, doping concentration of 1E20-5E20 cm-3), and gate patterning. When the gate is patterned, the difference between the 010 of the present application and the super-junction MOSFET should be noted.

[0218] S6: shallow doped drain (LDD): phosphorus (P) or arsenic (As) is implanted by ion implantation, with energy of 30-80 keV and dose of 1E13-5E13 cm-2, and 011 is formed after subsequent annealing.

[0219] S7: Side wall formation: SiN / SiO2 composite layer with thickness of 100-200 nm is deposited, and anisotropic etching is performed to form side wall with width of 50-150 nm009.

[0220] S8: Contact heavy doping: first, the injection area is defined by patterning, then arsenic (As) is injected with energy of 80-150 keV and dose of 1E5-5E5 cm-2, and finally rapid thermal annealing is performed at 950-1050 °C for 10-30 seconds to form005,006,007. It can be seen that the formation of005,007 in the embodiments of the present application does not require additional processes, but only needs to pay attention to the significant difference between the shape of010 in the embodiments of the present application and the super junction MOSFET when defining by patterning.

[0221] S9: Back-end process: metallization, wafer thinning and packaging.

[0222] As can be seen, the disclosed embodiments are fully compatible with the preparation process of the super junction MOSFET, and do not require additional steps.

[0223] It can be understood that the electrostatic protection device, super junction MOSFET and its preparation method of each embodiment described above are explained and described taking N conductive structure as an example. For P-type conductive structure, the corresponding structure is replaced based on the same inventive concept.

[0224] It can be understood that the super-junction MOSFET electrostatic protection device, the super-junction MOSFET and the preparation method provided by the embodiments of the present application can integrate the gate-drain breakdown current leading unit between the gate end-drain end of the super-junction MOSFET, integrate the gate-source breakdown current leading unit between the gate end-source end of the super-junction MOSFET, form the gate-drain charge discharge unit in the gate end-drain end of the super-junction MOSFET, and form the gate-source charge discharge unit between the gate end-source end of the super-junction MOSFET, so as to build the discharge channel between the gate end-source end and the gate end-drain end of the super-junction MOSFET, form the full-terminal electrostatic protection device integrated in the super-junction MOSFET, so that the discharge channel is silent when there is no ESD impact, and forms an effective discharge channel to discharge the ESD charge when the ESD impact comes, that is, the leading unit is used to introduce the impact current into the gate end of the super-junction MOSFET; the gate-drain breakdown current leading unit is used to introduce the impact current introduced by the leading unit into the epitaxial region of the super-junction MOSFET, and flow to the drain end through the substrate; the gate-source breakdown current leading unit is used to introduce the impact current introduced by the leading unit into the source end injection region of the super-junction MOSFET, and flow to the source end, so that the leading unit and the breakdown current leading unit form a current discharge channel between the gate end-drain end and the gate end-source end. The integrated leading unit and breakdown current leading unit in the super-junction MOSFET, that is, the discharge channel is built between the gate end-source end and the gate end-drain end of the super-junction MOSFET. Compared with the prior art method of adding an ESD single tube at the chip port during packaging, the electrostatic protection device can be implemented simultaneously during the preparation of the super-junction MOSFET, without the need for additional ESD single tubes, thereby reducing the implementation cost of ESD protection, and compared with the prior art method of implementing ESD function in the polycrystal in the same wafer, the present application is compatible with the super-junction MOSFET process, without additional process overhead, thereby ensuring the process yield. Finally, compared with the prior art method of modifying the drain end, the present application avoids any modification of the drain end, does not affect the withstand voltage characteristics of the super-junction MOSFET, and maintains the original high breakdown voltage of the super-junction MOSFET.

[0225] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0226] The principles and implementation modes of the present application are described by using specific examples. The above embodiments are only used to help understand the method and its core idea of the present application. For those skilled in the art, the specific implementation modes and application ranges can be changed according to the idea of the present application. Therefore, the content of the present application should not be understood as a limitation.

Claims

1. A superjunction MOSFET electrostatic discharge protection device, characterized in that, The electrostatic discharge protection device is integrated into the superjunction MOSFET and includes: Lead-in unit and breakdown drainage unit; The breakdown drainage unit includes a gate-drain breakdown drainage unit integrated between the gate and drain terminals of the superjunction MOSFET, and a gate-source breakdown drainage unit integrated between the gate and source terminals of the superjunction MOSFET. One end of the connection unit is electrically connected to the gate terminal of the superjunction MOSFET, and the other end is connected in series with the gate-drain breakdown drainage unit and the gate-source breakdown drainage unit, respectively. The lead-in unit is used to introduce the inrush current of the gate terminal of the superjunction MOSFET; the gate-drain breakdown current-draining unit is used to introduce the inrush current introduced by the lead-in unit into the epitaxial region of the superjunction MOSFET, and flow through the substrate to the drain terminal; the gate-source breakdown current-draining unit is used to introduce the inrush current introduced by the lead-in unit into the source injection region of the superjunction MOSFET, and flow to the source terminal, so that the lead-in unit and the breakdown current-draining unit form a current discharge channel between the gate terminal and the drain terminal and between the gate terminal and the source terminal.

2. The superjunction MOSFET electrostatic discharge protection device according to claim 1, characterized in that, It also includes a discharge unit, which includes a gate-drain charge discharge unit integrated between the gate and drain terminals of the superjunction MOSFET, and a gate-source charge discharge unit integrated between the gate and source terminals of the superjunction MOSFET; The gate drain charge discharge unit is connected in parallel with the series circuit of the gate drain breakdown current-draining unit and the lead-in unit, and the gate source charge discharge unit is connected in parallel with the series circuit of the gate source breakdown current-draining unit and the lead-in unit. The gate-drain charge discharge unit is used to discharge the large current before the gate end and the drain end, and the gate-source charge discharge unit is used to discharge the large current between the gate end and the source end.

3. The superjunction MOSFET electrostatic discharge protection device according to claim 2, characterized in that, An injection region is provided in the diffusion region of the superjunction MOSFET. The injection region and the functional region of the superjunction MOSFET constitute the lead-in unit, the breakdown current-draining unit, and the discharge unit.

4. The superjunction MOSFET electrostatic discharge protection device according to claim 3, characterized in that, The injection region includes a lead-in injection region and a breakdown current injection region. The lead-in injection region is in contact with the gate polysilicon of the superjunction MOSFET, and the breakdown current injection region is in an electrically floating state. The bonding injection region, the breakdown current injection region, and the diffusion region of the superjunction MOSFET constitute the bonding unit. The breakdown injection region, the diffusion region of the superjunction MOSFET, and the epitaxial region of the superjunction MOSFET constitute the gate-drain breakdown injection unit. The breakdown injection region, the diffusion region of the superjunction MOSFET, and the source injection region of the superjunction MOSFET constitute the gate-source breakdown injection unit. The injection region, the diffusion region of the superjunction MOSFET, and the epitaxial region of the superjunction MOSFET constitute the gate drain charge discharge unit. The lead-in injection region, the diffusion region of the superjunction MOSFET, and the source injection region of the superjunction MOSFET constitute the gate-source charge discharge unit.

5. The superjunction MOSFET electrostatic discharge protection device according to claim 4, characterized in that, The projections of the lead-in injection region and the breakdown lead-in injection region onto the substrate of the source-end injection region of the superjunction MOSFET are T-shaped. The projected area of ​​the puncture drainage injection area is located between the lead injection area and the source injection area, and the puncture drainage injection area, the lead injection area and the source injection area do not contact each other.

6. The superjunction MOSFET electrostatic discharge protection device according to claim 4, characterized in that, The lead unit includes a lead transistor, the gate-drain breakdown current-driving unit includes a gate-drain breakdown current-driving transistor, and the gate-source breakdown current-driving unit includes a gate-source breakdown current-driving transistor. The drain of the lead transistor is connected to the gate of the superjunction MOSFET; The drain of the gate-drain breakdown transistor is connected to the source of the lead transistor, and the source of the gate-drain breakdown transistor is connected to the drain of the superjunction MOSFET. The drain of the gate-source breakdown transistor is connected to the source of the lead transistor, and the source of the gate-source breakdown transistor is connected to the source of the superjunction MOSFET.

7. The superjunction MOSFET electrostatic discharge protection device according to claim 6, characterized in that, The gate-drain charge discharge unit includes a gate-drain high-current charge discharge transistor, and the gate-source charge discharge unit includes a gate-source auxiliary current charge discharge transistor. The drain of the gate-drain high-current charge discharge transistor is connected to the gate terminal of the superjunction MOSFET, and the source of the gate-drain high-current charge discharge transistor is connected to the drain terminal of the superjunction MOSFET. The drain of the gate-source auxiliary current charge discharge transistor is connected to the gate terminal of the superjunction MOSFET, and the source of the gate-drain large current charge discharge transistor is connected to the source terminal of the superjunction MOSFET.

8. The superjunction MOSFET electrostatic discharge protection device according to claim 7, characterized in that, The lead-in injection region, the breakdown lead-in injection region, and the diffusion region of the superjunction MOSFET constitute the lead transistor; The breakdown injection region, the diffusion region of the superjunction MOSFET, and the epitaxial region of the superjunction MOSFET constitute the gate-drain breakdown transistor. The breakdown injection region, the diffusion region of the superjunction MOSFET, and the source injection region of the superjunction MOSFET constitute the gate-source breakdown injection transistor. The lead-in injection region, the diffusion region of the superjunction MOSFET, and the source injection region of the superjunction MOSFET constitute the gate-source auxiliary current charge discharge transistor.

9. A superjunction MOSFET, characterized in that, include: Semiconductor substrate, epitaxial layer, gate structure layer and metal electrode layer; The epitaxial layer has a cylindrical region of superstructure, and an injection region is provided in the diffusion region on the cylindrical region. The injection region cooperates with the functional regions of the superjunction MOSFET to form a superjunction MOSFET electrostatic protection device as described in any one of claims 1-8.

10. A method for fabricating a superjunction MOSFET, characterized in that, The method is used for fabricating the superjunction MOSFET as described in claim 9, the method comprising: An epitaxial layer is formed on the substrate; A columnar region of a superstructure is formed on the epitaxial layer; A gate structure is formed on the epitaxial layer and the pillar region; A drain electrode is formed by shallow doping on the other side of the substrate; Contact heavy doping is performed in the diffusion region of the epitaxial layer between the gate structures to form an implantation region; The above structure is encapsulated.

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