Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device including a transistor having high saturation. A vertical transistor including a back gate electrode is provided in a semiconductor device. A lower electrode, a spacer, and an upper electrode are provided in this order in a semiconductor device. The spacer includes a first opening portion reaching the lower electrode, and the upper electrode includes a second opening portion having a region overlapping the first opening portion. The back gate electrode is provided inside the first opening and has a region in contact with the lower electrode. The back gate insulating layer, the semiconductor layer, the gate insulating layer, and the gate electrode are provided in this order so as to cover the back gate electrode. After the first opening and the second opening are formed, a back gate electrode can be formed by forming a conductive film so as to cover the first opening and anisotropically etching the conductive film. In addition, by forming an insulating film so as to cover the back gate electrode and anisotropically etching the insulating film, a back gate insulating layer can be formed.

Description

TECHNICAL FIELD

[0001] One embodiment of the present application relates to a semiconductor device and a manufacturing method thereof. One embodiment of the present application relates to a transistor and a manufacturing method thereof. One embodiment of the present application relates to a display device including a semiconductor device.

[0002] Note that one embodiment of the present application is not limited to the technical field described above. Examples of a technical field to which one embodiment of the present application pertains are a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device generally means a device that utilizes semiconductor characteristics, and means a circuit including a semiconductor element (e.g., a transistor, a diode, or a photodiode) and a device including the circuit, and the like. Further, a semiconductor device means all devices that can function by utilizing semiconductor characteristics. For example, as examples of a semiconductor device, an integrated circuit, a chip having an integrated circuit, and an electronic component in which a chip is enclosed in a package are given. Further, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device themselves can be a semiconductor device, and include a semiconductor device. BACKGROUND

[0004] A semiconductor device including a transistor is widely used in electronic devices. For example, by reducing the area occupied by a transistor in a display device, the pixel size can be reduced to achieve high definition. Thus, there is a demand for miniaturization of transistors.

[0005] As a device requiring a high-definition display device, development of a device for virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR) is very active, for example.

[0006] As a display device, development of a light-emitting device including an organic EL (Electro Luminescence) element or a light-emitting diode (LED) is active, for example.

[0007] Patent Document 1 discloses a high-definition display device using an organic EL element. [Patent Document 1] [Patent Document 1]

[0008] [Patent Document 1] International Patent Application Publication No. 2016 / 038508 SUMMARY PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] When a transistor is miniaturized, the channel length is shortened, which makes the saturation property of the transistor low. For example, when a driver transistor which controls current flowing through a light-emitting element (also referred to as a light-emitting device) included in a pixel of a display device is miniaturized, the channel length of the driver transistor is shortened. Thus, when the saturation property of the driver transistor is low, the current flowing through the light-emitting element is unstable, and the luminance of the light-emitting element is sometimes unstable. For example, unevenness in the current flowing through the light-emitting element over time occurs, and unevenness in the luminance of the light-emitting element over time occurs in the case of displaying a still image, for example.

[0010] In this specification and the like, the saturation property is high in the case where the current change in the saturation region in the Id-Vd characteristics of a transistor is small (the inclination is small). In addition, the saturation property is low in the case where the current change in the saturation region in the Id-Vd characteristics of a transistor is large (the inclination is large).

[0011] One object of one embodiment of the present application is to provide a transistor with high saturation property. Another object of one embodiment of the present application is to provide a miniaturized transistor. Another object of one embodiment of the present application is to provide a transistor with good electrical characteristics. Another object of one embodiment of the present application is to provide a semiconductor device including the transistor. Another object of one embodiment of the present application is to provide a semiconductor device with high reliability. Another object of one embodiment of the present application is to provide a display device which can display high-quality images.

[0012] Another object of one embodiment of the present application is to provide a small semiconductor device. Another object of one embodiment of the present application is to provide a semiconductor device with small wiring resistance. Another object of one embodiment of the present application is to provide a semiconductor device which is driven at high speed. Another object of one embodiment of the present application is to provide a semiconductor device which is inexpensive. Another object of one embodiment of the present application is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present application is to provide a high-definition display device. Another object of one embodiment of the present application is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present application is to provide a method for manufacturing a semiconductor device at low cost. Another object of one embodiment of the present application is to provide a novel transistor, a semiconductor device, a display device, or a method for manufacturing any of them.

[0013] Note that the description is not limiting to the above-mentioned objects. One embodiment of the present application does not necessarily achieve all the above-mentioned objects. Note that an object other than the above-mentioned objects can be extracted from the description, drawings, or claims. Means for solving the technical problem

[0014] One embodiment of the present application is a semiconductor device including a transistor and a first insulating layer, the transistor including a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a second insulating layer, and a third insulating layer, the first insulating layer being provided over the first conductive layer and including a first opening portion reaching the first conductive layer, the second conductive layer being provided over the first insulating layer and including a second opening portion having a region overlapping with the first opening portion, the third conductive layer having a region in contact with a side surface of the first insulating layer positioned in the first opening portion, the third conductive layer having a region in contact with the first conductive layer, an uppermost portion of the third conductive layer being positioned below a top end portion of the first insulating layer on a side of the first opening portion, the second insulating layer being provided so as to cover the third conductive layer inside the first opening portion, the semiconductor layer being provided so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer and have a region opposite to the third conductive layer with the second insulating layer interposed therebetween inside the first opening portion, and the third insulating layer being provided over the semiconductor layer so as to have a region positioned inside the first opening portion, the fourth conductive layer being provided so as to have a region opposite to the third conductive layer with the second insulating layer, the semiconductor layer, and the third insulating layer interposed therebetween inside the first opening portion.

[0015] Further, in the above embodiment, the semiconductor device can include a fourth insulating layer, the fourth insulating layer can be provided between the first insulating layer and the third insulating layer, and the fourth insulating layer can have a region in contact with a side surface of the second conductive layer on a side opposite to the second opening portion.

[0016] Further, in the above embodiment, the second insulating layer can have a region over the first insulating layer, and the second conductive layer can be provided over the second insulating layer.

[0017] Further, in the above embodiment, the semiconductor layer can include a metal oxide. The metal oxide can include two or more selected from In, an element M, and Zn, and the element M can be one or more selected from Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.

[0018] Further, one embodiment of the present application is a method for manufacturing a semiconductor device, including the steps of: forming a first conductive layer; forming a first insulating layer over the first conductive layer; forming a second conductive layer over the first insulating layer; forming a first opening portion having a region overlapping with the first conductive layer by processing the second conductive layer; forming a second opening portion reaching the first conductive layer by processing the first insulating layer so as to have a region overlapping with the first opening portion; forming a conductive film so as to cover the first opening portion and the second opening portion; forming a third conductive layer by anisotropic etching of the conductive film so as to have a region in contact with the first conductive layer and a bottom surface end portion of the first opening portion on the side of the second conductive layer; forming an insulating film so as to cover the second conductive layer and the third conductive layer; forming a second insulating layer covering the third conductive layer by anisotropic etching of the insulating film until at least a part of a top surface of the second conductive layer is exposed; forming a semiconductor layer so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer; forming a third insulating layer so as to have a region inside the second opening portion; and forming a fourth conductive layer over the third insulating layer so as to have a region inside the second opening portion.

[0019] Further, one embodiment of the present application is a method for manufacturing a semiconductor device, including the steps of: forming a first conductive layer; forming a first insulating layer over the first conductive layer; forming a first opening portion reaching the first conductive layer by processing the first insulating layer; forming a conductive film so as to cover the first opening portion; forming a second conductive layer by anisotropic etching of the conductive film so as to have a region in contact with the first conductive layer and a top surface end portion of the first insulating layer on the side of the first opening portion; forming a second insulating layer so as to cover the first conductive layer, the second conductive layer, and the first insulating layer; forming a third conductive layer including a second opening portion having a region overlapping with the first opening portion over the second insulating layer; forming a third opening portion reaching the first conductive layer in the second insulating layer, the third opening portion being formed inside the first opening portion; forming a semiconductor layer so as to have a region in contact with the first conductive layer and a region in contact with the third conductive layer; forming a third insulating layer so as to have a region inside the first opening portion; and forming a fourth conductive layer over the third insulating layer so as to have a region inside the first opening portion.

[0020] Further, in the above embodiment, the semiconductor layer can be formed by processing the semiconductor film after the semiconductor film is formed by the ALD method. Effects of Invention

[0021] According to one embodiment of the present application, a transistor with high saturation can be provided. Furthermore, a micro transistor can be provided. Furthermore, a transistor with excellent electric characteristics can be provided. Furthermore, a semiconductor device including the transistor can be provided. Furthermore, a semiconductor device with high reliability can be provided. Furthermore, a display device capable of displaying high-quality images can be provided.

[0022] Furthermore, a small semiconductor device can be provided. Furthermore, a semiconductor device with small wiring resistance can be provided. Furthermore, a semiconductor device capable of high-speed driving can be provided. Furthermore, an inexpensive semiconductor device can be provided. Furthermore, a semiconductor device with low power consumption can be provided. Furthermore, a high-definition display device can be provided. Furthermore, a method for manufacturing a semiconductor device with high productivity can be provided. Furthermore, a method for manufacturing a semiconductor device with low cost can be provided. Furthermore, a novel transistor, a semiconductor device, a display device, or a method for manufacturing the same can be provided.

[0023] Note that the description of these effects does not preclude the presence of other effects. One embodiment of the present application does not necessarily achieve all the effects described above. Note that the effects described above are extracted from the description of the specification, the attached drawings, and the like, and are not limited to the above-mentioned effects. BRIEF DESCRIPTION OF DRAWINGS

[0024] FIG. 1A is a plan view illustrating a structure example of a semiconductor device. FIG. 1B and FIG. 1C are cross-sectional views illustrating a structure example of a semiconductor device. FIG. 2A to FIG. 2C is a plan view illustrating a structure example of a semiconductor device. FIG. 3A is a plan view illustrating a structure example of a semiconductor device. FIG. 3B is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 4A and FIG. 4B are cross-sectional views illustrating a structure example of a semiconductor device. FIG. 5 is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 6A is a plan view illustrating a structure example of a semiconductor device. FIG. 6B is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 7A , FIG. 7B1 and FIG. 7B2 are cross-sectional views illustrating a structure example of a semiconductor device. FIG. 8 is a cross-sectional view illustrating a structure example of a semiconductor device. FIG. 9 is a cross-sectional view showing a structure example of a semiconductor device. FIG. 10A is a plan view showing a structure example of a semiconductor device. FIG. 10B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 11A is a plan view showing a structure example of a semiconductor device. FIG. 11B and FIG. 11C is a cross-sectional view showing a structure example of a semiconductor device. FIG. 12A to FIG. 12D is a plan view showing one example of a shape of an opening portion. FIG. 13A is a block diagram showing a structure example of a display device. FIG. 13B is a plan view showing a structure example of a pixel. FIG. 13C and FIG. 13D is a circuit diagram showing a structure example of a pixel. FIG. 14A to FIG. 14D is a circuit diagram showing a structure example of a pixel. FIG. 15A is a plan view showing a structure example of a pixel. FIG. 15B is a cross-sectional view showing a structure example of a pixel. FIG. 16A to FIG. 16I is a circuit diagram showing a structure example of a semiconductor device. FIG. 17A is a plan view showing a structure example of a semiconductor device. FIG. 17B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 18A and FIG. 18B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 19A and FIG. 19B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 20A is a plan view showing a structure example of a semiconductor device. FIG. 20B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 21A and FIG. 21B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 22A is a plan view showing a structure example of a semiconductor device. FIG. 22B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 23A is a plan view showing a structure example of a semiconductor device. FIG. 23B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 24A is a plan view showing a structure example of a semiconductor device. FIG. 24B is a cross-sectional view showing a structure example of a semiconductor device. FIG. 25A to FIG. 25C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 26A to FIG. 26C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 27A to FIG. 27C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 28A and FIG. 28B is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 29A and FIG. 29B is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 30A to FIG. 30C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 31A to FIG. 31C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 32A to FIG. 32C is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 33A and FIG. 33B is a cross-sectional view showing one example of a manufacturing method of a semiconductor device. FIG. 34A to FIG. 34G is a plan view showing a structure example of a pixel. FIG. 35A to FIG. 35K is a plan view showing a structure example of a pixel. FIG. 36 is a perspective view showing a structure example of a display device. FIG. 37A and FIG. 37B is a cross-sectional view showing a structure example of a display device. FIG. 38 is a cross-sectional view showing a structure example of a display device. FIG. 39A to FIG. 39C is a cross-sectional view showing a structure example of a display device. FIG. 40A and FIG. 40B is a cross-sectional view showing a structure example of a display device. FIG. 41 is a cross-sectional view showing a structure example of a display device. FIG. 42 is a cross-sectional view showing a structure example of a display device. FIG. 43 is a cross-sectional view showing a structure example of a display device. FIG. 44A and FIG. 44B is a cross-sectional view showing a structure example of a display device. FIG. 45A to FIG. 45D is a diagram showing one example of an electronic device. FIG. 46A to FIG. 46F is a diagram showing one example of an electronic device. FIG. 47A to FIG. 47G is a diagram showing one example of an electronic device. Embodiment of the Invention

[0025] Embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is readily apparent to those skilled in the art that the present invention can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the content below.

[0026] Note that, in the drawings described below, the same or similar portions to those described are denoted with the same reference numerals, and repeated explanation is omitted. Furthermore, when portions having similar functions are represented, the same hatching is sometimes used without particularly adding the same reference numerals.

[0027] Furthermore, for convenience of explanation, the position, size, range, and the like of each component shown in the drawings are not necessarily shown to the actual position, size, range, and the like. Therefore, the disclosed invention is not necessarily limited to the position, size, range, and the like disclosed in the drawings.

[0028] Note that, in this specification and the like, the ordinal numbers "first", "second", and the like are added to avoid confusion about the components. Therefore, the ordinal numbers "first", "second", and the like do not limit the number or the order of the components (for example, the order of the steps or the order of the layers). In addition, the ordinal numbers "first", "second", and the like attached to the components in one portion of this specification are sometimes different from the ordinal numbers "first", "second", and the like attached to the components in another portion of this specification or claims.

[0029] Furthermore, depending on the case or state, "a film" and "a layer" can be interchanged. For example, "a conductive layer" can be changed to "a conductive film". Furthermore, for example, "an insulating layer" can be changed to "an insulating film". Moreover, for example, "a semiconductor layer" can be changed to "a semiconductor film".

[0030] Further, the transistor is one of semiconductor elements, and can realize a function of amplifying current or voltage, a switching operation of controlling on or off, and the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0031] Further, in the case of using transistors of different polarities or in the case where the direction of current flowing in a circuit is changed, the functions of the "source" and the "drain" are sometimes exchanged with each other. Therefore, in this specification, the "source" and the "drain" can be used with each other by exchange.

[0032] In this specification and the like, "electrically connected" includes the case where components are connected through an "element having a certain function". Here, the "element having a certain function" is not particularly limited as long as it can receive and transmit an electric signal between objects to be connected. For example, the "element having a certain function" includes a switching element such as a transistor, a resistor, a coil, another element having a certain function, in addition to an electrode or a wiring.

[0033] In this specification and the like, in the case where not particularly stated otherwise, an off-state current refers to a leakage current between a source and a drain when a transistor is in an off state (also referred to as a non-conducting state, a blocking state). In the case where not particularly stated otherwise, in an n-channel transistor, the off state refers to a state where a voltage V gs is lower than a threshold voltage V th (p-channel transistor V gs is higher than V th ).

[0034] In this specification and the like, a normally-on property refers to a state where a channel exists even when no voltage is applied to a gate, and current flows through a transistor. Further, a normally-off property refers to a state where no current flows through a transistor when no voltage is applied to a gate or a ground potential is supplied to the gate.

[0035] In this specification and the like, "planar shapes are substantially the same" means that at least a part of edges of each of layers in a stack is overlapped. For example, a case where an upper layer and a lower layer are processed by the same mask pattern or a mask pattern which is a part of the same mask pattern is included. However, in fact, the edges are not overlapped in some cases, so that the upper layer is positioned inside the lower layer or the upper layer is positioned outside the lower layer, and such a case can also be said "planar shapes are substantially the same". When the planar shapes are the same or substantially the same, it can also be said that end portions are aligned or substantially aligned.

[0036] Further, in this specification and the like, a planar shape of a component means an outline shape of the component when viewed from a planar surface. Further, viewed from a planar surface means a case where the component is viewed from a normal direction of a surface of a support (e.g., a substrate) on which the component is formed or a surface of a formed surface.

[0037] In this specification and the like, a tapered shape means a shape in which at least a part of a side surface of a component is inclined with respect to a substrate surface or a formed surface. For example, a region in which an angle (also referred to as a tapered angle) formed by an inclined side surface and a substrate surface or a formed surface is greater than 0° and less than 90° is preferably included. Here, the side surface of the component, the substrate surface, and the formed surface do not necessarily have to be completely flat, and can be approximately planar with a slight curvature or approximately planar with fine irregularities.

[0038] Note that in this specification and the like, an oxynitride refers to a material in which the content of oxygen is higher than that of nitrogen in its composition. A nitride oxide refers to a material in which the content of nitrogen is higher than that of oxygen in its composition. Here, an oxide film includes a film including an oxynitride, and a nitride film includes a film including a nitride oxide.

[0039] In this specification and the like, in the case where it is stated that A is in contact with B, at least a part of A is in contact with B. Thus, for example, it can be said that A has a region in contact with B.

[0040] In this specification and the like, in the case where it is stated that A is positioned on B, at least a part of A is positioned on B. Thus, for example, it can be said that A has a region positioned on B.

[0041] In this specification and the like, in the case where it is stated that A overlaps with B, at least a part of A overlaps with B. Thus, for example, it can be said that A has a region overlapping with B.

[0042] In this specification and the like, a device manufactured using a metal mask or an FMM (Fine Metal Mask) is sometimes referred to as a device having an MM (Metal Mask) structure. Further, in this specification and the like, a device manufactured without using a metal mask or an FMM is sometimes referred to as a device having an MML (Metal Mask Less) structure.

[0043] In this specification and the like, a structure in which light emitting layers are separately manufactured between light emitting elements (also referred to as light emitting devices) different in emission wavelength is sometimes referred to as an SBS (Side By Side) structure. The SBS structure can improve the degree of freedom of selection of materials and structures because the materials and the structures can be optimized for each light emitting element, and can easily achieve improvement in luminance and reliability.

[0044] In this specification and the like, a hole or an electron is sometimes referred to as a "carrier". Specifically, a hole injection layer or an electron injection layer is sometimes referred to as a "carrier injection layer", a hole transport layer or an electron transport layer is sometimes referred to as a "carrier transport layer", and a hole blocking layer or an electron blocking layer is sometimes referred to as a "carrier blocking layer". Note that the above-described carrier injection layer, carrier transport layer, and carrier blocking layer are not always clearly distinguishable. Furthermore, one layer sometimes functions as two or all of a carrier injection layer, a carrier transport layer, and a carrier blocking layer.

[0045] In this specification and the like, a light-emitting element includes, between a pair of electrodes, an EL layer. The EL layer includes at least a light-emitting layer. Here, as a layer included in the EL layer (also referred to as a functional layer), a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier blocking layer (a hole blocking layer and an electron blocking layer) can be given. In this specification and the like, a light-receiving element (also referred to as a light-receiving device) includes, between a pair of electrodes, at least an active layer serving as a photoelectric conversion layer. In this specification and the like, one of a pair of electrodes is referred to as a pixel electrode, and the other is referred to as a common electrode.

[0046] In this specification and the like, a sacrificial layer (also referred to as a mask layer) is at least positioned over a light-emitting layer (more specifically, a layer included in an EL layer and processed into an island shape) and has a function of protecting the light-emitting layer in a manufacturing process.

[0047] In this specification and the like, an island shape means a state where two or more layers formed in the same process using the same material are physically separated. For example, an island-shaped light-emitting layer means a state where the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0048] In this specification and the like, disconnection means a phenomenon in which a layer, a film, or an electrode is disconnected due to the shape of a formed surface (e.g., a step or the like).

[0049] (Embodiment 1) In this embodiment, a structure example and a manufacturing method example of a semiconductor device of one embodiment of the present application will be described.

[0050] In a transistor included in a semiconductor device of one embodiment of the present application (also referred to as a transistor of one embodiment of the present application), a source electrode and a drain electrode are positioned at different levels, and current flowing through a semiconductor layer flows in the direction of the levels. In other words, it can be said that the channel length direction has a component of the direction of the levels (the vertical direction), and the transistor of one embodiment of the present application can also be referred to as a vertical transistor or a vertical channel transistor.

[0051] More specifically, an insulating layer serving as a spacer is provided between a lower electrode serving as one of a source electrode and a drain electrode of a transistor and an upper electrode serving as the other. Note that in the following description, the insulating layer serving as a spacer is sometimes simply referred to as a spacer, but the spacer can also be referred to as an insulating layer. A first opening portion reaching the lower electrode is provided in the spacer, and a second opening portion having an area overlapping with the first opening portion is provided in the upper electrode.

[0052] Further, the semiconductor layer forming a channel has an area in contact with the lower electrode and an area in contact with the upper electrode, and has an area inside the first opening portion and an area inside the second opening portion. A gate insulating layer and a gate electrode are provided inside the first opening portion and inside the second opening portion in a manner overlapping with the semiconductor layer. Since the source electrode, the semiconductor layer, and the drain electrode can be provided in an overlapping manner, the occupied area can be greatly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged on a plane.

[0053] Further, since the channel length direction of the transistor having the above structure has a component in the vertical direction, the channel length can be made smaller than the limit resolution of an exposure device. Thus, for example, a transistor with a large on-state current can be provided. However, in the case where the channel length is shortened, the saturation property of the transistor is sometimes lowered. Thus, for example, when the above transistor is used as a driver transistor of a light-emitting device, the current flowing through a light-emitting element is unstable, and the luminance of the light-emitting element is sometimes unstable. For example, unevenness in the current flowing through the light-emitting element over time occurs, and unevenness in the luminance of the light-emitting element over time occurs in the case of displaying a still image.

[0054] In this specification and the like, a driver transistor of a light-emitting device refers to a transistor having a function of controlling a current flowing through a light-emitting element of a pixel included in a display device. For example, one of a source and a drain of the driver transistor is electrically connected to one electrode of the light-emitting element. Further, in the case where a pixel has a capacitor, one electrode of the capacitor can be electrically connected to one of a source and a drain of a driver transistor and one electrode of a light-emitting element, and the other electrode of the capacitor can be electrically connected to a gate of the driver transistor.

[0055] Thus, in the transistor of one embodiment of the present application, a back gate electrode is provided. The back gate electrode is provided inside the first opening portion of the spacer. For example, the back gate electrode is provided in a manner having an area in contact with a side surface of the spacer positioned inside the first opening portion and an area in contact with a top surface of the lower electrode. Further, the above gate electrode can be referred to as a front gate electrode. Alternatively, the above gate electrode can be referred to as a first gate electrode and the back gate electrode can be referred to as a second gate electrode. Further, the back gate electrode can be referred to as a first gate electrode and the above gate electrode can be referred to as a second gate electrode.

[0056] With the above structure, the back gate electrode is electrically connected to the lower electrode which serves as one of the source electrode and the drain electrode of the transistor. Thus, when the lower electrode is used as the source electrode of the transistor, a phenomenon that a barrier between the source and the channel of the transistor is lowered due to a drain electric field, i.e., a DIBL (Drain-Induced Barrier Lowering) effect, is suppressed. Therefore, the saturation property of the transistor can be improved. By using the transistor with high saturation property for a display device, specifically, a driving transistor of a light emitting device, the display device can display a high-quality image. Further, when the lower electrode is used as the drain electrode of the transistor, the transistor of one embodiment of the present application can be used as a diode.

[0057] When the above transistor is manufactured, first, the lower electrode, the spacer, and the upper electrode are formed in this order. Next, the second opening portion is formed in the upper electrode, and the first opening portion is formed in the spacer. Then, the conductive film is formed so as to cover the first opening portion. Specifically, the conductive film is formed so as to cover side surfaces of the spacer positioned in the first opening portion and a top surface of the lower electrode exposed by the first opening portion. For example, the conductive film is formed so as to have a region in contact with the side surfaces of the spacer positioned in the first opening portion and a region in contact with the lower electrode.

[0058] After the conductive film is deposited, the conductive film is subjected to anisotropic etching. Thus, the back gate electrode can be formed so as to be electrically connected to the lower electrode inside the first opening portion. The back gate electrode can be formed along the side surfaces of the spacer positioned in the first opening portion so as to have a region in contact with the lower electrode inside the first opening portion.

[0059] Next, the insulating film is formed so as to cover the back gate electrode. Then, the back gate insulating layer is formed so as to cover the back gate electrode by subjecting the insulating film to anisotropic etching. Further, the gate insulating layer can be referred to as a front gate insulating layer. Alternatively, the above gate insulating layer can be referred to as a first gate insulating layer and the back gate insulating layer can be referred to as a second gate insulating layer. Further, the back gate insulating layer can be referred to as a first gate insulating layer and the above gate insulating layer can be referred to as a second gate insulating layer.

[0060] Then, the semiconductor layer, the gate insulating layer, and the gate electrode are formed. Thus, the transistor of one embodiment of the present application can be manufactured.

[0061] In the case where the back gate electrode is formed using anisotropic etching, a mask does not need to be used unlike in the case where the back gate electrode is formed using photolithography, for example. Thus, by using anisotropic etching, the back gate electrode can be formed in such a manner that, for example, the alignment accuracy of a mask is not taken into account. As described above, even if the first opening portion in which the back gate electrode is formed is miniaturized, the back gate electrode can be prevented from not being formed in, for example, the inside of the first opening portion. Thus, the transistor of one embodiment of the present application can be a miniaturized transistor.

[0062] <Structure Example 1 of Semiconductor Device> FIG. 1A is a plan view illustrating a structure example of a semiconductor device of one embodiment of the present application, and illustrates a structure example of a transistor 100 included in the semiconductor device. In FIG. 1A , part of the components is omitted. Part of the components is also omitted in the plan views shown below.

[0063] FIG. 1B is a cross-sectional view taken along the dotted line A1-A2 shown in FIG. 1A , a cross-sectional view taken along the dotted line B1-B2 shown in FIG. 1C , and a cross-sectional view taken along the dotted line C1-C2 shown in FIG. 1A . FIG. 2A , FIG. 2B , and FIG. 2C are plan views in which part of the components in FIG. 1A is omitted.

[0064] The semiconductor device of one embodiment of the present application includes a substrate 102, an insulating layer 110 over the substrate 102, and a transistor 100. The transistor 100 includes a conductive layer 112a, a conductive layer 112b, a conductive layer 103, an insulating layer 105, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104. Each layer included in the transistor 100 can have a single-layer structure or a stacked-layer structure.

[0065] The conductive layer 112a is provided over the substrate 102. The conductive layer 112a is used as one of a source electrode and a drain electrode of the transistor 100.

[0066] The insulating layer 110 is provided over the substrate 102 and the conductive layer 112a. The insulating layer 110 can have a region in contact with a top surface of the conductive layer 112a and a region in contact with a side surface of the conductive layer 112a. An opening portion 141 reaching the conductive layer 112a is provided in the insulating layer 110. Further, an insulating layer can be provided between the substrate 102 and the conductive layer 112a and the insulating layer 110. The insulating layer is used as a base insulating layer, for example.

[0067] The conductive layer 112b is provided over the insulating layer 110. The conductive layer 112b can have a region in contact with the top surface of the insulating layer 110. An opening portion 143 having a region overlapping with the opening portion 141 is provided in the conductive layer 112b. The conductive layer 112b is used as the other of the source and drain electrodes of the transistor 100.

[0068] As described above, the conductive layer 112a is provided below the insulating layer 110 and the conductive layer 112b is provided over the insulating layer 110. Thus, the conductive layer 112a can be referred to as a lower electrode of the transistor 100 and the conductive layer 112b can be referred to as an upper electrode of the transistor 100. As described above, the conductive layer 112a is used as one of the source and drain electrodes of the transistor 100 and the conductive layer 112b is used as the other of the source and drain electrodes of the transistor 100. As described above, the transistor 100 is a transistor whose one of the source and drain electrodes is a lower electrode and whose other of the source and drain electrodes is an upper electrode. Further, the insulating layer 110 is used as a spacer that controls the distance between the lower electrode and the upper electrode of the transistor 100.

[0069] The insulating layer 110 has a stacked structure of the insulating layer 110a over the substrate 102 and the conductive layer 112a, the insulating layer 110b over the insulating layer 110a, and the insulating layer 110c over the insulating layer 110b. That is, the insulating layer 110 has a three-layer stacked structure. FIG. 1B and FIG. 1C An example in which the insulating layer 110 has a three-layer stacked structure is shown. Note that the insulating layer 110 can not have a three-layer stacked structure, and can have a single-layer structure, for example.

[0070] The insulating layer 110a can have a region in contact with the top surface of the conductive layer 112a and a region in contact with the side surface of the conductive layer 112a. The insulating layer 110c can have a region in contact with the bottom surface of the conductive layer 112b. In other words, the conductive layer 112b can have a region in contact with the top surface of the insulating layer 110c.

[0071] The opening portion 143 is provided in the region of the conductive layer 112b overlapping with the conductive layer 112a. Further, the conductive layer 112b is preferably not provided in the inside of the opening portion 141. That is, the conductive layer 112b preferably has no region in contact with the side surface of the insulating layer 110 positioned in the opening portion 141.

[0072] The conductive layer 103 is provided in the inside of the opening portion 141 in a manner electrically connected to the conductive layer 112a. The conductive layer 103 has, for example, a region in contact with the conductive layer 112a, which is provided along a side surface of the insulating layer 110 in the inside of the opening portion 141. The conductive layer 103 can have a region in contact with a side surface of the insulating layer 110 in the inside of the opening portion 141. Note that in the case where the conductive layer 103 has a region in contact with the conductive layer 112a, the boundary between the conductive layer 103 and the conductive layer 112a is not always clear.

[0073] The uppermost part of the conductive layer 103 is preferably positioned below the top end portion of the opening portion 141 side of the insulating layer 110. That is, the conductive layer 103 is preferably not provided in the inside of the opening portion 143 included in the conductive layer 112b. Thus, for example, the conductive layer 103 can be prevented from being in contact with the conductive layer 112b and short-circuiting. Note that although the conductive layer 103 is not provided in the inside of the opening portion 143 included in the conductive layer 112b in the above embodiment, the conductive layer 103 can be provided in the inside of the opening portion 143 included in the conductive layer 112b. FIG. 1B and FIG. 1C An example is shown in which the conductive layer 103 is in contact with side surfaces of the insulating layer 110a and the insulating layer 110b in the inside of the opening portion 141 and is not in contact with a side surface of the insulating layer 110c in the inside of the opening portion 141, but the conductive layer 103 can have a region in contact with a side surface of the insulating layer 110c in the inside of the opening portion 141.

[0074] The conductive layer 103 can be formed by the following method: after a conductive film is formed so as to cover the opening portion 141 and the opening portion 143, the conductive film is subjected to anisotropic etching. Thus, the conductive layer 112a can be formed in the inside of the opening portion 141 in a manner electrically connected to the conductive layer 112a.

[0075] In the case where the conductive layer 103 is formed by anisotropic etching, a mask does not need to be used, unlike in the case where the conductive layer 103 is formed by photolithography, for example. Thus, by anisotropic etching, the conductive layer 103 can be formed in a manner not taking into account the alignment accuracy of a mask, for example. As described above, even when the opening portion 141 in which the conductive layer 103 is formed is miniaturized, the conductive layer 103 can be prevented from not being formed in the inside of the opening portion 141, for example. Thus, the transistor 100 can be a miniaturized transistor.

[0076] The insulating layer 105 is provided in a manner covering the conductive layer 103 in the inside of the opening portion 141. The insulating layer 105 has, for example, a region in contact with the conductive layer 103 in the inside of the opening portion 141 and a region in contact with the conductive layer 112a.

[0077] The insulating layer 105 can be formed by performing anisotropic etching on an insulating film formed so as to cover the opening portion 141 and the opening portion 143. In this case, for example, in a case where anisotropic etching is performed until at least a part of the top surface of the conductive layer 112b is exposed, the uppermost portion of the insulating layer 105 can be aligned with or substantially aligned with the top surface of the conductive layer 112b. When the uppermost portion of the insulating layer 105 is aligned with or substantially aligned with the top surface of the conductive layer 112b, the insulating layer 105 can have a region in contact with the side surface of the conductive layer 112b positioned inside the opening portion 143.

[0078] When the insulating layer 105 is formed by anisotropic etching, the insulating layer 105a is sometimes provided so as to cover at least a part of the side surface of the conductive layer 112b, specifically, the side surface on the side opposite to the opening portion 143. The insulating layer 105a can have a region in contact with the side surface of the conductive layer 112b on the side opposite to the opening portion 143. The insulating layer 105a is sometimes formed as a result of the formation process of the insulating layer 105. For example, when the uppermost portion of the insulating layer 105 is positioned above the top surface of the insulating layer 110, for example, the top end portion on the side of the opening portion 141 of the insulating layer 110, the insulating layer 105a is sometimes provided. For example, when the insulating layer 105 has a region in contact with the side surface of the conductive layer 112b positioned inside the opening portion 143, the insulating layer 105a is sometimes provided. The insulating layer 105a is formed, for example, as a residue when the insulating layer 105 is formed. Note that the insulating layer 105a is sometimes not provided. For example, when the uppermost portion of the insulating layer 105 is aligned with or positioned below the top surface of the insulating layer 110, for example, the top end portion on the side of the opening portion 141 of the insulating layer 110, the insulating layer 105a is sometimes not provided.

[0079] By forming the insulating layer 105 in a manner that the insulating layer 105a can be provided, the conductive layer 103 can be prevented from being exposed as a result of the anisotropic etching described above. Thus, the conductive layer 103 can be prevented from being in contact with the semiconductor layer 108 and short-circuited.

[0080] FIG. 2A is a view in which the conductive layer 104 and the semiconductor layer 108 in FIG. 1A are omitted. As shown in FIG. 2A , the insulating layer 105 is provided inside the opening portion 141 and the opening portion 143 along the periphery thereof when viewed in plan.

[0081] FIG. 2B is a view in which the insulating layer 105 in FIG. 2A is also omitted. As shown in FIG. 1B , FIG. 1C , and FIG. 2B , the conductive layer 103 is provided inside the opening portion 141 along the periphery thereof when viewed in plan.

[0082] FIG. 2C is also omitted FIG. 2B A diagram of the insulating layer 110 in FIG. 1 is shown. As shown in FIG. 1, the opening portion 141 has a region overlapping with the conductive layer 103. FIG. 2C

[0083] The semiconductor layer 108 has a region inside the opening portion 141 and a region inside the opening portion 143. The semiconductor layer 108 is provided so as to cover the insulating layer 105. The semiconductor layer 108 has a region in contact with the conductive layer 112a, a region in contact with the insulating layer 105, and a region in contact with the conductive layer 112b. Further, the semiconductor layer 108 is provided so as to have a region inside the opening portion 141 opposing the conductive layer 103 through the insulating layer 105. In other words, the semiconductor layer 108 is provided so as to have a region inside the opening portion 141 overlapping with the semiconductor layer 108 through the insulating layer 105.

[0084] The insulating layer 106 is provided on the insulating layer 110 so as to cover the insulating layer 105a, the conductive layer 112b, and the semiconductor layer 108. The insulating layer 106 is provided on the semiconductor layer 108 so as to have a region inside the opening portion 141 and a region inside the opening portion 143. The insulating layer 106 is used as a gate insulating layer of the transistor 100.

[0085] In the case where the insulating layer 105a is provided in the semiconductor device of one embodiment of the present application, the insulating layer 105a is provided between the insulating layer 110 and the insulating layer 106. As described above, the insulating layer 105a can have a region in contact with a side surface of the conductive layer 112b on the side opposite to the opening portion 143.

[0086] The conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 has a region inside the opening portion 141 and a region inside the opening portion 143. The conductive layer 104 is provided so as to have a region inside the opening portion 141 and inside the opening portion 143 opposing the semiconductor layer 108 through the insulating layer 106. In other words, the conductive layer 104 is provided so as to have a region inside the opening portion 141 and inside the opening portion 143 overlapping with the semiconductor layer 108 through the insulating layer 106. The conductive layer 104 is used as a gate electrode of the transistor 100.

[0087] ​As described above, the semiconductor layer 108 is provided so as to have a region that opposes the conductive layer 103 through the insulating layer 105 inside the opening portion 141. Further, the conductive layer 104 is provided so as to have a region that opposes the semiconductor layer 108 through the insulating layer 106 inside the opening portion 141. As described above, the conductive layer 104 is provided so as to have a region that opposes the conductive layer 103 through the insulating layer 105, the semiconductor layer 108, and the insulating layer 106 inside the opening portion 141. In other words, the conductive layer 103 and the conductive layer 104 have a region that overlaps through the insulating layer 105, the semiconductor layer 108, and the insulating layer 106 inside the opening portion 141.

[0088] Thus, the conductive layer 104 can be used as the gate electrode of the transistor 100, and the conductive layer 103 can be used as the gate electrode of the transistor 100. In this case, the conductive layer 103 can be referred to as a back gate electrode. In the case where the conductive layer 103 is referred to as a back gate electrode, the conductive layer 104 can be referred to as a front gate electrode. Further, the conductive layer 104 can be referred to as a first gate electrode and the conductive layer 103 can be referred to as a second gate electrode. Further, the conductive layer 103 can be referred to as a first gate electrode and the conductive layer 104 can be referred to as a second gate electrode. Hereinafter, the conductive layer 103 is referred to as a back gate electrode.

[0089] The back gate electrode of the transistor 100 has a region that is in contact with the top surface of the conductive layer 112a inside the opening portion 141. Thus, the back gate electrode of the transistor 100 is supplied with the potential of the conductive layer 112a. Thus, when the conductive layer 112a is used as the source electrode of the transistor 100, occurrence of the DIBL effect is suppressed. Thus, the transistor 100 can be, for example, a transistor whose saturation property is higher than that of a transistor that does not include the conductive layer 103. Further, by using the transistor 100 whose saturation property is high for a display device, specifically, a driver transistor of a light-emitting device, the display device can display a high-quality image. Further, when the conductive layer 112a is used as the drain electrode of the transistor 100, the transistor 100 can be used as a diode.

[0090] As described above, the driver transistor of a light-emitting device refers to a transistor that has a function of controlling current flowing through a light-emitting element included in a display device. For example, one of the source and the drain of the driver transistor is electrically connected to one electrode of the light-emitting element.

[0091] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can all be used as a wiring, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and a wiring, the area occupied by the transistor 100 and the wiring can be reduced. Thus, the area occupied by the circuit can be reduced to achieve a small semiconductor device.

[0092] An insulating layer 107 is provided on the conductive layer 104 and the insulating layer 106. The insulating layer 107 is provided so as to cover the conductive layer 104.

[0093] The insulating layer 107 is used as a protective layer. The insulating layer 107 preferably uses a material in which impurities are not easily diffused. By providing the insulating layer 107, diffusion of impurities from the outside into the transistor 100 can be effectively suppressed, and thus the reliability of the semiconductor device can be improved. As the impurities, for example, water and hydrogen can be given. The insulating layer 107 includes one or both of an inorganic insulating film and an organic insulating film, for example. The insulating layer 107 can have a stacked structure of an inorganic insulating film and an organic insulating film.

[0094] When the insulating layer 107 uses an inorganic insulating film, the insulating layer 107 can use a material that can be used for the insulating layer 110. As the inorganic insulating film that can be used for the insulating layer 107, for example, an oxide insulating film and a nitride insulating film can be given. Specifically, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminum oxide can be used for the insulating layer 107. When the insulating layer 107 uses an organic insulating film, for example, one or both of an acrylic resin and a polyimide resin can be used.

[0095] FIG. 3A is a plan view illustrating a structure example of the semiconductor device of one embodiment of the present application, and illustrates a structure example of the transistor 100. In FIG. 3A , in FIG. 1A , a width D143 and a channel width W100 are illustrated in the plan view. FIG. 3B is an enlarged view of a structure including FIG. 1B , and illustrates a structure example of the transistor 100. FIG. 3B is a cross-sectional view along the dotted line A1-A2 illustrated in FIG. 3A . In FIG. 3B , a width D143, a channel width W100, a channel length L100, a thickness T110, and an angle Θ110 are illustrated.

[0096] In the semiconductor layer 108, a region in contact with the conductive layer 112a is used as one of a source region and a drain region, a region in contact with the conductive layer 112b is used as the other of the source region and the drain region, and a region provided between the source region and the drain region is used as a channel formation region.

[0097] In FIG. 3B , the channel length L100 of the transistor 100 is indicated by a double-headed arrow in a dashed line. As FIG. 3B illustrated, the channel length L100 can be the shortest distance between a portion of the semiconductor layer 108 in contact with the conductive layer 112a and a portion in contact with the conductive layer 112b when viewed in cross section.

[0098] The channel length L100 of the transistor 100 is determined in accordance with the thickness T110 of the insulating layer 110 and the angle θ110 formed by the side surface of the insulating layer 110 in the opening portion 141 and the surface of the insulating layer 110 (here, the top surface of the conductive layer 112a) on which the surface is formed. Thus, for example, the channel length L100 can be set to a value smaller than the resolution limit of an exposure device, and a transistor with a channel length that cannot be achieved by an exposure device used in mass production of conventional flat panel displays (e.g., a minimum line width of 2 μm or 1.5 μm or the like) can be achieved. Further, a transistor with a channel length of less than 10 nm can be achieved without using an exposure device that is very expensive and used in the most advanced LSI technology.

[0099] The channel length L100 is preferably greater than or equal to 0.01 μm and less than 3.0 μm, more preferably greater than or equal to 0.05 μm and less than 3.0 μm, more preferably greater than or equal to 0.10 μm and less than 3.0 μm, more preferably greater than or equal to 0.15 μm and less than 3.0 μm, more preferably greater than or equal to 0.20 μm and less than 3.0 μm, more preferably greater than or equal to 0.20 μm and less than 2.5 μm, more preferably greater than or equal to 0.20 μm and less than 2.0 μm, more preferably greater than or equal to 0.20 μm and less than 1.5 μm, more preferably greater than or equal to 0.30 μm and less than 1.5 μm, more preferably greater than or equal to 0.30 μm and less than 1.2 μm, more preferably greater than or equal to 0.40 μm and less than 1.2 μm, more preferably greater than or equal to 0.40 μm and less than 1.0 μm, and more preferably greater than or equal to 0.50 μm and less than 1.0 μm.

[0100] By reducing the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit that can operate at high speed can be manufactured. Thus, by applying the semiconductor device of one embodiment of the present application to a display device, the frame frequency of the display device can be increased.

[0101] By adjusting the thickness T110 and the angle θ110 of the insulating layer 110, the channel length L100 can be controlled. In FIG. 3B In FIG. 1, the thickness T110 of the insulating layer 110 is indicated by a dotted line double-headed arrow.

[0102] The thickness T110 of the insulating layer 110 is preferably 0.01 μm or more and less than 3.0 μm, more preferably 0.05 μm or more and less than 3.0 μm, more preferably 0.10 μm or more and less than 3.0 μm, more preferably 0.15 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and 1.2 μm or less, more preferably 0.40 μm or more and 1.2 μm or less, more preferably 0.40 μm or more and 1.0 μm or less, more preferably 0.50 μm or more and 1.0 μm or less.

[0103] The channel width W100 is determined by the planar shape of the opening portion 143. In FIG. 3A and FIG. 3B The width D143 of the opening portion 143 is indicated by a double-headed arrow of a double dot chain line in FIGS. 1A to 1C. The width D143 means a short side of a smallest rectangle circumscribing the opening portion 143 when viewed in plan. When the opening portion 143 is formed by photolithography, the width D143 of the opening portion 143 is equal to or more than the limit resolution of an exposure device. The width D143 is preferably, for example, 0.20 μm or more and less than 5.0 μm, more preferably 0.20 μm or more and less than 4.5 μm, more preferably 0.20 μm or more and less than 4.0 μm, more preferably 0.20 μm or more and less than 3.5 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and 1.2 μm or less, more preferably 0.40 μm or more and 1.2 μm or less, more preferably 0.40 μm or more and 1.0 μm or less, more preferably 0.50 μm or more and 1.0 μm or less. Note that when the planar shape of the opening portion 143 is circular, the width D143 corresponds to the diameter of the opening portion 143, and the channel width W10 can be equal to the length of the periphery of the opening portion 143 when viewed in plan, which can be calculated as "D143 x π".

[0104] Note that the width of the opening portion 141 and the width of the opening portion 143 are sometimes different. Further, the width of the opening portion 141 and the width of the opening portion 143 are sometimes changed in the depth direction. As the width of the opening, for example, an average of the width of the highest position of the insulating layer 110, the width of the lowest position, and the width of the position of the middle point thereof when viewed in cross section can be used. Alternatively, as the width of the opening, for example, any of the width of the highest position of the insulating layer 110, the width of the lowest position, and the width of the position of the middle point thereof when viewed in cross section can be used.

[0105] For example, as illustrated in FIG. 1A, the planar shape of the opening portion 141 and the planar shape of the opening portion 143 are preferably both circular. By setting the planar shape of the opening portion to be circular, the processing accuracy at the time of forming the opening portion can be improved, and a fine opening portion can be formed. Note that in this specification and the like, a circle does not necessarily mean a perfect circle. FIG. 3A

[0106] In this specification and the like, the planar shape of the opening portion 141 refers to the shape of the top end portion of the opening portion 141 side of the insulating layer 110. Further, the planar shape of the opening portion 143 refers to the shape of the bottom end portion of the opening portion 143 side of the conductive layer 112b.

[0107] For example, as illustrated in FIG. 1A, the planar shape of the opening portion 141 and the planar shape of the opening portion 143 are preferably both circular. By setting the planar shape of the opening portion to be circular, the processing accuracy at the time of forming the opening portion can be improved, and a fine opening portion can be formed. Note that in this specification and the like, a circle does not necessarily mean a perfect circle. FIG. 3A FIG. 3B At this time, as illustrated in FIG. 1A, the bottom end portion of the opening portion 143 side of the conductive layer 112b and the top end portion of the opening portion 141 side of the insulating layer 110 are preferably coincident or substantially coincident. The bottom surface of the conductive layer 112b refers to the surface on the side of the insulating layer 110. The top surface of the insulating layer 110 refers to the surface on the side of the conductive layer 112b.

[0108] The side surface of the insulating layer 110 positioned in the opening portion 141 preferably has a tapered shape or a vertical shape. The angle θ110 of the side surface of the insulating layer 110 positioned in the opening portion 141 and the surface of the insulating layer 110 formed by the formed surface (here, the top surface of the insulating layer 110a) is preferably 90 degrees or less. By reducing the angle θ110, the coverage of a layer provided over the insulating layer 110 (e.g., the semiconductor layer 108) can be improved. Further, the smaller the angle θ110, the larger the channel length L100 can be, and the larger the angle θ110, the smaller the channel length L100 can be. FIG. 1B FIG. 1C FIG. 3B An example in which the side surface of the insulating layer 110 positioned in the opening portion 141 has a tapered shape (the angle θ110 is less than 90 degrees) is illustrated.

[0109] In this embodiment, the planar shape of the opening portion 141 and the planar shape of the opening portion 143 are preferably both circular. By setting the planar shape of the opening portion to be circular, the processing accuracy at the time of forming the opening portion can be improved, and a fine opening portion can be formed. Note that in this specification and the like, a circle does not necessarily mean a perfect circle. FIG. 3B ​​​​In this case, the uppermost part of the conductive layer 103 is a portion 121. Further, the top end portion of the opening portion 141 side of the insulating layer 110 is a portion 123. As described above, the portion 121 is preferably positioned below the portion 123. Thus, for example, the conductive layer 103 can be prevented from contacting the conductive layer 112b and short-circuiting. Note that although the conductive layer 103 is in contact with the side surface of the insulating layer 110a and the insulating layer 110b in the opening portion 141, the conductive layer 103 can also have a region in contact with the side surface of the insulating layer 110c in the opening portion 141. FIG. 3B In this case, the uppermost part of the conductive layer 103 is a portion 121. Further, the top end portion of the opening portion 141 side of the insulating layer 110 is a portion 123. As described above, the portion 121 is preferably positioned below the portion 123. Thus, for example, the conductive layer 103 can be prevented from contacting the conductive layer 112b and short-circuiting. Note that although the conductive layer 103 is in contact with the side surface of the insulating layer 110a and the insulating layer 110b in the opening portion 141, the conductive layer 103 can also have a region in contact with the side surface of the insulating layer 110c in the opening portion 141.

[0110] Further, in this case, the region of the semiconductor layer 108 opposite to the conductive layer 103 is a region 125. The region 125 is opposite to the conductive layer 103 with the insulating layer 105 therebetween. Further, in this case, the region of the conductive layer 104 serving as the gate electrode of the transistor 100 opposite to the conductive layer 103 is a region 127. The region 127 is opposite to the conductive layer 103 with the insulating layer 105, the semiconductor layer 108, and the insulating layer 106 therebetween. FIG. 3B FIG. 3B In this case, the uppermost part of the conductive layer 103 is a portion 121. Further, the top end portion of the opening portion 141 side of the insulating layer 110 is a portion 123. As described above, the portion 121 is preferably positioned below the portion 123. Thus, for example, the conductive layer 103 can be prevented from contacting the conductive layer 112b and short-circuiting. Note that although the conductive layer 103 is in contact with the side surface of the insulating layer 110a and the insulating layer 110b in the opening portion 141, the conductive layer 103 can also have a region in contact with the side surface of the insulating layer 110c in the opening portion 141.

[0111] An electric field of the conductive layer 103 serving as a back gate electrode can be applied to the region 125. Further, an electric field of the conductive layer 103 can be applied to a region near the region 125 in some cases. As described above, the conductive layer 103 is supplied with a potential of the conductive layer 112a serving as one of a source electrode and a drain electrode of the transistor 100. Thus, when the conductive layer 112a is used as the source electrode of the transistor 100, the occurrence of a DIBL effect is further suppressed in the region 125 and a region near the region 125, for example, as compared to the case where the transistor 100 does not include the conductive layer 103. Thus, as described above, the transistor 100 can be a transistor whose saturation property is higher than that of a transistor not including the conductive layer 103, for example.

[0112] ​Here, the shorter the distance between portion 121 and portion 123, in other words, the smaller the difference in height between portion 123 and portion 121 from the surface of substrate 102, the larger the area of ​​region 125 can be. Therefore, the area of ​​the region in the channel formation region of semiconductor layer 108 that is not supplied with the electric field of conductive layer 103 can be reduced. Thus, the occurrence of the DIBL effect can be appropriately suppressed, thereby improving the saturation of transistor 100. On the other hand, the longer the distance between portion 121 and portion 123, in other words, the greater the difference in height between portion 123 and portion 121 from the surface of substrate 102, the more effectively short-circuiting due to contact between conductive layer 103 and conductive layer 112b can be suppressed. Therefore, it is preferable to increase the height of portion 121 from the surface of substrate 102 as much as possible within the range where conductive layer 103 and conductive layer 112b do not contact. Note that the higher the height of part 121 from the surface of substrate 102, the larger the area of ​​not only region 125, but also the area of ​​region 127 can be.

[0113] FIG. 3B Examples are shown where the uppermost part of insulating layer 105 and the uppermost part of insulating layer 105a are aligned or substantially aligned with the top surface of conductive layer 112b. Specifically, examples are shown where the uppermost part of insulating layer 105 is aligned or substantially aligned with the top surface end of the conductive layer 112b on the side of the opening 143, and the uppermost part of insulating layer 105a is aligned or substantially aligned with the top surface end of conductive layer 112b on the side opposite to the opening 143. However, one aspect of the invention is not limited to this. FIG. 4A This is a cross-sectional view showing an example of the uppermost part of insulating layer 105 and the uppermost part of insulating layer 105a located between the bottom and top surfaces of conductive layer 112b. FIG. 4A In the example shown, the uppermost part of the insulating layer 105 is located between the bottom end and the top end of the conductive layer 112b on the side of the opening 143. Furthermore, the uppermost part of the insulating layer 105a is located between the bottom end and the top end of the conductive layer 112b on the side opposite to the opening 143.

[0114] FIG. 4B This is a cross-sectional view showing an example where the uppermost part of the insulating layer 105 is located below the bottom surface of the conductive layer 112b. FIG. 4B In the example shown, the uppermost part of the insulating layer 105 is located below the bottom end of the opening 143 on the side of the conductive layer 112b. Furthermore, in FIG. 4B In the example shown, the uppermost part of the insulating layer 105 may be located at the top end of the top surface on the side of the opening 141 of the insulating layer 110, that is, below part 123.

[0115] When the uppermost part of the insulating layer 105 is positioned below the bottom surface of the conductive layer 112b, the insulating layer 105a can not be provided. Note that even when the uppermost part of the insulating layer 105 is positioned above the bottom surface of the conductive layer 112b, the insulating layer 105a is not always provided.

[0116] FIG. 4B An example in which the uppermost part of the insulating layer 105 is positioned between the bottom surface and the top surface of the insulating layer 110c is shown, but one embodiment of the present application is not limited to this. For example, the uppermost part of the insulating layer 105 can be positioned between the bottom surface and the top surface of the insulating layer 110b.

[0117] By providing the transistor 100 with the structure shown in FIG. 1A, the semiconductor layer 108 can have a region in contact with the top surface of the conductive layer 112b and a region in contact with the side surface of the conductive layer 112b positioned in the opening portion 143. Thus, for example, the contact area between the semiconductor layer 108 and the conductive layer 112b can be increased compared to the case where the transistor 100 has the structure shown in FIG. 1B. Accordingly, the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. Thus, the occurrence of a contact failure or the like in the transistor 100 can be prevented. On the other hand, by providing the transistor 100 with the structure shown in FIG. 1A, the semiconductor layer 108 is less likely to be in contact with the conductive layer 103 and short-circuit compared to the case where the transistor 100 has the structure shown in FIG. 1B. FIG. 4A FIG. 4B FIG. 3B By providing the transistor 100 with the structure shown in FIG. 1A, the semiconductor layer 108 can have a region in contact with the top surface of the conductive layer 112b and a region in contact with the side surface of the conductive layer 112b positioned in the opening portion 143. Thus, for example, the contact area between the semiconductor layer 108 and the conductive layer 112b can be increased compared to the case where the transistor 100 has the structure shown in FIG. 1B. Accordingly, the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. Thus, the occurrence of a contact failure or the like in the transistor 100 can be prevented. On the other hand, by providing the transistor 100 with the structure shown in FIG. 1A, the semiconductor layer 108 is less likely to be in contact with the conductive layer 103 and short-circuit compared to the case where the transistor 100 has the structure shown in FIG. 1B. FIG. 3B FIG. 4A FIG. 4B

[0118] FIG. 5 is a cross-sectional view showing an example in which, in the conductive layer 112a shown in FIG. 1A, the thickness of a region in contact with the bottom surface of the semiconductor layer 108 or the bottom surface of the insulating layer 105 is thinner than that of a region overlapping with the conductive layer 103 or the insulating layer 110. In the example shown in FIG. 1C, it can be said that a recess 129 is formed in the region of the conductive layer 112a in contact with the bottom surface of the semiconductor layer 108 or the bottom surface of the insulating layer 105. FIG. 3B FIG. 5

[0119] In the conductive layer 112a, the height from the surface to be formed (here, the top surface of the substrate 102) to the lowest position of the bottom surface of the conductive layer 104 is the height H104. Further, the height from the top surface of the substrate 102 to the bottom surface of the insulating layer 110 or the conductive layer 103 is the height H112. The height H112 can be the thickness of the conductive layer 112a in a region other than the recess 129. FIG. 5

[0120] ​​​​​​​​By making the height H104 lower than the height H112, the electric field applied to the gate electrode of the channel formation region in the vicinity of the conductive layer 112a can be enhanced, and thus the on-state current of the transistor 100 can be increased. Further, the electric field applied to the gate electrode of the channel formation region can be made uniform. Further, even when the height H104 is equal to or substantially equal to the height H112, the electric field applied to the gate electrode of the channel formation region in the vicinity of the conductive layer 112a can be enhanced. Further, the electric field applied to the gate electrode of the channel formation region can be made uniform.

[0121] Here, when the electric field applied to the gate electrode of the channel formation region is not uniform, the electrical characteristics in the case where the conductive layer 112a is used as a source electrode and the conductive layer 112b is used as a drain electrode are sometimes different from the electrical characteristics in the case where the conductive layer 112a is used as a drain electrode and the conductive layer 112b is used as a source electrode. When the electric field applied to the gate electrode of the channel formation region of the transistor 100 is more uniform, the respective electrical characteristics can be made equal. Thus, the transistor 100 can be appropriately used in a circuit structure in which the source and the drain are switched.

[0122] In the transistor 100 illustrated in FIG. 1A, the conductive layer 103 can be used as a back gate electrode of the transistor 100. In the transistor 100 illustrated in FIG. 1A, the conductive layer 112a can be used as a back gate electrode of the transistor 100. FIG. 5 In the transistor 100 illustrated in FIG. 1A, the conductive layer 103 can be used as a back gate electrode of the transistor 100. In the transistor 100 illustrated in FIG. 1A, the conductive layer 112a can be used as a back gate electrode of the transistor 100. FIG. 5 In the transistor 100 illustrated in FIG. 1A, the conductive layer 103 can be used as a back gate electrode of the transistor 100. In the transistor 100 illustrated in FIG. 1A, the conductive layer 112a can be used as a back gate electrode of the transistor 100. FIG. 5 In the transistor 100 illustrated in FIG. 1A, the conductive layer 103 can be used as a back gate electrode of the transistor 100. In the transistor 100 illustrated in FIG. 1A, the conductive layer 112a can be used as a back gate electrode of the transistor 100.

[0123] Note that the thickness of the conductive layer 112a can be adjusted as appropriate so that the height H104 is lower than the height H112, for example. Further, the thickness of the conductive layer 112a can be adjusted as appropriate so that the height H104 is equal to or substantially equal to the height H112, for example. FIG. 5 The structure of the conductive layer 112a illustrated in FIG. 1A can be applied to other structural examples, such as those illustrated in other drawings. For example, the conductive layer 112a illustrated in FIG. 1A can have a structure in which the conductive layer 112a is in contact with the insulating layer 105. FIG. 4A The conductive layer 112a illustrated in FIG. 1A can have a recess 129. Further, the conductive layer 112a illustrated in FIG. 1A can have a structure in which the conductive layer 112a is in contact with the insulating layer 105. FIG. 4B The conductive layer 112a illustrated in FIG. 1A can have a recess 129. Further, the conductive layer 112a illustrated in FIG. 1A can have a structure in which the conductive layer 112a is in contact with the insulating layer 105.

[0124] For example, although the conductive layer 112a has a single-layer structure in the transistor 100 illustrated in FIG. 1A, the conductive layer 112a can have a stacked-layer structure of a plurality of layers. FIG. 5 For example, although the conductive layer 112a has a single-layer structure in the transistor 100 illustrated in FIG. 1A, the conductive layer 112a can have a stacked-layer structure of a plurality of layers. FIG. 6A FIG. 6B FIG. 7A ​​is a drawing illustrating an example of a two-layer stacked structure in which the conductive layer 112a has a conductive layer 112a1 and a conductive layer 112a2 which is positioned on the conductive layer 112a1. FIG. 6A is a plan view illustrating a structure example of the conductive layer 112a1, the conductive layer 112a2, the conductive layer 103, the opening portion 141, and the opening portion 143. Note that in FIG. 6A , the conductive layer 103 is not hatched. FIG. 6B is a cross-sectional view taken along the dotted line A1-A2 in FIG. 5 . FIG. 6A is a cross-sectional view taken along the plan view illustrated in FIG. 6B . FIG. 6A is a cross-sectional view taken along the dotted line A1-A2 in FIG. 7A . FIG. 6A is a cross-sectional view taken along the dotted line B1-B2 in .

[0125] In the examples illustrated in FIG. 6A , FIG. 6B , and FIG. 7A , the conductive layer 112a2 is provided so as to cover the side surface of the conductive layer 112a1. In the recess 129 of the conductive layer 112a, the conductive layer 112a2 is removed. In the recess 129, there is a region in which the bottom surface of the semiconductor layer 108 is in contact with the top surface of the conductive layer 112a1. Further, in the recess 129, there can be a region in which the bottom surface of the insulating layer 105 is in contact with the top surface of the conductive layer 112a1 and a region in which the side surface of the insulating layer 105 is in contact with the side surface of the conductive layer 112a2. Furthermore, there is a region in which the bottom surface of the conductive layer 103 is in contact with the top surface of the conductive layer 112a2.

[0126] For example, FIG. 6B illustrates an example in which the thickness of the conductive layer 112a1 in a region overlapping with the recess 129 is equal to the thickness of the conductive layer 112a1 in a region not overlapping with the recess 129, but one embodiment of the present application is not limited to this. For example, the thickness of the conductive layer 112a1 in a region overlapping with the recess 129 can be smaller than the thickness of the conductive layer 112a1 in a region not overlapping with the recess 129. That is, in the recess 129, not only the conductive layer 112a2 but also part of the conductive layer 112a1 can be processed. Further, the conductive layer 112a2 can be provided in the recess 129 without exposing the top surface of the conductive layer 112a1. That is, in the recess 129, part of the conductive layer 112a2 can be left without being completely removed. In this case, it can be said that the recess 129 is formed in the conductive layer 112a2. When part of the conductive layer 112a2 is left in the recess 129, the thickness of the conductive layer 112a2 in the recess 129 is smaller than the thickness of the conductive layer 112a2 in a region other than the recess 129.

[0127] As FIG. 6A and FIG. 6B indicated, the conductive layer 112a2 has a region extending in the A1-A2 direction. Thus, when a material with low resistivity, for example, a material with lower resistivity than the conductive layer 112al is used as the conductive layer 112a2, the wiring resistance of the conductive layer 112a can be reduced, and thus is preferable. For example, as the conductive layer 112al, a conductive oxide such as indium oxide, zinc oxide, an In-Sn oxide, an In-Zn oxide, an In-W oxide, an In-W-Zn oxide, an In-Ti oxide, an In-Ti-Sn oxide, an In-Sn oxide, an In-Sn-Si oxide, or a Ga-Zn oxide can be used. Further, as the conductive layer 112a2, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, and an alloy containing the metal element can be used.

[0128] Here, when a material with low resistivity is used as the conductive layer 103, the wiring resistance of the conductive layer 103 can be reduced, and thus is preferable. The conductive layer 103 preferably uses the same material as that used for the conductive layer 112a2, for example. For example, the conductive layer 112a2 and the conductive layer 103 can use the same material.

[0129] In the above case, for example, the etching selectivity of the conductive layer 112a and the conductive layer 103 is sometimes lower than that in the case where one of the conductive layer 112a2 and the conductive layer 103 is formed using a metal and the other is formed using a conductive oxide. Here, in the method for manufacturing a semiconductor device of one embodiment of the present application, a conductive film to be the conductive layer 103 can be formed, and the conductive layer 103 can be formed by processing the conductive film using an etching method, as will be described later in detail. If the conductive layer 112a is also processed when the conductive layer is processed, a recess 129 is formed in the conductive layer 112a. In that case, a material with high etching selectivity to the conductive layer 103, such as a conductive oxide, can be used as the conductive layer 112al to inhibit the conductive layer 112al from being processed. Thus, the conductive layer 112a can be prevented from being completely removed in a region overlapping with the bottom surface of the semiconductor layer 108. Thus, the bottom surface of the semiconductor layer 108 can be prevented from being in contact with the conductive layer 112a.

[0130] As described above, by using a material with high etching selectivity to the conductive layer 103 as the conductive layer 112al and a material with low resistivity as the conductive layer 112a2, a semiconductor device in which the transistor has high electric characteristics and high reliability can be provided. Further, the recess 129 can be easily formed in the conductive layer 112a, and thus the conductive layer 112a can be prevented from being completely removed in a region overlapping with the bottom surface of the semiconductor layer 108. Thus, the bottom surface of the semiconductor layer 108 can be prevented from being in contact with the conductive layer 112a. FIG. 5The explanation states that this makes it easy to form transistors with large on-state current.

[0131] FIG. 7B1 and FIG. 7B2 This is a cross-sectional view showing an example of a conductive layer 112a having a two-layer stacked structure of conductive layer 112a1 and conductive layer 112a2 on conductive layer 112a1, with the ends of conductive layer 112a1 aligned or substantially aligned with the ends of conductive layer 112a2. Regarding... FIG. 7B1 and FIG. 7B2 The planar structure example of transistor 100 shown can be referred to... FIG. 1A . FIG. 7B1 It is along FIG. 1A The cross-sectional view of the dotted line A1-A2 shown. FIG. 7B2 It is along FIG. 1A The cross-sectional view shown is the dotted line B1-B2.

[0132] exist FIG. 7B1 and FIG. 7B2 In the example shown, with FIG. 7A Compared to the example shown, the number of manufacturing steps for conductive layer 112a can be reduced. On the other hand, in FIG. 7A In the example shown, the step of the surface on which the layer (e.g., insulating layer 110) is formed on the conductive layer 112a is reduced, thereby improving the coverage of the layer. As a result, defects such as breaks or voids in the layer can be suppressed.

[0133] Although FIG. 6A to FIG. 7B2 An example is shown where the conductive layer 112a has a two-layer stacked structure, but the conductive layer 112a can also have a three-layer or more stacked structure. Furthermore, FIG. 6A to FIG. 7B2 The conductive layer 112a shown in the accompanying drawings, other than those shown, can also have a two-layer stacked structure or a three-layer or more stacked structure. For example, it can be... FIG. 6A to FIG. 7B2 The conductive layer 112a shown is used as FIG. 1A to FIG. 4B The conductive layer 112a shown is illustrated. For the conductive layer 112a shown in subsequent figures, it can also be used... FIG. 6A to FIG. 7B2 The conductive layer 112a is shown.

[0134] FIG. 8 It is shown that FIG. 6B The conductive layers 112a2 and 103 shown are cross-sectional views of an example of conductive layer 116. For example, sometimes it is not clearly visible... FIG. 6B The boundary between conductive layer 112a2 and conductive layer 103 is shown. For example, when conductive layer 112a2 and conductive layer 103 are made of the same type of material, sometimes the boundary between conductive layer 112a2 and conductive layer 103 cannot be seen. In this case, as shown... FIG. 8As shown, conductive layer 112a2 and conductive layer 103 are sometimes considered as a single conductive layer 116. Note that even if conductive layer 112a has a single-layer structure, sometimes the boundary between conductive layer 112a2 and conductive layer 103 cannot be clearly seen, as described above. In this case, conductive layer 112a and conductive layer 103 are sometimes considered as a single conductive layer 116.

[0135] Although FIG. 3B , FIG. 4A , FIG. 4B and FIG. 5 An example is shown in which the angle formed by the side surface of the conductive layer 112b located in the opening 143 and the surface on which the conductive layer 112b is formed (the top surface of the insulating layer 110) is equal to the angle θ110 formed by the side surface of the insulating layer 110 located in the opening 141 and the surface on which the insulating layer 110 is formed (the top surface of the conductive layer 112a). However, one aspect of the present invention is not limited to this. FIG. 9 It is shown FIG. 3B Cross-sectional views of the transistor 100 shown above at two different angles.

[0136] exist FIG. 9 In this configuration, the angle formed between the side surface of the conductive layer 112b located within the opening 143 and the surface on which the conductive layer 112b is formed (the top surface of the insulating layer 110) is angle θ112. Angle θ112 is preferably smaller than angle θ110. This reduces the step on the surface of layers such as the semiconductor layer 108 that are disposed to cover at least a portion of the opening 143. Therefore, the coverage of the layer can be improved. Consequently, defects such as breaks or voids in the layer can be suppressed.

[0137] For example, by using different methods to form openings 141 and 143, different angles θ110 and θ112 can be set. For example, by using a dry etching method to form opening 141 and a wet etching method to form opening 143, angle θ112 can be made smaller than angle θ110.

[0138] For example, although FIG. 3A An example is shown where the planar shape of opening 141 is the same as that of opening 143, but they may not be the same. FIG. 10A This is a plan view showing an example where the planar shape of the opening 141 is inconsistent with the planar shape of the opening 143, and showing the conductive layer 112a, the insulating layer 110 including the opening 141, and the conductive layer 112b including the opening 143. FIG. 10B Is to make FIG. 3B The opening 143 shown corresponds to FIG. 10A The cross-sectional view of the plan view shown. FIG. 10B It is along FIG. 10A The cross-sectional view of the dotted line A1-A2 shown.FIG. 10B An example is shown where the top end of the opening 141 side of the insulating layer 110, i.e., portion 123, is not aligned with the bottom end of the opening 143 side of the conductive layer 112b.

[0139] FIG. 10A An example is shown in which opening 143 includes opening 141 when viewed from a plane. FIG. 10B An example is shown in which, when viewed in cross-section, the insulating layer 110 has a region that protrudes further toward the opening 141 compared to the conductive layer 112b. FIG. 10B In the example shown, the semiconductor layer 108 has a shape along the top surface of the conductive layer 112b, the insulating layer 105, and the top surface of the conductive layer 112a. Note that when the planar shapes of the openings 141 and 143 are circular, the openings 141 and 143 may or may not be concentric circles.

[0140] FIG. 11A , FIG. 11B and FIG. 11C Show FIG. 1A , FIG. 1B and FIG. 1C The example shown has an insulating layer 105 having a region located on the insulating layer 110 and a conductive layer 112b disposed on the insulating layer 105. FIG. 11A , FIG. 11B and FIG. 11C In the example shown, an opening 145 is provided in the insulating layer 105 to reach the conductive layer 112a. The opening 145 is located inside the opening 141. Note that... FIG. 11A Insulating layer 105 is not shown.

[0141] To form the opening 145, the insulating layer 105 can be patterned, for example, using photolithography, after its formation, and the insulating layer 105 can be processed according to the pattern. By forming the semiconductor layer 108 after the opening 145 is formed, the conductive layer 112a can be made to contact the semiconductor layer 108.

[0142] exist FIG. 11A , FIG. 11B and FIG. 11C In the example shown, only a portion of the insulating layer 105 is etched. Therefore, even when the insulating layer 105 is relatively thin, regions in the insulating layer 105 that are thinner than other regions can be suppressed. Thus, while reducing the thickness of the insulating layer 105, short-circuiting between the conductive layer 103 and the semiconductor layer 108 can be prevented. By reducing the thickness of the insulating layer 105, the electric field of the conductive layer 103, which serves as the back gate electrode of the transistor 100, can be easily applied to the semiconductor layer 108.

[0143] On the other hand, FIG. 1A ,FIG. 1B and FIG. 1C In the example shown, it is not necessary to expose the top surface of the conductive layer 112a, for example, through photolithography. Therefore, the alignment accuracy of the mask does not need to be considered, and the opening 141 can be miniaturized. Therefore, the transistor 100 can be a microtransistor. Furthermore, even if the opening 141 is miniaturized, non-uniformity of electrical characteristics among multiple transistors 100, such as non-uniformity of channel length, can be suppressed.

[0144] FIG. 11A An example is shown in which opening 143 includes opening 141 when viewed from a plane. FIG. 11B An example is shown in which, when viewed in cross-section, the insulating layer 110 has a region that protrudes further toward the opening 141 than the conductive layer 112b. Note that when the planar shapes of the openings 141 and 143 are circular, the openings 141 and 143 may or may not be concentric.

[0145] In this embodiment, the planar shape of openings 141, 143 and 145 is circular, but the planar shape of openings 141, 143 and 145 is not limited to circular. FIG. 12A , FIG. 12B , FIG. 12C and FIG. 12D This is a plan view showing an example of the shapes of openings 141, 143, and 145. The planar shapes of openings 141, 143, and 145 can be... FIG. 12A The ellipse shown FIG. 12B The rectangle or shown FIG. 12C The rectangle shown has rounded corners. Furthermore, as... FIG. 12D As shown, the planar shapes of openings 141, 143, and 145 can also be one or both of straight and curved shapes. Furthermore, the planar shapes of openings 141, 143, and 145 can also be parallelograms, rhombuses, or squares. Additionally, the planar shapes of openings 141, 143, and 145 can be triangles, pentagons, star-shaped polygons, or other polygons. The polygons can also be concave polygons (polygons with at least one interior angle exceeding 180 degrees) or convex polygons (polygons with all interior angles less than 180 degrees). Moreover, the planar shapes of openings 141, 143, and 145 can also be shapes with curved corners as described above.

[0146] <Components of a Semiconductor Device> The following describes the constituent elements of a semiconductor device according to one aspect of the present invention. For example, materials that can be used in these constituent elements will be described.

[0147] [Semiconductor layer 108] The semiconductor layer 108 includes a metal oxide (also referred to as an oxide semiconductor) which exhibits a semiconductor property.

[0148] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 108, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor in which part of the semiconductor has a crystalline region) can be used. The use of a single crystal semiconductor or a semiconductor having crystallinity can suppress deterioration in the characteristics of the transistor, and is thus preferable.

[0149] The band gap of the metal oxide used for the semiconductor layer 108 is preferably 2.0 eV or more, further preferably 2.5 eV or more.

[0150] As the metal oxide which can be used for the semiconductor layer 108, an indium oxide, a gallium oxide, and a zinc oxide can be given, for example. The metal oxide preferably contains at least indium or zinc. Further, the metal oxide preferably contains two or three of indium, an element M, and zinc. The element M is a metal element or a semi-metal element having a high bond energy with oxygen, and is a metal element or a semi-metal element having a higher bond energy with oxygen than indium, for example. As the element M, specifically, an aluminum, a gallium, a tin, a yttrium, a titanium, a vanadium, a chromium, a manganese, an iron, a cobalt, a nickel, a zirconium, a molybdenum, a hafnium, a tantalum, a tungsten, a lanthanum, a cerium, a neodymium, a magnesium, a calcium, a strontium, a barium, a boron, a silicon, a germanium, an antimony, and the like can be given. The element M contained in the metal oxide is preferably any one or a plurality of the above elements, further preferably one or a plurality of elements selected from an aluminum, a gallium, a tin, and a yttrium, and still further preferably a gallium. Note that in this specification and the like, a metal element and a semi-metal element are collectively referred to as a "metal element", and the "metal element" described in this specification and the like sometimes includes a semi-metal element.

[0151] The semiconductor layer 108 can be formed using, for example, indium-zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium-tin oxide (In-Sn oxide), indium-titanium oxide (In-Ti oxide), indium-gallium oxide (In-Ga oxide), indium-gallium-aluminum oxide (In-Ga-Al oxide), gallium-zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum-zinc oxide (Al-Zn oxide, also referred to as AZO), indium-aluminum-zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium-tin-zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium-titanium-zinc oxide (In-Ti-Zn oxide), indium-gallium-zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium-gallium-tin-zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium-tin-gallium oxide (In-Sn-Ga oxide, also referred to as IGTO), indium-gallium-aluminum-zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO), or the like. Alternatively, indium-tin oxide containing silicon, gallium-tin oxide (Ga-Sn oxide), aluminum-tin oxide (Al-Sn oxide), or the like can be used. Alternatively, the above oxide having an amorphous structure can be used. For example, indium oxide having an amorphous structure or indium-tin oxide having an amorphous structure, or the like can be used.

[0152] When the proportion of the number of atoms of indium to the sum of the numbers of atoms of all metal elements in the metal oxide is increased, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a large on-state current can be realized.

[0153] Note that the metal oxide can contain one or plural metal elements having a large period number in the periodic table in place of or in addition to indium. There is a tendency that the larger the orbital overlap of the metal elements, the larger the carrier conduction in the metal oxide. Thus, by containing a metal element having a large period number in the periodic table, the field-effect mobility of the transistor can be increased in some cases. As the metal element having a large period number in the periodic table, a metal element belonging to the 5th period and a metal element belonging to the 6th period, and the like can be given. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, and the like can be given. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0154] Furthermore, the metal oxide can contain one or plural non-metal elements. When the metal oxide contains a non-metal element, the field-effect mobility of the transistor can be increased in some cases because of an increase in carrier concentration, a narrowing of a band gap, or the like. As the non-metal element, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, hydrogen, and the like can be given.

[0155] Further, when the proportion of the number of atoms of zinc with respect to the sum of the numbers of atoms of all the metal elements in the metal oxide is increased, the metal oxide has high crystallinity, and diffusion of impurities in the metal oxide can be suppressed. Thus, variation in electrical characteristics of the transistor is suppressed, and reliability can be improved.

[0156] Further, when the proportion of the number of atoms of element M with respect to the sum of the numbers of atoms of all the metal elements in the metal oxide is increased, formation of oxygen vacancies in the metal oxide can be suppressed. Thus, generation of carriers due to oxygen vacancies is suppressed, and a transistor with small off-state current can be formed. Further, variation in electrical characteristics of the transistor is suppressed, and reliability can be improved.

[0157] The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer 108. Thus, by changing the composition of the metal oxide depending on the electrical characteristics and reliability required for the transistor, a semiconductor device with excellent electrical characteristics and high reliability can be realized.

[0158] In the case where the metal oxide is an In-M-Zn oxide, the proportion of the number of atoms of In in the In-M-Zn oxide is preferably higher than that of M. As the proportion of the number of atoms of metal elements in such an In-M-Zn oxide, for example, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and the like, or a composition close thereto can be given. Further, the composition close thereto includes a range of ±30 % of the desired proportion of the number of atoms. By increasing the proportion of the number of atoms of indium in the metal oxide, the on-state current or the field-effect mobility of the transistor, or the like can be increased.

[0159] Further, the proportion of the number of atoms of In in the In-M-Zn oxide can be lower than that of M. As the proportion of the number of atoms of metal elements in such an In-M-Zn oxide, for example, In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and the like, or a composition close thereto can be given. By increasing the proportion of the number of atoms of M in the metal oxide, generation of oxygen vacancies can be suppressed.

[0160] Note that, in the case where a plurality of metal elements are included as element M, the total of the proportions of the number of atoms of the metal elements can be the proportion of the number of atoms of element M.

[0161] In this specification and the like, the proportion of the number of atoms of indium to the sum of the numbers of atoms of all metal elements contained is sometimes described as the indium content. The same applies to other metal elements.

[0162] The metal oxide can be formed using an atomic layer deposition (ALD) method or a sputtering method, as appropriate. Here, the ALD method is a deposition method in which a film is formed by a reaction at the surface of a processed object. Thus, by forming the semiconductor layer 108 including a metal oxide using the ALD method, damage to the semiconductor layer 108 can be reduced, and thus the ALD method is preferable. Note that in the case where the metal oxide is formed using a sputtering method, the composition of the metal oxide after deposition is sometimes different from that of a target. In particular, the indium content in the metal oxide after deposition is sometimes reduced to about 50 % of that of the target.

[0163] The semiconductor layer 108 can also have a stacked structure including two or more metal oxide layers. The composition of the two or more metal oxide layers included in the semiconductor layer 108 can be the same or substantially the same.

[0164] The composition of the two or more metal oxide layers included in the semiconductor layer 108 can be different from each other. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn = 1:3:4 [atomic ratio] or its neighborhood and a second metal oxide layer having a composition of In:M:Zn = 1:1:1 [atomic ratio] or its neighborhood provided over the first metal oxide layer can be used as appropriate. Further, as the element M, gallium, aluminum, or tin is particularly preferable. For example, a stacked structure selected from any of indium oxide, indium gallium oxide, and IGZO and any of IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0165] The semiconductor layer 108 preferably includes a metal oxide layer having crystallinity. As a structure of a metal oxide having crystallinity, a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a microcrystalline (nc: nano-crystal) structure can be given, for example. By using a metal oxide layer having crystallinity for the semiconductor layer 108, the density of defect states in the semiconductor layer 108 can be reduced, and thus a semiconductor device with high reliability can be achieved.

[0166] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 108, the lower the density of defect states in the semiconductor layer 108 can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of flowing a large current can be achieved.

[0167] The semiconductor layer 108 can also have a stacked-layer structure of two or more metal oxide layers having different crystallinity. For example, the semiconductor layer 108 can have a stacked-layer structure of a first metal oxide layer and a second metal oxide layer provided over the first metal oxide layer, and the second metal oxide layer can include a region having higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can include a region having lower crystallinity than the first metal oxide layer. In that case, the first metal oxide layer and the second metal oxide layer can have different, the same, or substantially the same composition.

[0168] The thickness of the semiconductor layer 108 is preferably greater than or equal to 3 nm and less than or equal to 200 nm, more preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 5 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 100 nm, more preferably greater than or equal to 10 nm and less than or equal to 70 nm, more preferably greater than or equal to 15 nm and less than or equal to 70 nm, more preferably greater than or equal to 15 nm and less than or equal to 50 nm, more preferably greater than or equal to 20 nm and less than or equal to 50 nm.

[0169] In the case where the semiconductor layer 108 includes an oxide semiconductor, hydrogen in the oxide semiconductor sometimes reacts with oxygen bonded to a metal atom to form water, and an oxygen vacancy (V O ) is formed in the oxide semiconductor. Further, a defect (V O H) in which hydrogen enters the oxygen vacancy is used as a donor to generate an electron serving as a carrier. Furthermore, an electron serving as a carrier is generated in some cases because part of hydrogen is bonded to oxygen bonded to a metal atom. Thus, a transistor using an oxide semiconductor including a large amount of hydrogen tends to have a normally-on characteristic (i.e., a threshold voltage is negative). Furthermore, since hydrogen in the oxide semiconductor easily moves due to heat or an electric field, a transistor including an oxide semiconductor including a large amount of hydrogen can have reduced reliability.

[0170] When an oxide semiconductor is used as the semiconductor layer 108, the carrier concentration of the oxide semiconductor in a region serving as a channel formation region is preferably lower than 1 x 10 18 cm -3 -2, more preferably lower than 1 x 10 17 cm -3 -1, further preferably lower than 1 x 10 16 cm -3 -0, more preferably lower than 1 x 10 13 cm -3 -9, and further preferably lower than 1 x 10 12 cm -3 -8. There is no particular limitation on the lower limit of the carrier concentration of the oxide semiconductor in a region serving as a channel formation region, and for example, it can be set to 1 x 10 -9 cm -3 -1.

[0171] The field-effect mobility of a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) is very high compared with that of a transistor using amorphous silicon. Furthermore, the off-state current of the OS transistor is extremely low, and the OS transistor can hold a charge stored in a capacitor connected in series to the transistor for a long period. Furthermore, by using the OS transistor, the power consumption of a semiconductor device can be reduced.

[0172] The OS transistor has a small change in electrical characteristics due to irradiation with a radiation ray, i.e., high resistance to a radiation ray, and thus can be appropriately used in an environment where there is a possibility that a radiation ray will be incident. The OS transistor can also be said to have high reliability against a radiation ray. For example, the OS transistor can be appropriately used for a pixel circuit of a flat panel detector for X-rays. Furthermore, the OS transistor can be appropriately used for a semiconductor device used in space. As a radiation ray, an electromagnetic radiation ray (e.g., an X-ray and a γ-ray) and a particle radiation ray (e.g., an α-ray, a β-ray, a neutron radiation, and a proton radiation) can be given.

[0173] As other semiconductor materials that can be used for the semiconductor layer 108, a semiconductor composed of a single element or a compound semiconductor can be given, for example. As a semiconductor composed of a single element, silicon and germanium can be given, for example. As a compound semiconductor, gallium arsenide and silicon germanium can be given, for example. Furthermore, as a compound semiconductor, an organic semiconductor and a nitride semiconductor can be given, for example. The oxide semiconductor described above is one of compound semiconductors. These semiconductor materials can also contain impurities as dopants.

[0174] As silicon that can be used for the semiconductor layer 108, single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be given. As polycrystalline silicon, low-temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be given, for example.

[0175] A transistor in which amorphous silicon is used for the semiconductor layer 108 can be formed over a large-sized glass substrate and can be manufactured at low cost. A transistor in which polycrystalline silicon is used for the semiconductor layer 108 has high field-effect mobility and can operate at high speed. Furthermore, a transistor in which microcrystalline silicon is used for the semiconductor layer 108 has high field-effect mobility compared with a transistor in which amorphous silicon is used and can operate at high speed.

[0176] The semiconductor layer 108 can also include a layered substance used as a semiconductor. The layered substance is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals force, which are weaker than covalent bonds and ionic bonds. The layered substance has high conductivity in a unit layer, i.e., has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity for a channel formation region, a transistor in which the on-state current is large can be implemented.

[0177] As the above layered substance, for example, graphene, silicene, chalcogenide, or the like can be given. The chalcogenide is a compound including an oxygen group element (a group 16 element). Further, as the chalcogenide, a transition metal chalcogenide, a group 13 chalcogenide, or the like can be given. As the transition metal chalcogenide which can be used as a semiconductor layer of a transistor, specifically, molybdenum sulfide (typically, MoS2), molybdenum selenide (typically, MoSe2), molybdenum telluride (typically, MoTe2), tungsten sulfide (typically, WS2), tungsten selenide (typically, WSe2), tungsten telluride (typically, WTe2), hafnium sulfide (typically, HfS2), hafnium selenide (typically, HfSe2), zirconium sulfide (typically, ZrS2), zirconium selenide (typically, ZrSe2), or the like can be given.

[0178] [Insulating layer 110] As the insulating layer 110, an inorganic insulating film is preferably used. As the inorganic insulating film, for example, an oxide insulating film and a nitride insulating film can be given. As the oxide insulating film, for example, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a magnesium oxide film, a gallium oxide film, a gallium oxynitride film, a germanium oxide film, a yttrium oxide film, a yttrium oxynitride film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a hafnium oxynitride film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminum oxide film can be given. As the nitride insulating film, for example, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, and an aluminum nitride oxide film can be given.

[0179] The insulating layer 110a and the insulating layer 110c can be formed using a material which is not easy to diffuse hydrogen. By this means, diffusion of hydrogen from the outside of the transistor through the insulating layer 110a or the insulating layer 110c to the semiconductor layer 108 can be suppressed. By this means, the channel length of the transistor 100 can be prevented from being shortened, which in turn can suppress the threshold voltage of the transistor 100 from being lowered, i.e., can suppress the threshold voltage from being shifted in the negative direction. By this means, the off-state current can be reduced, and thus a transistor with a normally-off characteristic can be implemented. Accordingly, the reliability of the transistor 100 can be improved, and thus the reliability of the semiconductor device of one embodiment of the present application can be improved.

[0180] The insulating layer 110c can include the same material as that included in the insulating layer 110a. For example, the insulating layer 110c can use the same material as the insulating layer 110a. At this time, the insulating layer 110a and the insulating layer 110c can be deposited under the same conditions. Note that the thickness of the insulating layer 110a can be made different from the thickness of the insulating layer 110c, for example, by making the deposition time of the insulating layer 110a different from the deposition time of the insulating layer 110c.

[0181] In the calculation of the diffusion coefficient, for example, a thermal desorption spectroscopy (TDS) method can be used. Alternatively, a secondary ion mass spectrometry (SIMS) method can be used.

[0182] The insulating layer 110a and the insulating layer 110c preferably use one or more of the above-described oxide insulating films and nitride insulating films, and preferably use one or more of a silicon nitride film, a silicon oxynitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, an aluminum nitride film, a hafnium oxide film, and a hafnium aluminum oxide film.

[0183] The insulating layer 110a and the insulating layer 110c preferably use one or more of the above-described nitride insulating films. Specifically, the insulating layer 110a and the insulating layer 110c preferably use one or both of a silicon nitride film and a silicon oxynitride film.

[0184] A silicon nitride film and a silicon oxynitride film can achieve a film that releases impurities (e.g., water and hydrogen) less and is less likely to transmit hydrogen, and thus can be appropriately used as the insulating layer 110a and the insulating layer 110c.

[0185] The insulating layer 110a and the insulating layer 110c can also use the above-described film containing aluminum. For example, the insulating layer 110a and the insulating layer 110c preferably each use an aluminum oxide film.

[0186] The insulating layer 110a and the insulating layer 110c can include hydrogen. When the insulating layer 110a includes hydrogen, a region near the conductive layer 112a of the semiconductor layer 108 can be supplied with hydrogen to be n-type, for example. When the insulating layer 110c includes hydrogen, a region near the conductive layer 112b of the semiconductor layer 108 can be supplied with hydrogen to be low-resistance. Thus, a transistor with low on-state current resistance can be achieved.

[0187] The thickness of the insulating layer 110a can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 20 nm or more, 50 nm or more, or 70 nm or more and less than 1 μm, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, or 120 nm or less. The thickness of the insulating layer 110a can be the shortest distance from the surface of the insulating layer 110a (in this case, the top surface of the conductive layer 112a) to the top surface of the insulating layer 110a when viewed in cross section.

[0188] The thickness of the insulating layer 110c can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more and 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 120 nm or less, or 100 nm or less. The thickness of the insulating layer 110c can be the shortest distance from the surface of the insulating layer 110c (in this case, the top surface of the insulating layer 110b) to the top surface of the insulating layer 110c when viewed in cross section.

[0189] The hydrogen content of the insulating layer 110b is preferably extremely small. With this, supply of hydrogen to the channel formation region of the semiconductor layer 108 can be suppressed. Thus, the transistor 100 can be a transistor that exhibits good electrical characteristics and has high reliability. As described above, in the case where the insulating layer 110a and the insulating layer 110c contain hydrogen and the hydrogen content of the insulating layer 110b is extremely small, supply of hydrogen to the channel formation region can be suppressed while the source region and the drain region of the transistor 100 are low-resistance.

[0190] The insulating layer 110b can be an insulating layer containing oxygen. In that case, one or more of the above-described oxide and oxynitride can be used for the insulating layer 110b. For example, one or both of silicon oxide and silicon oxynitride is / are suitably used. Further, an insulating layer containing nitrogen can also be used for the insulating layer 110b. For example, the same material as that described above as a material that can be used for the insulating layer 110a and the insulating layer 110c can be used for the insulating layer 110b.

[0191] When an insulating layer containing oxygen is used as the insulating layer 110b, the insulating layer 110b preferably uses a film that releases oxygen by heating. By releasing oxygen from the insulating layer 110b due to heat applied in a manufacturing process of the display device 10, oxygen can be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the channel formation region of the semiconductor layer 108, oxygen vacancies (V O ) are filled, so that the number of oxygen vacancies (V O ) can be reduced. Thus, a transistor that exhibits good electrical characteristics and has high reliability can be implemented.

[0192] It is preferable that the substance easily diffuse in the insulating layer 110b. In other words, the diffusion coefficient of the substance in the insulating layer 110b is preferably large. For example, when an insulating layer containing oxygen is used as the insulating layer 110b, it is preferable that oxygen easily diffuse in the insulating layer 110b. That is, the diffusion coefficient of oxygen in the insulating layer 110b is preferably large. Oxygen diffusion in the insulating layer 110b is supplied to the semiconductor layer 108 through the insulating layer 105. By using the insulating layer 110b in which oxygen easily diffuses, oxygen in the insulating layer 110b can be efficiently supplied to the channel formation region of the semiconductor layer 108.

[0193] The diffusion coefficient of oxygen in the insulating layer 110b at 350 °C is preferably 5 x 10 -12 cm 2 / sec or more, more preferably 1 x 10 -11 cm 2 / sec or more, still more preferably 5 x 10 -11 cm 2 / sec or more, yet more preferably 1 x 10 -10 cm 2 / sec or more. Thus, oxygen in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108. The larger the diffusion coefficient is, the better, and thus there is no particular upper limit. Note that the diffusion coefficient of oxygen in the insulating layer 110b is not limited to the above range.

[0194] The thickness of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0195] [Conductive layer 112a, conductive layer 112b, conductive layer 103, and conductive layer 104] As the conductive layer 112a, the conductive layer 112b, the conductive layer 103, and the conductive layer 104, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, and an alloy containing the metal element are preferably used, for example. In addition, a nitride of the above metal or alloy or an oxide of the above metal or alloy can be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, or the like is preferably used. In addition, a semiconductor having low resistivity typified by polycrystalline silicon containing an impurity element such as phosphorus and a silicide such as nickel silicide can be used.

[0196] Further, as the conductive layer 112a, the conductive layer 112b, the conductive layer 103, and the conductive layer 104, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. They are conductive materials which are not easily oxidized or conductive materials which maintain conductivity even if oxidized, and thus are preferable.

[0197] Further, as the conductive layer 112a, the conductive layer 112b, the conductive layer 103, and the conductive layer 104, an electrically conductive oxide such as indium oxide, zinc oxide, an In-Sn oxide, an In-Zn oxide, an In-W oxide, an In-W-Zn oxide, an In-Ti oxide, an In-Ti-Sn oxide, an In-Sn oxide, an In-Sn-Si oxide, or a Ga-Zn oxide can be used. In particular, an electrically conductive oxide containing indium has high conductivity, and thus is preferable.

[0198] The conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108. When the semiconductor layer 108 is a metal oxide layer, in the case where a metal which is easily oxidized is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide is formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, and thus conduction of these layers can be hindered. Thus, a conductive material which is not easily oxidized, a conductive material which maintains conductivity even if oxidized, or an oxide conductive material is preferably used for the conductive layer 112a and the conductive layer 112b.

[0199] As the conductive layer 112a, the conductive layer 112b, the conductive layer 103, and the conductive layer 104, a plurality of layers containing the above-described conductive material can also be stacked. Here, when the semiconductor layer 108 is a metal oxide layer, oxygen is sometimes supplied from the semiconductor layer 108 to the conductive layer 112a or the conductive layer 112b having a region in contact with the semiconductor layer 108. Thus, a layer having a region in contact with the semiconductor layer 108, for example, a layer having the largest contact area with the semiconductor layer 108 preferably uses a conductive material which is not easily oxidized, a conductive material which maintains conductivity even if oxidized, or an oxide conductive material.

[0200] Note that the materials used for the conductive layer 112a, the conductive layer 112b, the conductive layer 103, and the conductive layer 104 can be the same or at least a part of them can be different.

[0201] [Insulating layer 106] The insulating layer 106 can have a single-layer structure or a stacked-layer structure of two or more layers. The insulating layer 106 preferably includes one or more inorganic insulating films. As the inorganic insulating film, for example, an oxide insulating film and a nitride insulating film can be given. Specific examples of these inorganic insulating films are described above.

[0202] The insulating layer 106 has a portion in contact with the semiconductor layer 108. When the semiconductor layer 108 uses an oxide semiconductor, at least the film of the film constituting the insulating layer 106 in contact with the semiconductor layer 108 preferably uses the above-described oxide insulating film.

[0203] Specifically, when the insulating layer 106 has a single-layer structure, the insulating layer 106 preferably uses a silicon oxide film or a silicon oxynitride film.

[0204] Further, the insulating layer 106 can also have a stacked structure of an oxide insulating film in contact with the semiconductor layer 108 side and a nitride insulating film in contact with the conductive layer 104 side. As the oxide insulating film, for example, a silicon oxide film or a silicon oxynitride film is preferably used. As the nitride insulating film, a silicon nitride film or a silicon oxynitride film is preferably used.

[0205] A silicon nitride film and a silicon oxynitride film have characteristics that they hardly release impurities (e.g., water and hydrogen) themselves and are not easy to transmit hydrogen, and thus can be appropriately used as the insulating layer 106. Since diffusion of impurities from the insulating layer 106 to the semiconductor layer 108 is inhibited, good electrical characteristics of the transistor can be achieved and reliability can be improved.

[0206] Note that in a micro transistor, when the thickness of the gate insulating layer is small, the leakage current is sometimes increased. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, low voltage operation of the transistor can be achieved while the physical thickness is maintained. As the high-k material which can be used for the insulating layer 106, for example, gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium can be given.

[0207] [Substrate 102] Although there is no particular limitation on the material of the substrate 102, at least heat resistance to a subsequent heat treatment is needed. For example, as the substrate 102, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, a single crystal semiconductor substrate or a polycrystal semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate of silicon germanium, or an SOI substrate (Silicon On Insulator) can be used. Further, a semiconductor element can be provided over the substrate 102. Further, as the substrate 102, a polarizing plate can be used. Note that the shape of the semiconductor substrate and the insulating substrate can be circular or angular.

[0208] As the substrate 102, a flexible substrate can also be used, and the transistor 100, for example, can be formed directly over the flexible substrate. Alternatively, a separation layer can be provided between the substrate 102 and the transistor 100. The separation layer can be used when part or all of a semiconductor device is manufactured over the separation layer, which is then separated from the substrate 102 and transferred to another substrate. At this time, the transistor 100, for example, can be transferred to a substrate with low heat resistance or a flexible substrate.

[0209] As the substrate 102, a material such as a polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), a polyacrylonitrile resin, an acrylic resin, a polyimide resin, a polymethyl methacrylate resin, a polycarbonate (PC) resin, a polyethersulfone (PES) resin, a polyamide resin (nylon or aramid), a polysiloxane resin, a cyclic olefin resin, a polystyrene resin, a polyamide-imide resin, a polyurethane resin, a polyvinyl chloride resin, a polyvinylidene chloride resin, a polypropylene resin, a polytetrafluoroethylene (PTFE) resin, an ABS resin, or a cellulose nanofiber can be used. Further, a glass with a thickness thin enough to have flexibility can also be used as the substrate 102.

[0210] <Structure Example of Display Device> A structure example of a display device using the transistor 100 is described below. FIG. 13A is a block diagram illustrating a structure example of a display device 10 which is a display device of one embodiment of the present application. The display device 10 includes a display portion 20, a scan line driver circuit 11, and a signal line driver circuit 13. The display portion 20 includes a plurality of pixels 21 arranged in a matrix.

[0211] The scan line driver circuit 11 is electrically connected to the pixel 21 through a wiring 41. The wiring 41 extends in the row direction of the above matrix, for example.

[0212] The signal line driver circuit 13 is electrically connected to the pixel 21 through a wiring 43. The wiring 43 extends in the column direction of the above matrix, for example.

[0213] The pixel 21 includes a display element, and an image can be displayed on the display portion 20 by the display element. As the display element, a light-emitting element can be used, specifically, an organic EL element can be used. Further, as the display element, a liquid crystal element (also referred to as a liquid crystal device) can be used.

[0214] The scan line driver circuit 11 has a function of selecting the pixels 21 to which image data is written, for example, by row. Specifically, the scan line driver circuit 11 can select the pixels 21 to which image data is written by outputting a signal to the wiring 41. Here, the scan line driver circuit 11 can output the above-described signal to the wiring 41 of the second row after outputting the above-described signal to the wiring 41 of the first row, and sequentially output the above-described signal to the wiring 41 of the last row, thereby selecting all the pixels 21. Thus, the signal output to the wiring 41 by the scan line driver circuit 11 is a scan signal, and the wiring 41 can be said to be a scan line.

[0215] The signal line driver circuit 13 has a function of generating image data. The image data is supplied to the pixels 21 through the wiring 43. For example, image data can be written to all the pixels 21 included in the row selected by the scan line driver circuit 11. Here, the image data can be expressed as a signal (image signal). Thus, the wiring 43 can be said to be a signal line.

[0216] FIG. 13B is a plan view illustrating an example of the structure of the pixel 21. The pixel 21 includes a plurality of sub-pixels 23. FIG. 13B An example in which the pixel 21 includes a sub-pixel 23R, a sub-pixel 23G, and a sub-pixel 23B is illustrated. Here, in a case where the pixel 21 includes a light-emitting element as a display element, for example, FIG. 13B The planar shape of the sub-pixel illustrated in FIG. 13B is equivalent to the planar shape of the light-emitting region of the light-emitting element. Note that, in

[0217] In this specification and the like, when contents common to the sub-pixel 23R, the sub-pixel 23G, and the sub-pixel 23B are described, for example, the letters distinguishing them are sometimes omitted and described as the sub-pixel 23. When contents common to other structural elements distinguished by letters are described, the description is sometimes performed using a symbol in which the letters are omitted.

[0218] In the pixel 21 illustrated in FIG. 13B , a stripe arrangement is employed as the arrangement method of the sub-pixels 23. Further, as the arrangement method of the sub-pixels 23, an S stripe arrangement, a matrix arrangement, a Delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like can be employed. One example of the planar shape of the sub-pixel and the arrangement of the sub-pixels and the like can be referred to Embodiment 2.

[0219] The sub-pixels 23R, 23G, and 23B emit light of different colors. As the sub-pixels 23R, 23G, and 23B, sub-pixels of three colors of red (R), green (G), and blue (B), sub-pixels of three colors of yellow (Y), cyan (C), and magenta (M), or the like can be given. Further, four or more sub-pixels 23 can be provided in the pixel 21. For example, sub-pixels of four colors of R, G, B, and white (W) can be provided in the pixel 21. Thus, by including a plurality of sub-pixels 23 that emit light of different colors in the pixel 21 in the display device 10, a full-color image can be displayed on the display portion 20. Further, in the pixel 21, for example, sub-pixels of R, G, B, and infrared light (IR) can be provided.

[0220] Further, the display portion 20 can be provided with a sensor, and for example, the display portion 20 can be provided with a sensor in the pixel 21. For example, the display portion 20 can have a function of a fingerprint sensor. For example, the display portion 20 can have a function of an optical type or an ultrasonic type fingerprint sensor.

[0221] FIG. 13C FIG. 13D FIG. 14A FIG. 14B FIG. 14C FIG. 14D is a circuit diagram illustrating a structure example of the sub-pixel 23. FIG. 13C The sub-pixel 23 illustrated in FIG. 8 includes a pixel circuit 40A and a light emitting element 60.

[0222] The pixel circuit 40A includes a transistor 51, a transistor 52, and a capacitor 57. That is, the pixel circuit 40A is a 2Tr1C type pixel circuit.

[0223] In the pixel circuit 40A, one of a source and a drain of the transistor 51 is electrically connected to a wiring 43. The other of the source and the drain of the transistor 51 is electrically connected to a gate of the transistor 52. The gate of the transistor 52 is electrically connected to one electrode of the capacitor 57. A gate of the transistor 51 is electrically connected to a wiring 41.

[0224] One of a source and a drain of the transistor 52 is electrically connected to a wiring 45. The other of the source and the drain of the transistor 52 is electrically connected to the other electrode of the capacitor 57. The other electrode of the capacitor 57 is electrically connected to one electrode of the light emitting element 60. The other electrode of the light emitting element 60 is electrically connected to a wiring 47. Here, the one electrode of the light emitting element 60 is referred to as a pixel electrode. Further, for example, the wiring 47 can be commonly used among all the sub-pixels 23. Thus, the other electrode of the light emitting element 60 can be referred to as a common electrode.

[0225] ​​​​​As described above, the wiring 41 is used as a scan line, and the wiring 43 is used as a signal line. Further, the wiring 45 and the wiring 47 are used as power supply lines, for example, the wiring 47 is supplied with a low power supply potential when the wiring 45 is supplied with a high power supply potential.

[0226] The transistor 51 is used as a switch, also referred to as a selection transistor. The transistor 51 has a function of controlling a conduction state and a non-conduction state between the wiring 43 and a gate of the transistor 52 in accordance with a potential of the wiring 41. When the transistor 51 is made to be in an on state, image data is written to the pixel circuit 40A, and when the transistor 51 is made to be in an off state, the written image data is held.

[0227] The transistor 52 has a function of controlling an amount of current flowing through the light emitting element 60, also referred to as a drive transistor. The capacitor 57 has a function of holding a gate potential of the transistor 52. The light emitting brightness of the light emitting element 60 is controlled in accordance with a potential supplied to the gate of the transistor 52, which corresponds to the image data. Specifically, in the case where the wiring 45 is supplied with a high power supply potential and the wiring 47 is supplied with a low power supply potential, the size of the current flowing from the wiring 45 to the wiring 47 is controlled in accordance with the gate potential of the transistor 52. Thus, the light emitting brightness of the light emitting element 60 is controlled.

[0228] As the transistor 51 and the transistor 52, an OS transistor is preferably used. The OS transistor has a higher field effect mobility than a transistor using amorphous silicon, for example. Thus, by using the OS transistor as the transistor 51 and the transistor 52, the display device 10 can be driven at a high speed.

[0229] Further, the leakage current between a source and a drain in the off state of the OS transistor, also referred to as an off-state current, is significantly small. Thus, by using the OS transistor as the transistor 51, the charge stored in the capacitor 57 can be held for a long period. Thus, the image data written to the sub-pixel 23 can be held for a long period, so the frequency of refresh operation (writing of image data to the sub-pixel 23 again) can be reduced. Thus, the power consumption of the display device 10 can be reduced.

[0230] Here, in increasing the light emitting brightness of the light emitting element 60, it is necessary to increase the amount of current flowing through the light emitting element 60. For this reason, it is necessary to increase the voltage between the source and the drain of the transistor 52, which is a drive transistor. Since the voltage resistance between the source and the drain of the OS transistor is higher than that of a transistor using silicon, also referred to as a Si transistor, a high voltage can be applied to the source and the drain of the OS transistor. Thus, by using the OS transistor as the transistor 52, the amount of current flowing through the light emitting element 60 can be increased, and the light emitting brightness of the light emitting element 60 can be increased.

[0231] When the transistor is driven in the saturation region, the OS transistor allows for a smaller change in the source-drain current in response to changes in the gate-source voltage, compared to a Si transistor. Therefore, by using an OS transistor as transistor 52, the current flowing through the source-drain can be determined precisely based on the change in the gate-source voltage. This allows for precise control of the amount of current flowing through the light-emitting element 60. Consequently, the brightness of the light emitted by the sub-pixel 23 can be precisely controlled. This, in turn, increases the number of grayscale values ​​that the sub-pixel 23 can display.

[0232] Regarding the saturation characteristics of the current flowing through a transistor when driven in the saturation region, compared to a Si transistor, an OS transistor can maintain a stable current (saturation current) even when the source-drain voltage is gradually increased. Therefore, by using an OS transistor as transistor 52, even if the current-voltage characteristics of the light-emitting element 60 are non-uniform for each light-emitting element 60, a stable current can still flow through the light-emitting element 60. In other words, when driven in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is increased, thus stabilizing the brightness of the light-emitting element 60.

[0233] As described above, by using the OS transistor as transistor 52, it is possible to achieve "suppression of black blur", "increase in light emission brightness", "multi-grayscale conversion" and "suppression of light emission brightness of light-emitting element 60 not uniformly per light-emitting element 60".

[0234] Note that in FIG. 13C Transistors 51 and 52 are n-channel transistors, but one or both of transistors 51 and 52 may also be p-channel transistors. The same applies to other transistors shown in this specification.

[0235] Examples of light-emitting elements 60 include self-emissive light-emitting elements such as LEDs, OLEDs (Organic LEDs), and semiconductor lasers. Examples of LEDs include mini LEDs and micro LEDs.

[0236] The light-emitting material contained in the light-emitting element 60 may include, for example, a fluorescent material, a phosphorescent material, a material that exhibits thermally activated delayed fluorescence (TADF) material, and an inorganic compound (quantum dot material, etc.).

[0237] The light-emitting element 60 can emit colors such as infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, when the light-emitting element has a microcavity structure, color purity can be improved.

[0238] In the pair of electrodes included in the light emitting element 60, one electrode is used as an anode and the other electrode is used as a cathode.

[0239] The display device of one embodiment of the present application can employ any of the following structures: a top emission type which emits light in a direction opposite to a substrate on which a light emitting element is formed, a bottom emission type which emits light to a substrate side on which a light emitting element is formed, and a dual emission type which emits light to both sides.

[0240] FIG. 13D The subpixel 23 illustrated includes a pixel circuit 40B and a light emitting element 60. The pixel circuit 40B has a structure in which a transistor 53 is added to the pixel circuit 40A. The pixel circuit 40B is a 3Tr1C type pixel circuit.

[0241] In the pixel circuit 40B, the gate of the transistor 51 is electrically connected to the wiring 41a. One of the source and the drain of the transistor 53 is electrically connected to the other of the source and the drain of the transistor 52, the other electrode of the capacitor 57, and one electrode of the light emitting element 60. The other of the source and the drain of the transistor 53 is electrically connected to the wiring 48. The gate of the transistor 53 is electrically connected to the wiring 41b.

[0242] The transistor 53 is used as a switch and has a function of controlling a conduction state and a non-conduction state between the wiring 48 and one electrode of the light emitting element 60 in accordance with a potential of the wiring 41b. The wiring 48 is supplied with a reference potential, for example. According to the reference potential of the wiring 48 supplied through the transistor 53, unevenness of the gate-source potential of the transistor 52 of each transistor 52 can be suppressed.

[0243] In addition, a current value which can be used for setting of a pixel parameter can be obtained in accordance with a current value of the wiring 48. More specifically, the wiring 48 can be used as a monitor line which outputs a current flowing through the transistor 52 or a current flowing through the light emitting element 60 to the outside of the pixel 21. The current output to the wiring 48 can be converted into a potential by a source follower circuit, for example. Alternatively, it can be converted into a digital signal by an A-D converter, for example.

[0244] As the transistor 53, an OS transistor is preferably used. As described above, the OS transistor has higher field-effect mobility than a transistor using amorphous silicon, for example. Thus, by using the OS transistor as the transistor 53, the display device 10 can be driven at high speed.

[0245] FIG. 14AThe illustrated subpixel 23 includes a pixel circuit 40C and a light emitting element 60. The pixel circuit 40C has a structure in which a transistor 54 and a capacitor 58 are added to the pixel circuit 40B. The pixel circuit 40C is a 4Tr2C type pixel circuit.

[0246] In the pixel circuit 40C, one of the source and drain of the transistor 52 is electrically connected to one of the source and drain of the transistor 54. The other of the source and drain of the transistor 54 is electrically connected to the wiring 45. The gate of the transistor 54 is electrically connected to the wiring 41c. One electrode of the capacitor 58 is electrically connected to the other of the source and drain of the transistor 52, one of the source and drain of the transistor 53, the other electrode of the capacitor 57, and one electrode of the light emitting element 60.

[0247] The wiring 41c is electrically connected to the scan line driver circuit 11. That is, when the subpixel 23 included in the pixel 21 has the structure illustrated, the wiring 41a, the wiring 41b, and the wiring 41c are provided as the wiring 41 in the display device 10. FIG. 14A

[0248] The transistor 54 is used as a switch, and has a function of controlling the on state and the off state between the wiring 45 and one of the source and drain of the transistor 52 in accordance with the potential of the wiring 41c.

[0249] When the transistor 54 is made to be in the on state, a current corresponding to the magnitude of the gate potential of the transistor 52 flows, for example, from the wiring 45 to the wiring 47. Thus, the light emitting element 60 emits light of a luminance corresponding to the gate potential of the transistor 52. On the other hand, when the transistor 54 is made to be in the off state, a current can not flow to the light emitting element 60, and thus the light emitting element 60 can not emit light.

[0250] As the transistor 54, an OS transistor is preferably used. As described above, the OS transistor has a higher field effect mobility, for example, than a transistor using amorphous silicon. Thus, by using the OS transistor as the transistor 54, the display device 10 can be driven at a high speed.

[0251] FIG. 14B The illustrated subpixel 23 includes a pixel circuit 40D and a light emitting element 60. The pixel circuit 40D has a structure in which a transistor 54 is added to the pixel circuit 40B. The pixel circuit 40D is a 4Tr1C type pixel circuit.

[0252] In the pixel circuit 40D, one of the source and drain of the transistor 54 is electrically connected to the other of the source and drain of the transistor 51, the gate of the transistor 52, and one electrode of the capacitor 57. The other of the source and drain of the transistor 54 is electrically connected to the wiring 49. The gate of the transistor 54 is electrically connected to the wiring 41c. When the subpixel 23 has​FIG. 14B In the structure shown, wiring 41a, wiring 41b and wiring 41c are provided as wiring 41 in the display device 10.

[0253] When transistor 54 is turned on, the gate of transistor 52 can be at the potential of wiring 49. Here, wiring 49 can be supplied with a low potential, for example. As described above, for example, no current flows through the light-emitting element 60, so the light-emitting element 60 does not emit light.

[0254] As described above, the transistor 100, which is a transistor according to one aspect of the present invention, has high saturation. Therefore, by using the transistor 100 as... FIG. 13C , FIG. 13D , FIG. 14A and FIG. 14B The transistor 52 shown, which acts as a driving transistor, ensures a stable current flowing through the light-emitting element 60. This, in turn, stabilizes the brightness of the light-emitting element 60. For example, it can suppress the time-varying inconsistency of the current flowing through the light-emitting element 60. Consequently, the display device 10 can display high-quality images on the display section 20.

[0255] Furthermore, transistor 100 can be a miniature transistor. Therefore, by using transistor 100 as the transistor included in sub-pixel 23, pixel 21 can be miniaturized. As a result, display device 10 can be a high-definition display device. Thus, display device 10 can display high-quality images on display unit 20. For example, transistor 100 can be used as transistors 51 to 54.

[0256] The transistor 100 can also be used as a transistor included in the driving circuit of the display device 10. For example, the transistor 100 can also be used as a transistor included in the scan line driving circuit 11 and the signal line driving circuit 13. By using the transistor 100 as at least a portion of the transistors included in the driving circuit of the display device 10, the area occupied by the driving circuit can be reduced. Thus, the display device 10 can be a narrow bezel display device.

[0257] FIG. 14C and FIG. 14D The sub-pixel 23 shown includes pixel circuit 40E and liquid crystal element 69.

[0258] The pixel circuit 40E includes a transistor 51 and a capacitor 57. That is to say, the pixel circuit 40E is a 1Tr1C type pixel circuit.

[0259] In the pixel circuit 40E, one of a source and a drain of the transistor 51 is electrically connected to the wiring 43. The other of the source and the drain of the transistor 51 is electrically connected to one electrode of the capacitor 57. One electrode of the capacitor 57 is electrically connected to one electrode of the liquid crystal element 69. The gate of the transistor 51 is electrically connected to the wiring 41. Here, one electrode of the liquid crystal element 69 is also referred to as a pixel electrode.

[0260] In FIG. 14C In the example shown, the other electrode of the capacitor 57 and the other electrode of the liquid crystal element 69 are electrically connected to the same wiring 46. In FIG. 14D In the example shown, the other electrode of the capacitor 57 is electrically connected to the wiring 46a and the other electrode of the liquid crystal element 69 is electrically connected to the wiring 46b. That is, FIG. 14D An example in which the wiring 46 electrically connected to the other electrode of the capacitor 57 is different from the wiring 46 electrically connected to the other electrode of the liquid crystal element 69 is shown. The wiring 46 is used as a power supply line, for example, and can supply a ground potential. Here, the other electrode of the liquid crystal element 69 is sometimes referred to as a common electrode.

[0261] In the pixel circuit 40E, the transistor 51 is used as a switch and has a function of controlling a conduction state or a non-conduction state between the wiring 43 and one electrode of the liquid crystal element 69 in accordance with a potential of the wiring 41. Image data is written to the pixel circuit 40E by making the transistor 51 an on state, and the written image data is held by making the transistor 51 an off state.

[0262] The capacitor 57 has a function of holding a potential of one electrode of the liquid crystal element 69. An alignment state of the liquid crystal element 69 is controlled in accordance with a potential corresponding to image data supplied to one electrode of the liquid crystal element 69.

[0263] When the liquid crystal element 69 is used as a display element, the display device 10 can adopt various modes. As the mode, for example, a vertical alignment (VA) mode, a fringe field switching (FFS) mode, an in-plane switching (IPS) mode, a twisted nematic (TN) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, an electrically controlled birefringence (ECB) mode, and a guest-host mode can be given. As the VA mode, for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, and an advanced super view (ASV) mode can be given.

[0264] As the liquid crystal material which can be used for the liquid crystal element 69, for example, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a polymer dispersed liquid crystal (PDLC), a polymer network liquid crystal (PNLC), a ferroelectric liquid crystal, and an anti-ferroelectric liquid crystal can be given. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, a blue phase, or the like depending on conditions. Further, as the liquid crystal material, either one of a positive liquid crystal and a negative liquid crystal can be used, and can be selected depending on the mode or design used.

[0265] When the liquid crystal element 69 is used as a display element, the display device 10 can be, for example, a transmissive liquid crystal display device, a reflective liquid crystal display device, or a semi-transmissive liquid crystal display device.

[0266] As described above, transistor 100 can be a miniature transistor. Therefore, by using transistor 100 as transistor 51 included in pixel circuit 40E, pixel 21 can be miniaturized. As a result, display device 10 can be a high-definition display device. As a result, display device 10 can display high-quality images on display unit 20.

[0267] FIG. 15A This is a plan view showing an example of the structure of transistors 51 and 52. FIG. 15B It is along FIG. 15A The cross-sectional view shown is the dotted line C1-C2. FIG. 15A and FIG. 15B Transistor 51 is shown to have a... FIGS. 1A-1C The transistor 100 shown is an example of a structure in which the conductive layer 103 and the insulating layer 105 are omitted. Furthermore, FIG. 15A and FIG. 15B Showing will FIGS. 1A-1C The transistor 100 shown is used as an example of transistor 52.

[0268] exist FIG. 15A and FIG. 15B In transistor 51, the conductive layer 112a, semiconductor layer 108, conductive layer 112b, and conductive layer 104 are respectively referred to as conductive layer 112a_1, semiconductor layer 108_1, conductive layer 112b_1, and conductive layer 104_1. Furthermore, the openings 141 and 143 provided in transistor 51 are respectively referred to as opening 141_1 and opening 143_1. Similarly, in transistor 52, the conductive layers 112a, semiconductor layer 108, conductive layer 112b, and conductive layer 104 are respectively referred to as conductive layer 112a_2, semiconductor layer 108_2, conductive layer 112b_2, and conductive layer 104_2. Furthermore, the openings 141 and 143 provided in transistor 52 are respectively referred to as opening 141_2 and opening 143_2.

[0269] like FIG. 15BAs shown, an insulating layer 109 is provided on the insulating layer 107. Furthermore, openings 146a leading to the conductive layer 112b_1 are provided in the insulating layers 106, 107, and 109. Additionally, openings 146b leading to the conductive layer 104_2 are provided in the insulating layers 107 and 109. The conductive layer 119 is provided with a region located inside the opening 146a, a region located inside the opening 146b, and a region located on the insulating layer 109. For example, the conductive layer 119 has a region inside the opening 146a that contacts the conductive layer 112b_1, and a region inside the opening 146b that contacts the conductive layer 104_2. Thus, the conductive layer 112b_1, which serves as the source or drain electrode of the transistor 51, is electrically connected to the conductive layer 104_2, which serves as the gate electrode of the transistor 52.

[0270] The insulating layer 109 can be used as a planarization layer. The insulating layer 109 can be made of the same material that can be used for the insulating layer 107, such as an organic or inorganic insulating film. In particular, when an organic insulating film is used as the insulating layer 109, it facilitates planarization and is therefore preferred. Alternatively, the insulating layer 109 may not be provided.

[0271] Conductive layer 119 is used as a lead. Conductive layer 119 can be made of the same material that can be used for at least one of conductive layers 112a, 112b, 103, and 104. In particular, it is preferred to use a metal or alloy as conductive layer 119, as this can reduce the resistance of conductive layer 119.

[0272] exist FIG. 15A In the present invention, the planar shape of openings 146a and 146b is a rectangle with rounded corners, but the planar shape of openings 146a and 146b is not limited to this. For example, the planar shape of openings 146a and 146b can be the same as the planar shape that opening 141 can have. For example, the planar shape of openings 146a and 146b can be circular, elliptical, or include one or both of straight and curved portions.

[0273] FIG. 15A and FIG. 15B An example is shown in which the insulating layer 105a is provided in such a manner that it covers the side of conductive layer 112b_1 opposite to the opening 143_1 and the side of conductive layer 112b_2 opposite to the opening 143_2. FIG. 15A and FIG. 15BIn the example shown, the insulating layer 105 can have a region in contact with the side of the conductive layer 112b_1 opposite the opening portion 143_1 and a region in contact with the side of the conductive layer 112b_2 opposite the opening portion 143_2. Further, as shown in FIG. 15A and FIG. 15B the insulating layer 105a covering the side of the conductive layer 112b_1 opposite the opening portion 143_1 and the insulating layer 105a covering the side of the conductive layer 112b_2 opposite the opening portion 143_2 can be separate from each other.

[0274] The conductive layer 103 is not provided inside the opening portion 141_1. Further, the insulating layer 105 is not provided inside the opening portion 141_1 and the opening portion 143_1. Thus, as shown in FIG. 15A the width D143_1 of the opening portion 143_1 can be smaller than the width D143_2 of the opening portion 143_2. Therefore, for example, as compared with the transistor 100 shown in FIG. 1A the transistor 51 can be miniaturized. On the other hand, the transistor 52 can be a transistor whose saturation property is higher than that of the transistor 51. Thus, by not providing the conductive layer 103 and the insulating layer 105 in the transistor 51, the pixel 21 can be miniaturized while the saturation property of the transistor 52 used as a driver transistor is ensured. Further, the conductive layer 103 and the insulating layer 105 can be provided in the transistor 51. At this time, the transistor 51 and the transistor 52 can be formed by the same process.

[0275] FIGS. 13D-14B The transistors 53 and 54 are used as switches like the transistor 51. Thus, the transistors 53 and 54 preferably have the same structure as the transistor 51. For example, when the transistor 51 does not include the conductive layer 103 and the insulating layer 105, the transistors 53 and 54 also preferably do not include the conductive layer 103 and the insulating layer 105. Further, one or both of the transistors 53 and 54 can have the same structure as the transistor 52.

[0276] <Structure Example 2 of Semiconductor Device> A semiconductor device including a plurality of transistors will be described below with reference to FIGS. 16A-24B FIGS. 16A-16I is a circuit diagram illustrating a structure example of a semiconductor device of one embodiment of the present application.

[0277] For example, FIG. 16A The semiconductor device shown in

[0278] Note that, FIGS. 16A-16C ​The transistors 100 and 200 shown are n-channel transistors, but one embodiment of the present application is not limited to this. One or both of the transistors 100 and 200 can be p-channel transistors.

[0279] FIG. 17A FIG. 1A is a plan view that shows a structure example of a semiconductor device 30 which is a semiconductor device of one embodiment of the present application. FIG. 17A The conductive layer 103, the insulating layer 105, the insulating layer 105a, and the insulating layer 110 are not shown. The same applies to the plan views below.

[0280] FIG. 17B FIG. 1C is a cross-sectional view along the dotted line D1-D2 shown in FIG. 1A. FIG. 17A FIG. 18A FIG. 1D is a cross-sectional view along the dotted line E1-E2 shown in FIG. 1A. FIG. 17A FIG. 18B FIG. 1E is a cross-sectional view along the dotted line E3-E4 shown in FIG. 1A. FIG. 17A

[0281] The semiconductor device 30 includes the transistor 100 and the transistor 150. The transistor 100 and the transistor 150 are each formed over the substrate 102.

[0282] Since the transistor 100 can be referred to the above description, detailed description is omitted.

[0283] The transistor 150 includes the conductive layer 202, the insulating layer 110, the insulating layer 120, the semiconductor layer 208, the insulating layer 106, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b. Each layer included in the transistor 150 can have a single-layer structure or a stacked-layer structure.

[0284] ​​​A conductive layer 202 is provided over the substrate 102. The conductive layer 202 is used as a back gate electrode of the transistor 150. The conductive layer 202 can be formed using the same material as the conductive layer 112a included in the transistor 100. The conductive layer 202 can be formed by the same process as the conductive layer 112a. For example, the conductive layer 112a and the conductive layer 202 can be formed by processing a film to be the conductive layer 112a and the conductive layer 202. Alternatively, the conductive layer 202 can be formed by a different process from the conductive layer 112a. By being formed by a different process, the conductive layer 202 can be formed using a different material from the conductive layer 112a. The conductive layer 202 has no region in contact with the semiconductor layer 108 and no region in contact with the semiconductor layer 208, and thus there is no particular limitation on the material to be used. For example, the conductive layer 202 preferably uses a material having a lower resistivity than the conductive layer 112a. By this means, the resistance of the conductive layer 202 can be reduced. For example, the conductive layer 112a is formed using In-Sn-Si oxide (ITSO) and the conductive layer 202 is formed using copper or tungsten. Note that the transistor 150 can not include a back gate electrode.

[0285] The insulating layer 110 is provided so as to cover the conductive layer 202, and the insulating layer 120 is provided over the insulating layer 110. The insulating layer 110 and the insulating layer 120 are used as a back gate insulating layer of the transistor 150. Since the insulating layer 120 is a layer in contact with the channel formation region of the semiconductor layer 208, it is preferably an insulating layer containing oxygen. The insulating layer 120 can be formed using a material that can be appropriately used for the insulating layer 110b, for example.

[0286] The semiconductor layer 208 is provided over the insulating layer 120. The semiconductor layer 208 has a region overlapping with the conductive layer 202 with the insulating layer 110 and the insulating layer 120 interposed therebetween. The semiconductor layer 208 can be formed using the same material as the semiconductor layer 108. The semiconductor layer 208 can be formed by the same process as the semiconductor layer 108.

[0287] The insulating layer 106 is provided so as to cover the insulating layer 120 and the semiconductor layer 208. The insulating layer 106 is used as a gate insulating layer of the transistor 150. Further, the insulating layer 106 has an opening portion 147a and an opening portion 147b reaching the semiconductor layer 208.

[0288] Conductive layers 204, 212a, and 212b are disposed on insulating layer 106. Conductive layers 204, 212a, and 212b can be made of the same material as conductive layer 104. Conductive layers 204, 212a, and 212b can be formed using the same process as conductive layer 104. For example, conductive layers 104, 204, 212a, and 212b can be formed by processing the film to form the conductive layers 104, 204, 212a, and 212b.

[0289] Conductive layer 212a is disposed such that it covers at least a portion of opening 147a, and conductive layer 212b is disposed such that it covers at least a portion of opening 147b. Both conductive layers 212a and 212b have regions that contact semiconductor layer 208. Conductive layer 212a is electrically connected to semiconductor layer 208 through opening 147a. Conductive layer 212b is electrically connected to semiconductor layer 208 through opening 147b. Conductive layer 212a is used as one of the source and drain electrodes of transistor 150. Conductive layer 212b is used as the other of the source and drain electrodes of transistor 150.

[0290] The conductive layer 204 has a region that overlaps with the semiconductor layer 208 through the insulating layer 106. The conductive layer 204 is used as the gate electrode of the transistor 150.

[0291] like FIG. 18B As shown, conductive layer 204 can also be in contact with conductive layer 202 for electrical connection. Therefore, conductive layer 204 and conductive layer 202 can be supplied with the same potential. By supplying conductive layer 204 and conductive layer 202 with the same potential, the current that can flow when transistor 150 is in the on state can be increased. Conductive layer 204 can be electrically connected to conductive layer 202 through openings 149 provided in insulating layer 106 and insulating layer 110.

[0292] Conductive layer 212a or conductive layer 212b can also be electrically connected to conductive layer 202. By supplying the same potential to the source and back gate, the DIBL effect in transistor 150 can be suppressed. Therefore, the saturation of transistor 100 can be improved. Conductive layer 212a or conductive layer 212b contacts conductive layer 202 through openings provided in insulating layer 106 and insulating layer 110.

[0293] The conductive layer 202 may also not be electrically connected to the conductive layers 204, 212a, and 212b. For example, a constant potential can be supplied to the back gate and a signal for driving the transistor 150 can be supplied to the gate. Thus, the potential supplied to the back gate can be controlled at the threshold voltage when driving the transistor 150.

[0294] In the semiconductor layer 208, the entire region of the region where the gate electrode overlaps with the source electrode and the drain electrode with the gate insulating layer interposed therebetween is used as a channel formation region. The semiconductor layer 208 has a pair of regions 208L sandwiching the channel formation region and a pair of regions 208D outside thereof.

[0295] The regions 208D can also be said to be regions whose carrier concentration is higher than that of the channel formation region or regions whose resistance is low. The regions 208D in the semiconductor layer 208 in contact with the conductive layer 212a and the regions 208D adjacent thereto are used as one of the source region and the drain region. The regions 208D in the semiconductor layer 208 in contact with the conductive layer 212b and the regions 208D adjacent thereto are used as the other of the source region and the drain region.

[0296] The regions 208L can also be said to be regions whose resistance is equal to or lower than that of the channel formation region, regions whose carrier concentration is equal to or higher than that of the channel formation region, regions whose oxygen vacancy density is equal to or higher than that of the channel formation region, or regions whose impurity concentration is equal to or higher than that of the channel formation region. Further, the regions 208L can also be said to be regions whose resistance is equal to or higher than that of the regions 208D, regions whose carrier concentration is equal to or lower than that of the regions 208D, regions whose oxygen vacancy density is equal to or lower than that of the regions 208D, or regions whose impurity concentration is equal to or lower than that of the regions 208D.

[0297] The regions 208L are used as buffer regions for relaxing the electric field of the drain. Since the regions 208L do not overlap with the conductive layer 204, a channel is hardly formed when a gate voltage is supplied to the conductive layer 204. The carrier concentration in the regions 208L is preferably higher than that of the channel formation region. This allows the regions 208L to be used as LDD (Lightly Doped Drain) regions. By providing the regions 208L serving as LDD regions between the channel formation region and the regions 208D, a transistor 150 with high drain withstand voltage can be achieved.

[0298] For example, after the conductive layers 204, 212a, and 212b are formed, the regions 208L and the regions 208D are formed by adding impurity elements to the semiconductor layer 208 with the use of these conductive layers as masks. The regions 208L are regions in the semiconductor layer 208 which overlap with the insulating layer 106 and do not overlap with the conductive layer 204. The regions 208D are regions in the semiconductor layer 208 which do not overlap with the insulating layer 106 and the conductive layer 204.

[0299] As FIG. 17A and FIG. 17BAs shown, the end portions of the portions of the conductive layer 212a and the conductive layer 212b are preferably positioned inside the opening portions 147a and 147b. In other words, in the opening portions 147a and 147b, the end portions of the portions of the conductive layer 212a and the conductive layer 212b are preferably in contact with the semiconductor layer 208. Thus, the region in contact with the conductive layer 212a can be adjacent to one of the pair of regions 208D, and similarly, the region in contact with the conductive layer 212b can be adjacent to the other of the pair of regions 208D. Note that the planar shape of the opening portions 147a and 147b is not particularly limited.

[0300] The regions 208L and 208D contain impurity elements. As the impurity elements, one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or a rare gas, or the like can be used. As typical examples of the rare gas, helium, neon, argon, krypton, and xenon can be given. As the impurity elements, one or more of boron, phosphorus, aluminum, magnesium, or silicon is particularly preferable.

[0301] When the regions 208L and 208D are formed by adding impurity elements to the semiconductor layer 208 with the conductive layer 104 as a mask, the impurity elements can also be supplied to the semiconductor layer 108 through the insulating layer 106. Thus, a region containing the impurity elements is formed in a region of the semiconductor layer 108 which does not overlap with the conductive layer 104. Here, in the transistor 100, a region of the semiconductor layer 108 in contact with the conductive layer 112b is used as a source region or a drain region. Thus, a region containing the impurity elements is formed in part of the source region or the drain region.

[0302] The transistor 150 is a so-called top gate transistor having a gate electrode over the semiconductor layer 208. For example, by adding impurity elements to the semiconductor layer 208 with the conductive layer 204 serving as a gate electrode as a mask, a source region and a drain region can be formed in a self-aligned manner. The transistor 150 can be said to be a TGSA (Top Gate Self-Aligned) transistor.

[0303] The transistor 150 can control the channel length with the width of the conductive layer 204 in the channel length direction. Thus, the channel length of the transistor 150 is a value greater than or equal to the resolution limit of an exposure device used in the manufacture of the transistor. By increasing the channel length, a transistor with high saturation property can be realized.

[0304] The insulating layer 107 is provided so as to cover the transistor 100 and the transistor 150. As described above, the insulating layer 107 is used as a protective layer.

[0305] In the production of the semiconductor device 30, the transistor 100 having a short channel length and the transistor 150 having a long channel length can be formed by one process and on the same substrate. For example, the transistor 100 is applied to a transistor in which a drain current is required to be large and the transistor 150 is applied to a transistor in which high saturation is required, and thus a high-performance semiconductor device can be achieved.

[0306] Although FIG. 17B An example is shown in which the conductive layer 212a and the conductive layer 212b are formed by the same process as the conductive layer 104 and the conductive layer 204, but one embodiment of the present application is not limited to this. For example, the conductive layer 212a and the conductive layer 212b can be formed after the insulating layer 107 is formed. Specifically, after the insulating layer 107 is provided so as to cover the conductive layer 104 and the conductive layer 204, an opening portion reaching the semiconductor layer 208 is provided in the insulating layer 107 and the insulating layer 106, the conductive layer 212a and the conductive layer 212b are provided so as to cover the opening portion, and the conductive layer 212a and the conductive layer 212b are electrically connected to the semiconductor layer 208. Note that after the conductive layer 204 is formed, impurity elements can be added to the semiconductor layer 208 with the conductive layer 204 as a mask, and a low-resistance region can be formed in the semiconductor layer 208.

[0307] The structures of the semiconductor device 30A, the semiconductor device 30B, the semiconductor device 30C, the semiconductor device 30D, and the semiconductor device 30E are described below as modified examples of the semiconductor device 30.

[0308] [Semiconductor Device 30A] FIG. 19A and FIG. 19B is a cross-sectional view illustrating a structure example of the semiconductor device 30A. For a planar structure example of the semiconductor device 30A, reference can be made to FIG. 17A . FIG. 19A is a cross-sectional view along the dot-dash line D1-D2 indicated by FIG. 17A . FIG. 19B is a cross-sectional view along the dot-dash line E3-E4 indicated by FIG. 17A . Further, for a cross-sectional structure example along the dot-dash line E1-E2 indicated by FIG. 17A , reference can be made to FIG. 18A .

[0309] The semiconductor device 30A includes the transistor 100 and the transistor 150A. The transistor 150A is mainly different from the transistor 150 illustrated in FIG. 17B , for example, in that the conductive layer 202 is provided between the insulating layer 110 and the insulating layer 120 in the transistor 150A.

[0310] In semiconductor device 30A, a conductive layer 202 is provided on the insulating layer 110. The conductive layer 202 can be made of the same material as the conductive layer 112b. The conductive layer 202 can be formed by the same process as the conductive layer 112b.

[0311] An insulating layer 120 is disposed on the conductive layer 202. The insulating layer 120 is disposed such that it covers a portion of the top and side surfaces of the conductive layer 202. The insulating layer 120 is disposed at least in the region where the semiconductor layer 208 overlaps with the conductive layer 204. In the transistor 150A, a portion of the insulating layer 120 is used as a back gate insulating layer. By disposing the conductive layer 202 between the insulating layers 110 and 120, the thickness of the back gate insulating layer of the transistor 150A can be made thin. This enhances the electric field of the back gate electrode. Furthermore, it improves the saturation of the transistor 150A. In addition, threshold voltage drift can be suppressed, and a transistor with a small cutoff current can be realized.

[0312] The insulating layer 120 preferably has a stacked structure. For example, the insulating layer 120 may have a two-layer stacked structure. In this case, the lower layer of the insulating layer 120 may have a region in contact with the conductive layer 202, and the upper layer of the insulating layer 120 may have a region in contact with the channel forming region of the semiconductor layer 208.

[0313] The lower layer of insulating layer 120 is preferably made of a material from which the metal elements contained in conductive layer 202 do not readily diffuse. This suppresses the diffusion of the metal elements contained in conductive layer 202 into the channel formation region in semiconductor layer 208. The lower layer of insulating layer 120 is suitable for using materials applicable to insulating layers 110a and 110c. For example, silicon nitride is suitable for the lower layer of insulating layer 120.

[0314] The upper layer of insulating layer 120 is preferably an oxygen-containing insulating layer. The upper layer of insulating layer 120 may use a material suitable for insulating layer 110b. For example, silicon oxynitride is suitable for the upper layer of insulating layer 120.

[0315] For details regarding transistor 100, please refer to the above description; therefore, detailed explanations are omitted.

[0316] [Semiconductor Device 30B] FIG. 16B This is a circuit diagram showing an example of the structure of semiconductor device 30B. FIG. 20A This is a plan view showing an example of the structure of semiconductor device 30B. FIG. 20B It is along FIG. 20A The cross-sectional view of the dotted line D1-D2 shown. FIG. 21A It is along FIG. 20A The cross-sectional view shown is the dotted line E1-E2. FIG. 21B It is along FIG. 20AA cross-sectional view of the dot-dashed line E3-E4 shown.

[0317] The semiconductor device 30B includes the transistor 100 and the transistor 200. Another of a source and a drain of the transistor 200 is electrically connected to another of a source and a drain of the transistor 100.

[0318] The transistor 100 and the transistor 200 are each formed over the substrate 102.

[0319] Since the transistor 100 can be described above, detailed description is omitted.

[0320] The transistor 200 includes the conductive layer 112b, the conductive layer 112c, the conductive layer 203, the insulating layer 205, the semiconductor layer 208, the insulating layer 106, and the conductive layer 204. The transistor 200 can have the same structure as the transistor 100.

[0321] The conductive layer 112c is used as one of a source and a drain of the transistor 200. The conductive layer 112b is used as another of a source and a drain of the transistor 100 and another of a source and a drain of the transistor 200. When the transistor 100 and the transistor 200 share the conductive layer 112b, the area occupied by the semiconductor device can be reduced.

[0322] The conductive layer 203 is used as a back gate electrode of the transistor 200. The insulating layer 205 is used as a back gate insulating layer of the transistor 200. A part of the insulating layer 106 is used as a gate insulating layer of the transistor 200. The conductive layer 204 is used as a gate electrode of the transistor 200.

[0323] The conductive layer 112c can use the same material as the conductive layer 112a. The conductive layer 112c can be formed by the same process as the conductive layer 112a. The insulating layer 110 includes an opening portion 241 reaching the conductive layer 112c. The opening portion 241 can be formed by the same process as the opening portion 141. The conductive layer 112b includes an opening portion 243 in a region overlapping with the opening portion 241. The opening portion 243 can be formed by the same process as the opening portion 143. Further, the opening portion 241 can have the same shape as the shape that the opening portion 141 can have. The opening portion 243 can have the same shape as the shape that the opening portion 143 can have.

[0324] Further, the width of the opening portion 141 and the width of the opening portion 241 can be made different. By making the widths of the openings different, two transistors having different channel widths from each other can be manufactured.

[0325] The conductive layer 203 is provided so as to be positioned inside the opening portion 241 and electrically connected to the conductive layer 112c. The conductive layer 203 has, for example, a region in contact with the conductive layer 112c and a region in contact with a side surface of the insulating layer 110 positioned inside the opening portion 241. Note that in the case where the conductive layer 203 has a region in contact with the conductive layer 112c, the boundary between the conductive layer 203 and the conductive layer 112c is not always clearly visible.

[0326] The conductive layer 203 can be formed using the same material as the conductive layer 103. The conductive layer 203 can be formed by the same process as the conductive layer 103. The conductive layer 103 and the conductive layer 203 can be formed, for example, by forming a conductive film so as to cover the opening portion 141, the opening portion 143, the opening portion 241, and the opening portion 243, and then performing anisotropic etching on the conductive film. By forming the conductive layer 203 using anisotropic etching, the transistor 200 can be a micro transistor.

[0327] The insulating layer 205 is provided so as to cover the conductive layer 203 inside the opening portion 241. The insulating layer 205 has, for example, a region in contact with the conductive layer 203 inside the opening portion 241 and a region in contact with the conductive layer 112c.

[0328] The insulating layer 205 can be formed using the same material as the insulating layer 105. The insulating layer 205 can be formed by the same process as the insulating layer 105. The insulating layer 105 and the insulating layer 205 can be formed, for example, by forming an insulating film so as to cover the opening portion 141, the opening portion 143, the opening portion 241, and the opening portion 243, and then performing anisotropic etching on the insulating film.

[0329] The semiconductor layer 208 is provided so as to cover the opening portion 241 and the opening portion 243. The semiconductor layer 208 can be formed by the same process as the semiconductor layer 108. The semiconductor layer 208 has the insulating layer 106 provided thereover, and the conductive layer 204 provided over the insulating layer 106. The conductive layer 204 can be formed by the same process as the conductive layer 104.

[0330] Note that, FIG. 20A and FIG. 20B An example in which the semiconductor layers of the transistor 100 and the transistor 200 are divided into the semiconductor layer 108 and the semiconductor layer 208 is illustrated, but one embodiment of the present application is not limited to this. The transistor 100 and the transistor 200 can also share a semiconductor layer.

[0331] [Semiconductor device 30C] FIG. 16C FIG. 17A is a circuit diagram illustrating a structure example of the semiconductor device 30C. FIG. 22A FIG. 17B is a plan view illustrating a structure example of the semiconductor device 30C. FIG. 22B FIG. 17C is a cross-sectional view along line F-G in FIG. 17B.FIG. 22A The cross-sectional view shown is along the dotted line D1-D2. Regarding the area along... FIG. 22A The example of the cross-sectional structure shown by the dotted line E1-E2 can be referenced. FIG. 21A Furthermore, regarding along FIG. 22A The example of the cross-sectional structure shown by the dotted lines E3-E4 can be referenced. FIG. 21B .

[0332] Semiconductor device 30C includes transistor 100 and transistor 200. One of the source and drain of transistor 200 is electrically connected to one of the source and drain of transistor 100.

[0333] Transistor 100 and transistor 200 are both formed on substrate 102.

[0334] Since transistor 100 can be described in the above description, detailed instructions are omitted.

[0335] Transistor 200 includes conductive layer 112a, conductive layer 112c, conductive layer 203, insulating layer 205, semiconductor layer 208, insulating layer 106 and conductive layer 204.

[0336] Conductive layer 112a is used as one of the source and drain electrodes of transistor 100 and transistor 200. Conductive layer 112c is used as the other of the source and drain electrodes of transistor 200. When transistors 100 and 200 share conductive layer 112a, the footprint of the semiconductor device can be reduced.

[0337] The conductive layer 112c can be made of the same material as the conductive layer 112b. The conductive layer 112c can be formed by the same process as the conductive layer 112b. In the semiconductor device 30C, an opening 241 leading to the conductive layer 112a is formed in the insulating layer 110. Furthermore, an opening 243 is formed in the conductive layer 112c.

[0338] [Semiconductor Device 30D] FIG. 16D This is a circuit diagram showing an example of the structure of a semiconductor device 30D. FIG. 23A This is a plan view showing an example of the structure of a semiconductor device 30D. FIG. 23B It is along FIG. 23A The cross-sectional view of the dotted line D1-D2 shown.

[0339] Semiconductor device 30D includes transistor 100 and transistor 250. One of the source and drain of transistor 250 is electrically connected to one of the source and drain of transistor 100.

[0340] Transistor 100 and transistor 250 are both disposed on substrate 102.

[0341] The semiconductor device 30D includes a conductive layer 259 over the substrate 102, includes an insulating layer 252 over the substrate 102 and the conductive layer 259, and includes a semiconductor layer 253 over the insulating layer 252. Further, an insulating layer 254 is included over the insulating layer 252 and the semiconductor layer 253, and a conductive layer 255 is included over the insulating layer 254. The semiconductor layer 253 and the conductive layer 255 have a region where they overlap with each other. The conductive layer 259 is used as a back gate electrode of a transistor 250, and the insulating layer 252 is used as a back gate insulating layer. The insulating layer 254 is used as a gate insulating layer, and the conductive layer 255 is used as a gate electrode.

[0342] An insulating layer 256 is provided over the insulating layer 254 and the conductive layer 255. Further, an opening portion 257a is provided in the insulating layer 254 and the insulating layer 256 in a region overlapping with part of the semiconductor layer 253. Further, an opening portion 257b is provided in the insulating layer 254 and the insulating layer 256 in a region overlapping with another part of the semiconductor layer 253.

[0343] A conductive layer 258a is provided so as to have a region over the insulating layer 256 and a region inside the opening portion 257a. A conductive layer 258b is provided so as to have a region over the insulating layer 256 and a region inside the opening portion 257b. The conductive layer 258a has a region which is in contact with the semiconductor layer 253 inside the opening portion 257a. The conductive layer 258b has a region which is in contact with the semiconductor layer 253 inside the opening portion 257b.

[0344] In the semiconductor layer 253, a region overlapping with the conductive layer 255 is used as a channel formation region. The semiconductor layer 253 has a pair of regions 253D which sandwich the channel formation region. One of the pair of regions 253D is used as one of a source region and a drain region and is electrically connected to the conductive layer 258a. The other of the pair of regions 253D is used as the other of the source region and the drain region and is electrically connected to the conductive layer 258b.

[0345] An insulating layer 110 is provided over the insulating layer 256, the conductive layer 258a, and the conductive layer 258b, and a conductive layer 112b is provided over the insulating layer 110.

[0346] The conductive layer 259 preferably overlaps with the channel formation region of the transistor 250 and extends beyond an end portion of the channel formation region of the transistor 250. In other words, the conductive layer 259 is preferably larger than the channel formation region of the transistor 250. Further, the conductive layer 259 preferably extends beyond an end portion of the semiconductor layer 253. In other words, the conductive layer 259 is preferably larger than the semiconductor layer 253.

[0347] The gate electrode and back gate electrode are configured such that a channel forming a region sandwiching the semiconductor layer is used. Furthermore, the threshold voltage of the transistor can be changed by altering the potential of the back gate electrode. The potential of the back gate electrode can be ground or any other potential.

[0348] The back gate electrode can be formed using the same materials and methods as the gate, source, and drain electrodes. Furthermore, since the gate and back gate electrodes are conductive layers, they prevent external electric fields from affecting the semiconductor layer forming the channel (especially providing electrostatic discharge shielding). In other words, they prevent changes in the transistor's electrical characteristics due to external electric fields such as electrostatic discharge. Additionally, by providing a back gate electrode, the change in the transistor's threshold voltage before and after BT (Bias Temperature) stress testing can be reduced. By providing a back gate electrode, transistor characteristic non-uniformity is reduced, improving the reliability of the semiconductor device.

[0349] like FIG. 16E As shown, the back gate and gate of transistor 250 can also be electrically connected to each other. Furthermore, as... FIG. 16F As shown, the back gate of transistor 250 is electrically connected to either the source or drain. Furthermore, as... FIG. 16G As shown, transistor 250 may also not include a back gate.

[0350] exist FIGS. 16D-16H In this embodiment, transistor 100 is an n-channel transistor and transistor 250 is a p-channel transistor; however, this is not the only embodiment of the invention. Both transistor 100 and transistor 250 can be either n-channel or p-channel transistors. Furthermore, transistor 100 can also be a p-channel transistor and transistor 250 can also be an n-channel transistor.

[0351] Similar to transistor 100, an OS transistor can also be used as transistor 250.

[0352] Here, semiconductor layer 108 and semiconductor layer 253 may be made of the same material or different materials. The structure of semiconductor layer 108 and semiconductor layer 253 can be referred to the description of semiconductor layer 108 and semiconductor layer 208 in semiconductor device 30.

[0353] Transistor 250 can also be a transistor that uses silicon for the channel formation region (hereinafter also referred to as a Si transistor).

[0354] Examples of silicon include monocrystalline silicon, polycrystalline silicon, and amorphous silicon. In particular, transistors containing LTPS in the semiconductor layer (hereinafter also referred to as LTPS transistors) can be used. LTPS transistors have high field-effect mobility and good frequency characteristics.

[0355] The transistor 100 included in the semiconductor device 30D includes the conductive layer 258a instead of the conductive layer 112a, and has the same structure as described above except for this.

[0356] The conductive layer 258a is used as one of a source electrode and a drain electrode of the transistor 100 and as one of a source electrode and a drain electrode of the transistor 250. When the transistor 100 and the transistor 250 share the conductive layer 258a, the semiconductor device can be reduced in size.

[0357] As described above, the transistor 100 is a vertical channel transistor. On the other hand, in the transistor 250, current flowing through the semiconductor layer flows in a lateral direction, i.e., a direction parallel or substantially parallel to a surface of the substrate 102. Such a transistor can be referred to as a lateral channel transistor or a lateral channel transistor.

[0358] Thus, the semiconductor device of one embodiment of the present application can include a lateral channel transistor in addition to a vertical channel transistor.

[0359] Further, the transistor 100 can be formed in a region overlapping with the opening portion 257a. Specifically, a structure in which the opening portion 141 and the opening portion 143 are provided in a region overlapping with the opening portion 257a and the conductive layer 258a is in contact with the semiconductor layer 108 and the conductive layer 103 in the opening portion 257a can be employed. Alternatively, a structure in which the conductive layer 258a is not provided and the region 253D is in contact with the semiconductor layer 108 and the conductive layer 103 in the opening portion 257a can be employed. With such a structure, a semiconductor device can be reduced in size.

[0360] [Semiconductor Device 30E] FIG. 16H FIG. 17A is a circuit diagram illustrating a structure example of the semiconductor device 30E. FIG. 24A FIG. 17B is a plan view illustrating the structure example of the semiconductor device 30E. FIG. 24B FIG. 17C is a cross-sectional view along the dot-dash line D1-D2 in FIG. 17B. FIG. 24A

[0361] The semiconductor device 30E includes the transistor 100 and the transistor 250. The gate of the transistor 250 is electrically connected to one of the source and the drain of the transistor 100.

[0362] The semiconductor device 30E differs from the semiconductor device 30D mainly in that the opening portion 141 and the opening portion 143 are provided so as to overlap with the conductive layer 255 serving as the gate electrode of the transistor 250 in the semiconductor device 30E. Thus, in the semiconductor device 30D, the transistor 100 is provided so as to overlap with the gate electrode of the transistor 250. ​

[0363] In FIG. 24A In FIG. 24B In the semiconductor device 30E, the conductive layer 255 is used as a gate electrode of the transistor 250 and as one of a source electrode and a drain electrode of the transistor 100.

[0364] By overlapping the transistor 250 and the transistor 100, a semiconductor device with a further reduced area occupation can be implemented.

[0365] The semiconductor device 30E differs from the semiconductor device 30D in the structure of the opening 257a, the opening 257b, the conductive layer 258a, and the conductive layer 258b.

[0366] The openings 257a and 257b are formed in regions overlapping with the region 253D of the semiconductor layer 253 by selectively removing parts of the insulating layer 254 and the insulating layer 110, respectively. The conductive layer 258a and the conductive layer 258b are provided over the insulating layer 110 and electrically connected to the region 253D through the openings 257a and 257b.

[0367] In the semiconductor device 30E, the conductive layer 258a and the conductive layer 258b can be formed by the same process as the conductive layer 112b. Since the conductive layer 258a and the conductive layer 258b do not need to be formed by a different process from the conductive layer 112b, the manufacturing process of the semiconductor device can be shortened, which increases the productivity of the semiconductor device.

[0368] A semiconductor device of one embodiment of the present application includes at least one transistor and at least one capacitor element, and a source or a drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor element. FIG. 16I An example is shown in which a source or a drain of the transistor 100 is electrically connected to one electrode of the capacitor element 190.

[0369] The transistor of one embodiment of the present application is one of vertical transistors, and can be made much smaller than a planar transistor because the source electrode, the semiconductor layer, and the drain electrode can be provided in a stacked manner. Furthermore, by using a p-channel Si transistor as a planar transistor and an n-channel OS transistor as a vertical transistor, a CMOS (Complementary Metal Oxide Semiconductor) circuit can be formed. Furthermore, by employing this structure and providing a planar transistor and a vertical transistor in a stacked manner, the area occupied by the CMOS circuit can be reduced.

[0370] Example 1 of a method for manufacturing a semiconductor device A method for manufacturing a semiconductor device of one embodiment of the present application will be described below with reference to drawings.

[0371] The thin films (insulating films, semiconductor films, and conductive films) included in the semiconductor device can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, or an ALD method. As the CVD method, there are a PECVD method and a thermal CVD method. As the thermal CVD method, there is a metal organic CVD (MOCVD) method.

[0372] In addition, the thin films (insulating films, semiconductor films, and conductive films) included in the semiconductor device can be formed by a wet deposition method such as a spin coating method, an immersion method, a spray coating method, an inkjet method, a dispenser method, a screen printing method, an offset printing method, a doctor knife method, a slit coating method, a roll coating method, a curtain coating method, or a blade coating method.

[0373] In processing the above thin films, for example, the thin films can be etched in accordance with a pattern of a resist mask after the resist mask is formed by a photolithography method. Alternatively, the thin films can be processed by a nanoimprint method, a sandblasting method, or a lift-off method. In addition, the thin films can be formed in an island shape by a deposition method using a shadow mask or the like. Further, the thin films having photosensitivity can be processed by exposure and development. That is, the thin films having photosensitivity can be processed by a photolithography method.

[0374] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion exposure techniques can be employed. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferred because they allow for extremely fine processing. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0375] As a method for etching thin films, dry etching or wet etching can be used.

[0376] Here, refer to FIGS. 25A-29B illustrate FIG. 1B and FIG. 1C An example of a method for manufacturing a semiconductor device is shown. FIGS. 25A-29B Arrange FIG. 1B The cross-sectional view along the dotted line A1-A2 shown below and FIG. 1C The cross-sectional view shown is along the dotted line B1-B2.

[0377] First, a conductive layer 112a is formed on the substrate 102. FIG. 25A For example, a conductive film that will become a conductive layer 112a is formed on a substrate 102, and the conductive film is processed to form the conductive layer 112a. The conductive film that becomes the conductive layer 112a can be formed, for example, by sputtering. Alternatively, after forming a photoresist mask on the conductive film by a photolithography process, the metal film can be processed, for example, by using one or both of wet etching and dry etching methods to form the conductive layer 112a. The conductive layer 112a can be formed, for example, using conductive oxides such as In-Sn oxide, metallic elements such as titanium, or alloys containing multiple metallic elements.

[0378] For example, when forming FIG. 6B and FIG. 7A When forming the conductive layer 112a, a conductive film that will become the conductive layer 112a1 is first formed on the substrate 102, and the conductive film is processed to form the conductive layer 112a1. Next, a conductive film that will become the conductive layer 112a2 is formed on the conductive layer 112a1 and the substrate 102, and the conductive film is processed to form the conductive layer 112a2. Thus, the conductive layer 112a1 and the conductive layer 112a2 covering the conductive layer 112a1 can be formed. Furthermore, when forming... FIG. 7B1 and FIG. 7B2When the conductive layer 112a is formed as shown, the conductive layer 112a2 and the conductive layer 112a1 can be formed by sequentially forming a conductive film to be the conductive layer 112a1 and a conductive film to be the conductive layer 112a2 over the substrate 102, and processing the conductive films. The conductive layer 112a1 can be formed using a conductive oxide, for example. Further, the conductive layer 112a2 can be formed using a metal element such as titanium or an alloy containing a plurality of metal elements.

[0379] Next, the insulating layer 110 is formed over the conductive layer 112a and the substrate 102. As the insulating layer 110, for example, the insulating layer 110a, the insulating layer 110b over the insulating layer 110a, and the insulating layer 110c over the insulating layer 110b are sequentially formed. FIG. 25B ).

[0380] The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be formed by a PECVD method or a sputtering method, for example. For example, by successively forming the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c in a vacuum, attachment of impurities from the atmosphere to the surface of the insulating layer 110a and the surface of the insulating layer 110b can be inhibited, which is preferable. As the impurities, water and an organic substance can be given, for example.

[0381] The insulating layer 110a and the insulating layer 110c can be formed in an atmosphere containing hydrogen. For example, when an insulating film containing nitrogen is formed as the insulating layer 110a and the insulating layer 110c, the insulating layer 110a and the insulating layer 110c can be formed in an atmosphere containing hydrogen. For example, by a PECVD method using ammonia as a nitrogen source, the insulating layer 110a and the insulating layer 110c can be formed in an atmosphere containing hydrogen. Thus, the insulating layer 110a and the insulating layer 110c can contain hydrogen. Thus, the resistance of the source region and the drain region of the semiconductor layer 108 formed in a later step can be reduced. Accordingly, a transistor whose on-state current is low can be formed.

[0382] The insulating layer 110b is preferably formed by a method which does not use a gas containing hydrogen. For example, when an oxide insulating film is formed as the insulating layer 110b by a PECVD method, the insulating layer 110b can be formed without using a gas containing hydrogen. Thus, a film with little hydrogen can be formed as the insulating layer 110b. Accordingly, hydrogen can be prevented from being supplied to the channel formation region of the semiconductor layer 108 formed in a later step. Thus, a transistor which has a good electrical characteristic and is highly reliable can be manufactured. Further, when an oxide insulating film is formed as the insulating layer 110b by a sputtering method, the insulating layer 110b can be formed without using a gas containing hydrogen.

[0383] As described above, by forming the insulating layer 110a and the insulating layer 110c in an atmosphere containing hydrogen and forming the insulating layer 110b by a method that does not use a gas containing hydrogen, the resistance of the source region and the drain region of the semiconductor layer 108 formed in a later step can be reduced while the supply of hydrogen to the channel formation region is inhibited.

[0384] The substrate temperature at the time of forming the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c is preferably higher than or equal to 180 °C and lower than or equal to 450 °C, more preferably higher than or equal to 200 °C and lower than or equal to 450 °C, further more preferably higher than or equal to 250 °C and lower than or equal to 450 °C, still further more preferably higher than or equal to 300 °C and lower than or equal to 450 °C, yet further more preferably higher than or equal to 300 °C and lower than or equal to 400 °C, and extremely further more preferably higher than or equal to 350 °C and lower than or equal to 400 °C. By setting the substrate temperature at the time of forming the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c in the above range, the release of impurities (e.g., water and hydrogen) from the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c themselves can be reduced, and thus the diffusion of impurities to the semiconductor layer 108 formed in a later step can be inhibited. Thus, the transistor included in the semiconductor device of one embodiment of the present application can be a transistor which has good electrical characteristics and high reliability.

[0385] Note that since the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are formed first and then the semiconductor layer 108 is formed, there is no concern that oxygen is released from the semiconductor layer 108 due to heat applied at the time of forming the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c.

[0386] Further, oxygen can be supplied to the insulating layer 110b after the formation of the insulating layer 110b and before the formation of the insulating layer 110c. As a method for supplying oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used, for example. As the plasma treatment, a device for plasma-izing an oxygen gas with high-frequency power can be suitably used. As the device for plasma-izing a gas with high-frequency power, a PECVD device, a plasma etching device, and a plasma ashing device can be given, for example. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, the plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N20), nitrogen dioxide (NO2), carbon monoxide, and carbon dioxide.

[0387] Further, the plasma treatment can be performed without exposing the surface of the insulating layer 110b to the atmosphere after the insulating layer 110b is formed. For example, in the case where the insulating layer 110b is formed using a PECVD apparatus, the plasma treatment is preferably performed using the PECVD apparatus. This can increase the productivity. Specifically, the N2O plasma treatment can be continuously performed after the insulating layer 110b is formed using the PECVD apparatus.

[0388] Further, by forming a film such as an insulating film, a semiconductor film, or a conductive film over the insulating layer 110b in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110b. As the film, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used.

[0389] As the film, an oxide material containing one or more elements which are the same as those of the semiconductor layer 108 is preferably used. In particular, an oxide semiconductor material which can be used for the semiconductor layer 108 is preferably used.

[0390] When the film is formed, the higher the oxygen flow ratio of a deposition gas introduced into a treatment chamber of a deposition apparatus or the oxygen partial pressure in the treatment chamber, the more oxygen can be supplied to the insulating layer 110b. The oxygen flow ratio or the oxygen partial pressure is, for example, higher than or equal to 50 % and lower than or equal to 100 %, preferably higher than or equal to 65 % and lower than or equal to 100 %, more preferably higher than or equal to 80 % and lower than or equal to 100 %, still more preferably higher than or equal to 90 % and lower than or equal to 100 %. In particular, the oxygen flow ratio is preferably set to 100 % so that the oxygen partial pressure is as close to 100 % as possible.

[0391] In this manner, by forming the film by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating layer 110b while preventing oxygen from being released from the insulating layer 110b at the time of forming the film. As a result, more oxygen can be enclosed in the insulating layer 110b. Further, more oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, the oxygen vacancy and V O H, and a transistor with high reliability which has favorable electrical characteristics can be manufactured.

[0392] Further, a heat treatment can be performed after the film is formed. By performing a heat treatment after the film is formed, oxygen can be efficiently supplied to the insulating layer 110b from the film.

[0393] The temperature of the heat treatment is preferably higher than or equal to 150 °C and lower than the strain point of the substrate, more preferably higher than or equal to 200 °C and lower than 450 °C, still more preferably higher than or equal to 250 °C and lower than 450 °C, further more preferably higher than or equal to 300 °C and lower than 450 °C, still further more preferably higher than or equal to 300 °C and lower than 400 °C, and yet further more preferably higher than or equal to 350 °C and lower than 400 °C. The heat treatment can be performed in an atmosphere containing one or more of a rare gas, nitrogen, and oxygen. As the nitrogen-containing atmosphere or the atmosphere containing oxygen, dry air (CDA: Clean Dry Air) can also be used. Note that the content of hydrogen and oxygen and the like in the atmosphere is preferably as low as possible. As the atmosphere, a high-purity gas whose dew point is -60 °C or lower, preferably -100 °C or lower, is preferably used. By using an atmosphere whose content of hydrogen and water and the like is as low as possible, absorption of hydrogen and water and the like into the insulating layer 110a and the insulating layer 110b and the like can be prevented as much as possible. The heat treatment can be performed using an oven or a rapid thermal annealing (RTA) apparatus or the like. By using an RTA apparatus, the heat treatment time can be shortened.

[0394] Oxygen can also be supplied to the insulating layer 110b through the film after the film is formed or after the heat treatment. As a method for supplying oxygen, for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used. As for the plasma treatment, the above description can be referred to, and thus a detailed description thereof is omitted.

[0395] Next, the film is removed. Although there is no particular limitation on the method for removing the film, a wet etching method can be appropriately employed. By using a wet etching method, the insulating layer 110b can be prevented from being etched when the film is removed. Thus, the thickness of the insulating layer 110b can be prevented from being reduced, and the thickness of the insulating layer 110b can be made uniform.

[0396] Next, a conductive film 112f (b) which will become a conductive layer 112b is formed over the insulating layer 110. FIG. 25C For example, the conductive film 112f is formed so as to have a region in contact with the top surface of the insulating layer 110c. For example, a sputtering method is preferably used when the conductive film 112f is formed. Then, the conductive film 112f is processed into a desired shape to form the conductive layer 112b (b) over the insulating layer 110. FIG. 26A For example, the conductive layer 112b is formed so as to have a region in contact with the top surface of the insulating layer 110c. As the conductive layer 112b, for example, a conductive oxide such as In-Sn oxide is preferably used. Further, when the conductive layer 112b has a stacked-layer structure of two or more layers, it is preferable to use a conductive oxide such as In-Sn oxide as the uppermost layer in contact with the semiconductor layer 108 formed in a later step.

[0397] Next, the opening portion 143 is formed by processing the conductive layer 112b. FIG. 26B The opening portion 143 is formed so as to have an area overlapping with the conductive layer 112a. Further, the conductive layer 112b provided with the opening portion 143 can be formed by processing the conductive film 112f into a desired shape after the opening portion 143 is formed in the conductive film 112f. In other words, the order of the processes shown in FIG. 12A and FIG. 12B can be reversed. FIG. 26A The process shown in FIG. 12A and the process shown in FIG. 12B. FIG. 26B The process shown in FIG. 12A and the process shown in FIG. 12B.

[0398] Next, the opening portion 141 is formed by processing the insulating layer 110. FIG. 26C The opening portion 141 is formed so as to have an area overlapping with the opening portion 143 and to reach the conductive layer 112a. By forming the opening portion 141, the area of the conductive layer 112a overlapping with the opening portion 141 and the opening portion 143 can be exposed.

[0399] The opening portion 143 and the opening portion 141 can be formed using one or both of a wet etching method and a dry etching method. The opening portion 143 is, for example, suitably formed using a wet etching method. The opening portion 141 is, for example, suitably formed using a dry etching method. Further, the wet etching method can be a processing method having higher isotropy than the dry etching method. Therefore, in a case where the opening portion 143 is formed using a wet etching method and the opening portion 141 is formed using a dry etching method, as shown in FIG. 13A and FIG. 13B, the bottom end portion of the opening portion 143 on the side of the conductive layer 112b can not be aligned with the portion 123. For example, the insulating layer 110 can have an area protruding further toward the side of the opening portion 141 than the conductive layer 112b when viewed in cross section. FIG. 10A FIG. 10B

[0400] The opening portion 141 can be formed using a resist mask used to form the opening portion 143, for example. For example, after the conductive layer 112b is formed, a resist mask is formed on the conductive layer 112b. Next, a portion of the conductive layer 112b is removed using the resist mask to form the opening portion 143. Then, a portion of the insulating layer 110 can be removed using the resist mask to form the opening portion 141. Further, the opening portion 141 and the opening portion 143 can be formed using different resist masks, respectively.

[0401] Next, the conductive film 103f to be the conductive layer 103 is formed so as to cover the opening portion 141 and the opening portion 143. FIG. 27A ​​). The conductive film 103f is formed on the insulating layer 110 in a manner to cover the side surface of the insulating layer 110 positioned inside the opening portion 141 and the top surface of the conductive layer 112a exposed by the opening portion 141. The conductive film 103f can be formed in a manner to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the insulating layer 110, a region in contact with the side surface of the conductive layer 112b, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the top surface of the insulating layer 110. For example, the conductive film 103f can be formed by a sputtering method, a thermal CVD method (including a MOCVD method), or an ALD method.

[0402] Next, the conductive film 103f is anisotropically etched. Thus, the conductive layer 103 is formed inside the opening portion 141 in a manner to be electrically connected to the conductive layer 112a FIG. 27B Specifically, the conductive layer 103 is formed along the side surface of the insulating layer 110 positioned inside the opening portion 141 in a manner to have a region in contact with the conductive layer 112a inside the opening portion 141. Further, the conductive layer 103 can be formed in a manner to have a region in contact with the side surface of the insulating layer 110 positioned inside the opening portion 141.

[0403] It is preferable to anisotropically etch the conductive film 103f in a manner that the uppermost portion of the conductive layer 103 is positioned below the top end portion of the opening portion 141 side of the insulating layer 110. That is, it is preferable to anisotropically etch the conductive film 103f in a manner that the conductive layer 103 is not provided inside the opening portion 143. For example, it is preferable to adjust the speed and time of the anisotropic etching to provide the conductive layer 103 inside the opening portion 141 and not inside the opening portion 143. Thus, for example, it is possible to prevent the conductive layer 103 from contacting the conductive layer 112b and shorting.

[0404] It is preferable to anisotropically etch the conductive film 103f under conditions that the selectivity with respect to the conductive layer 112a and the conductive layer 112b is high. That is, it is preferable to anisotropically etch the conductive film 103f under conditions that the etching speed of the conductive film 103f is faster than the etching speed of the conductive layer 112a and the conductive layer 112b. Thus, it is possible to suppress the conductive layer 112a and the conductive layer 112b from being unintentionally etched when the conductive film 103f is anisotropically etched. Therefore, it is possible to improve the manufacturing yield of the semiconductor device. Further, it is possible to provide a semiconductor device with high reliability.

[0405] As the conductive film 103f, it is preferable to use a metallic element such as titanium or an alloy containing multiple metallic elements. This allows, for example, the formation of a conductive layer 103 with low resistance. Furthermore, by using a metal such as titanium as the conductive film 103f and a conductive oxide such as In-Sn oxide as the conductive layers 112a and 112b, the etch selectivity ratio of the conductive film 103f to the conductive layers 112a and 112b can be improved.

[0406] Here, sometimes anisotropic etching of the conductive film 103f results in, for example, the formation of, within the conductive layer 112a. FIG. 5 The recess 129 is shown. For example, the recess 129 is sometimes formed when the etch selectivity of the conductive film 103f relative to the conductive layer 112a is lower than that relative to the conductive layer 112b.

[0407] For example, in conductive layer 112a having FIGS. 6B-7B2 In the structure shown, by using a material with a higher etch selectivity relative to the conductive film 103f as the conductive layer 112a1 compared to the conductive layer 112a2, the processing of the conductive layer 112a1 when forming the recess 129 in the conductive layer 112a can be suppressed. Therefore, it is possible to prevent the conductive layer 112a from being completely removed in the area overlapping with the opening 141 but not with the conductive layer 103. This prevents the bottom surface of the semiconductor layer 108 formed in subsequent processes from not contacting the conductive layer 112a.

[0408] Furthermore, by using a material with a lower etch selectivity relative to the conductive film 103f compared to the conductive layer 112a1 as the conductive layer 112a2, it is easy to form the recess 129 in the conductive layer 112a. Therefore, as described above, it is easy to form a transistor with a large on-state current.

[0409] As described above, conductive layer 112a1 can be, for example, a conductive oxide. Furthermore, conductive layer 112a2 is preferably made of the same material as the material that can be used for conductive film 103f. For example, conductive layer 112a2 and conductive film 103f can use the same material.

[0410] In the case where the conductive film 103f is anisotropically etched to form the conductive layer 103, unlike the case where the conductive film 103f is processed to form the conductive layer 103 after being patterned by photolithography, for example, a mask is not needed to be used. Thus, in the method for manufacturing the semiconductor device of one embodiment of the present application, the conductive layer 103 can be formed without considering the alignment accuracy of a mask, for example. By the above process, even when the opening portion 141 in which the conductive layer 103 is formed is miniaturized, the conductive layer 103 can be prevented from not being formed in the inside of the opening portion 141, for example. Thus, in the method for manufacturing the semiconductor device of one embodiment of the present application, a miniaturized transistor can be manufactured.

[0411] Next, the insulating film 105f is formed so as to cover the conductive layer 103 and the conductive layer 112b. FIG. 27C For example, the insulating film 105f can be formed so as to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the conductive layer 103, a region in contact with the side surface of the insulating layer 110, a region in contact with the top surface of the insulating layer 110, a region in contact with the side surface of the conductive layer 112b, and a region in contact with the top surface of the conductive layer 112b. For example, the insulating film 105f can be formed by a PECVD method or an ALD method.

[0412] Next, the insulating film 105f is anisotropically etched. For example, the insulating film 105f is anisotropically etched until at least part of the top surface of the conductive layer 112b is exposed. By anisotropic etching of the insulating film 105f, the insulating layer 105 FIG. 28A ) is formed so as to cover the conductive layer 103. The insulating layer 105 can be formed so as to have a region in contact with the conductive layer 103 in the inside of the opening portion 141 and a region in contact with the conductive layer 112a. Further, the insulating layer 105 can be formed so as to have a region in contact with the side surface of the conductive layer 112b in the inside of the opening portion 143.

[0413] The uppermost portion of the insulating layer 105 can be aligned or substantially aligned with the top surface of the conductive layer 112b. Further, as FIG. 4A indicated, the uppermost portion of the insulating layer 105 and the uppermost portion of the insulating layer 105a are sometimes positioned between the bottom surface and the top surface of the conductive layer 112b. Further, as FIG. 4B indicated, the uppermost portion of the insulating layer 105 is sometimes positioned below the bottom surface of the conductive layer 112b. The position of the uppermost portion of the insulating layer 105 can be changed depending on the speed and time of anisotropic etching, for example.

[0414] The insulating layer 105a is formed by anisotropic etching of the insulating film 105f, and is sometimes formed so as to cover at least part of the side surface of the conductive layer 112b, specifically, the side surface on the side opposite to the opening portion 143. The insulating layer 105a is formed as a residue when the insulating layer 105 is formed.

[0415] The insulating layer 105a can be formed so as to have a region in contact with the side surface of the conductive layer 112b on the side opposite to the opening portion 143. For example, when the insulating film 105f is anisotropically etched so that the uppermost part of the insulating layer 105 is positioned above the top surface of the insulating layer 110, e.g., the top surface end portion on the side of the opening portion 141 of the insulating layer 110, the insulating layer 105a is sometimes formed. For example, when the insulating layer 105 is formed so as to have a region in contact with the side surface of the conductive layer 112b positioned in the opening portion 143, the insulating layer 105a is sometimes formed. Note that the insulating layer 105a is not always formed. When the insulating layer 105 is formed so that the uppermost part of the insulating layer 105 is aligned with or positioned below the top surface of the insulating layer 110, e.g., the top surface end portion on the side of the opening portion 141 of the insulating layer 110, the insulating layer 105a is not always formed. Further, even when the insulating layer 105 is formed so that the uppermost part of the insulating layer 105 is positioned above the top surface of the insulating layer 110, e.g., the top surface end portion on the side of the opening portion 141 of the insulating layer 110, the insulating layer 105a is not always formed.

[0416] By anisotropic etching of the insulating film 105f in a manner to form the insulating layer 105a, exposure of the conductive layer 103 can be prevented. For example, by slowing down the speed of anisotropic etching, the insulating layer 105 can be formed in a manner to prevent exposure of the conductive layer 103. Thus, the semiconductor layer 108 formed in a later step can be prevented from being in contact with the conductive layer 103 and short-circuiting. Therefore, the yield of the semiconductor device of one embodiment of the present application can be increased. On the other hand, since the throughput decreases when the speed of anisotropic etching of the insulating film 105f is slowed down, the speed of anisotropic etching is preferably adjusted in consideration of the yield of the semiconductor device and the throughput.

[0417] Here, a part of the insulating layer 110 is sometimes processed due to anisotropic etching of the insulating film 105f. Due to this, the thickness of a region of the insulating layer 110 which neither overlaps with the conductive layer 112b nor overlaps with the insulating layer 105a is sometimes thinner than the thickness of a region of the insulating layer 110 which overlaps with the conductive layer 112b or the insulating layer 105a. That is, a recess is sometimes formed in a region of the insulating layer 110 which neither overlaps with the conductive layer 112b nor overlaps with the insulating layer 105a. For example, when the etching selectivity ratio of the insulating film 105f to the insulating layer 110c is low, a recess is sometimes formed in the insulating layer 110. Note that, for example, in the case where the insulating layer 110 has a three-layer stacked structure of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c, as long as the etching selectivity ratio of the insulating film 105f to the insulating layer 110c is high, a recess can be inhibited from being formed in the insulating layer 110 even in the case where the etching selectivity ratio of the insulating film 105f to the insulating layer 110b is low. For example, as the insulating film 105f, the same material as the insulating layer 110b can be used.

[0418] Further, one or both of a part of the conductive layer 112a and a part of the conductive layer 112b are sometimes processed due to anisotropic etching of the insulating film 105f. By a part of the conductive layer 112a being processed, a recess is sometimes formed in the conductive layer 112a in a region overlapping with the opening portion 141 and not overlapping with the conductive layer 103. For example, when the etching selectivity ratio of the insulating film 105f to the conductive layer 112a is low, a recess is sometimes formed in the conductive layer 112a. When a part of the conductive layer 112b is processed, the thickness of the conductive layer 112b is sometimes thinned. Specifically, the thickness of the conductive layer 112b after the insulating layer 105 is formed is sometimes thinner than the thickness of the conductive layer 112b before the insulating layer 105 is formed. For example, when the etching selectivity ratio of the insulating film 105f to the conductive layer 112b is low, the thickness of the conductive layer 112b is sometimes thinned.

[0419] Next, a semiconductor film 108f which will become the semiconductor layer 108 is formed so as to cover the opening portion 141 and the opening portion 143 (see FIG 6B). FIG. 28B The semiconductor film 108f is formed so as to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the insulating layer 105, a region in contact with the insulating layer 105a, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the top surface of the insulating layer 110.

[0420] It is preferable to form the semiconductor film 108f by an ALD method. As described above, the ALD method is a deposition method in which a film is formed due to a reaction at the surface of a processed object. Thus, by forming the semiconductor film 108f by the ALD method, damage to the semiconductor film 108f can be reduced.

[0421] When the semiconductor film 108f is damaged, oxygen vacancies are sometimes generated in the semiconductor film 108f, for example. As a method of filling the oxygen vacancies, a method of supplying oxygen to the semiconductor layer 108 having the oxygen vacancies can be given. For example, by causing one or both of the insulating layer 105 and the insulating layer 106 formed in a later step to contain excess oxygen and performing heat treatment or the like, oxygen can be supplied to the semiconductor layer 108. However, when the insulating layer 105 contains excess oxygen, the resistance of the conductive layer 103, the conductive layer 112a, and the conductive layer 112b is sometimes increased due to oxidation of the conductive layer 103, the conductive layer 112a, and the conductive layer 112b. Further, when the insulating layer 106 contains excess oxygen, the resistance of the conductive layer 104 and the conductive layer 112b is sometimes increased due to oxidation of the conductive layer 104 and the conductive layer 112b.

[0422] In this specification and the like, excess oxygen refers to oxygen which exists in a layer and is not bonded to the layer (free) or oxygen which has low bonding energy to the layer.

[0423] Thus, when the semiconductor film 108f is formed using a deposition method which has little damage such as an ALD method, generation of oxygen vacancies can be suppressed as compared to the case where the semiconductor film 108f is formed using a deposition method which has much damage. Thus, a process for filling the oxygen vacancies of the semiconductor layer 108 is not needed. As described above, generation of oxygen vacancies in the semiconductor layer 108 can be suppressed while oxidation of the conductive layer included in the transistor of one embodiment of the present application is suppressed. Thus, a semiconductor device with high reliability can be manufactured.

[0424] When the semiconductor film 108f is formed using an ALD method, a deposition method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) is preferably used. The thermal ALD method has extremely high step coverage and is thus preferable. Further, the PEALD method has high step coverage and can perform low-temperature deposition, and is thus preferable.

[0425] The semiconductor film 108f can be formed using a precursor containing a constituent metal element and an oxidizing agent, for example, by an ALD method.

[0426] As a precursor containing indium, for example, trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, indium cyclopentadienyl, indium (III) chloride, and (3-(dimethylamino)propyl)dimethylindium can be given.

[0427] As a precursor containing gallium, for example, trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium (III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium (III) chloride can be given.

[0428] As the precursor containing tin, for example, tetramethyltin, tetraethyltin, tetravinyltin, tetraallyltin, tributylvinyltin, allyltributyltin, tributylethyltin, tributylphenyltin, trimethyltin chloride, triethyltin chloride, and tin (IV) chloride can be given.

[0429] As the precursor containing zinc, for example, dimethylzinc, diethylzinc, bis (2, 2, 6, 6-tetramethyl-3, 5-heptanedionate) zinc, and zinc chloride can be given.

[0430] For example, when an In-Ga-Zn oxide is formed, three kinds of precursors, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc can be used. Alternatively, two kinds of precursors, a precursor containing indium, and a precursor containing gallium and zinc can be used.

[0431] As the oxidizing agent, for example, ozone, oxygen, and water can be given.

[0432] As a method of controlling the composition of the obtained film, adjustment of the flow ratio of source gases, the time during which source gases flow, the order in which source gases flow, and the like can be given. By adjusting them, a film whose composition continuously changes can be formed. Furthermore, films whose compositions are different can be formed continuously.

[0433] Note that the semiconductor film 108f can be formed by a deposition method other than the ALD method. For example, the semiconductor film 108f can be formed by a sputtering method. Furthermore, when the semiconductor film 108f has a stacked structure of two or more layers, all the layers can be formed by the same deposition method, or each layer can be formed by a different deposition method. For example, when the semiconductor film 108f has a two-layer stacked structure, one layer can be formed by the ALD method and the other layer can be formed by the sputtering method. Here, when the semiconductor film 108f is formed by a deposition method other than the ALD method, it is preferable to supply oxygen to the insulating layer 110b by the above method after the insulating layer 110b is formed and before the insulating layer 110c is formed. Thus, oxygen vacancies in the semiconductor film 108f can be filled.

[0434] Before the formation of the semiconductor film 108f, at least one of a treatment for releasing water, hydrogen, and organic substances, and the like, adsorbed on the surface of the insulating layer 110, and a treatment for supplying oxygen to the insulating layer 110 is preferably performed. For example, heat treatment can be performed at a temperature higher than or equal to 70 °C and lower than or equal to 200 °C in a reduced pressure atmosphere. Alternatively, plasma treatment in an atmosphere containing oxygen can be performed. Alternatively, by performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N20), oxygen can be supplied to the insulating layer 110. When plasma treatment is performed in an atmosphere containing nitrous oxide gas, organic substances on the surface of the insulating layer 110 can be removed and oxygen can be supplied to the insulating layer 110. It is preferable that the semiconductor film 108f be continuously formed without exposure of the surface of the insulating layer 110 to the air after the treatment.

[0435] Note that in the case where the semiconductor layer 108 has a stacked-layer structure, it is preferable that the upper metal oxide film be continuously formed without exposure of the surface thereof to the air after the formation of the lower metal oxide film.

[0436] Next, the semiconductor film 108f is processed into an island shape, and the semiconductor layer 108 is formed. FIG. 29A The semiconductor layer 108 can be formed so as to have a region inside the opening portion 141 and a region inside the opening portion 143. The semiconductor layer 108 can be formed so as to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the insulating layer 105, and a region in contact with the top surface of the conductive layer 112b, for example.

[0437] The semiconductor layer 108 can be formed using one or both of a wet etching method and a dry etching method, and is preferably formed using a wet etching method, for example. At this time, part of the conductive layer 112b in a region not overlapping with the semiconductor layer 108 is sometimes etched and thinned. Furthermore, part of the insulating layer 105a is sometimes etched and thinned. Furthermore, part of the insulating layer 110 in a region not overlapping with the semiconductor layer 108, the conductive layer 112b, and the insulating layer 105a is sometimes etched and thinned.

[0438] It is preferable that heat treatment be performed after the formation of the semiconductor film 108f or after the processing of the semiconductor film 108f into the semiconductor layer 108. By the heat treatment, hydrogen or water included in the semiconductor film 108f or the semiconductor layer 108 or adsorbed on the surface of the semiconductor film 108f or the semiconductor layer 108 can be removed. Furthermore, by the heat treatment, the quality of the semiconductor film 108f or the semiconductor layer 108 is sometimes improved (e.g., the number of defects is reduced or the crystallinity is improved). It is more preferable that heat treatment be performed before the processing into the semiconductor layer 108.

[0439] The heat treatment temperature is preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, and typically 350°C. Other heat treatment conditions can be found in the description of heat treatment after the formation of the metal oxide layer 149.

[0440] Note that this heat treatment is not always necessary. Alternatively, a heat treatment performed in a later step can be used instead of this one. Sometimes, high-temperature treatments in later steps (e.g., deposition processes) can be used as the heat treatment for this step.

[0441] Next, an insulating layer 106 is formed in such a manner that it covers the semiconductor layer 108, the conductive layer 112b, the insulating layer 105a, and the insulating layer 110. FIG. 29B The insulating layer 106 can be formed on the semiconductor layer 108 in such a manner that it has a region located inside the opening 141 and a region located inside the opening 143. The insulating layer 106 can be formed along the sidewalls of the opening 141 and the opening 143, with respect to the semiconductor layer 108. The insulating layer 106 can be formed, for example, using PECVD or ALD methods.

[0442] When a metal oxide layer is used in the semiconductor layer 108, the insulating layer 106 is preferably used as a barrier film to suppress oxygen diffusion. Because the insulating layer 106 has the function of suppressing oxygen diffusion, oxygen can be prevented from diffusing from the upper side of the insulating layer 106 to the conductive layer 104, thereby preventing the conductive layer 104 from being oxidized. As a result, transistors exhibiting good electrical characteristics and high reliability can be manufactured.

[0443] Note that in this specification, a barrier film refers to a film that has barrier properties. For example, an insulating layer that has barrier properties can be called a barrier insulating layer. In this specification, barrier properties refer to one or both of the functions of inhibiting the diffusion of the corresponding substance (also known as low permeability) and capturing or fixing the corresponding substance (also known as gettering).

[0444] By increasing the formation temperature of the insulating layer 106 used as the gate insulating layer, an insulating layer with fewer defects can be formed. However, when the temperature during the formation of the insulating layer 106 is too high, oxygen escapes from the semiconductor layer 108, and sometimes oxygen vacancies and V in the semiconductor layer 108... OH is increased. The substrate temperature at the time of forming the insulating layer 106 is preferably higher than or equal to 180 °C and lower than or equal to 450 °C, more preferably higher than or equal to 200 °C and lower than or equal to 450 °C, still more preferably higher than or equal to 250 °C and lower than or equal to 450 °C, yet more preferably higher than or equal to 300 °C and lower than or equal to 450 °C, and even more preferably higher than or equal to 300 °C and lower than or equal to 400 °C. By setting the substrate temperature at the time of forming the insulating layer 106 to be within the above range, oxygen can be prevented from being released from the semiconductor layer 108 while reducing defects in the insulating layer 106. Thus, a transistor which has favorable electrical characteristics and high reliability can be manufactured.

[0445] The surface of the semiconductor layer 108 can also be subjected to plasma treatment before the insulating layer 106 is formed. By the plasma treatment, impurities such as water adsorbed on the surface of the semiconductor layer 108 can be reduced. Thus, impurities in the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a transistor with high reliability can be achieved. In particular, in the case where the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the formation of the insulating layer 106, it is preferable to perform plasma treatment. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, or argon. The plasma treatment and the deposition of the insulating layer 106 are preferably continuously performed in a manner not to be exposed to the atmosphere.

[0446] Next, the conductive layer 104 is formed over the insulating layer 106. Through the above steps, the transistor 100 FIG. 29B ) is formed.The conductive layer 104 is formed so as to have a region inside the opening portion 141 and a region inside the opening portion 143, and to have a region which faces the semiconductor layer 108 with the insulating layer 106 interposed therebetween.

[0447] For example, a conductive film which will be the conductive layer 104 can be formed over the insulating layer 106, and the conductive film can be processed to form the conductive layer 104. The conductive film which will be the conductive layer 104 is formed using, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method. The conductive film is processed after a resist mask is formed using a photolithography process, whereby the island-shaped conductive layer 104 which serves as a gate electrode can be formed.

[0448] Next, the insulating layer 107 FIG. 1B is formed so as to cover the conductive layer 104 and the insulating layer 106. FIG. 1C The insulating layer 107 can be formed using, for example, a CVD method, specifically, a PECVD method. For example, the insulating layer 107 can also be formed using a sputtering method.

[0449] Through the above steps, the semiconductor device illustrated in FIGS. 1A to 1D and FIGS. 2A to 2D can be manufactured. FIG. 1B FIG. 1C Thus, a transistor which has favorable electrical characteristics and high reliability can be manufactured.

[0450] In the above-described semiconductor device manufacturing method, a conductive layer 103 serving as the back gate electrode of a transistor 100 and an insulating layer 105 serving as the back gate insulating layer of a transistor 100 are formed by anisotropic etching without the use of a mask. Therefore, in the above-described semiconductor device manufacturing method, the conductive layer 103 and the insulating layer 105 can be formed, for example, without considering the alignment accuracy of the mask. Through the above process, even if the opening 141 in which the conductive layer 103 and the insulating layer 105 are formed is miniaturized, it is possible to prevent, for example, the conductive layer 103 and the insulating layer 105 from not forming inside the opening 141. Therefore, in a semiconductor device manufacturing method according to one aspect of the present invention, miniature transistors can be manufactured.

[0451] <Example 2 of Semiconductor Device Manufacturing Methods> The following is for reference FIGS. 30A-31C illustrate FIG. 11B and FIG. 11C An example of a method for manufacturing a semiconductor device is shown. FIGS. 30A-31C Arrange FIG. 11B The cross-sectional view along the dotted line A1-A2 shown below and FIG. 11C The cross-sectional view shown is along the dotted line B1-B2.

[0452] First, by conducting with FIG. 25A and FIG. 25B The same process as shown involves sequentially forming a conductive layer 112a and an insulating layer 110 on the substrate 102. Next, an opening 141 is formed in the insulating layer 110 to reach the conductive layer 112a. FIG. 30A For example, a resist mask is formed on the insulating layer 110, and the opening 141 can be formed by removing the portion of the insulating layer 110 that does not overlap with the resist mask using an etching method. As described above, the insulating layer 110 can be removed using an etching method, such as dry etching.

[0453] Next, by conducting with FIG. 27A The same process shown is used to form a conductive film 103f in a manner that covers the opening 141. FIG. 30A The conductive film 103f can be formed in such a way that it has a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the insulating layer 110, and a region in contact with the top surface of the insulating layer 110.

[0454] Next, by conducting with FIG. 27B and FIG. 27C The same process shown is used to sequentially form conductive layer 103 and insulating layer 105. FIG. 30B Here, FIG. 27C The insulating film 105f shown corresponds to FIG. 30BThe insulating layer 105 is shown. Note that the conductive layer 112b is not formed at this stage.

[0455] Next, the conductive layer 112b is formed by performing the same process as the process shown in FIG. 6A. FIG. 25C The conductive film 112f is formed in the same manner as the conductive film 112e shown in FIG. 6A. FIG. 30C ) in such a manner as to cover the opening portion 141. The conductive film 112f is formed over the insulating layer 105.

[0456] Next, the conductive layer 112b including the opening portion 143 is formed by processing the conductive film 112f. FIG. 31A The opening portion 143 is formed in such a manner as to have an area overlapping with the opening portion 141.

[0457] The conductive layer 112b including the opening portion 143 can be formed by photolithography and etching, for example. Specifically, a resist mask can be formed over the conductive film 112f, and the conductive film 112f can be removed by etching in a region not overlapping with the resist mask, whereby the conductive layer 112b including the opening portion 143 can be formed. In this case, the two steps of forming the conductive layer 112b by processing the conductive film 112f and forming the opening portion 143 in the conductive layer 112b can be performed by the same process. That is, the same resist mask can be used to form the conductive layer 112b and the opening portion 143 in the conductive layer 112b. Alternatively, the conductive layer 112b can be formed and the opening portion 143 can be formed in the conductive layer 112b by different processes. For example, a resist mask can be formed and the conductive film 112f can be processed according to the resist mask to form the conductive layer 112b, and after the resist mask is removed, the resist mask can be formed again. Then, the opening portion 143 can be formed by processing the conductive layer 112b according to the resist mask. Alternatively, the opening portion 143 can be formed in the conductive film 112f, and the conductive layer 112b including the opening portion 143 can be formed by processing the conductive film 112f.

[0458] Next, the opening portion 145 is formed by processing the insulating layer 105. FIG. 31B The opening portion 145 is formed in such a manner as to be positioned inside the opening portion 141 and reach the conductive layer 112a. By forming the opening portion 145, a region of the conductive layer 112a overlapping with the opening portion 145 is exposed.

[0459] For example, the opening portion 145 can be formed using photolithography and etching. Specifically, a resist mask can be formed on the insulating layer 105, and a portion of the insulating layer 105 which does not overlap with the resist mask can be removed using etching to form the opening portion 145. In particular, by removing the insulating layer 105 using dry etching, the opening portion 145 can be miniaturized. Thus, it is preferable to prevent the semiconductor layer 108 formed in a later step from being in contact with the conductive layer 103 and short-circuiting.

[0460] Next, the same process as that shown in FIG. 1A is performed to form a semiconductor film 108f which covers the opening portion 141, the opening portion 143, and the opening portion 145. FIG. 28B FIG. 31B In addition, the semiconductor film 108f is formed so as to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the insulating layer 105, a region in contact with the side surface of the conductive layer 112b, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the top surface of the insulating layer 110.

[0461] Next, the same process as that shown in FIG. 1A is performed to form a semiconductor film 108f which covers the opening portion 141, the opening portion 143, and the opening portion 145. FIG. 29A FIG. 29B Next, the same process as that shown in FIG. 1A is performed to form a semiconductor film 108f which covers the opening portion 141, the opening portion 143, and the opening portion 145. FIG. 31C

[0462] Next, the same process as that shown in FIG. 1A is performed to form a semiconductor film 108f which covers the opening portion 141, the opening portion 143, and the opening portion 145. FIG. 11B FIG. 11C Next, the same process as that shown in FIG. 1A is performed to form a semiconductor film 108f which covers the opening portion 141, the opening portion 143, and the opening portion 145.

[0463] The semiconductor device of one embodiment of the present application can be manufactured by the above process.

[0464] In FIGS. 30A-31C ​​​​In the semiconductor device manufacturing method shown, only a portion of the insulating layer 105 is etched during fabrication, without anisotropic etching. Therefore, even with a reduced thickness of the insulating layer 105, regions thinner than other areas within the insulating layer 105 can be prevented. Consequently, while reducing the thickness of the insulating layer 105, short circuits between the conductive layer 103 and the semiconductor layer 108 can be prevented. By reducing the thickness of the insulating layer 105, the electric field of the conductive layer 103, which serves as the back gate electrode of the transistor 100, can be easily applied to the semiconductor layer 108.

[0465] On the other hand, FIGS. 25A-29B In the semiconductor device manufacturing method shown, for example, photolithography is not required to expose the top surface of the conductive layer 112a. Therefore, the alignment accuracy of the mask does not need to be considered, and the opening 141 can be miniaturized. Therefore, micro-transistors can be manufactured. When manufacturing a semiconductor device including multiple transistors 100, even if the opening 141 is miniaturized, non-uniformity of electrical characteristics among the multiple transistors 100, such as non-uniformity of channel length, can be suppressed.

[0466] <Example 3 of Semiconductor Device Manufacturing Methods> The following is for reference FIGS. 32A-33B illustrate FIG. 15B An example of a method for manufacturing a semiconductor device is shown. FIGS. 32A-33B Show FIG. 15B The cross-sectional view shown is along the dotted line C1-C2.

[0467] First, by conducting with FIGS. 25A-26A The same process shown applies, in which conductive layers 112a_1 and 112a_2, insulating layer 110, conductive layers 112b_1 and 112b_2 are sequentially formed on substrate 102. FIG. 32A Here, conductive layers 112a_1 and 112a_2 can be formed by processing the same conductive film. Furthermore, conductive layers 112b_1 and 112b_2 can be formed by processing the same conductive film.

[0468] Next, by processing the conductive layer 112b_2, an opening 143_2 is formed. FIG. 32A The opening 143_2 can be connected with... FIG. 26B The opening 143 shown is formed in the same way.

[0469] Next, by processing the insulating layer 110, an opening 141_2 is formed. FIG. 32A The opening 141_2 can be connected with... FIG. 26C The opening 141 shown is formed in the same way.

[0470] Next, by performing the same process as the process shown in FIGS. 27A-28A , the conductive layer 103 and the insulating layer 105 are formed inside the opening portion 141_2. FIG. 32B Here, sometimes due to the formation process of the conductive layer 103, specifically, FIG. 27A the anisotropic etching of the conductive film 103f to form the recess 129 in the conductive layer 112a_2. FIG. 5

[0471] The insulating layer 105 is sometimes formed in a manner having a region inside the opening portion 143_2. Further, the insulating layer 105a is sometimes formed in a manner covering at least a part of the side surface of the conductive layer 112b_1 and at least a part of the side surface of the conductive layer 112b_2 on the side opposite to the opening portion 143_2. For example, the insulating layer 105a is sometimes formed in a manner having a region in contact with the side surface of the conductive layer 112b_1 and a region in contact with the side surface of the conductive layer 112b_2 on the side opposite to the opening portion 143_2.

[0472] Next, the conductive layer 112b_1 is processed to form the opening portion 143_1, and the insulating layer 110 is processed to form the opening portion 141_1. FIG. 32C The opening portion 143_1 can be formed by the same method as the opening portion 143 shown in FIG. 26B The opening portion 141_1 can be formed by the same method as the opening portion 141 shown in FIG. 26C

[0473] Next, by performing the same process as the process shown in FIGS. 28B-29B , the semiconductor layer 108_1 and the semiconductor layer 108_2, the insulating layer 106, the conductive layer 104_1 and the conductive layer 104_2 are sequentially formed. FIG. 33A Here, by processing the semiconductor film 108f shown in FIG. 28B , the semiconductor layer 108_1 and the semiconductor layer 108_2 can be formed. Further, by processing the same conductive film, the conductive layer 104_1 and the conductive layer 104_2 can be formed.

[0474] Next, the insulating layer 107 is formed in a manner covering the conductive layer 104 and the insulating layer 106. FIG. 33A As described above, the insulating layer 107 can be formed, for example, by the CVD method, specifically, by the PECVD method. For example, the insulating layer 107 can also be formed by the sputtering method.

[0475] Next, the insulating layer 109 is formed on the insulating layer 107. FIG. 33A ​​). At this time, in the case where the organic insulating film is used as the insulating layer 109, the insulating layer 109 can be formed by, for example, a wet deposition method such as a spin coating method, a dip coating method, a spray coating method, an inkjet method, a dispenser method, a screen printing method, an offset printing method, a doctor blade method, a slit coating method, a roll coating method, a curtain coating method, or a blade coating method. In the case where the inorganic insulating film is used as the insulating layer 109, the insulating layer 109 can be formed by, for example, a CVD method or a sputtering method.

[0476] Next, an opening portion 146a reaching the conductive layer 112b_1 is formed in the insulating layer 109, the insulating layer 107, and the insulating layer 106. Further, an opening portion 146b reaching the conductive layer 112b_2 is formed in the insulating layer 109 and the insulating layer 107 FIG. 33B ). The opening portion 146a and the opening portion 146b can be formed at the same time.

[0477] For example, the opening portion 146a and the opening portion 146b can be formed by a photolithography method and an etching method. Specifically, a resist mask can be formed on the insulating layer 109, and the portions of the insulating layer 109, the insulating layer 107, and the insulating layer 105 which do not overlap with the resist mask can be removed by an etching method to form the opening portion 146a and the opening portion 146b. In particular, when the insulating layer 109, the insulating layer 107, and the insulating layer 105 are removed by a dry etching method, the opening portion 146a and the opening portion 146b can be miniaturized, and thus the dry etching method is preferable.

[0478] Next, a conductive layer 119 is formed so as to have a region inside the opening portion 146a and a region inside the opening portion 146b FIG. 15B ). The conductive layer 119 can be formed so as to have a region inside the opening portion 146a in contact with the conductive layer 112b_1 and a region inside the opening portion 146b in contact with the conductive layer 104_2.

[0479] For example, a conductive film to be the conductive layer 119 can be formed on the insulating layer 109 so as to have a region inside the opening portion 146a and a region inside the opening portion 146b, and the conductive film can be processed to form the conductive layer 119. The conductive film to be the conductive layer 119 is preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method. By forming a resist mask on the conductive film by a photolithography process and then processing the conductive film, the conductive layer 119 serving as a lead can be formed.

[0480] By the above process, a semiconductor device 100 can be manufactured FIG. 15BThe conductive layer 103 is not formed inside the opening portion 141_1, and is formed inside the opening portion 141_2. Thus, when a recess is formed in the conductive layer 112a_2, a recess is not formed in the conductive layer 112a_1 in some cases.

[0481] The present embodiment can be appropriately combined with other embodiments. In addition, in the present specification, in a case where a plurality of structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0482] (Embodiment 2) In the present embodiment, the display device of one embodiment of the present application will be described with reference to FIGS. 34A-34G and FIGS. 35A-35K A display device of one embodiment of the present application will be described.

[0483] The arrangement of the subpixels is not particularly limited, and various arrangement methods can be employed. As the arrangement of the subpixels, for example, a stripe arrangement, an S stripe arrangement, a matrix arrangement, a Delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like can be given.

[0484] The planar shape of the subpixel shown in the drawing in the present embodiment corresponds to the planar shape of the display region (or light-receiving region).

[0485] In addition, as the planar shape of the subpixel, for example, a polygon such as a triangle, a quadrangle (including a rectangle and a square), a pentagon, or the like, the above-described polygon shape with rounded corners, an elliptical shape, or a circular shape, or the like can be given.

[0486] The circuit layout constituting the subpixel is not limited to the range of the subpixel shown in the drawing, and can be arranged outside the range.

[0487] FIG. 34A The pixel 21 shown in FIG. 1A adopts an S stripe arrangement. FIG. 34A The pixel 21 shown in FIG. 1A is composed of three kinds of subpixels, a subpixel 23a, a subpixel 23b, and a subpixel 23c.

[0488] FIG. 34B The pixel 21 shown in FIG. 1A includes the subpixel 23a and the subpixel 23b each having a planar shape of an approximately trapezoidal shape or an approximately triangular shape with rounded corners, and the subpixel 23c having a planar shape of an approximately quadrangular shape or an approximately hexagonal shape with rounded corners. In addition, the display region of the subpixel 23b is larger than that of the subpixel 23a. In this way, the shape and the size of each subpixel can be determined independently. For example, the size of the subpixel including a display element with high reliability can be smaller.

[0489] FIG. 34C The pixel 21a and the pixel 21b shown in FIG. 1B adopt a Pentile arrangement. FIG. 34CAn example in which the pixel 21a including the sub-pixel 23a and the sub-pixel 23b and the pixel 21b including the sub-pixel 23b and the sub-pixel 23c are alternately arranged is shown.

[0490] FIGS. 34D-34F The pixels 21a and 21b shown adopt a Delta arrangement. The pixel 21a includes two sub-pixels (the sub-pixel 23a and the sub-pixel 23b) in the upper row (the first row) and one sub-pixel (the sub-pixel 23c) in the lower row (the second row). The pixel 21b includes one sub-pixel (the sub-pixel 23c) in the upper row (the first row) and two sub-pixels (the sub-pixel 23a and the sub-pixel 23b) in the lower row (the second row).

[0491] FIG. 34D is an example in which each sub-pixel has a planar shape of an approximate quadrangle with rounded corners, FIG. 34E is an example in which each sub-pixel has a planar shape of a circle, FIG. 34F is an example in which each sub-pixel has a planar shape of an approximate hexagon with rounded corners.

[0492] In FIG. 34F , each sub-pixel is arranged inside a region arranged as the closest hexagon. Each sub-pixel is arranged in a manner surrounded by six sub-pixels when one of the sub-pixels is focused on. Further, sub-pixels that emit light of the same color are arranged in a manner not adjacent to each other. For example, each sub-pixel is arranged in a manner surrounded by three sub-pixels 23b and three sub-pixels 23c alternately arranged when the sub-pixel 23a is focused on.

[0493] FIG. 34G An example in which sub-pixels of each color are arranged in a zigzag shape is shown. Specifically, positions of upper edges of two sub-pixels (for example, the sub-pixel 23a and the sub-pixel 23b or the sub-pixel 23b and the sub-pixel 23c) arranged in the row direction are staggered when viewed from a planar surface.

[0494] In FIGS. 34A-34G , for example, it is preferable that the sub-pixel 23a be a sub-pixel R that emits red light, the sub-pixel 23b be a sub-pixel G that emits green light, and the sub-pixel 23c be a sub-pixel B that emits blue light. Note that the structure of the sub-pixels is not limited to this, and the colors emitted by the sub-pixels and the arrangement order can be appropriately decided. For example, the sub-pixel 23b can also be a sub-pixel R that emits red light, and the sub-pixel 23a can also be a sub-pixel G that emits green light.

[0495] In photolithography, the more minute the pattern to be processed, the more the influence of diffraction of light cannot be ignored, so the fidelity is degraded when transferring the pattern of a photomask by exposure, and it is difficult to process a resist mask into a desired shape. Therefore, even if the pattern of a photomask is a rectangle, a pattern with rounded corners is easily formed. Therefore, the planar shape of a sub-pixel is sometimes a polygonal shape with rounded corners, an elliptical shape, or a circular shape, or the like.

[0496] In order to make the planar shape of a sub-pixel a desired shape, a technique (OPC (Optical Proximity Correction) technique) of correcting a mask pattern in advance in a manner that the design pattern coincides with the transferred pattern can also be used. Specifically, in the OPC technique, for example, a correction pattern is added to the corner of a pattern on a mask pattern.

[0497] As shown in FIG. 1A, a pixel can include four sub-pixels. FIGS. 35A-35I

[0498] FIGS. 35A-35C The pixel 21 shown in FIG. 2A adopts a stripe arrangement.

[0499] FIG. 35A is an example in which each sub-pixel has a rectangular planar shape, FIG. 35B is an example in which each sub-pixel has a planar shape in which two semicircles and a rectangle are connected, FIG. 35C is an example in which each sub-pixel has an elliptical planar shape.

[0500] FIGS. 35D-35F The pixel 21 shown in FIG. 3A adopts a matrix arrangement.

[0501] FIG. 35D is an example in which each sub-pixel has a square planar shape, FIG. 35E is an example in which each sub-pixel has a planar shape of an approximate square with rounded corners, FIG. 35F is an example in which each sub-pixel has a circular planar shape.

[0502] FIG. 35G and FIG. 35H shows an example in which one pixel 21 is constituted of two rows and three columns.

[0503] FIG. 35G The pixel 21 shown in FIG. 4A includes three sub-pixels (sub-pixel 23a, sub-pixel 23b, and sub-pixel 23c) in the upper row (first row) and one sub-pixel (sub-pixel 23d) in the lower row (second row). In other words, the pixel 21 includes the sub-pixel 23a in the left column (first column), the sub-pixel 23b in the middle column (second column), the sub-pixel 23c in the right column (third column), and the sub-pixel 23d that spans the three columns.

[0504] FIG. 35H ​The pixel 21 shown includes three sub-pixels (sub-pixel 23a, sub-pixel 23b, and sub-pixel 23c) in the upper row (first row) and three sub-pixels 23d in the lower row (second row). In other words, the pixel 21 includes the sub-pixel 23a and the sub-pixel 23d in the left column (first column), the sub-pixel 23b and the sub-pixel 23d in the middle column (second column), and the sub-pixel 23c and the sub-pixel 23d in the right column (third column). As shown in FIG. 2, the sub-pixels 23a, 23b, 23c, and 23d are arranged in a staggered manner. FIG. 35H As shown, by employing a structure in which the configurations of the sub-pixels of the upper row and the lower row are aligned, for example, dust that can be generated in a manufacturing process can be efficiently removed. Thus, a display device with high display quality can be provided.

[0505] FIG. 35I An example in which one pixel 21 is formed of three rows and two columns is shown.

[0506] FIG. 35I The pixel 21 shown includes the sub-pixel 23a in the upper row (first row), the sub-pixel 23b in the middle row (second row), the sub-pixel 23c across the first row and the second row, and one sub-pixel (sub-pixel 23d) in the lower row (third row). In other words, the pixel 21 includes the sub-pixel 23a and the sub-pixel 23b in the left column (first column), the sub-pixel 23c in the right column (second column), and the sub-pixel 23d across the two columns.

[0507] FIGS. 35A-35I The pixel 21 shown is formed of four sub-pixels, the sub-pixel 23a, the sub-pixel 23b, the sub-pixel 23c, and the sub-pixel 23d.

[0508] The sub-pixels 23a, 23b, 23c, and 23d can emit light of different colors from each other. As the sub-pixels 23a, 23b, 23c, and 23d, four-color sub-pixels of R, G, B, and W; four-color sub-pixels of R, G, B, and Y; or sub-pixels of R, G, B, and infrared light (IR); etc. can be given.

[0509] In FIGS. 35A-35I In each pixel 21 shown, for example, it is preferable that the sub-pixel 23a be a sub-pixel R that emits red light, the sub-pixel 23b be a sub-pixel G that emits green light, the sub-pixel 23c be a sub-pixel B that emits blue light, and the sub-pixel 23d be a sub-pixel W that emits white light, a sub-pixel Y that emits yellow light, or a sub-pixel IR that emits near-infrared light. In employing the above structure, in FIG. 35G and FIG. 35H In the pixel 21 shown, the arrangement of R, G, and B is in a striped arrangement, so display quality can be improved. Further, in FIG. 35IIn the pixel 21 shown, the arrangement of R, G, and B is a so-called S-stripe arrangement, and thus display quality can be improved.

[0510] The pixel 21 can also include a sub-pixel including a light-receiving element.

[0511] In the pixel 21 shown, FIGS. 35A-35I In the pixel 21 shown, any one of the sub-pixels 23a to 23d can also be a sub-pixel including a light-receiving element.

[0512] In the pixel 21 shown, FIGS. 35A-35I In the pixel 21 shown, for example, it is preferable that the sub-pixel 23a be a red light-emitting sub-pixel R, the sub-pixel 23b be a green light-emitting sub-pixel G, the sub-pixel 23c be a blue light-emitting sub-pixel B, and the sub-pixel 23d be a sub-pixel S including a light-receiving element. When the above-described structure is employed, in the pixel 21 shown, FIG. 35G and FIG. 35H In the pixel 21 shown, the arrangement of R, G, and B is a stripe arrangement, and thus display quality can be improved. Further, in the pixel 21 shown, FIG. 35I In the pixel 21 shown, the arrangement of R, G, and B is a so-called S-stripe arrangement, and thus display quality can be improved.

[0513] The wavelength of light detected by the sub-pixel S including a light-receiving element is not particularly limited. The sub-pixel S can detect either or both of visible light and infrared light.

[0514] As shown in FIG. 35J and FIG. 35K The pixel can include five sub-pixels.

[0515] FIG. 35J One pixel 21 is shown as an example of a two-row, three-column configuration.

[0516] FIG. 35J The pixel 21 shown includes three sub-pixels (sub-pixel 23a, sub-pixel 23b, and sub-pixel 23c) in the upper row (first row) and two sub-pixels (sub-pixel 23d and sub-pixel 23e) in the lower row (second row). In other words, the pixel 21 includes the sub-pixel 23a and the sub-pixel 23d in the left column (first column), the sub-pixel 23b in the middle column (second column), the sub-pixel 23c in the right column (third column), and the sub-pixel 23e spanning the second column to the third column.

[0517] FIG. 35K One pixel 21 is shown as an example of a three-row, two-column configuration.

[0518] FIG. 35KThe pixel 21 shown in FIG. 1A includes the sub-pixel 23a in the upper row (first row), the sub-pixel 23b in the middle row (second row), the sub-pixel 23c across the first row to the second row, and two sub-pixels (the sub-pixel 23d and the sub-pixel 23e) in the lower row (third row). In other words, the pixel 21 includes the sub-pixel 23a, the sub-pixel 23b, and the sub-pixel 23d in the left column (first column), and the sub-pixel 23c and the sub-pixel 23e in the right column (second column).

[0519] In FIG. 35J and FIG. 35K In each of the pixels 21 shown in FIG. 1A, for example, it is preferable that the sub-pixel 23a be a sub-pixel R that emits red light, the sub-pixel 23b be a sub-pixel G that emits green light, and the sub-pixel 23c be a sub-pixel B that emits blue light. In the case of employing the above-described structure, in the pixel 21 shown in FIG. 1A, the layout of R, G, and B is a stripe arrangement, so the display quality can be improved. FIG. 35J FIG. 35K In the pixel 21 shown in FIG. 1A, the layout of R, G, and B is a so-called S-stripe arrangement, so the display quality can be improved.

[0520] In FIG. 35J and FIG. 35K In each of the pixels 21 shown in FIG. 1A, for example, it is preferable that at least one of the sub-pixel 23d and the sub-pixel 23e be a sub-pixel S that includes a light-receiving element. When a light-receiving element is used in both the sub-pixel 23d and the sub-pixel 23e, the structures of the light-receiving elements can be different from each other. For example, at least a part of the wavelength region of the detected light can be different from each other. Specifically, one of the sub-pixel 23d and the sub-pixel 23e can include a light-receiving element that mainly detects visible light, and the other can include a light-receiving element that mainly detects infrared light.

[0521] In FIG. 35J and FIG. 35K In each of the pixels 21 shown in FIG. 1A, for example, it is preferable that at least one of the sub-pixel 23d and the sub-pixel 23e be a sub-pixel S that includes a light-receiving element, and the other be a sub-pixel that includes a light-emitting element that can be used as a light source. For example, it is preferable that one of the sub-pixel 23d and the sub-pixel 23e be a sub-pixel IR that emits infrared light, and the other be a sub-pixel S that includes a light-receiving element that detects infrared light.

[0522] In the pixel that includes the sub-pixels R, G, B, IR, and S, it is possible to display an image using the sub-pixels R, G, and B, and detect reflected light of infrared light emitted from the sub-pixel IR using the sub-pixel S as a light source.

[0523] ​As described above, in the display device of one embodiment of the present application, various layouts can be employed for a pixel including a subpixel including a display element. Furthermore, the display device of one embodiment of the present application can employ a structure including both a light-emitting element and a light-receiving element in a pixel. In this case, too, various layouts can be employed.

[0524] This embodiment mode can be combined as appropriate with other embodiment modes. Furthermore, in this specification, in the case where a plurality of structural examples are shown in one embodiment mode, the structural examples can be combined as appropriate.

[0525] (Embodiment 3) In this embodiment mode, a display device of one embodiment of the present application is described.

[0526] The display device of this embodiment mode can be a high-resolution display device or a large display device. Thus, for example, the display device of this embodiment mode can be used as a display portion of an electronic device such as a television device, a desktop or notebook personal computer, a display for a computer or the like, a digital sign, a large game machine such as a pachinko machine, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, or a sound reproduction device, which has a large screen.

[0527] The display device of this embodiment mode can be a high-definition display device. Thus, for example, the display device of this embodiment mode can be used as a display portion of an information terminal device (wearable device) such as a watch-type and bracelet-type, and a display portion of a wearable device such as a head-mounted display (HMD) for VR and a glasses-type AR device, which can be mounted on the head.

[0528] The semiconductor device of one embodiment of the present application can be used for a display device or a module including the display device. As the module including the display device, a module in which a flexible printed circuit (FPC) or a tape carrier package (TCP) or the like is connected to the display device, a module in which an integrated circuit (IC) is directly mounted on the display device by a chip on glass (COG) method or a chip on film (COF) method, or the like can be given.

[0529] The display device of this embodiment mode can also have a function of a touch panel. For example, various detection elements (which can be referred to as sensor elements) capable of detecting proximity or contact of a detection object such as a finger can also be used for the display device.

[0530] As a method of a sensor, for example, an electrostatic capacity method, a resistance film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be given.

[0531] As the electrostatic capacitance type, for example, there are a surface type electrostatic capacitance type and a projection type electrostatic capacitance type. Further, as the projection type electrostatic capacitance type, for example, there are a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferably used because multi-point sensing can be performed at the same time.

[0532] As the touch panel, for example, there are an Out-Cell type, an On-Cell type, and an In-Cell type. Note that the In-Cell type touch panel refers to a structure in which an electrode that configures a detection element is provided in one or both of a support substrate and a counter substrate that support a display element.

[0533] [Display device 10A] FIG. 36 is a perspective view illustrating a structure example of the display device 10A.

[0534] The display device 10A has a structure in which a support substrate 102 and a counter substrate 152 are attached. In FIG. 36 , the support substrate 102 is indicated by a solid line and the counter substrate 152 is indicated by a dashed line.

[0535] The display device 10A includes a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, and the like. FIG. 36 An example in which the display device 10A is provided with an IC 173 and an FPC 172 is illustrated. Thus, the structure illustrated in FIG. 36 can be referred to as a display module including the display device 10A, the IC, and the FPC.

[0536] The connection portion 140 is provided outside the display portion 162. The connection portion 140 can be provided along one side or a plurality of sides of the display portion 162. The connection portion 140 can be one or a plurality. FIG. 36 An example in which the connection portion 140 is provided so as to surround four sides of the display portion is illustrated. In the connection portion 140, a common electrode of a display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0537] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Further, the circuit portion 164 can include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0538] The conductive layer 165 has a function of supplying a signal and power to the display portion 162 and the circuit portion 164. The signal and the power are input to the conductive layer 165 from the outside through the FPC 172 or from the IC 173.

[0539] FIG. 36An example of providing the IC 173 over the substrate 102 by a COG method or a COF method, or the like is shown. As the IC 173, an IC including one or both of a scan line driver circuit and a signal line driver circuit can be used, for example. Note that the display device 10A and the display module do not necessarily have to be provided with the IC. For example, an IC can be mounted to an FPC by a COF method.

[0540] The semiconductor device of one embodiment of the present application can be used in one or both of the display portion 162 and the circuit portion 164 of the display device 10A, for example. The channel formation region of a transistor included in a display device can be appropriately formed using an oxide semiconductor (OS). By using an OS transistor, a display device with low power consumption can be realized. Furthermore, the semiconductor device of one embodiment of the present application can be used for both the display portion 162 and the circuit portion 164, i.e., all the transistors included in a display device can be OS transistors. In that case, by using OS transistors as all the transistors included in a display device, an effect of reducing manufacturing cost can be obtained.

[0541] For example, when the semiconductor device of one embodiment of the present application is used for a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be realized. Furthermore, for example, when the semiconductor device of one embodiment of the present application is used for a driver circuit of a display device, the area occupied by the driver circuit can be reduced, and a display device with narrow bezel can be realized. Furthermore, the semiconductor device of one embodiment of the present application has favorable electrical characteristics, and by using the semiconductor device for a display device, the reliability of the display device can be improved.

[0542] The display portion 162 is an image display region in the display device 10A and includes a plurality of pixels 21 arranged periodically. FIG. 36 An enlarged view of one pixel 21 is shown in FIG. 1B.

[0543] There is no particular limitation on the arrangement of pixels in the display device of this embodiment, and various methods can be employed. As the arrangement of pixels, for example, a stripe arrangement, an S stripe arrangement, a matrix arrangement, a Delta arrangement, a Bayer arrangement, and a Pentile arrangement can be given.

[0544] FIG. 37A The pixel 21 shown in FIG. 1A includes a sub-pixel 23R which emits red light, a sub-pixel 23G which emits green light, and a sub-pixel 23B which emits blue light. Note that there is no particular limitation on the number of sub-pixels included in one pixel.

[0545] Each of the sub-pixel 23R, the sub-pixel 23G, and the sub-pixel 23B includes a display element and a circuit which controls driving of the display element.

[0546] As the display element, a variety of elements can be used, for example, a light-emitting element and a liquid crystal element can be given. In addition to the light-emitting element and the liquid crystal element, a MEMS (Micro Electro Mechanical Systems) element of a shutter type or a light interference type, a display element using a microcapsule, an electrophoretic type, an electrowetting type, an electronic ink type, or the like can be used. Furthermore, a color conversion technology using a light source and a quantum dot material can be used for a QLED (Quantum-dot LED).

[0547] FIG. 37A One example of a cross section of a portion of a region including the FPC 172, a portion of the circuit portion 164, a portion of the display portion 162, a portion of the connection portion 140, and a portion of a region including an end portion of the display device 10A is shown.

[0548] FIG. 37A The display device 10A shown includes a transistor 205D, a transistor 205R, a transistor 205G, a transistor 205B, a light-emitting element 60R, a light-emitting element 60G, a light-emitting element 60B, and the like between the substrate 102 and the substrate 152. The light-emitting element 60R is a display element included in a sub-pixel 23R which emits red light, the light-emitting element 60G is a display element included in a sub-pixel 23G which emits green light, and the light-emitting element 60B is a display element included in a sub-pixel 23B which emits blue light. Note that the description of the light-emitting element 60 in Embodiment 1 can be applied to the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B.

[0549] The display device 10A employs an SBS structure. In the SBS structure, the material and the structure of each light-emitting element can be optimized separately, and thus the degree of freedom in selection of the material and the structure is increased, which makes it easy to improve the luminance and the reliability.

[0550] The display device 10A employs a top emission type. In the top emission type, for example, a transistor can be provided so as to overlap with a light-emitting region of a light-emitting element, and thus the aperture ratio of a pixel can be further increased as compared with a bottom emission type.

[0551] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are each formed over the substrate 102. These transistors can be manufactured using the same material and the same process. Alternatively, the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B can each be a transistor having a different structure.

[0552] In this embodiment, an example in which an OS transistor is used as the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B is shown. As the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B, a transistor of one embodiment of the present application can be used. That is, in the display device 10A, both the display portion 162 and the circuit portion 164 include a transistor of one embodiment of the present application. By using a transistor of one embodiment of the present application in the display portion 162, the pixel size can be reduced and high definition can be achieved. Further, by using a transistor of one embodiment of the present application in the circuit portion 164, the occupied area of the circuit portion 164 can be reduced and narrow bezel design can be achieved. The transistor of one embodiment of the present application can be referred to the description of the above embodiments.

[0553] Specifically, the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B each include the conductive layer 104 serving as a gate electrode, the insulating layer 106 serving as a gate insulating layer, the conductive layer 103 serving as a back gate electrode, the insulating layer 105 serving as a back gate insulating layer, the conductive layer 112a and the conductive layer 112b serving as a source electrode and a drain electrode, the semiconductor layer 108 including a metal oxide, and the insulating layer 110. Further, the insulating layer 105a is sometimes provided so as to cover at least part of a side surface of the conductive layer 112b. The insulating layer 105a can have a region in contact with the side surface of the conductive layer 112b. FIG. 37A An example in which the insulating layer 110 has a three-layer stacked structure of the insulating layer 110a, the insulating layer 110b over the insulating layer 110a, and the insulating layer 110c over the insulating layer 110b is shown. Examples in which the insulating layer 110 has a three-layer stacked structure are also shown in the following drawings.

[0554] In FIG. 37A In the drawings, the same hatching pattern is applied to the multiple layers of the same conductive film. This is the same in the drawings below. The insulating layer 110 is provided so as to cover an end portion of the conductive layer 112a. The conductive layer 112b is provided over the insulating layer 110. The insulating layer 106 is provided between the conductive layer 104 and the semiconductor layer 108.

[0555] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present application. For example, a transistor including the transistor of one embodiment of the present application and another structure can be combined.

[0556] The display device of this embodiment may include, for example, any one or more of planar transistors, interleaved transistors, and anti-interleaved transistors. The transistors included in the display device of this embodiment have either a top-gate or bottom-gate structure. Alternatively, gates may be disposed above and below the semiconductor layer forming the channel. Furthermore, the display device of this embodiment may also include Si transistors.

[0557] The transistors included in the circuit section 164 and the transistors included in the display section 162 may have the same structure or different structures. The multiple transistors included in the circuit section 164 may have the same structure or two or more different structures. Similarly, the multiple transistors included in the display section 162 may have the same structure or two or more different structures.

[0558] An insulating layer 107 is provided to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on the insulating layer 107.

[0559] As shown in Embodiment 1, the insulating layer 107 is preferably used as a protective layer for the transistor. The insulating layer 107 is preferably made of a material from which impurities such as water and hydrogen do not easily diffuse. Therefore, the insulating layer 107 can be used as a barrier layer. By employing this structure, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0560] The insulating layer 235 is preferably used as a planarization layer, and an organic insulating film is suitable. Materials suitable for use as organic insulating films include, for example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenolic resin, and precursors of these resins. Furthermore, the insulating layer 235 can also be a laminated structure of organic and inorganic insulating films. The outermost layer of the insulating layer 235 is preferably used as an etching protection layer. Therefore, when processing the pixel electrodes 111R, 111G, and 111B, the formation of recesses in the insulating layer 235 can be suppressed. Alternatively, recesses can be formed in the insulating layer 235 during the processing of the pixel electrodes 111R, 111G, and 111B.

[0561] Light-emitting elements 60R, 60G, and 60B are disposed on the insulating layer 235.

[0562] The light-emitting element 60R includes a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. FIG. 37A The light-emitting element 60R shown emits red light (R). The EL layer 113R includes a light-emitting layer that emits red light.

[0563] The light-emitting element 60G includes a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. FIG. 37A The light-emitting element 60G shown emits green light (G). The EL layer 113G includes a light-emitting layer that emits green light.

[0564] The light-emitting element 60B includes a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. FIG. 37A The light-emitting element 60B shown emits blue light (B). The EL layer 113B includes a light-emitting layer that emits blue light.

[0565] Note that in FIG. 37A The EL layers 113R, 113G, and 113B are shown with the same thickness, but this is not a limitation. The thicknesses of EL layers 113R, 113G, and 113B can also be different. For example, it is preferable to set the thickness to enhance the optical path of the light emitted by EL layers 113R, 113G, and 113B. This allows for the realization of a microcavity structure to improve the color purity of the light emitted from each light-emitting element.

[0566] Pixel electrode 111R is electrically connected to the conductive layer 112b of transistor 205R through openings provided in insulating layers 106, 107, and 235. Similarly, pixel electrode 111G is electrically connected to the conductive layer 112b of transistor 205G, and pixel electrode 111B is electrically connected to the conductive layer 112b of transistor 205B.

[0567] Each end of pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B is covered by insulating layer 237. Insulating layer 237 serves as a partition wall. Insulating layer 237 can be configured as a single layer or a multilayer structure using one or both of inorganic and organic insulating materials. For example, insulating layer 237 can use materials suitable for insulating layer 107 and insulating layer 235. Insulating layer 237 electrically insulates the pixel electrodes from the common electrode. Furthermore, insulating layer 237 electrically insulates adjacent light-emitting elements.

[0568] An insulating layer 237 is provided at least in the display section 162. The insulating layer 237 can be provided not only in the display section 162, but also in the connecting section 140 and the circuit section 164. Furthermore, the insulating layer 237 can also be provided at the end of the display device 10A.

[0569] The common electrode 115 is a continuous film shared by the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B. The common electrode 115 shared by a plurality of light-emitting elements is electrically connected to the conductive layer 183 provided in the connection portion 140. The conductive layer 183 is preferably formed using a conductive layer formed using the same material and process as the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B.

[0570] In the display device of one embodiment of the present application, a conductive film that transmits visible light is used as the electrode on the light-extraction side in the pixel electrode and the common electrode. Furthermore, as the electrode on the non-light-extraction side, a conductive film that reflects visible light is preferably used.

[0571] The electrode on the non-light-extraction side can also be a conductive film that transmits v...

Claims

1. A semiconductor device, comprising: transistor; as well as First insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a second insulating layer, and a third insulating layer. The first insulating layer is disposed on the first conductive layer and includes a first opening extending into the first conductive layer. The second conductive layer is disposed on the first insulating layer and includes a second opening having a region overlapping the first opening. The third conductive layer has a region that contacts the side surface of the first insulating layer located within the first opening. The third conductive layer has a region that contacts the first conductive layer. The uppermost part of the third conductive layer is located below the top end of the first opening side of the first insulating layer. The second insulating layer is provided such that it covers the third conductive layer inside the first opening. The semiconductor layer is disposed such that it has a region in contact with the first conductive layer and a region in contact with the second conductive layer, and has a region inside the first opening that is opposite to the third conductive layer, separated by the second insulating layer. The third insulating layer is disposed on the semiconductor layer in such a manner that it has a region located inside the first opening. Furthermore, the fourth conductive layer is provided in such a manner that the second insulating layer, the semiconductor layer, and the third insulating layer are separated from the third conductive layer inside the first opening.

2. The semiconductor device according to claim 1, further comprising a fourth insulating layer, The fourth insulating layer is disposed between the first insulating layer and the third insulating layer. Furthermore, the fourth insulating layer has a region that contacts the side of the second conductive layer opposite to the second opening.

3. The semiconductor device according to claim 1, The second insulating layer has a region located on the first insulating layer. Furthermore, the second conductive layer is disposed on the second insulating layer.

4. The semiconductor device according to any one of claims 1 to 3, The semiconductor layer comprises a metal oxide.

5. The semiconductor device according to claim 4, The metal oxide contains two or three elements selected from In, M, and Zn. Furthermore, the element M is selected from one or more of Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb.

6. A method for manufacturing a semiconductor device, comprising the following steps: Form the first conductive layer; A first insulating layer is formed on the first conductive layer; A second conductive layer is formed on the first insulating layer; By processing the second conductive layer, a first opening is formed having a region overlapping with the first conductive layer; A second opening reaching the first conductive layer is formed by processing the first insulating layer to have a region that overlaps with the first opening. A conductive film is formed in such a way that it covers the first opening and the second opening; A third conductive layer is formed by anisotropically etching the conductive film to have a region in contact with the first conductive layer and the uppermost part being located below the bottom end of the first opening side of the second conductive layer. An insulating film is formed in such a manner that it covers the second conductive layer and the third conductive layer; A second insulating layer covering the third conductive layer is formed by anisotropically etching the insulating film until at least a portion of the top surface of the second conductive layer is exposed; A semiconductor layer is formed in such a manner that it has a region in contact with the first conductive layer and a region in contact with the second conductive layer; The third insulating layer is formed in such a manner that it has a region located inside the second opening; as well as A fourth conductive layer is formed on the third insulating layer in such a way that it has a region located inside the second opening.

7. A method for manufacturing a semiconductor device, comprising the following steps: Form the first conductive layer; A first insulating layer is formed on the first conductive layer; By processing the first insulating layer, a first opening is formed that reaches the first conductive layer; A conductive film is formed in such a way that it covers the first opening; A second conductive layer is formed by anisotropically etching the conductive film to have a region in contact with the first conductive layer and the uppermost part being located below the top end of the first opening side of the first insulating layer. The second insulating layer is formed in such a manner that it covers the first conductive layer, the second conductive layer, and the first insulating layer; A third conductive layer is formed on the second insulating layer, including a second opening having a region overlapping the first opening; A third opening is formed in the second insulating layer to reach the first conductive layer, and the third opening is formed inside the first opening; A semiconductor layer is formed in such a manner that it has a region in contact with the first conductive layer and a region in contact with the third conductive layer; A third insulating layer is formed in such a manner that it has a region located inside the first opening; as well as, A fourth conductive layer is formed on the third insulating layer in such a way that it has a region located inside the first opening.

8. The method for manufacturing a semiconductor device according to claim 6 or 7, The semiconductor layer is formed by processing the semiconductor film after it is formed using the ALD method.

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