Array substrate and display device

Abstract

The invention discloses an array substrate and a display device, and relates to the technical field of display. The array substrate comprises: a substrate; the sub-pixels, the grid lines and the signal lines are arranged on one side of the substrate, the signal lines comprise data lines, the sub-pixels comprise pixel driving circuits, the pixel driving circuits comprise first transistors and second transistors, grid electrodes of the first transistors are connected with the grid lines, and source electrodes of the first transistors are connected with the data lines; the grid line comprises a plurality of first line segments and bending parts connected between every two adjacent first line segments, the first line segments extend in the first direction, the bending parts are bent towards the side away from the second transistor, and a source electrode of the second transistor extends into the bending parts; the bending part is located between the first signal line and the second signal line, the bending part is arranged close to the second signal line, the bending part comprises a second line segment arranged close to the second signal line, the orthographic projection of the second line segment and the orthographic projection of the second signal line on the substrate base plate are not overlapped, and the extension length of the second line segment is larger than the width of the first line segment.

Description

Array substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Micro-LED (Micro Light-Emitting Diode) displays are a type of microdisplay that has recently developed, and silicon-based OLED (Organic Organic Light Emitting Diode) microdisplays are one such type. Silicon-based OLED microdisplays not only enable active pixel addressing but also allow the fabrication of pixel driver circuits and other structures on a silicon substrate, contributing to reduced size and weight.

[0003] Overview

[0004] The present disclosure provides an array substrate, comprising:

[0005] substrate;

[0006] a plurality of sub-pixels arranged on one side of the base substrate, a plurality of gate lines arranged along the second direction, and a plurality of signal lines arranged along the first direction, the signal lines including data lines, the orthographic projections of the gate lines and the data lines on the base substrate intersecting each other and defining the plurality of sub-pixels, the sub-pixels including a pixel driving circuit and a light-emitting device connected to each other, the pixel driving circuit including a first transistor and a second transistor, the gate of the first transistor being connected to the gate line and the source being connected to the data line, the plurality of signal lines including adjacent first signal lines and second signal lines;

[0007] The gate line includes a plurality of first line segments arranged in sequence along a first direction, and a bending portion connecting two adjacent first line segments, wherein the first line segments extend along the first direction, the bending portion bends toward a side away from the second transistor, and the source of the second transistor extends into an avoidance area formed by the bending portion;

[0008] The bending portion is located between the first signal line and the second signal line, the distance between the bending portion and the second signal line is less than or equal to the distance between the bending portion and the first signal line, the bending portion includes a second line segment arranged close to the second signal line, the extension direction of the second line segment intersects with the first direction, the second line segment and the second signal line have no overlap in their orthographic projections on the base substrate, and the extension length of the second line segment is greater than the width of the first line segment.

[0009] In some embodiments, in the first direction, a distance between the second line segment and the second signal line is greater than or equal to a distance between the second line segment and the source of the second transistor.

[0010] In some embodiments, the source of the second transistor is connected to the first power signal line through a first via, and in the orthographic projection on the substrate, the first via is arranged close to the first edge, and the first edge is the edge of the source of the second transistor close to the first signal line.

[0011] In some embodiments, a distance between the second line segment and the first via is greater than a distance between the second line segment and the second signal line.

[0012] In some embodiments, the bent portion further includes a third line segment and a fourth line segment, the second line segment, the third line segment, and the fourth line segment are sequentially connected between two adjacent first line segments and are located on a side of the first line segment away from the second transistor, the third line segment extends along the first direction, and the second line segment and the fourth line segment extend along the second direction; and

[0013] In the first direction, a distance between the second line segment and the source of the second transistor is less than or equal to a distance between the fourth line segment and the source of the second transistor.

[0014] In some embodiments, the gate of the second transistor is connected to a second control signal line, and the second control signal line includes:

[0015] A fifth line segment, and multiple first branches connected to one side of the fifth line segment, different first branches are connected to the gates of different second transistors through second vias, the fifth line segment extends along the first direction, the first branch includes a sixth line segment, the sixth line segment extends along the second direction, the sixth line segment and the data line have no overlap in their orthographic projection on the substrate, and the extension length of the sixth line segment is greater than the width of the fifth line segment.

[0016] In some embodiments, the first branch is located between the first signal line and the second signal line, and the distance between the first branch and the second signal line is less than or equal to the distance between the first branch and the first signal line;

[0017] The first branch also includes a seventh line segment, the sixth line segment connects the fifth line segment and the seventh line segment, the seventh line segment is located on a side of the sixth line segment close to the second signal line, the seventh line segment is connected to the gate of the second transistor through the second via, the seventh line segment and the second signal line have an overlapping area in their orthographic projections on the substrate, and the width of the seventh line segment along the second direction is less than the extension length of the sixth line segment.

[0018] In some embodiments, the width of the overlapping region along the first direction is less than or equal to the width of the second signal line along the first direction; and / or

[0019] The width of the seventh line segment along the second direction is greater than the width of the fifth line segment along the second direction and the width of the sixth line segment along the first direction; and / or

[0020] A width of the overlapping region along the second direction is smaller than an extending length of the sixth line segment.

[0021] In some embodiments, the gate line is located in the first conductive layer, and the pixel driving circuit further comprises: a driving transistor, whose source is connected to the drain of the second transistor, and whose drain is connected to the anode of the light-emitting device;

[0022] The source of the second transistor is connected to a first power signal line, the first power signal line includes a first extension line, a second extension line, and a third extension line, the first extension line extends along the second direction, the second extension line and the third extension line both extend along the first direction, and the second extension line and the third extension line are arranged along the second direction and connected between two adjacent first extension lines;

[0023] The first extension line, the second extension line and the third extension line are all located in the second conductive layer. Two adjacent first extension lines, the second extension line and the third extension line together form a closed ring structure surrounding the driving transistor.

[0024] In some embodiments, the gate of the second transistor is connected to a second control signal line, and the second control signal line is located in the first conductive layer;

[0025] In the orthographic projection on the base substrate, the second control signal line, the gate line and the second extension line are located between two adjacent rows of sub-pixels and do not overlap with each other, the second extension line is located between the second control signal line and the gate line, and the second extension line is connected to the source of the second transistor through a via.

[0026] In some embodiments, the data line is located in a fourth conductive layer, and the second conductive layer is stacked between the first conductive layer and the fourth conductive layer;

[0027] The orthographic projection of the first extension line on the base substrate covers the orthographic projection of the data line on the base substrate at least in a first direction.

[0028] In some embodiments, the first power signal line further includes: a fourth extension line extending along the second direction, and a fifth extension line extending along the first direction, the fifth extension line being connected between two adjacent fourth extension lines, the fourth extension lines corresponding to different sub-pixels being spaced apart from each other, the fourth extension line overlapping with the orthographic projection of the first extension line on the base substrate and being connected through a via hole, and the fifth extension line overlapping with the orthographic projection of the second extension line on the base substrate and being connected through a via hole; and

[0029] The fourth extension line and the fifth extension line are both located in a third conductive layer, and the third conductive layer is stacked between the second conductive layer and the fourth conductive layer.

[0030] In some embodiments, the third conductive layer further includes: a first connecting line connected to a side of the fifth extension line facing away from the driving transistor;

[0031] The fourth conductive layer further includes a first transfer pattern, wherein the first transfer pattern is connected to the first transfer line through a via hole;

[0032] The first power signal line further includes: a sixth extension line, a seventh extension line, and an eighth extension line, the sixth extension line extending along the second direction, the seventh extension line and the eighth extension line both extending along the first direction, the seventh extension line and the eighth extension line arranged along the second direction and connected between two adjacent sixth extension lines, the sixth extension line and the data line having an orthographic projection overlapped on the base substrate, the seventh extension line and the eighth extension line being located on both sides of the second extension line in the orthographic projection on the base substrate, and the eighth extension line being connected to the first transfer pattern through a via;

[0033] The sixth extension line, the seventh extension line, and the eighth extension line are all located in a fifth conductive layer. The fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate.

[0034] In some embodiments, the anode of the light-emitting device is arranged on the side of the fifth conductive layer away from the base substrate, and the fifth conductive layer also includes an auxiliary anode extending along the second direction, and the auxiliary anode is respectively connected to the anode and the drain of the driving transistor. In the orthographic projection on the base substrate, the auxiliary anode is located between two adjacent sixth extension lines and on the side of the seventh extension line away from the eighth extension line.

[0035] In some embodiments, the pixel driving circuit further includes:

[0036] The second capacitor has a first electrode connected to the source of the driving transistor, and a second electrode located in the fourth conductive layer and connected to the seventh extension line through a via hole.

[0037] In some embodiments, the array substrate further includes:

[0038] A second power signal line is located in the first conductive layer and includes an eighth line segment extending along the first direction;

[0039] In an orthographic projection on the base substrate, the third extension line is located within the region of the eighth line segment, and the third extension line is centered relative to the eighth line segment in the second direction.

[0040] In some embodiments, the pixel driving circuit further includes: a third transistor, having a gate connected to the first control signal line, a source connected to the drain of the driving transistor, and a drain connected to the second power signal line;

[0041] The first control signal line is located in the third conductive layer, the second conductive layer further includes a third transfer pattern, the first control signal line is connected to the third transfer pattern through a third via, and the third transfer pattern is connected to the gate of the third transistor through a fifth via;

[0042] The orthographic projection of the third via hole on the base substrate is located within the orthographic projection of the channel region of the third transistor on the base substrate, and the orthographic projection of the fifth via hole and the channel region of the third transistor on the base substrate do not overlap.

[0043] In some embodiments, in the orthographic projection on the substrate, the first control signal line is located on a side of the third extension line close to the third transistor, the first control signal line does not overlap with the third extension line, and the first control signal line overlaps with the eighth line segment.

[0044] In some embodiments, the channel region of the driving transistor is located in a semiconductor layer, and the semiconductor layer further includes: a first semiconductor pattern extending along the second direction and overlapping with an orthographic projection of the data line on the base substrate;

[0045] The second power signal line further includes a ninth line segment and a tenth line segment, wherein the ninth line segment and the tenth line segment are both located on a side of the eighth line segment close to the third transistor and are respectively connected to the eighth line segment;

[0046] The first semiconductor pattern is connected to the ninth line segment through a via hole, and the tenth line segment is connected to the drain of the third transistor through a via hole.

[0047] In some embodiments, the first control signal line includes an eleventh line segment and a twelfth line segment connected to each other, the eleventh line segment extends along the first direction, the twelfth line segment is located on a side of the eleventh line segment close to the third transistor, and the twelfth line segment is connected to the gate of the third transistor through a via;

[0048] The eleventh line segment is located on a side of the third transistor away from the driving transistor, and the orthographic projection of the eleventh line segment and the third transistor on the substrate does not overlap.

[0049] In some embodiments, the first extension line is located between two adjacent driving transistors, and a second transfer pattern is further provided between the first extension line and the driving transistor. Different second transfer patterns are spaced apart from each other and correspond to different sub-pixels. The second transfer pattern is located in the first conductive layer, and a first portion of the second transfer pattern is connected to the first extension line through a via.

[0050] In some embodiments, the channel region of the driving transistor is located in a semiconductor layer, and the semiconductor layer further includes:

[0051] The second semiconductor pattern extends along the second direction and is located between the first extension line and the driving transistor. Different second semiconductor patterns are spaced apart and correspond to different sub-pixels. The second semiconductor pattern is connected to the second portion of the second switching pattern through a via.

[0052] In some embodiments, the pixel driving circuit further includes:

[0053] a driving transistor, whose source is connected to the drain of the second transistor and whose drain is connected to the anode of the light-emitting device; and

[0054] a first capacitor, wherein a first plate is connected to the source of the driving transistor, and a second plate is connected to the gate of the driving transistor through a fourth via hole;

[0055] In which, the drain of the first transistor is connected to the gate of the driving transistor through a second transfer line, the second transfer line is arranged in the same layer as the gate line and both are located in the first conductive layer, the first plate of the first capacitor is located in the second conductive layer, the first plate of the first capacitor overlaps with the orthographic projection of the driving transistor on the substrate, and the first plate of the first capacitor does not overlap with the orthographic projection of the second transfer line, the first transistor, and the channel region of the second transistor on the substrate.

[0056] In some embodiments, the second plate of the first capacitor is located in the third conductive layer, the first plate of the first capacitor includes a first capacitor pattern and a second capacitor pattern arranged along the second direction, the width of the first capacitor pattern along the first direction is greater than the width of the second capacitor pattern along the first direction, the second capacitor pattern is located on the side of the second capacitor pattern close to the second adapter line, the first capacitor pattern and the second capacitor pattern are spliced ​​together to form a gap, and the gap is used to avoid the fourth via.

[0057] In some embodiments, the pixel driving circuit further includes: a driving transistor and a third transistor;

[0058] Wherein, the gate of the second transistor is connected to the second control signal line, the source is connected to the first power signal line, and the drain is connected to the source of the driving transistor;

[0059] The driving transistor has a gate connected to the drain of the first transistor, a source connected to the drain of the second transistor, and a drain connected to the anode of the light emitting device; and

[0060] The third transistor has a gate connected to the first control signal line, a source connected to the drain of the driving transistor, and a drain connected to the second power signal line;

[0061] In the orthographic projection on the substrate, the first control signal line and the second control signal line are respectively located on opposite sides of the driving transistor, the gate line is located on the side of the second control signal line away from the driving transistor, and the second power signal line is located on the side of the first control signal line away from the driving transistor.

[0062] In some embodiments, the gate line overlaps with an orthographic projection of the first transistor on the substrate, and the gate line does not overlap with an orthographic projection of the second transistor on the substrate.

[0063] The second control signal line overlaps with the orthographic projections of the first transistor and the second transistor on the substrate.

[0064] The present disclosure provides a display device, comprising:

[0065] The array substrate as described in any one of the items; and

[0066] The driving circuit is connected to the array substrate and is used to provide a driving signal to the array substrate.

[0067] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0068] BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0070] FIG1 exemplarily shows a schematic diagram of a planar structure of an array substrate;

[0071] FIG2 is a schematic structural diagram of a pixel driving circuit provided by the present disclosure;

[0072] FIG3 is a schematic diagram of an equivalent structure of a pixel driving circuit provided by the present disclosure in the first stage;

[0073] FIG4 is a schematic diagram of an equivalent structure of a pixel driving circuit provided by the present disclosure in the second stage;

[0074] FIG5 is a schematic diagram of an equivalent structure of a pixel driving circuit provided by the present disclosure in the third stage;

[0075] FIG6 is a schematic diagram of an equivalent structure of a pixel driving circuit provided by the present disclosure in the fourth stage;

[0076] FIG7 is a top view of the structure of the semiconductor layer in the array substrate provided by the present disclosure;

[0077] FIG8 is a schematic top view of the structure of the gate layer in the array substrate provided by the present disclosure;

[0078] FIG9 is a top view of the structure of the semiconductor layer and the gate layer after stacking in the array substrate provided by the present disclosure;

[0079] FIG10 is a schematic top view of the structure of the first conductive layer in the array substrate provided by the present disclosure;

[0080] FIG11 is a top view of the structure of the semiconductor layer, the gate layer, and the first conductive layer after stacking in the array substrate provided by the present disclosure;

[0081] FIG12 is a schematic top view of the structure of the second conductive layer in the array substrate provided by the present disclosure;

[0082] FIG13 is a top view of the structure of the semiconductor layer, the gate layer, the first conductive layer, and the second conductive layer in the array substrate provided by the present disclosure after being stacked;

[0083] FIG14 is a schematic top view of the structure of the third conductive layer in the array substrate provided by the present disclosure;

[0084] FIG15 is a top view of the structure of the second conductive layer and the third conductive layer after being stacked in the array substrate provided by the present disclosure;

[0085] FIG16 is a top view of the structure of the semiconductor layer, gate layer, first conductive layer, second conductive layer, and third conductive layer after stacking in the array substrate provided by the present disclosure;

[0086] FIG17 is a schematic top view of the structure of the fourth conductive layer in the array substrate provided by the present disclosure;

[0087] FIG18 is a top view of the structure of the array substrate provided by the present disclosure after the third conductive layer and the fourth conductive layer are stacked;

[0088] FIG19 is a schematic top view of the structure of the fifth conductive layer provided by the present disclosure;

[0089] FIG20 is a top view of the structure of the fourth conductive layer and the fifth conductive layer after being stacked in the array substrate provided by the present disclosure;

[0090] FIG21 is a top view of the structure of the array substrate provided by the present disclosure after the third conductive layer, the fourth conductive layer, and the fifth conductive layer are stacked;

[0091] FIG22 is a signal timing diagram of the pixel driving circuit shown in FIG1 .

[0092] Detailed description

[0093] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0094] In this specification, the terms "electrically connected" and "coupled" include components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0095] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0096] The polygons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, rounded corners, arc edges and deformations.

[0097] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0098] Example embodiments will now be described more fully with reference to the accompanying drawings.

[0099] The present disclosure provides an array substrate, as shown in Figure 1, the array substrate includes: a base substrate; a plurality of sub-pixels P arranged on one side of the base substrate, a plurality of gate lines WS arranged along a second direction f2, and a plurality of signal lines arranged along a first direction f1, the signal lines include data lines DL, the orthographic projections of the gate lines WS and the data lines DL on the base substrate intersect with each other and define a plurality of sub-pixels P, the sub-pixels P include a pixel driving circuit DC and a light-emitting device 6 connected to each other.

[0100] Exemplarily, as shown in FIG. 2 , the pixel driving circuit DC includes: an input module 1 , a driving module 2 , a compensation module 3 , a second control module 4 and a first control module 5 .

[0101] Exemplarily, as shown in FIG2 , the input module 1 is electrically connected to the gate line WS, the data line DL and the first node G, and is configured to write the data signal transmitted by the data line DL into the first node G under the control of the scan signal transmitted by the gate line WS.

[0102] Exemplarily, as shown in FIG2 , the driving module 2 is electrically connected to the first node G, the second node S and the anode of the light-emitting device 6, respectively, and is configured to, under the control of the voltage of the first node G, conduct the path between the second node S and the anode, and generate a current in the path for causing the light-emitting device 6 to emit light; the second node S is coupled to the first power signal line ELVDD.

[0103] Exemplarily, as shown in FIG. 2 , the compensation module 3 is electrically connected to the first node G, the second node S and the first power signal line ELVDD, respectively, and is configured to compensate for the threshold voltage of the driving module 2 .

[0104] Exemplarily, as shown in Figure 2, the second control module 4 is electrically connected to the first power signal line ELVDD, the second control signal line DS and the driving module 2, respectively, and is configured to transmit the first power signal transmitted in the first power signal line ELVDD to the driving module 2 under the control of the second control signal transmitted by the second control signal line DS, and generate a current in the auxiliary path for making the light-emitting device 6 emit light.

[0105] Exemplarily, as shown in Figure 2, the first control module 5 is electrically connected to the first control signal line AZ, the second power signal line VSS and the anode of the light-emitting device 6, respectively, and is configured to transmit the second power signal transmitted by the second power signal line VSS to the anode under the control of the first control signal transmitted by the first control signal line AZ.

[0106] Exemplarily, the voltage of the first power signal is greater than the voltage of the second power signal.

[0107] Exemplarily, as shown in FIG2 , the input module 1 includes a first transistor T1 , a gate of the first transistor T1 electrically connected to the gate line WS, a source of the first transistor T1 electrically connected to the data line DL, and a drain of the first transistor T1 electrically connected to the gate gt-4 of the driving transistor DMOS.

[0108] Exemplarily, as shown in FIG2 , the driving module 2 includes a driving transistor DMOS, a drain of which is connected to the anode of the light emitting device 6 .

[0109] Exemplarily, as shown in Figure 2, the compensation module 3 includes a first capacitor C1 and a second capacitor C2, the first plate C1-DJ1 of the first capacitor C1 is electrically connected to the source of the driving transistor DMOS, and the second plate C1-DJ2 of the first capacitor C1 is electrically connected to the gate gt-4 of the driving transistor DMOS; the first plate C2-DJ1 of the second capacitor C2 is electrically connected to the source of the driving transistor DMOS, and the second plate C2-DJ2 of the second capacitor C2 is electrically connected to the first power signal line ELVDD.

[0110] Exemplarily, as shown in Figure 2, the second control module 4 includes a second transistor T2, the gate gt-2 of the second transistor T2 is electrically connected to the second control signal line DS, the source of the second transistor T2 is electrically connected to the first power signal line ELVDD, and the drain of the second transistor T2 is electrically connected to the source of the driving transistor DMOS.

[0111] For example, as shown in FIG2 , the first control module 5 includes a third transistor T3. The gate of the third transistor T3 is electrically connected to the first control signal line AZ, the source of the third transistor T3 is electrically connected to the drain of the drive transistor DMOS, and the drain of the third transistor T3 is electrically connected to the second power signal line VSS. The orthographic projection of the gate of the third transistor T3 on the substrate partially overlaps with the orthographic projection of the first control signal line AZ on the substrate.

[0112] Exemplarily, as shown in FIG7 , the first transistor T1 and the second transistor T2 are located on the same side of the driving transistor DMOS, and the third transistor T3 is located on a side of the driving transistor DMOS away from the second transistor T2 .

[0113] Exemplarily, as shown in Figure 8, the first transistor T1 and the second transistor T2 are staggered in the second direction f2. For example, in the second direction f2, the distance between the gate gt-1 of the first transistor T1 and the gate gt-4 of the driving transistor DMOS is greater than the distance between the gate gt-2 of the second transistor T2 and the gate gt-4 of the driving transistor DMOS.

[0114] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode (also called a gate), a drain electrode (also called a drain), and a source electrode (also called a source). The transistor has a channel region (channel region) between the drain and the source, and current can flow through the drain, the channel region, and the source. Note that in this specification, the channel region refers to the region where the current mainly flows. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of "source" and "drain" are sometimes interchanged. Therefore, in this specification, "source" and "drain" can be interchanged.

[0115] There is no limitation on the types of the above transistors.

[0116] Exemplarily, each transistor may be a P-type MOS tube; exemplary, each transistor may be an N-type MOS tube; exemplary, some transistors are P-type MOS tubes, and some transistors are N-type MOS tubes, for example, the driving transistor DMOS is a P-type MOS tube, and the other transistors are N-type MOS tubes; for another example, the driving transistor DMOS is an N-type MOS tube, and the other transistors are P-type MOS tubes.

[0117] In the design layout of the pixel driving circuit DC provided in this specification, an example is provided in which the third transistor T3 is an N-type MOS transistor and the other transistors are P-type MOS transistors. Based on this, any design layout of the pixel driving circuit DC that evolves by varying the transistor types is within the scope of protection of this disclosure.

[0118] It should be noted that the first node G and the second node S in the above pixel driving circuit DC do not actually exist, but are concepts proposed for the convenience of describing the connection relationship of the circuit and are hereby explained.

[0119] Here, the display color of each sub-pixel P is not limited.

[0120] In some embodiments, the display colors of the sub-pixels P may be the same. For example, all the sub-pixels P display blue. For another example, all the sub-pixels P display white.

[0121] In some other embodiments, the array substrate may include multiple sub-pixels P that display different colors. For example, the array substrate may simultaneously include three sub-pixels P that display red, blue, and green; for another example, the array substrate may simultaneously include four sub-pixels P that display red, blue, green, and white.

[0122] The type of the light emitting device 6 is not limited here.

[0123] Exemplarily, the above-mentioned light-emitting device 6 can be a light-emitting diode, etc.; the light-emitting diode can be an organic light-emitting diode (Organic Light Emitting Diode, abbreviated as OLED), a quantum dot light-emitting diode (QD Light Emitting Diode, abbreviated as QLED), a micro light-emitting diode (Micro Light Emitting Diode, abbreviated as Micro-LED), etc.

[0124] As shown in Figure 11, the pixel driving circuit DC includes a first transistor T1 and a second transistor T2, and the plurality of signal lines include adjacent first signal lines SL1 and second signal lines SL2. A plurality of sub-pixels P are arrayed along a first direction f1 and a second direction f2.

[0125] Exemplarily, as shown in Figures 10 and 11, the gate line WS includes a plurality of first line segments XD1 arranged in sequence along the first direction f1, and a bending portion WZ connected between two adjacent first line segments XD1. The first line segment XD1 extends along the first direction f1, and the bending portion WZ bends toward a side away from the second transistor T2. The source of the second transistor T2 extends into the avoidance area formed by the bending portion WZ.

[0126] As shown in Figure 11, the bending portion WZ is located between the first signal line SL1 and the second signal line SL2, the distance between the bending portion WZ and the second signal line SL2 is less than or equal to the distance between the bending portion WZ and the first signal line SL1, the bending portion WZ includes a second line segment XD2 arranged close to the second signal line SL2, the extension direction of the second line segment XD2 intersects with the first direction f1, the second line segment XD2 and the second signal line SL2 have no overlap in their orthographic projections on the base substrate, and the extension length of the second line segment XD2 is greater than the width of the first line segment XD1.

[0127] As shown in Figure 11, the second line segment XD2 extends along the second direction f2, and the extension length of the second line segment XD2 is the length of the second line segment XD2 along the second direction f2. The width of the first line segment XD1 is the width of the first line segment XD1 in the second direction f2.

[0128] As shown in FIG. 11 , the first line segment XD1 and the second signal line SL2 overlap in orthographic projection on the base substrate.

[0129] By setting the second line segment XD2 and the second signal line SL2 to have no overlap in their orthographic projections on the base substrate, it can be understood that the bent portion WZ and the second signal line SL2 have no overlap in their orthographic projections on the base substrate, which is beneficial to reducing the overlapping area between the gate line WS and the signal line, thereby reducing the coupling capacitance between the gate line WS and the signal line, reducing signal interference, and improving display stability.

[0130] For example, the first signal line SL1 and the second signal line SL2 may both be portions of the first power signal line ELVDD extending along the second direction f2, or may both be data lines DL, which is not limited in the present disclosure.

[0131] For example, the substrate can be a rigid substrate, such as a silicon substrate or a glass substrate; or a flexible substrate, such as a flexible polyimide or other flexible polymer film. Using a silicon substrate helps reduce system volume and achieve lightweighting, and is more suitable for display products with high PPI (Pixels Per Inch) and narrow bezels.

[0132] The material of the silicon substrate includes silicon material, such as single crystal silicon or polycrystalline silicon; before preparing the pixel driving circuit DC, N-type ion implantation can be performed on the silicon substrate to form an N-type well region (N-Well, NW), and then P-type ion implantation is performed in the N-type well region NW to form an SP region for forming a channel region of a transistor on the SP region. The specific processing of the silicon substrate is not limited here, and the ion implantation type in different regions of the silicon substrate is described by taking the preparation of PMOS transistors (P-type Metal Oxide Semiconductor) as an example. When the transistor is an NMOS transistor, the specific processing of the silicon substrate is similar to the steps of the above-mentioned processing, but the polarity of the ion implantation in each step is opposite. The specific processing of the silicon substrate can be referred to the introduction in the relevant technology and will not be repeated here.

[0133] Illustratively, the first power signal line ELVDD can continuously provide a high-level voltage signal, and the signal provided by the first power signal line ELVDD is called an ELVDD signal; the second power signal line VSS can continuously provide a low-level voltage signal, and the signal provided by the second power signal line VSS is called a VSS signal.

[0134] Exemplarily, as shown in FIG11 , in the first direction f1 , the distance between the second line segment XD2 and the second signal line SL2 is greater than or equal to the distance between the second line segment XD2 and the source of the second transistor T2 .

[0135] In FIG11 , the gap width between the second line segment XD2 and the second signal line SL2 is greater than or equal to the gap width between the second line segment XD2 and the source of the second transistor T2. For example, the gap width between the second line segment XD2 and the second signal line SL2 is greater than zero, and the gap width between the second line segment XD2 and the source of the second transistor T2 is zero.

[0136] Exemplarily, as shown in FIG11 , the bending portion WZ further includes a third line segment XD3 and a fourth line segment XD4. The second line segment XD2, the third line segment XD3, and the fourth line segment XD4 are sequentially connected between two adjacent first line segments XD1 and are located on the side of the first line segment XD1 away from the second transistor T2. The third line segment XD3 extends along the first direction f1, and the extension directions of the second line segment XD2 and the fourth line segment XD4 both intersect with the first direction f1. For example, in FIG11 , the second line segment XD2 and the fourth line segment XD4 both extend along the second direction f2.

[0137] As shown in FIG11 , the second line segment XD2 , the third line segment XD3 and the fourth line segment XD4 are sequentially connected to form a U-shaped bending portion WZ, the opening of the U-shaped bending portion WZ faces the second transistor T2 , and the source of the second transistor T2 extends from the opening of the U-shaped bending portion WZ into the U-shaped structure.

[0138] As shown in FIG. 11 , in the first direction f1 , the distance between the second line segment XD2 and the source of the second transistor T2 is less than or equal to the distance between the fourth line segment XD4 and the source of the second transistor T2 .

[0139] In FIG11 , in the first direction f1, the gap width between the second line segment XD2 and the source of the second transistor T2 is less than or equal to the gap width between the fourth line segment XD4 and the source of the second transistor T2. For example, the gap width between the second line segment XD2 and the source of the second transistor T2 is zero, and the gap width between the fourth line segment XD4 and the source of the second transistor T2 is greater than zero.

[0140] Exemplarily, as shown in Figure 11, the source of the second transistor T2 is connected to the first power signal line ELVDD through a first via VIA1. In the orthographic projection on the substrate, the first via VIA1 is set close to the first edge S1, and the first edge S1 is the edge of the source of the second transistor T2 close to the first signal line SL1.

[0141] Exemplarily, as shown in FIG11 , the distance between the second line segment XD2 and the first via VIA1 is greater than the distance between the second line segment XD2 and the second signal line SL2 .

[0142] As shown in Figure 11, the first power signal line ELVDD is connected to the overlapping pattern DP, the overlapping pattern DP is connected to the source of the second transistor T2 through the first via VIA1, the overlapping pattern DP and the second line segment XD2 are located on the same layer, and by setting the distance between the second line segment XD2 and the first via VIA1 to be greater than the distance between the second line segment XD2 and the second signal line SL2, the parasitic capacitance between the overlapping pattern DP and the second line segment XD2 can be reduced, thereby reducing signal interference.

[0143] As shown in FIG. 11 , the gate gt-2 of the second transistor T2 is connected to the second control signal line DS.

[0144] Exemplarily, as shown in Figures 10 and 11, the second control signal line DS includes: a fifth line segment XD5, and a plurality of first branches FZ connected to one side of the fifth line segment XD5, different first branches FZ are connected to the gates gt-2 of different second transistors T2 through second vias VIA2, the fifth line segment XD5 extends along the first direction f1, the first branch FZ includes a sixth line segment XD6, the sixth line segment XD6 extends along the second direction f2, the sixth line segment XD6 has no overlap with the data line DL in their orthographic projections on the substrate, and the extension length of the sixth line segment XD6 is greater than the width of the fifth line segment XD5.

[0145] The extension length of the sixth line segment XD6 is the length of the sixth line segment XD6 along the second direction f2, and the width of the fifth line segment XD5 is the width along the second direction f2.

[0146] By setting the sixth line segment XD6 and the data line DL to have no overlap in their orthographic projection on the substrate, the overlapping area between the second control signal line DS and the data line DL can be reduced, thereby reducing the coupling capacitance between the second control signal line DS and the data line DL and reducing signal interference.

[0147] For example, as shown in FIG11 , the first branch FZ is located between the first signal line SL1 and the second signal line SL2. The distance between the first branch FZ and the second signal line SL2 is less than or equal to the distance between the first branch FZ and the first signal line SL1. The first branch FZ also includes a seventh line segment XD7. The sixth line segment XD6 connects between the fifth line segment XD5 and the seventh line segment XD7. The seventh line segment XD7 is located on the side of the sixth line segment XD6 that is closer to the second signal line SL2. The seventh line segment XD7 is connected to the gate gt-2 of the second transistor T2 via a second via VIA2. The orthographic projections of the seventh line segment XD7 and the second signal line SL2 on the substrate overlap. The width of the seventh line segment XD7 along the second direction f2 is less than the extended length of the sixth line segment XD6.

[0148] As shown in FIG11 , the sixth line segment XD6 , the oppositely disposed fifth line segment XD5 , and the seventh line segment XD7 form a U-shaped structure, and the opening of the U-shaped structure faces the second signal line SL2 .

[0149] Exemplarily, the width of the overlapping region along the first direction f1 is less than or equal to the width of the second signal line SL2 along the first direction f1.

[0150] Exemplarily, as shown in FIG11 , the width of the seventh line segment XD7 along the second direction f2 is greater than the width of the fifth line segment XD5 along the second direction f2 and the width of the sixth line segment XD6 along the first direction f1.

[0151] Exemplarily, as shown in FIG11 , the width of the overlapping region along the second direction f2 is smaller than the extension length of the sixth line segment XD6 .

[0152] Exemplarily, the gate line WS is located in the first conductive layer M1 .

[0153] Exemplarily, as shown in Figures 12 and 13, the first power signal line ELVDD includes a first extension line YS1, a second extension line YS2 and a third extension line YS3, the first extension line YS1 extends along the second direction f2, the second extension line YS2 and the third extension line YS3 both extend along the first direction f1, the second extension line YS2 and the third extension line YS3 are arranged at intervals along the second direction f2 and connected between two adjacent first extension lines YS1; the first extension line YS1, the second extension line YS2 and the third extension line YS3 are all located in the second conductive layer M2, and the two adjacent first extension lines YS1, the second extension line YS2 and the third extension line YS3 together form a closed ring structure that surrounds the driving transistor DMOS (the closed rectangular ring structure shown in Figures 12 and 13).

[0154] Since the driving transistor DMOS is located in a closed ring structure, the driving transistors DMOS of two adjacent sub-pixels P are separated, which plays a shielding role for the driving transistor DMOS, thereby avoiding the signal crosstalk problem between the two adjacent sub-pixels P, and improving the driving stability of the pixel driving circuit DC and the display effect.

[0155] Exemplarily, as shown in FIG13 , a portion of the first transistor T1, a portion of the second transistor T2, and the third transistor T3 are also located within a closed ring structure formed by the first extension line YS1, the second extension line YS2, and the third extension line YS3. Therefore, the closed ring structure also shields the first transistor T1, the second transistor T2, and the third transistor T3.

[0156] The first extension line YS1 , the second extension line YS2 , and the third extension line YS3 constitute a first portion ELVDD- 1 of the first power signal line ELVDD. The first portion ELVDD- 1 is located in the second conductive layer M2 .

[0157] Exemplarily, the width of the first extension line YS1 in the first direction f1 is greater than the widths of the second extension line YS2 and the third extension line YS3 in the second direction f2.

[0158] Exemplarily, the second extension line YS2 is connected to the source of the second transistor T2 through a via.

[0159] Exemplarily, the second control signal line DS and the gate line WS are disposed in the same layer, both located in the first conductive layer M1 .

[0160] 13 , in the orthographic projection on the substrate, the second control signal line DS, the gate line WS and the second extension line YS2 are located between two adjacent rows of sub-pixels P and do not overlap each other, and the second extension line YS2 is located between the second control signal line DS and the gate line WS.

[0161] Exemplarily, the first extension line YS1 overlaps with the orthographic projection of the data line DL on the base substrate. As shown in FIG13 , the second line segment XD2 does not overlap with the orthographic projection of the first extension line YS1 on the base substrate.

[0162] Exemplarily, the data line DL is located in the fourth conductive layer M4, and the second conductive layer M2 is stacked between the first conductive layer M1 and the fourth conductive layer M4. The orthographic projection of the first extension line YS1 on the base substrate covers the orthographic projection of the data line DL on the base substrate at least in the first direction f1.

[0163] Since the gate line WS is located in the first conductive layer M1 and the data line DL is located in the fourth conductive layer M4, by setting the first part ELVDD-1 of the first power signal line ELVDD in the second conductive layer M2, and the second conductive layer M2 is stacked between the first conductive layer M1 and the fourth conductive layer M4, the first power signal line ELVDD can shield the signal interference between the gate line WS and the data line DL.

[0164] Exemplarily, the width of the first extension line YS1 in the first direction f1 is greater than the width of the data line DL in the first direction f1. Furthermore, in an orthographic projection on the substrate, the data line DL is centered relative to the first extension line YS1 in the first direction f1.

[0165] For example, as shown in FIG15 , the first power signal line ELVDD further includes: a fourth extension line YS4 extending along the second direction f2, and a fifth extension line YS5 extending along the first direction f1. The fifth extension line YS5 is connected between two adjacent fourth extension lines YS4. The fourth extension lines YS4 corresponding to different sub-pixels P are spaced apart from each other. The orthographic projections of the fourth extension line YS4 and the first extension line YS1 on the substrate overlap and are connected via vias. The orthographic projections of the fifth extension line YS5 and the second extension line YS2 on the substrate overlap and are connected via vias. The fourth extension line YS4 and the fifth extension line YS5 are both located in the third conductive layer M3, which is stacked between the second conductive layer M2 and the fourth conductive layer M4.

[0166] As shown in FIG. 15 , two adjacent fourth extension lines YS4 and a fifth extension line YS5 connected between the two adjacent fourth extension lines YS4 form an H-shaped structure.

[0167] The fourth extension line YS4 and the fifth extension line YS5 constitute the second portion ELVDD-2 of the first power signal line ELVDD, which is located in the third conductive layer M3. For example, the second portion ELVDD-2 is provided in the same layer as the first control signal line AZ.

[0168] Exemplarily, the width of the fourth extension line YS4 in the first direction f1 is greater than the width of the fifth extension line YS5 in the second direction f2.

[0169] For example, the width of the fourth extension line YS4 in the first direction f1 is substantially equal to the width of the first extension line YS1 in the first direction f1, and the width of the fifth extension line YS5 in the second direction f2 is substantially equal to the width of the second extension line YS2 in the second direction f2.

[0170] By setting the first part ELVDD-1 of the first power signal line ELVDD in the second conductive layer M2 and setting the second part ELVDD-2 of the first power signal line ELVDD in the third conductive layer M3, the conductivity of the first power signal line ELVDD can be significantly improved, the IR Drop (voltage drop) problem of the first power signal line ELVDD can be reduced, and the stability of the signal provided by the first power signal line ELVDD to the pixel driving circuit DC of each sub-pixel P can be improved, thereby improving the stability and uniformity of the luminous brightness of each sub-pixel P and improving the display effect.

[0171] In addition, since the third conductive layer M3 is stacked between the second conductive layer M2 and the fourth conductive layer M4, the signal interference between the gate line WS and the data line DL can be better shielded by disposing the second portion ELVDD-2 of the first power signal line ELVDD in the third conductive layer M3.

[0172] For example, as shown in FIG18 , the third conductive layer M3 further includes a first transfer line ZL1, which is connected to a side of the fifth extension line YS5 facing away from the drive transistor DMOS. For example, the first transfer line ZL1 extends along the second direction f2. The fourth conductive layer M4 further includes a first transfer pattern ZP1, which is connected to the first transfer line ZL1 via a via.

[0173] Exemplarily, as shown in Figures 19 and 21, the first power signal line ELVDD also includes: a sixth extension line YS6, a seventh extension line YS7 and an eighth extension line YS8, the sixth extension line YS6 extends along the second direction f2, the seventh extension line YS7 and the eighth extension line YS8 both extend along the first direction f1, the seventh extension line YS7 and the eighth extension line YS8 are arranged at intervals along the second direction f2 and are connected between two adjacent sixth extension lines YS6, the sixth extension line YS6 overlaps with the data line DL in the orthographic projection on the base substrate, and in the orthographic projection on the base substrate, the seventh extension line YS7 and the eighth extension line YS8 are located on both sides of the second extension line YS2 or the fifth extension line YS5, and the eighth extension line YS8 is connected to the first transfer pattern ZP1 through a via.

[0174] The sixth extension line YS6, the seventh extension line YS7 and the eighth extension line YS8 constitute the third portion ELVDD-3 of the first power signal line ELVDD. The third portion ELVDD-3 is located in the fifth conductive layer M5. The fifth conductive layer M5 is located on the side of the fourth conductive layer M4 away from the substrate.

[0175] Exemplarily, the width of the sixth extension line YS6 in the first direction f1 is substantially equal to the widths of the seventh extension line YS7 and the eighth extension line YS8 in the second direction f2.

[0176] Exemplarily, the width of the sixth extension line YS6 in the first direction f1 is greater than that of the fourth extension line YS4 in the first direction f1. The widths of the seventh extension line YS7 and the eighth extension line YS8 in the second direction f2 are greater than that of the fifth extension line YS5 in the second direction f2.

[0177] Exemplarily, the third portion ELVDD- 3 of the first power signal line ELVDD is disposed in the same layer as the auxiliary anode ANF.

[0178] Illustratively, the anode of the light-emitting device 6 is disposed on a side of the fifth conductive layer M5 facing away from the base substrate. The fifth conductive layer M5 further includes an auxiliary anode ANF extending along the second direction f2. The auxiliary anode ANF is connected to the anode of the light-emitting device 6 and the drain of the drive transistor DMOS, respectively. As shown in FIG. 19 , in an orthographic projection onto the base substrate, the auxiliary anode ANF is located between two adjacent sixth extension lines YS6 and on the side of the seventh extension line YS7 facing away from the eighth extension line YS8.

[0179] As shown in FIG19 , the auxiliary anode ANF is located in a U-shaped region surrounded by the sixth extension line YS6 and the seventh extension line YS7 , so that the sixth extension line YS6 and the seventh extension line YS7 shield the auxiliary anode ANF and prevent signal interference between adjacent auxiliary anodes ANF.

[0180] Exemplarily, the orthographic projection of the auxiliary anode ANF on the substrate partially overlaps with the driving transistor DMOS, the orthographic projection of the auxiliary anode ANF on the substrate partially overlaps with the third transistor T3, the orthographic projection of the auxiliary anode ANF on the substrate partially overlaps with the first capacitor C1, and the orthographic projection of the auxiliary anode ANF on the substrate partially overlaps with the second capacitor C2.

[0181] Exemplarily, the second electrode plate C2 - DJ2 of the second capacitor C2 is disposed in the same layer as the data line DL.

[0182] Exemplarily, as shown in FIG. 17 and FIG. 20 , the second electrode C2 - DJ2 of the second capacitor C2 is located in the fourth conductive layer M4 and is connected to the seventh extension line YS7 through a via.

[0183] For example, as shown in Figures 10 and 13, the array substrate further includes a second power signal line VSS located in the first conductive layer M1 and including an eighth line segment XD8 extending along the first direction f1. In an orthographic projection onto the base substrate, a third extension line YS3 is located within the region of the eighth line segment XD8 and is centered relative to the eighth line segment XD8 in the second direction f2.

[0184] Exemplarily, as shown in Figure 16, the first control signal line AZ is located in the third conductive layer M3, the second conductive layer M2 also includes a third transfer pattern ZP3, the first control signal line AZ is connected to the third transfer pattern ZP3 through a third via VIA3, and the third transfer pattern ZP3 is connected to the gate of the third transistor T3 through a fifth via VIA5.

[0185] The orthographic projection of the third via VIA3 on the substrate is located within the orthographic projection of the channel region of the third transistor T3 on the substrate, and the orthographic projection of the fifth via VIA5 does not overlap with the orthographic projection of the channel region of the third transistor T3 on the substrate.

[0186] By arranging the third via VIA3 within the channel region of the third transistor T3, the distance between the second power signal line VSS or the eighth line segment XD8 and the first control signal line AZ can be reduced, thus saving wiring space and further improving resolution.

[0187] By arranging the fifth via VIA5 so as not to overlap with the channel region of the third transistor T3 , ie, arranging the fifth via VIA5 outside the channel region of the third transistor T3 , the influence of the fifth via VIA5 on the channel region of the third transistor T3 can be avoided.

[0188] For example, as shown in Figures 14 to 16, in the orthographic projection on the substrate, the first control signal line AZ is located on the side of the third extension line YS3 close to the third transistor T3, the first control signal line AZ does not overlap with the third extension line YS3, and the first control signal line AZ overlaps with the eighth line segment XD8.

[0189] For example, as shown in FIG14 , the first control signal line AZ includes an eleventh line segment XD11 and a twelfth line segment XD12 connected to each other. The eleventh line segment XD11 extends along the first direction f1, and the twelfth line segment XD12 is located on a side of the eleventh line segment XD11 close to the third transistor T3. The twelfth line segment XD12 is connected to the gate of the third transistor T3 via a via. For example, the twelfth line segment XD12 extends along the second direction f2.

[0190] The eleventh line segment XD11 is located on a side of the third transistor T3 away from the driving transistor DMOS, and the eleventh line segment XD11 does not overlap with the orthographic projection of the third transistor T3 on the substrate.

[0191] For example, as shown in FIG7 , the channel region of the drive transistor DMOS is located in the semiconductor layer AL. The semiconductor layer AL further includes a first semiconductor pattern aa-6 extending along the second direction f2 and overlapping with the orthographic projection of the data line DL on the substrate. As shown in FIG10 and FIG13 , the second power signal line VSS further includes a ninth line segment XD9 and a tenth line segment XD10. Both the ninth line segment XD9 and the tenth line segment XD10 are located on a side of the eighth line segment XD8 near the third transistor T3 and are respectively connected to the eighth line segment XD8. The first semiconductor pattern aa-6 is connected to the ninth line segment XD9 via a via, and the tenth line segment XD10 is connected to the drain of the third transistor T3 via a via.

[0192] Exemplarily, as shown in Figure 13, the first extension line YS1 is located between two adjacent driving transistors DMOS, and a second transfer pattern ZP2 is also provided between the first extension line YS1 and the driving transistor DMOS. Different second transfer patterns ZP2 are arranged at intervals from each other and correspond to different sub-pixels P. The second transfer pattern ZP2 is located in the first conductive layer M1, and the first part of the second transfer pattern ZP2 is connected to the first extension line YS1 through a via.

[0193] For example, as shown in FIG7 , the semiconductor layer AL further includes a second semiconductor pattern aa-5 extending along the second direction f2. As shown in FIG13 , the second semiconductor pattern aa-5 is located between the first extension line YS1 and the drive transistor DMOS. Different second semiconductor patterns aa-5 are spaced apart and correspond to different sub-pixels P. The second semiconductor pattern aa-5 is connected to the second portion of the second transfer pattern ZP2 via a via.

[0194] As shown in FIG. 13 , in the orthographic projection along the first direction f1 , the first semiconductor pattern aa- 6 overlaps with the driving transistor DMOS.

[0195] Exemplarily, the second semiconductor pattern aa-5 and the first semiconductor pattern aa-6 are both electrically connected to the base substrate.

[0196] Exemplarily, when the third transistor T3 is an N-type transistor and the other transistors are P-type transistors, the substrate substrate of the area where the third transistor T3 is located is a P-type silicon substrate, the substrate substrate of the area where the other transistors are located is an N-type silicon substrate, and the first semiconductor pattern aa-6 of the semiconductor layer AL set near the third transistor T3 is electrically connected to the area of ​​the P-type silicon substrate, and the second semiconductor pattern aa-5 of the semiconductor layer AL set near the driving transistor DMOS is electrically connected to the area of ​​the N-type silicon substrate.

[0197] 15 and 16 , the second plate C1-DJ2 of the first capacitor C1 is connected to the gate gt-4 of the driving transistor DMOS through the fourth via VIA4, and the drain of the first transistor T1 is connected to the gate gt-4 of the driving transistor DMOS through the second adapter ZL2.

[0198] The second adapter line ZL2 is provided on the same layer as the gate line WS and is located in the first conductive layer M1. The first plate C1-DJ1 of the first capacitor C1 is located in the second conductive layer M2. As shown in Figures 15 and 16, the first plate C1-DJ1 of the first capacitor C1 overlaps with the orthographic projection of the drive transistor DMOS on the substrate. The first plate C1-DJ1 of the first capacitor C1 does not overlap with the orthographic projections of the second adapter line ZL2, the first transistor T1, and the second transistor T2 on the substrate.

[0199] Since the orthographic projections of the first plate C1-DJ1 of the first capacitor C1 and the second switching line ZL2, the first transistor T1, and the channel region of the second transistor T2 on the substrate do not overlap, the coupling capacitance between the first plate C1-DJ1 of the first capacitor C1 and the second switching line ZL2, between the first plate C1-DJ1 of the first capacitor C1 and the gate gt-1 of the first transistor T1, and between the first plate C1-DJ1 of the first capacitor C1 and the gate gt-2 of the second transistor T2 is reduced, thereby preventing signal interference.

[0200] In addition, since the first plate C1-DJ1 of the first capacitor C1 and the first part ELVDD-1 of the first power signal line ELVDD are arranged in the same layer and are both located in the second conductive layer M2, the closed ring structure formed by the first extension line YS1, the second extension line YS2 and the third extension line YS3 can shield the first plate C1-DJ1 of the first capacitor C1, thereby preventing signal interference between the first plates C1-DJ1 of adjacent first capacitors C1.

[0201] As shown in FIG. 15 and FIG. 16 , the first plate C1 - DJ1 of the first capacitor C1 overlaps with the orthographic projections of the source, drain, and channel region of the driving transistor DMOS on the substrate.

[0202] Exemplarily, as shown in Figures 15 and 16, the second plate C1-DJ2 of the first capacitor C1 is located in the third conductive layer M3, and the first plate C1-DJ1 of the first capacitor C1 includes a first capacitor pattern CP1 and a second capacitor pattern CP2 closely arranged along the second direction f2. The width of the first capacitor pattern CP1 along the first direction f1 is greater than the width of the second capacitor pattern CP2 along the first direction f1. The second capacitor pattern CP2 is located on the side of the second capacitor pattern CP2 close to the second adapter line ZL2. The first capacitor pattern CP1 and the second capacitor pattern CP2 are spliced ​​together to form a gap, which is used to avoid the fourth via VIA4.

[0203] In addition, since the second plate C1-DJ2 of the first capacitor C1 is arranged on the same layer as the second portion of the first power signal line ELVDD (i.e., the fourth extension line YS4 and the fifth extension line YS5), the second plate C1-DJ2 of the first capacitor C1 is located, for example, in the area enclosed by the fourth extension line YS4 and the fifth extension line YS5. Therefore, the fourth extension line YS4 and the fifth extension line YS5 can shield the second plate C1-DJ2 of the first capacitor C1, thereby preventing signal interference between the second plates C1-DJ2 of adjacent first capacitors C1.

[0204] Exemplarily, each of the via holes is filled with a conductive material, such as metal tungsten.

[0205] In the present disclosure, the orthographic projections of the two parts connected by the via on the substrate overlap.

[0206] For example, as shown in FIG16 , in the orthographic projection on the substrate, the first control signal line AZ and the second control signal line DS are respectively located on opposite sides of the driving transistor DMOS, the gate line WS is located on the side of the second control signal line DS away from the driving transistor DMOS, and the second power signal line VSS is located on the side of the first control signal line AZ away from the driving transistor DMOS.

[0207] Exemplarily, as shown in FIG16 , the orthographic projection of the first control signal line AZ on the substrate partially overlaps with the orthographic projection of the third transistor T3 on the substrate.

[0208] For example, as shown in FIG16 , the gate line WS overlaps with the orthographic projection of the first transistor T1 on the substrate, and the gate line WS does not overlap with the orthographic projection of the second transistor T2 on the substrate. The orthographic projection of the gate line WS on the substrate overlaps with the orthographic projection of the gate gt-1 of the first transistor T1 on the substrate.

[0209] For example, as shown in FIG16 , the second control signal line DS overlaps with the orthographic projections of the first transistor T1 and the second transistor T2 on the substrate. The orthographic projection of the second control signal line DS on the substrate overlaps with the orthographic projection of the gate electrode gt-1 of the first transistor T1 on the substrate, the orthographic projection of the second control signal line DS on the substrate overlaps with the orthographic projection of the source electrode of the second transistor T2 on the substrate, and the orthographic projection of the second control signal line DS on the substrate does not overlap with the orthographic projection of the gate electrode gt-2 of the second transistor T2 on the substrate.

[0210] Exemplarily, the orthographic projection of the first capacitor C1 on the substrate overlaps with the orthographic projection of the driving transistor DMOS on the substrate, and the orthographic projection of the second capacitor C2 on the substrate overlaps with the orthographic projection of the driving transistor DMOS on the substrate.

[0211] By arranging the driving transistor DMOS, the first capacitor C1 and the second capacitor C2 in a stacked configuration, the design space of the pixel driving circuit DC can be greatly saved, and it is more conducive to preparing a high PPI (Pixels Per Inch, pixel density unit) display product.

[0212] Illustratively, the array substrate provided by the present disclosure includes a semiconductor layer AL, a gate layer GT, a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4 and a fifth conductive layer M5 stacked in sequence on one side of a base substrate, and the semiconductor layer AL is arranged close to the base substrate.

[0213] Exemplarily, as shown in FIG. 7 , the semiconductor layer AL includes a first portion aa- 1 , a second portion aa- 2 , a third portion aa- 3 , a fourth portion aa- 4 , a second semiconductor pattern aa- 5 , and a first semiconductor pattern aa- 6 .

[0214] As shown in FIG. 7 , the orthographic projection area of ​​the fourth portion aa- 4 of the semiconductor layer AL on the base substrate is larger than the orthographic projection areas of the other portions on the base substrate.

[0215] As shown in Figure 7, the first part aa-1 of the semiconductor layer AL includes the source, drain and channel region of the first transistor T1, the second part aa-2 of the semiconductor layer AL includes the source, drain and channel region of the second transistor T2, the third part aa-3 of the semiconductor layer AL includes the source, drain and channel region of the third transistor T3, and the fourth part aa-4 of the semiconductor layer AL includes the source, drain and channel region of the driving transistor DMOS.

[0216] Illustratively, the orthographic projections of the first portion aa-1, the second portion aa-2, the third portion aa-3, the fourth portion aa-4, the second semiconductor pattern aa-5 and the first semiconductor pattern aa-6 of the semiconductor layer AL on the base substrate all include quadrilaterals.

[0217] Exemplarily, the first portion aa-1, the second portion aa-2, the fourth portion aa-4, the second semiconductor pattern aa-5, and the first semiconductor pattern aa-6 of the semiconductor layer AL extend in the same direction, and the third portion aa-3 of the semiconductor layer AL extends in a direction that intersects with the extension directions of the other portions. For example, the third portion aa-3 of the semiconductor layer AL extends along the first direction f1.

[0218] In one sub-pixel P, the second portion aa-2 of the semiconductor layer AL and the fourth portion aa-4 of the semiconductor layer AL are an integrated structure.

[0219] The specific material of the semiconductor layer AL is not limited here. For example, the material of the semiconductor layer AL may be silicon material, such as polysilicon.

[0220] Here, there is no limitation on the size of the graphic area of ​​the second semiconductor pattern aa-5 of the semiconductor layer AL and the first semiconductor pattern aa-6 of the semiconductor layer AL; for example, the second semiconductor pattern aa-5 of the semiconductor layer AL is larger than the graphic area of ​​the first semiconductor pattern aa-6 of the semiconductor layer AL; for another example, the second semiconductor pattern aa-5 of the semiconductor layer AL is smaller than or equal to the graphic area of ​​the first semiconductor pattern aa-6 of the semiconductor layer AL; the specific area can be determined according to the electrical connection requirements of the design space.

[0221] The following uses a silicon substrate as an example to illustrate substrate requirements for different types of transistors (MOS transistors): When the third transistor T3 is an N-type transistor and the other transistors are P-type transistors, the silicon substrate in the region where the third transistor T3 is located is a P-type silicon substrate, and the silicon substrate in the region where the other transistors are located is an N-type silicon substrate. The second semiconductor pattern aa-5 of the semiconductor layer AL is electrically connected to the region of the N-type silicon substrate, and the first semiconductor pattern aa-6 of the semiconductor layer AL is electrically connected to the region of the P-type silicon substrate. The second semiconductor pattern aa-5 of the semiconductor layer AL is electrically connected to the first power signal line ELVDD, and the first semiconductor pattern aa-6 of the semiconductor layer AL is electrically connected to the second power signal line VSS, so that the first power signal line ELVDD provides an ELVDD potential to the region of the N-type silicon substrate, and the second power signal line VSS provides a VSS potential to the region of the P-type silicon substrate. The ELVDD potential is greater than the VSS potential. For example, the ELVDD potential can be a positive voltage potential, and the VSS potential can be a ground potential or a negative voltage potential. For another example, the ELVDD potential can be a high-level potential, and the VSS potential can be a low-level potential.

[0222] Exemplarily, as shown in Figure 8, the gate layer GT includes the gates of each transistor, for example, the gate gt-1 of the first transistor T1, the gate gt-2 of the second transistor T2, the gate gt-3 of the third transistor T3, and the gate gt-4 of the driving transistor DMOS; the area of ​​the positive projection of the gate gt-4 of the driving transistor DMOS on the substrate is larger than the area of ​​the positive projection of the gates of other transistors on the substrate.

[0223] Figure 9 shows a top-down view of the structure after the semiconductor layer AL and the gate layer GT are stacked. As shown in Figure 9, the orthographic projection of the gate layer GT on the substrate partially overlaps with the orthographic projection of the semiconductor layer AL on the substrate. The area of ​​the semiconductor layer AL that overlaps with the orthographic projection of the gate layer GT on the substrate is the channel region of each transistor, and the area of ​​the semiconductor layer AL that does not overlap with the orthographic projection of the gate layer GT on the substrate is the source or drain of each transistor.

[0224] As shown in FIG9 , the upper and lower sides of the channel regions of the first transistor T1 , the second transistor T2 , and the driving transistor DMOS are source and drain respectively; the left and right sides of the channel region of the third transistor T3 are source and drain respectively.

[0225] For example, the source and drain of each transistor may be doped to improve their conductivity, and the doping element may be boron or the like.

[0226] For example, in order to save the arrangement space of various components and wirings in the pixel driving circuit DC, the source (or drain) of one transistor may be set to be shared with the source (or drain) of another transistor.

[0227] Exemplarily, as shown in FIG9 , the drain of the second transistor T2 and the source of the driving transistor DMOS may be integrated; exemplary, the drain of the second transistor T2 and the source of the driving transistor DMOS may share the same structure.

[0228] It should be noted that an integrated structure refers to a structure that is prepared using the same precursor material in the same preparation process; the final materials of the two structures corresponding to the integrated structure can be the same or different; sharing a structure means that the same material is prepared in the same preparation process, and the final materials are the same.

[0229] Exemplarily, the array substrate further includes a gate insulating layer (GI), which covers the gate layer GT and is located between the gate layer GT and the first conductive layer M1.

[0230] Exemplarily, as shown in FIG10 , the first conductive layer M1 includes a gate line WS, a second control signal line DS, a second power signal line VSS, a second transfer pattern ZP2 , and a second transfer line ZL2 .

[0231] Figure 11 shows a top-down view of the stacked structure of the semiconductor AL, gate layer GT, first conductive layer M1, and data line DL. As shown in Figure 11 , the second power signal line VSS is located on the side of the third transistor T3 that is away from the driver transistor DMOS. Because the second power signal line VSS is electrically connected to the drain of the third transistor T3, it can be positioned adjacent to the third transistor T3 to save design space.

[0232] Exemplarily, as shown in FIG12 , the second conductive layer M2 includes a first extension line YS1 , a second extension line YS2 , a third extension line YS3 , and a first electrode plate C1 - DJ1 of the first capacitor C1 .

[0233] 13 is a top view of the structure of the semiconductor AL, the gate layer GT, the first conductive layer M1 and the second conductive layer M2 after being stacked together.

[0234] For example, as shown in Figure 14 , the third conductive layer M3 includes a fourth extension line YS4, a fifth extension line YS5, a first control signal line AZ, and a second electrode plate C1-DJ2 of the first capacitor C1. Referring to Figure 15 , a top view of the second conductive layer M2 and the third conductive layer M3 after being stacked together is shown. Referring to Figure 16 , a top view of the semiconductor AL, the gate layer GT, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 after being stacked together is shown.

[0235] For example, as shown in Figure 17 , the fourth conductive layer M4 includes the data line DL and the second electrode C2 - DJ2 of the second capacitor C2 . Figure 18 is a top view of the structure of the third conductive layer M3 and the fourth conductive layer M4 stacked together.

[0236] For example, as shown in FIG19 , the fifth conductive layer M5 includes a sixth extension line YS6, a seventh extension line YS7, an eighth extension line YS8, and an auxiliary anode ANF. FIG20 shows a top view of the structure after the fourth conductive layer M4 and the fifth conductive layer M5 are stacked together. FIG21 shows a top view of the structure after the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 are stacked together.

[0237] Exemplarily, the gate layer GT, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4 and the fifth conductive layer M5CTOP can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al) or molybdenum (Mo); or, alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb); the alloy material can be a single-layer structure; or it can be a multi-layer composite structure, such as a stacked structure consisting of a Mo layer, a Cu layer and a Mo layer.

[0238] An insulating layer is provided between every two adjacent conductive layers. The insulating layer may be made of silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiON, etc., and the insulating layer may be a single-layer structure or a multi-layer composite structure.

[0239] In addition, the number of connection holes (also called via holes) on the insulating layer between the conductive layers in the present disclosure can be determined according to actual needs and is not limited here.

[0240] In local areas, for example, to improve the conductivity stability between connecting lines or components of different film layers, multiple vias filled with conductive materials can be set between two conductive structures. The number of vias drawn in the drawings provided in the present disclosure does not represent a limitation on their number, but is only an exemplary description.

[0241] The shapes and arrangements of the plurality of vias are not limited here either.

[0242] For example, the planar shape of the via hole may be rectangular, circular, or elliptical, etc., and the sizes of the plurality of via holes may be the same or different.

[0243] The array substrate provided in the present disclosure may also include a pixel definition layer, an organic light-emitting layer, a cathode, a common electrode layer (Common electrode), a first packaging layer, a color film structure layer, and a second packaging layer, etc. For details, please refer to the introduction in the relevant technology and will not be repeated here.

[0244] FIG22 shows a signal timing diagram of the operation process of the pixel driving circuit shown in FIG2 . As shown in FIG22 , the operation process of the pixel driving circuit includes four stages.

[0245] The following takes the pixel driving circuit shown in FIG2 as an example in which all transistors are P-type MOS tubes, and describes the working principle of the pixel driving circuit in combination with the signal timing diagram shown in FIG22.

[0246] 1. In the first stage H1 (Vofs writing stage, also called initialization stage), as shown in Figure 22, a low-level second control signal is input to the second control signal line DS, a low-level gate drive signal (also called scanning signal) is input to the gate line WS, and a low-level first control signal is input to the first control signal line AZ.

[0247] As shown in Figure 3, the transistor connected to the second control signal line DS receives a low-level second control signal, the transistor connected to the gate line WS receives a low-level gate drive signal, the transistor connected to the first control signal line AZ receives a low-level first control signal, the data line DL receives the Vofs voltage signal, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, the voltage value of Vofs is written to the first node G, and the voltage value of Vdd is written to the second node S. At this time, Vini = Vdd-Vofs.

[0248] 2. In the second stage H2 (self-discharge threshold voltage reading stage), as shown in Figure 22, a high-level second control signal is input to the second control signal line DS, a high-level gate drive signal is input to the gate line WS, and a low-level first control signal is input to the first control signal line AZ.

[0249] As shown in FIG4 , the transistor connected to the second control signal line DS receives a high-level second control signal, the transistor connected to the gate line WS receives a high-level gate drive signal, and the transistor connected to the first control signal line AZ receives a low-level first control signal; the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on; since the first node G is floating, under the action of the first capacitor C1, the voltage of the first node G changes with the voltage of the second node S, so that the voltage difference between the first node G and the second node S remains unchanged in the previous stage, that is, Vgs=Vini=Vdd-Vofs

[0250] Under the effect of the back gate, |V TH-EF |=a*(Vdd-Vs)+|V TH |, a is the coefficient of the back gate effect, Vs is the voltage of the second node S, as the voltage Vs of the second node S decreases, since Vgs remains unchanged at Vini, |V TH-EF When | increases to Vini, the discharge stops and the driving transistor DMOS is turned off. At this time: a*(Vdd-Vs)+|V TH |=Vini=Vdd-Vofs;

[0251] Then Vs=Vdd+(|V TH |-Vini) / a; Vg=Vdd-Vini+(|V TH |-Vini) / a.

[0252] 3. In the third stage H3 (Vdata writing and threshold compensation stage), as shown in Figure 22, a high-level second control signal is input to the second control signal line DS, a low-level gate drive signal is input to the gate line WS, and a low-level first control signal is input to the first control signal line AZ.

[0253] As shown in FIG5 , the transistor connected to the second control signal line DS receives a high-level second control signal, the transistor connected to the gate line WS receives a low-level gate drive signal, and the transistor connected to the first control signal line AZ receives a low-level first control signal. The first transistor T1 and the third transistor T3 are turned on, and the second transistor T2 is turned off. At this time, the Vdata signal is written to the first node G, and the voltage of the first node G changes from Vofs to Vdata. Since the second node S is floating, the voltage change value of the second node S is ΔVs; ΔVs=(1-b)*Vg, where b=C2 / (C1+C2); ΔVg=Vdata-Vdd+Vini-(|V TH |-Vini) / a =Vdata-Vdd+Vini+(Vini-|V TH |) / a;

[0254] Then, ΔVs=(1-b)*[Vdata-Vdd+Vini+(Vini-|V TH |) / a];

[0255] At this time, the voltage of the second node S is: Vdd-(Vini-|V TH |) / a+ΔVs=Vdd-(Vini-|V TH |) / a+(1-b)*[Vdata-Vdd+Vini+(Vini-|V TH |) / a] =Vdata+Vini-bVdata+bVdd*b(Vini-|V TH |) / a-bVini;

[0256] Then |Vgs|=(1-b / ab)*Vini+b|V TH | / a+b(Vdd-Vdata).

[0257] 4. In the fourth stage H4 (light-emitting stage), as shown in FIG22 , a low-level second control signal is input to the second control signal line DS, a high-level gate drive signal is input to the gate line WS, and a high-level first control signal is input to the first control signal line AZ.

[0258] As shown in Figure 6, the transistor connected to the second control signal line DS receives a low-level second control signal, the transistor connected to the gate line WS receives a high-level gate drive signal, the transistor connected to the first control signal line AZ receives a high-level first control signal, the first transistor T1 and the third transistor T3 are turned off, the second transistor T2 is turned on, and the driving transistor DMOS is turned on.

[0259] During the light emitting stage of the light emitting device 6, the current in the light emitting path between the second node S and the anode is:

[0260] It can be seen from the above formula that the current in the light emitting path between the second node S and the anode is independent of the threshold voltage VTH of the driving transistor DMOS.

[0261] It should be noted that in Figures 3-6, the mark "×" represents the transistor in the off state, and the mark "√" represents the transistor in the on state. In addition, at the nodes of the pixel driving circuit (e.g., the first node G, the second node S) and the signal line input end of the pixel driving circuit, the mark "H" represents the signal at this location is a high-level signal, and the mark "L" represents the signal at this location is a low-level signal. The high and low here only represent the relative magnitude relationship between the input voltage signals.

[0262] It should also be noted that in actual applications, when each of the above-mentioned pixel driving circuits is an N-type transistor, the signal timing diagram of the circuit (including the DS signal, WS signal and AZ signal) is opposite in phase to the timing signal as shown in Figure 22, and the working principle of the circuit is similar to the above process.

[0263] When the third transistor T3 in the above-mentioned pixel driving circuit is an N-type transistor and the other transistors are P-type transistors, the DS signal and the WS signal in the timing signal of the circuit diagram are the same as the timing signal in Figure 22, and the AZ signal is opposite in phase to the timing signal in Figure 22. The working principle of the circuit is similar to the above process.

[0264] The present disclosure provides a display device, including an array substrate as provided in any embodiment, and a driving circuit connected to the array substrate and configured to provide a driving signal to the array substrate.

[0265] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned array substrate.

[0266] For example, the display device disclosed herein may include but is not limited to an OLED display device or a QLED display device, which may be used in virtual reality devices or enhanced display devices, etc. The display device may include but is not limited to: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function.

[0267] For example, the array substrate of the substrate substrate in the display device can integrate the pixel driving circuit array, Source Driver (source driver), Gate Driver (gate driver), Emission Control Driver (light control driver, i.e., EOA unit in the present disclosure), OSC (oscillator), Gamma Register (Gamma register) and display control module on the same chip using integrated circuits. The pixel driving circuit, Source Driver, Gate Driver, Emission Driver and other parts are analog circuit modules, while the Gamma Register, interface and display control module are mainly digital modules. The array substrate of the substrate substrate that integrates digital modules and analog modules is a typical SOC (System ON Chip). Because the analog circuit modules and digital circuit modules are mixed on the same chip (One Chip technology), the manufacturing process node of the chip is determined by the digital circuit module with higher requirements between the analog circuit module and the digital circuit module.

[0268] For example, the array substrate of the One Chip technology can be manufactured using an integrated circuit manufacturing process with a thickness of 0.11 μm or less than 55 nm. In practical applications, due to the high cost of One Chip technology, One Chip technology is often used in small-sized display products, such as virtual reality (VR) or augmented reality (AR) near-eye display.

[0269] For example, the array substrate of the base substrate can also separate the analog circuit parts such as the pixel driving circuit array, source driver, gate driver, emission driver (i.e., the EOA unit disclosed in the present invention) from the OSC, gamma register, interface, and display control module, changing from One Chip technology to Two Chip technology. The size of the analog circuit part is determined by the size of the display area (Active Area) of the silicon-based microdisplay, but its manufacturing process requirements are low, and a low-process process can be used to reduce this part of the cost. Moreover, because the digital circuit part is separated, its size is reduced compared to the One Chip mode, and the cost can be further reduced. The digital circuit part mainly includes the OSC, gamma register, interface, and display control module. This part is smaller in size and can be prepared separately using a high-process process that matches the circuit manufacturing requirements. This is the so-called Two Chip mode. The two-chip mode uses a mode in which the display panel (Panel) and the DDIC (Display Driver Integrated Chip) are separated. OLED devices are processed on the panel. After processing and testing, the finished product that can display normally is bonded to the DDIC through COF (Chip on FPC) or COC (Chip on Chip), ultimately forming a controllable silicon-based micro-display device.

[0270] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0271] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0272] In this disclosure, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0273] References in this disclosure to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0274] In this disclosure, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0275] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this disclosure.

[0276] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0277] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0278] As used in this disclosure, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0279] The use of "for" or "configured to" in this disclosure is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0280] The use of "based on" or "according to" in this disclosure is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values.

[0281] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0282] As used in this disclosure, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute flushness and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

[0283] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0284] The present disclosure describes exemplary embodiments with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this disclosure, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0285] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. An array substrate, comprising: substrate; a plurality of sub-pixels arranged on one side of the base substrate, a plurality of gate lines arranged along the second direction, and a plurality of signal lines arranged along the first direction, the signal lines including data lines, the orthographic projections of the gate lines and the data lines on the base substrate intersecting each other and defining the plurality of sub-pixels, the sub-pixels including a pixel driving circuit and a light-emitting device connected to each other, the pixel driving circuit including a first transistor and a second transistor, the gate of the first transistor being connected to the gate line and the source being connected to the data line, the plurality of signal lines including adjacent first signal lines and second signal lines; The gate line includes a plurality of first line segments arranged in sequence along a first direction, and a bending portion connecting two adjacent first line segments, wherein the first line segments extend along the first direction, the bending portion bends toward a side away from the second transistor, and the source of the second transistor extends into an avoidance area formed by the bending portion; The bending portion is located between the first signal line and the second signal line, the distance between the bending portion and the second signal line is less than or equal to the distance between the bending portion and the first signal line, the bending portion includes a second line segment arranged close to the second signal line, the extension direction of the second line segment intersects with the first direction, the second line segment and the second signal line have no overlap in their orthographic projections on the base substrate, and the extension length of the second line segment is greater than the width of the first line segment.

2. The array substrate according to claim 1, wherein: In the first direction, a distance between the second line segment and the second signal line is greater than or equal to a distance between the second line segment and the source of the second transistor.

3. The array substrate according to claim 1, wherein: The source of the second transistor is connected to the first power signal line through a first via. In the orthographic projection on the substrate, the first via is arranged close to a first edge, which is the edge of the source of the second transistor close to the first signal line.

4. The array substrate according to claim 3, wherein: A distance between the second line segment and the first via is greater than a distance between the second line segment and the second signal line.

5. The array substrate according to claim 1, wherein: The bent portion further includes a third line segment and a fourth line segment, wherein the second line segment, the third line segment, and the fourth line segment are sequentially connected between two adjacent first line segments and are located on a side of the first line segment away from the second transistor, the third line segment extends along the first direction, and the second line segment and the fourth line segment extend along the second direction; and In the first direction, a distance between the second line segment and the source of the second transistor is less than or equal to a distance between the fourth line segment and the source of the second transistor.

6. The array substrate according to claim 1, wherein: The gate of the second transistor is connected to a second control signal line, and the second control signal line includes: A fifth line segment, and multiple first branches connected to one side of the fifth line segment, different first branches are connected to the gates of different second transistors through second vias, the fifth line segment extends along the first direction, the first branch includes a sixth line segment, the sixth line segment extends along the second direction, the sixth line segment and the data line have no overlap in their orthographic projection on the substrate, and the extension length of the sixth line segment is greater than the width of the fifth line segment.

7. The array substrate according to claim 6, wherein: The first branch is located between the first signal line and the second signal line, and the distance between the first branch and the second signal line is less than or equal to the distance between the first branch and the first signal line; The first branch also includes a seventh line segment, the sixth line segment connects the fifth line segment and the seventh line segment, the seventh line segment is located on a side of the sixth line segment close to the second signal line, the seventh line segment is connected to the gate of the second transistor through the second via, the seventh line segment and the second signal line have an overlapping area in their orthographic projections on the substrate, and the width of the seventh line segment along the second direction is less than the extension length of the sixth line segment.

8. The array substrate according to claim 7, wherein: The width of the overlapping region along the first direction is less than or equal to the width of the second signal line along the first direction; and / or The width of the seventh line segment along the second direction is greater than the width of the fifth line segment along the second direction and the width of the sixth line segment along the first direction; and / or A width of the overlapping region along the second direction is smaller than an extending length of the sixth line segment.

9. The array substrate according to claim 1, wherein: The gate line is located in the first conductive layer, and the pixel driving circuit further includes: a driving transistor, a source of which is connected to the drain of the second transistor, and a drain of which is connected to the anode of the light emitting device; The source of the second transistor is connected to the first power signal line, the first power signal line includes a first extension line, a second extension line and a third extension line, the first extension line is along the second direction Extension, the second extension line and the third extension line both extend along the first direction, the second extension line and the third extension line are arranged along the second direction and connected between two adjacent first extension lines; The first extension line, the second extension line and the third extension line are all located in the second conductive layer. Two adjacent first extension lines, the second extension line and the third extension line together form a closed ring structure surrounding the driving transistor.

10. The array substrate according to claim 9, wherein: The gate of the second transistor is connected to a second control signal line, and the second control signal line is located in the first conductive layer; In the orthographic projection on the base substrate, the second control signal line, the gate line and the second extension line are located between two adjacent rows of sub-pixels and do not overlap with each other, the second extension line is located between the second control signal line and the gate line, and the second extension line is connected to the source of the second transistor through a via.

11. The array substrate according to claim 9, wherein: The data line is located in the fourth conductive layer, and the second conductive layer is stacked between the first conductive layer and the fourth conductive layer; The orthographic projection of the first extension line on the base substrate covers the orthographic projection of the data line on the base substrate at least in a first direction.

12. The array substrate according to claim 11, wherein: The first power signal line further includes: a fourth extension line extending along the second direction, and a fifth extension line extending along the first direction, the fifth extension line being connected between two adjacent fourth extension lines, the fourth extension lines corresponding to different sub-pixels being spaced apart from each other, the fourth extension line overlapping with the orthographic projection of the first extension line on the base substrate and being connected through a via hole, and the fifth extension line overlapping with the orthographic projection of the second extension line on the base substrate and being connected through a via hole; and The fourth extension line and the fifth extension line are both located in a third conductive layer, and the third conductive layer is stacked between the second conductive layer and the fourth conductive layer.

13. The array substrate according to claim 12, wherein: The third conductive layer further includes: a first transfer line connected to a side of the fifth extension line away from the driving transistor; The fourth conductive layer further includes a first transfer pattern, wherein the first transfer pattern is connected to the first transfer line through a via hole; The first power signal line further includes: a sixth extension line, a seventh extension line, and an eighth extension line, the sixth extension line extending along the second direction, the seventh extension line and the eighth extension line both extending along the first direction, the seventh extension line and the eighth extension line arranged along the second direction and connected between two adjacent sixth extension lines, the sixth extension line and the data line having an orthographic projection overlapped on the base substrate, the seventh extension line and the eighth extension line being located on both sides of the second extension line in the orthographic projection on the base substrate, and the eighth extension line being connected to the first transfer pattern through a via; The sixth extension line, the seventh extension line, and the eighth extension line are all located in a fifth conductive layer. The fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate.

14. The array substrate according to claim 13, wherein: The anode of the light-emitting device is arranged on the side of the fifth conductive layer away from the base substrate. The fifth conductive layer also includes an auxiliary anode extending along the second direction. The auxiliary anode is respectively connected to the anode and the drain of the driving transistor. In the orthographic projection on the base substrate, the auxiliary anode is located between two adjacent sixth extension lines and on the side of the seventh extension line away from the eighth extension line.

15. The array substrate according to claim 13, wherein: The pixel driving circuit further includes: The second capacitor has a first electrode connected to the source of the driving transistor, and a second electrode located in the fourth conductive layer and connected to the seventh extension line through a via hole.

16. The array substrate according to claim 9, wherein: The array substrate further includes: A second power signal line is located in the first conductive layer and includes an eighth line segment extending along the first direction; In an orthographic projection on the base substrate, the third extension line is located within the region of the eighth line segment, and the third extension line is centered relative to the eighth line segment in the second direction.

17. The array substrate according to claim 16, wherein: The pixel driving circuit further includes: a third transistor, a gate connected to the first control signal line, a source connected to the drain of the driving transistor, and a drain connected to the second power signal line; The first control signal line is located in the third conductive layer, the second conductive layer further includes a third transfer pattern, the first control signal line is connected to the third transfer pattern through a third via, and the third transfer pattern is connected to the gate of the third transistor through a fifth via; The orthographic projection of the third via hole on the base substrate is located within the orthographic projection of the channel region of the third transistor on the base substrate, and the orthographic projection of the fifth via hole and the channel region of the third transistor on the base substrate do not overlap.

18. The array substrate according to claim 17, wherein: In the orthographic projection on the substrate, the first control signal line is located on a side of the third extension line close to the third transistor, the first control signal line does not overlap with the third extension line, and overlaps with the eighth line segment.

19. The array substrate according to claim 17, wherein: The channel region of the driving transistor is located in the semiconductor layer, and the semiconductor layer further includes: a first semiconductor pattern extending along the second direction and overlapping with the orthographic projection of the data line on the base substrate; The second power signal line further includes a ninth line segment and a tenth line segment, wherein the ninth line segment and the tenth line segment are both located on a side of the eighth line segment close to the third transistor and are respectively connected to the eighth line segment; The first semiconductor pattern is connected to the ninth line segment through a via hole, and the tenth line segment is connected to the drain of the third transistor through a via hole.

20. The array substrate according to claim 18, wherein: The first control signal line includes an eleventh line segment and a twelfth line segment connected to each other, the eleventh line segment extends along a first direction, the twelfth line segment is located on a side of the eleventh line segment close to the third transistor, and the twelfth line segment is connected to the gate of the third transistor through a via; The eleventh line segment is located on a side of the third transistor away from the driving transistor, and the orthographic projection of the eleventh line segment and the third transistor on the substrate does not overlap.

21. The array substrate according to claim 9, wherein: The first extension line is located between two adjacent driving transistors, and a second transfer pattern is also arranged between the first extension line and the driving transistor. Different second transfer patterns are arranged at intervals from each other and correspond to different sub-pixels. The second transfer pattern is located in the first conductive layer, and the first part of the second transfer pattern is connected to the first extension line through a via.

22. The array substrate according to claim 21, wherein: The channel region of the driving transistor is located in the semiconductor layer, and the semiconductor layer further comprises: The second semiconductor pattern extends along the second direction and is located between the first extension line and the driving transistor. Different second semiconductor patterns are spaced apart and correspond to different sub-pixels. The second semiconductor pattern is connected to the second portion of the second switching pattern through a via.

23. The array substrate according to claim 1, wherein: The pixel driving circuit further includes: a driving transistor, whose source is connected to the drain of the second transistor and whose drain is connected to the anode of the light-emitting device; and a first capacitor, wherein a first plate is connected to the source of the driving transistor, and a second plate is connected to the gate of the driving transistor through a fourth via hole; In which, the drain of the first transistor is connected to the gate of the driving transistor through a second transfer line, the second transfer line is arranged in the same layer as the gate line and both are located in the first conductive layer, the first plate of the first capacitor is located in the second conductive layer, the first plate of the first capacitor overlaps with the orthographic projection of the driving transistor on the substrate, and the first plate of the first capacitor does not overlap with the orthographic projection of the second transfer line, the first transistor, and the channel region of the second transistor on the substrate.

24. The array substrate according to claim 23, wherein: The second electrode plate of the first capacitor is located in the third conductive layer. The first electrode plate of the first capacitor includes a first capacitor pattern and a second capacitor pattern arranged along the second direction. The width of the first capacitor pattern along the first direction is greater than the width of the second capacitor pattern along the first direction. The second capacitor pattern is located on the side of the second capacitor pattern close to the second adapter line. The first capacitor pattern and the second capacitor pattern are spliced ​​together to form a gap, and the gap is used to avoid the fourth via.

25. The array substrate according to claim 1, wherein: The pixel driving circuit further includes: a driving transistor and a third transistor; Wherein, the gate of the second transistor is connected to the second control signal line, the source is connected to the first power signal line, and the drain is connected to the source of the driving transistor; The driving transistor has a gate connected to the drain of the first transistor, a source connected to the drain of the second transistor, and a drain connected to the anode of the light emitting device; and The third transistor has a gate connected to the first control signal line, a source connected to the drain of the driving transistor, and a drain connected to the second power signal line; In the orthographic projection on the substrate, the first control signal line and the second control signal line are respectively located on opposite sides of the driving transistor, the gate line is located on the side of the second control signal line away from the driving transistor, and the second power signal line is located on the side of the first control signal line away from the driving transistor.

26. The array substrate according to claim 25, wherein: The gate line overlaps with an orthographic projection of the first transistor on the substrate, and the gate line does not overlap with an orthographic projection of the second transistor on the substrate; The second control signal line overlaps with the orthographic projections of the first transistor and the second transistor on the substrate.

27. A display device comprising: The array substrate according to any one of claims 1 to 26; as well as The driving circuit is connected to the array substrate and is used to provide a driving signal to the array substrate.

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