Embedded resistor structure and preparation method and application thereof

Abstract

The invention discloses an embedded resistor structure and a preparation method and application thereof. The structure comprises an upper electrode (1), an upper embedded resistor layer (2), a lower embedded resistor layer (4), a lower electrode (3) and an insulating layer (5) between the upper embedded resistor layer (2) and the lower embedded resistor layer (4). The resistive layer is deposited on the surface of the electrode, the embedded technology and the electrode connection mode are combined, physical quantities such as mechanical stress, strain and temperature change can be sensed in real time, the specific position can be recognized, and the sensor has the advantages of being high in sensitivity and stability and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of sensors, in particular to a buried resistance structure and a preparation method and application thereof. BACKGROUND

[0002] With the rapid development of intelligent devices and flexible electronic technology, the demand for high-performance sensors is increasing. Especially in the fields of mechanical monitoring and temperature sensing, high-sensitivity, high-stability and integrated sensors are crucial for improving the sensing ability and interaction performance of devices.

[0003] However, traditional sensors generally have problems such as large size and poor environmental adaptability, which are difficult to meet the requirements of modern intelligent devices for miniaturization, integration and multifunctionalization. Buried resistance technology has great potential in the fields of monitoring and sensing due to its compact structure, excellent electrical and thermal performance, etc. Most current pressure and temperature sensors operate independently, and combined use often leads to increased device size and weight, affecting the convenience and applicability of the system.

[0004] Therefore, there is an urgent need for a new buried resistance-based structure to realize the miniaturization, integration and multifunctional sensing of intelligent devices, and to improve their application performance and scope. SUMMARY

[0005] The embodiments of the present application provide a buried resistance structure and a preparation method and application thereof. Through integrated design of electrodes and combined with buried process, high-sensitivity, high-stability integrated monitoring of mechanical stress, strain and temperature changes is realized.

[0006] In order to achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions:

[0007] A buried resistance structure includes an upper electrode 1 for circuit design; an upper buried resistance layer 2 disposed on the lower surface of the upper electrode 1; a lower electrode 3 for circuit design; a lower buried resistance layer 4 disposed on the upper surface of the lower electrode 3; and an insulating layer 5 disposed between the upper buried resistance layer 2 and the lower buried resistance layer 4 for isolating the upper and lower buried resistance layers 4.

[0008] Preferably, the surface roughness Rz of the upper electrode 1 is 0.5-3.5 μm; and the surface roughness Rz of the lower electrode 3 is less than 0.1 μm. The surface roughness Rz of the upper electrode 1 can be 0.8 μm, 1.0 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm or an interval consisting of any two values less than 3.5 μm. The surface roughness Rz of the copper foil of the lower electrode 3 can be 0.01 μm, 0.05 μm, 0.08 μm or an interval consisting of any two values less than 0.1 μm.

[0009] Preferably, the upper electrode 1 layer material and the lower electrode 3 layer material are respectively selected from at least one of aluminum, titanium, zinc, iron, nickel, chromium, cobalt, copper, silver, gold, and a circuit can be formed by etching.

[0010] Preferably, the upper buried resistance layer 2 is a transition metal oxide, wherein the transition metal is in a spinel structure and can change its resistance value in response to temperature changes. Specifically, the transition metal oxide can be NTC or PTC. The upper buried resistance layer 2 is deposited on the lower surface of the upper electrode 1 and has a square resistance of 5kΩ-25kΩ, which is used for temperature detection. Optionally, the square resistance can be 5kΩ, 8kΩ, 10kΩ, 15kΩ, 20kΩ, 25kΩ, or an interval formed by any two values less than 25kΩ. The thickness of the upper buried resistance layer 2 is 200nm-500nm, specifically, it can be 500nm, 450nm, 400nm, 380nm, 350nm, 320nm, 280nm, 240nm, 200nm, or an interval formed by any two values less than 500nm.

[0011] The lower buried resistance layer 4 is a thin film resistance, wherein the thin film resistance is selected from at least two of aluminum, titanium, zinc, iron, nickel, chromium, cobalt, and copper. Preferably, the lower buried resistance layer 4 is a NiCr alloy thin film deposited on the upper surface of the lower electrode 3 and has a square resistance of 25Ω-50Ω, which forms a loop with the upper buried resistance layer 2 and is used for monitoring stress changes. Optionally, the square resistance can be 25Ω, 28Ω, 30Ω, 33Ω, 35Ω, 38Ω, 42Ω, 45Ω, 50Ω, or an interval formed by any two values less than 50Ω. The thickness of the lower buried resistance layer 4 is 50nm-200nm, specifically, it can be 200nm, 180nm, 160nm, 140nm, 120nm, 100nm, 80nm, 70nm, 50nm, or an interval formed by any two values less than 200nm.

[0012] The insulating layer 5 is selected from at least one of epoxy resin, polyester resin, polyurethane resin, acrylic resin, alkyd resin, polyamide resin, polyimide resin, and polyether ether ketone resin. Preferably, the insulating layer 5 is a polyimide film. The insulating layer 5 is uniformly distributed, so that the upper and lower buried resistance layers 4 change in contact resistance when subjected to pressure.

[0013] The embodiment of the present application also provides a preparation method of the buried resistance structure, which is used for preparing the upper buried resistance layer 2 and the lower buried resistance layer 4 of the buried resistance structure.

[0014] Step 1: Perform ion source treatment on the surface of the upper electrode 1 to remove surface contaminants and improve adhesion;

[0015] Step 2: depositing transition metal oxide on the surface of the upper electrode 1 to form a uniform upper buried resistor layer 2;

[0016] Step 3: performing ion source treatment on the surface of the lower electrode 3 to remove surface contaminants and improve adhesion;

[0017] Step 4: depositing transition metal on the surface of the lower electrode 3 to form a uniform lower buried resistor layer 4.

[0018] Preferably, nickel (Ni), cobalt (Co) and iron (Fe) transition metals are used as target materials for sputtering in an argon and oxygen mixed atmosphere, with a sputtering power of 2-6 kW, a sputtering time of 30-60 min, and a sputtering gas pressure of 0.2-0.5 Pa.

[0019] Preferably, nickel (Ni) and chromium (Cr) transition metals are used as materials for sputtering in an argon atmosphere, with a sputtering power of 5-8 kW, a sputtering time of 30-60 min, and a sputtering gas pressure of 0.2-0.5 Pa.

[0020] The embodiment of the present application also provides an application of the buried resistor structure in an electronic device, wherein the electronic device contains the buried resistor structure.

[0021] Preferably, the buried resistor structure preparation method in the embodiment of the present application comprises the following steps:

[0022] Step 1: using an electrolytic method to prepare copper foil as electrode material, controlling temperature, copper liquid concentration, current density and different types of additives to obtain copper foil with different roughness, with a thickness of 10-25 μm and good conductivity;

[0023] Step 2: using Co-Ni-Fe as target material, sputtering in an argon and oxygen mixed atmosphere, with a sputtering power of 2-6 kW, a sputtering time of 30-60 min, and a sputtering gas pressure of 0.2-0.5 Pa, to prepare an upper buried resistor layer 2 with a thickness of 200-500 nm on the surface of copper foil with roughness of 0.5-3.5 μm, for sensing temperature change;

[0024] Step 3: using Ni and Cr as target materials, sputtering in an argon atmosphere, with a sputtering power of 5-8 kW, a sputtering time of 30-60 min, and a sputtering gas pressure of 0.2-0.5 Pa, to prepare a lower buried resistor layer 4 with a thickness of 50-200 nm on the surface of copper foil with roughness less than 0.1 μm, for forming a loop to sense pressure change;

[0025] Step 4: coating an insulating layer 5 on the surface of the upper buried resistor layer 2, and then pressing the lower buried resistor layer 4. The insulating layer 5 makes the upper and lower buried resistor layers 4 open when not subjected to pressure, and form a loop when subjected to pressure, and also has a certain supporting effect.

[0026] Step 5: curing the composite structure synthesized above at a certain temperature to ensure stable bonding force between the multilayer structure;

[0027] Step 6: designing patterns and lines on the upper electrode 1 layer, buried resistance layer and lower electrode 3 layer, buried resistance layer through photolithography and mask process to form a plurality of array micro area units for identifying the positions of stress and temperature sensing.

[0028] Working principle of the embedded resistance structure in the embodiment of the present application:

[0029] 1. When the base material senses temperature change, the embedded upper buried resistance layer 2 will change in resistance. By measuring the change in voltage, digital-to-analog conversion is carried out, and the signal is transmitted to the data processing system for analysis, so that the information of temperature change can be obtained in real time.

[0030] 2. When the surface of the structure is subjected to stress or strain, as the pressure gradually increases, the distance between the upper buried resistance layer 2 and the lower buried resistance layer 4 gradually becomes smaller until they contact each other to form a circuit connection. By measuring the change in voltage, the electrical signal is converted and then transmitted to the data processing system for analysis, so that the information of stress can be obtained in real time.

[0031] 3. By coordinate of the array micro area units of the upper buried resistance layer 2 and the lower buried resistance layer 4, the stress and temperature change area can be accurately identified, and higher precision control can be achieved.

[0032] Compared with the prior art, the embodiment of the present application has the following beneficial effects: through the laminated structure design of the upper electrode 1 layer, the upper buried resistance layer 2, the insulating layer 5, the lower buried resistance layer 4 and the lower electrode 3 layer, the integration of pressure and temperature sensing is realized, the volume and mass of the device are reduced, and the design of the embedded resistance layer improves the integration of the device. The micro area unit design with coordinate arrangement enables the buried resistance layer to have spatial resolution capability and accurately locate the specific positions of stress and temperature change. The insulating layer 5 not only realizes the electrical isolation of the upper and lower buried resistance layers, but also provides overall structural support to keep the device stable. In summary, the structure of the embodiment of the present application is small in size, easy to integrate, high in sensitivity and good in stability. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 It is a schematic diagram of the embedded resistance structure in the embodiment of the present application;

[0034] Figure 2 It is a schematic diagram of the temperature sensing structure of the embedded resistance in the embodiment of the present application;

[0035] Figure 3 It is a schematic diagram of the pressure sensing structure of the embedded resistance in the embodiment of the present application;

[0036] Figure 4 This is a schematic diagram illustrating the pressure sensing principle of the embedded resistor in an embodiment of the present invention.

[0037] Among them, 1. upper electrode; 2. upper buried resist layer; 3. lower electrode; 4. lower buried resist layer; 5. insulating layer. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention are described clearly and completely below in conjunction with specific embodiments. It should be understood that, for better illustration of these embodiments, some components in the accompanying drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. The described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the protection scope of this invention.

[0039] Example 1

[0040] like Figure 1 As shown, a schematic diagram of an embedded resistor structure includes an upper electrode 1, an upper embedded resistor layer 2, a lower electrode 3, and a lower embedded resistor layer 4. The upper embedded resistor layer 2 and the lower embedded resistor layer 4 are connected by an insulating layer 5.

[0041] The electrode layer is a copper foil prepared by electrolysis with a thickness of 18 μm. The surface roughness Rz of the lower surface of the upper electrode 1 is 3 μm, and the surface roughness Rz of the upper surface of the lower electrode 3 is 0.05 μm.

[0042] As a preferred embodiment of the present invention, the rough surface of the copper foil is subjected to ion source treatment under an argon atmosphere to remove surface impurities and increase surface activity.

[0043] As a preferred embodiment of the present invention, a uniform CoNiFeO layer is uniformly deposited on a copper foil surface with a roughness Rz of 3 μm under a mixed atmosphere of argon (95 vol%) and oxygen (5 vol%), a sputtering pressure of 0.3 Pa, and a sputtering power of 6 kW. x Thin film material with a thickness of 150 nm.

[0044] As a preferred embodiment of the present invention, CoNiFeO x Thin-film materials exhibit the characteristics of thermistors with a negative temperature coefficient and a sheet resistance of 15kΩ. They possess high sensitivity and high stability of resistance-temperature characteristics and are used to sense temperature changes.

[0045] As a preferred scheme of the embodiment of the present application, a uniform NiCr alloy thin film material is deposited on the surface of the copper foil with roughness of 0.05 μm under the atmosphere of argon, sputtering pressure of 0.3 Pa and sputtering power of 6.5 kW, and the thickness of the thin film material is 70 nm.

[0046] As a preferred scheme of the embodiment of the present application, the NiCr alloy thin film material has high sensitivity and high stability of resistance characteristics, and the square resistance is 40 Ω. The material has high sensitivity and high stability of resistance characteristics, and is used to form a loop to perceive pressure change.

[0047] As a preferred scheme of the embodiment of the present application, the upper buried resistance layer 2 is coated with polyimide, and after filling the surface roughness, a 2 μm adhesive layer is formed, and then the lower buried resistance layer 4 is pressed.

[0048] As a preferred scheme of the embodiment of the present application, the synthesized composite structure is cured at 160 °C for 2 h, and the adhesive layer is used as the insulating layer 5. The upper buried resistance layer 2 and the lower buried resistance layer 4 are open circuits when not subjected to pressure, and form a loop when subjected to pressure, and also have a certain supporting effect.

[0049] As a preferred scheme of the embodiment of the present application, the upper electrode 1, the upper buried resistance layer 2, the lower electrode 3 and the lower buried resistance layer 4 are designed to form a 4x3 array structure by photolithography and mask process, and then etched under acidic conditions to obtain the structure as shown in Figure 2 and Figure 3 .

[0050] As a preferred scheme of the embodiment of the present application, Figure 2 Each unit in the structure can realize real-time monitoring of temperature by analyzing data signals through external circuits.

[0051] As a preferred scheme of the embodiment of the present application, as shown in Figure 4 When the surface of the structure is subjected to stress F, the upper buried resistance layer 2 and the lower buried resistance layer 4 come into contact, a circuit is formed, and is converted into an electrical signal which is transmitted to a data processing system for analysis, and information of the stress can be obtained in real time.

[0052] The above embodiments are merely examples for clearly illustrating the present application, and are not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the embodiments can be modified, or some technical features can be replaced by equivalents. These modifications or replacements all belong to the protection scope of the present application, as long as they do not deviate from the spirit and essence of the technical solutions of the present application, and should be covered by the claims of the present application.

Claims

1. A buried resistor structure, characterized by, The buried resistance structure comprises an upper electrode (1) for line design; an upper buried resistance layer (2) arranged on the lower surface of the upper electrode (1); a lower electrode (3) for line design; a lower buried resistance layer (4) arranged on the upper surface of the lower electrode (3); and an insulation layer (5) arranged between the upper buried resistance layer (2) and the lower buried resistance layer (4) for isolating the upper buried resistance layer (2) and the lower buried resistance layer (4).

2. The embedded resistor structure of claim 1, wherein, The upper electrode (1) and the lower electrode (3) are at least one of aluminum, titanium, zinc, iron, nickel, chromium, cobalt, copper, silver, and gold.

3. The embedded resistor structure of claim 1, wherein, The surface roughness Rz of the upper electrode (1) is 0.5-3.5 μm, and the surface roughness Rz of the lower electrode (3) is less than 0.1 μm.

4. The embedded resistor structure of claim 1, wherein, The upper buried resistance layer (2) is a transition metal oxide with a thickness of 200-500 nm.

5. The embedded resistor structure of claim 1, wherein, The lower buried resistance layer (4) is a thin film resistance, and the thickness of the lower buried resistance layer (4) is 50-200 nm.

6. The embedded resistor structure of claim 1, wherein, The material of the insulation layer (5) is at least one of epoxy resin, polyester resin, polyurethane resin, acrylic resin, alkyd resin, polyamide resin, polyimide resin, and polyether ether ketone resin.

7. A method for manufacturing a buried resistor structure, characterized by, The upper buried resistance layer (2) and the lower buried resistance layer (4) for preparing the buried resistance structure as claimed in any one of claims 1-6 comprise the following steps: Step 1: ion source treatment is performed on the surface of the upper electrode (1) to remove surface contaminants and improve adhesion; Step 2: transition metal oxide is deposited on the surface of the upper electrode (1) to form a uniform upper buried resistance layer (2); Step 3: ion source treatment is performed on the surface of the lower electrode (3) to remove surface contaminants and improve adhesion; Step 4: transition metal is deposited on the surface of the lower electrode (3) to form a uniform lower buried resistance layer (4).

8. The method of claim 7, wherein the buried resistor structure is formed by a process comprising: Nickel (Ni), cobalt (Co), and iron (Fe) transition metals are used as target materials for sputtering in an argon-oxygen mixed atmosphere, with a sputtering power of 2-6 kW, a sputtering time of 30-60 min, and a sputtering pressure of 0.2-0.5 Pa.

9. The method for fabricating an embedded resistor structure according to claim 7, characterized in that, Nickel (Ni) and chromium (Cr) transition metals are used as materials for sputtering in an argon atmosphere, with a sputtering power of 5-8 kW, a sputtering time of 30-60 min, and a sputtering pressure of 0.2-0.5 Pa.

10. Use of a buried resistor structure in an electronic device, characterized in that, The electronic device contains the buried resistance structure as claimed in any one of claims 1-6.

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