Power device state monitoring method and device based on FPGA

Abstract

The invention provides a power device state monitoring method and device based on an FPGA, and belongs to the field of power electronics. According to the method, the parallel processing capability of the FPGA is utilized to realize real-time monitoring of a plurality of state quantities, including actual saturation voltage drop, junction temperature and collector current, of the power device, the state quantities are converted into corresponding digital signals, and then based on pre-stored electrical characteristic information of the power device, the converted digital information is judged, so that the state quantities of the power device are monitored in real time. And obtaining a degradation state monitoring result of the packaging-level bonding wire of the power device, then displaying the state monitoring result, and carrying out early warning in time. According to the method, the degradation state of the packaging-level bonding wire of the power device can be accurately and rapidly evaluated based on the real-time state quantity of the power device, the monitoring requirement of the state of the power device is met, the monitoring precision and the response speed are improved, and the stability and reliability of a power electronic system are enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power electronics, and in particular to a power device state monitoring method and device based on FPGA. BACKGROUND

[0002] In a power electronic system, stable operation of a power device is crucial to the reliability of the entire system, and the degradation state of a package-level bonding wire greatly affects the electrical performance, heat dissipation performance and mechanical stability of the power device. Therefore, in order to ensure stable operation of the system, it is necessary to monitor the degradation state of the package-level bonding wire of the power device in a timely manner.

[0003] Traditional state monitoring methods for power device package-level bonding wires usually rely on analog circuits or microprocessors, and these methods have problems such as slow response speed, low precision and poor flexibility, and cannot achieve fast, accurate and flexible monitoring of the state of the power device. SUMMARY

[0004] Embodiments of the present application provide a power device state monitoring method and device based on FPGA to solve the problem that the state of the power device cannot be monitored quickly, accurately and flexibly.

[0005] In a first aspect, embodiments of the present application provide a power device state monitoring method based on FPGA, which is applied to an FPGA, and the method comprises:

[0006] An analog signal of the power device in a working state is collected, and the analog signal is converted into a digital signal; wherein the analog signal includes an actual saturation voltage drop signal, a collector current signal and a junction temperature signal of the power device;

[0007] A state monitoring result of the power device is obtained according to pre-set electrical characteristic information of the power device and the digital signal; wherein the state monitoring result is used to represent the degradation state of the package-level bonding wire of the power device;

[0008] The state monitoring result is displayed, and a warning is given when the state monitoring result meets a failure warning condition.

[0009] In a possible implementation manner, before the state monitoring result of the power device is obtained according to the pre-set electrical characteristic information of the power device and the digital signal, the method further comprises:

[0010] An output characteristic curve cluster of the power device is obtained; wherein the output characteristic curve cluster includes output characteristic curves of the power device at different junction temperatures, and the output characteristic curve is used to represent the relationship between the collector-emitter saturation voltage drop and the collector current of the power device;

[0011] obtain electrical characteristic information of the power device based on the output characteristic curve cluster; wherein the electrical characteristic information is used to represent a relationship among a theoretical value of a saturation voltage drop, a junction temperature and a collector current corresponding to the power device.

[0012] In a possible implementation, the obtaining the electrical characteristic information of the power device based on the output characteristic curve cluster comprises:

[0013] obtain a preset collector current value, and obtain a curve parameter of each output characteristic curve at the preset collector current value; wherein the curve parameter comprises a tangent slope and a tangent intercept of the output characteristic curve at the preset collector current value;

[0014] obtain a first relationship between the tangent slope and the junction temperature of the output characteristic curve corresponding to the preset collector current value according to the curve parameter of each output characteristic curve at the preset collector current value and the junction temperature corresponding to the output characteristic curve, and obtain a second relationship between the tangent intercept and the junction temperature of the output characteristic curve corresponding to the preset collector current value;

[0015] obtain an update number of the preset collector current value, if the update number does not reach a preset update number, update the preset collector current value, and repeat the step of obtaining the preset collector current value and obtaining the curve parameter of each output characteristic curve at the preset collector current value until the preset update number is reached, and the first relationship and the second relationship corresponding to each preset collector current value are obtained;

[0016] obtain a first function expression between the collector current and the first relationship according to the first relationship corresponding to each preset collector current value, and obtain a second function expression between the collector current and the second relationship according to the second relationship corresponding to each preset collector current value;

[0017] obtain the electrical characteristic information of the power device according to the first function expression and the second function expression.

[0018] In a possible implementation, the obtaining the electrical characteristic information of the power device according to the first function expression and the second function expression comprises:

[0019] obtain the electrical characteristic information of the power device according to V CE (sat)=f(K,T j ,I C )·I C +f(B,T j ,I C ), wherein V CE(sat) is a theoretical value of a saturation voltage drop of the power device, f(K, T j C ) is the first function expression, f(B, T j C ) is the second function expression, I C is a collector current, T j is a junction temperature, K is a tangent slope, and B is a tangent intercept.

[0020] In a possible implementation, the method further includes:

[0021] obtaining a theoretical value of a saturation voltage drop corresponding to the collector current signal and the junction temperature signal based on the electrical characteristic information;

[0022] obtaining the state monitoring result of the power device according to the digital signal corresponding to the theoretical value of the saturation voltage drop and the actual saturation voltage drop signal.

[0023] In a possible implementation, the method further includes:

[0024] comparing the digital signal corresponding to the theoretical value of the saturation voltage drop and the actual saturation voltage drop signal to obtain a voltage increment corresponding to the power device; the voltage increment is a voltage increment caused by failure of a package-level bonding wire;

[0025] obtaining the state monitoring result of the power device according to the voltage increment and a pre-stored voltage increment threshold condition; the voltage increment threshold condition is used to indicate a corresponding relationship between a degradation state of the package-level bonding wire of the power device and the voltage increment.

[0026] In a possible implementation, the method further includes:

[0027] obtaining a resistance value of a thermistor built in the power device;

[0028] determining the junction temperature of the power device according to the resistance value.

[0029] In a possible implementation, the method further includes:

[0030] applying a driving voltage to a gate of the power device to make the power device fully conduct;

[0031] ​​A preset current is applied on the collector of the fully conducting power device to collect the actual saturation voltage drop signal.

[0032] In a second aspect, an embodiment of the present application provides a power device state monitoring device based on FPGA, characterized in that the device is based on FPGA, and the device comprises:

[0033] A signal processing module is configured to collect an analog signal when the power device is in a working state, and convert the analog signal into a digital signal; wherein the analog signal comprises an actual saturation voltage drop signal, a collector current signal and a junction temperature signal of the power device.

[0034] An FPGA processing module is configured to obtain a state monitoring result of the power device according to a preset electrical characteristic information of the power device and the digital signal; wherein the state monitoring result is used to represent a degradation state of a package-level bonding wire of the power device.

[0035] A display module is configured to display the state monitoring result, and give an early warning when the state monitoring result meets a failure early warning condition.

[0036] In a third aspect, an embodiment of the present application provides an FPGA, comprising at least one processor and a communication interface, wherein the communication interface provides information input and / or output for the at least one processor; further comprising at least one memory, wherein the memory is used to store computer instructions, and the at least one processor is used to call and run the computer instructions to execute the power device state monitoring method based on FPGA in the first aspect.

[0037] The FPGA-based power device state monitoring method and device provided by the embodiment of the present application can realize real-time monitoring of multiple state quantities of the power device, including actual saturation voltage drop, junction temperature and collector current, by using the parallel processing capability of FPGA, and convert the state quantities into corresponding digital signals, and then determine the converted digital information based on the pre-stored electrical characteristic information of the power device, to obtain a degradation state monitoring result of the package-level bonding wire of the power device, and display the state monitoring result and give an early warning in time. The method can accurately and quickly evaluate the degradation state of the package-level bonding wire of the power device based on real-time state quantities of the power device, meet the monitoring requirement of the power device state, improve the monitoring precision and response speed, and enhance the stability and reliability of the power electronic system. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0039] Figure 1 is an implementation flowchart of the power device state monitoring method based on FPGA provided by the embodiment of the present application;

[0040] Figure 2 is an implementation flowchart of another power device state monitoring method based on FPGA provided by the embodiment of the present application;

[0041] Figure 3 is a schematic diagram of the collector-emitter saturation voltage sampling circuit provided by the embodiment of the present application;

[0042] Figure 4 is a structural schematic diagram of the power device state monitoring device based on FPGA provided by the embodiment of the present application;

[0043] Figure 5 is a structural schematic diagram of the FPGA provided by the embodiment of the present application. DETAILED DESCRIPTION

[0044] In the following description, specific details are set forth in order to provide a thorough understanding of the embodiments of the present application, for purposes of explanation rather than limitation. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail. SUMMARY

[0046] In power electronic systems, the stable operation of power devices is crucial to the reliability of the entire system, and the degradation state of the package-level bonding wires can greatly affect the electrical performance, heat dissipation performance and mechanical stability of the power devices. Therefore, in order to ensure the stable operation of the system, it is necessary to monitor the degradation state of the package-level bonding wires of the power devices in a timely manner.

[0047] The inventor has found through research that the traditional state monitoring method for the package-level bonding wires of the power devices usually relies on analog circuits or microprocessors, and these methods have problems such as slow response speed, low precision and poor flexibility, and cannot achieve fast, accurate and flexible monitoring of the state of the power devices.

[0048] For the purpose of improving the accuracy and response speed of power device state monitoring, in the embodiment of the present application, the parallel processing capability of FPGA is utilized to realize real-time monitoring of multiple state quantities of the power device, including the actual saturation voltage drop, junction temperature and collector current, and convert them into corresponding digital signals, and then based on the pre-stored electrical characteristic information of the power device, the converted digital information is judged to obtain the deterioration state monitoring result of the power device package level bonding wire, and the state monitoring result is displayed and timely warning is given. This method can accurately and quickly evaluate the deterioration state of the power device package level bonding wire based on the real-time state quantities of the power device, meet the monitoring demand of the power device state, improve the monitoring precision and response speed, and enhance the stability and reliability of the power electronic system.

[0049] To make the objectives, technical solutions and advantages of the present application clearer, specific embodiments will be described below with reference to the accompanying drawings.

[0050] Figure 1 The implementation flowchart of the power device state monitoring method based on FPGA provided by the embodiment of the present application is as follows:

[0051] Step 101, collect the analog signals of the power device in the working state, and convert the analog signals into digital signals; wherein the analog signals include the actual saturation voltage drop signal, collector current signal and junction temperature signal of the power device.

[0052] Exemplarily, the three groups of temperature, voltage and current acquisition units of the power device are utilized to collect the analog signals of the power device in the working state, including the actual saturation voltage drop signal, collector current signal and junction temperature signal of the power device.

[0053] And after the analog signals are collected, they are converted into digital signals respectively.

[0054] In the embodiment, the FPGA (field-programmable gate array) is a semiconductor device.

[0055] The power device in the embodiment can be a power electronic transformer power device, which can be an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a silicon controlled rectifier (SCR), a bipolar junction transistor (BJT), or the like.

[0056] In one example, the embodiment can use an analog-to-digital converter (ADC chip) such as an AD9280 chip connected to the FPGA to convert analog signals to digital signals, with a maximum conversion rate of 32 mega samples per second (MSPS).

[0057] In step 102, a state monitoring result of the power device is obtained according to the preset electrical characteristic information of the power device and the digital signal, wherein the state monitoring result is used to represent the degradation state of the package-level bonding wire of the power device.

[0058] In an example, the embodiment compares the converted digital signal according to the pre-stored electrical characteristic information of the power device to analyze the state monitoring result of the degradation state of the package-level bonding wire of the power device.

[0059] The package-level bonding wire is a key element for connecting the chip and the external circuit in the power device package, and is usually a thin wire made of metal material, such as gold wire, aluminum wire, etc., with a diameter of several microns to tens of microns. In the power device packaging process, one end of the bonding wire is connected to the metal pad of the chip through ultrasonic bonding, thermal compression bonding, or the like, and the other end is connected to the corresponding position of the pin or substrate of the package, thereby providing the chip with a power supply, signal input / output, and the like.

[0060] In one example, the state monitoring result can be a failure rate, an aging rate, or the like, to show the degradation degree and aging degree of the package-level bonding wire of the power device.

[0061] In step 103, the state monitoring result is displayed, and a warning is given when the state monitoring result meets the failure warning condition.

[0062] In an example, after determining the state monitoring result, the embodiment displays the working state and the degradation state of the power electronic transformer power device in real time, and issues an alarm signal when the failure rate exceeds the preset failure rate threshold in an abnormal condition.

[0063] In summary, in the embodiment of the present application, the parallel processing capability of the FPGA is utilized to realize real-time monitoring of multiple state quantities of the power device, including the actual saturation voltage drop, the junction temperature and the collector current, and to convert them into corresponding digital signals, and then based on the pre-stored electrical characteristic information of the power device, the converted digital information is judged to obtain the deterioration state monitoring result of the package-level bonding wire of the power device, and the state monitoring result is displayed and timely warning is given. This method can accurately and quickly evaluate the deterioration state of the package-level bonding wire of the power device based on the real-time state quantities of the power device, meet the monitoring demand of the state of the power device, improve the monitoring accuracy and response speed, and enhance the stability and reliability of the power electronic system.

[0064] In this embodiment, the output characteristic curve cluster of the power device is obtained, the electrical characteristic information of the power device is analyzed, including the relationship among the corresponding saturation voltage drop theoretical value, the junction temperature and the collector current of the power device, and is stored in the FPGA. This process realizes accurate analysis of the electrical characteristics of the power device, and improves the response speed and accuracy of subsequent device state evaluation. Then, after obtaining the analog signal of the power device in the working state, the saturation voltage drop theoretical value corresponding to the current power device is obtained based on the pre-stored electrical characteristic information, and is compared with the obtained saturation voltage drop actual value to obtain the voltage increment caused by the failure of the package-level bonding wire, and then based on the corresponding relationship between the deterioration state of the package-level bonding wire of the power device and the voltage increment, the deterioration state of the package-level bonding wire of the power device is obtained. This process is simple and efficient, and further improves the response speed of device state evaluation. Finally, the state monitoring result is displayed and timely warning is given. The failure of the power device can be timely warned, and the stability and reliability of the power electronic system are enhanced. In addition, for different types of power devices, this embodiment only needs to obtain the corresponding output characteristic curve cluster, analyze the corresponding electrical characteristic information, and pre-store, so as to meet the monitoring demand of different power devices.

[0065] Figure 2 Another implementation flowchart of the FPGA-based power device state monitoring method provided by the embodiment of the present application is provided, and the method is applied to the FPGA, and the details are as follows:

[0066] Step 201, collecting the analog signal of the power device in the working state, and converting the analog signal into a digital signal; wherein the analog signal includes the actual saturation voltage drop signal, the collector current signal and the junction temperature signal of the power device.

[0067] In one example, step 201 includes the following steps:

[0068] A drive voltage is applied to the gate of the power device to make the power device fully turn on.

[0069] A preset current is applied to the collector of a fully conducting power device to acquire the actual saturation voltage drop signal.

[0070] In one example, Figure 3 This is a schematic diagram of the collector-emitter saturation voltage drop sampling circuit provided in an embodiment of the present invention. Taking an IGBT as an example, in the IGBT saturated conduction state, this embodiment follows... Figure 3 The sampling circuit shown measures the collector-emitter saturation voltage drop at the positions of VCE(sat)* and its corresponding arrows, and acquires the voltage drop VCE(sat)* between the collector and emitter. (Figure I) C The arrows indicate the direction of the collector current, which is the current flowing from the collector to the emitter.

[0071] For example, when acquiring the actual saturation voltage drop signal, this embodiment applies a specified voltage to the gate of the IGBT module to make the module fully conduct; then, a current of a specific size and pulse width is applied to the collector, and the saturation voltage drop between the collector and emitter is measured. The sampling pulse width for both current and voltage is 300 microseconds (μs).

[0072] Step 202: Obtain the output characteristic curve set of the power device; wherein, the output characteristic curve set includes the output characteristic curves of the power device at different junction temperatures, and the output characteristic curves are used to characterize the relationship between the collector-emitter saturation voltage drop and the collector current of the power device.

[0073] In one feasible implementation, this embodiment obtains the resistance value of the thermistor built into the power device; then determines the junction temperature of the power device based on the resistance value.

[0074] Taking an IGBT as an example, this embodiment exemplifies the use of a negative temperature coefficient thermistor (NTC) to determine the junction temperature of the power device. In an IGBT, the NTC resistance decreases as the temperature increases. Generally, the NTC temperature lies between the junction temperature and the case temperature; this embodiment uses the NTC temperature to estimate the IGBT junction temperature.

[0075] In this embodiment, the thermistor inside the IGBT module is subjected to NTC data acquisition and testing. The junction temperature of the IGBT is monitored in real time, and several sets of collector-emitter saturation voltage drop data of the IGBT are recorded at different junction temperatures to obtain a set of output characteristic curves.

[0076] In one possible implementation, the IGBT used in the embodiment is of FF150R12ME3G type, and the relationship between the NTC resistance and temperature is as follows:

[0077]

[0078] wherein R NTC represents the resistance value of the NTC; R 25 represents the resistance value at a general temperature (298.15 K), and the value is 5 kΩ (kilo-ohm); T2 represents the junction temperature of the IGBT, in Kelvin (K); B 25 / 50 represents a material constant, and the value is 3375 K. Through the expression, the junction temperature of the IGBT can be calculated.

[0079] In step 203, the electrical characteristic information of the power device is obtained based on the output characteristic curve cluster; wherein the electrical characteristic information is used to represent the relationship among the theoretical value of the saturation voltage drop, the junction temperature and the collector current corresponding to the power device.

[0080] In one possible implementation, step 203 includes the following steps:

[0081] First, a preset collector current value is obtained, and the curve parameters of each output characteristic curve in the output characteristic curve cluster at the preset collector current value are obtained; wherein the curve parameters include the tangent slope and the tangent intercept of the output characteristic curve at the preset collector current value.

[0082] wherein the tangent slope K is the inverse of the instantaneous on-resistance R0 of the power device, and the tangent intercept B is the on-voltage drop V CE0 .

[0083] Then, the first relationship between the tangent slope and the junction temperature of the output characteristic curve corresponding to the preset collector current value is obtained according to the curve parameters of each output characteristic curve at the preset collector current value and the junction temperature corresponding to the output characteristic curve, and the second relationship between the tangent intercept and the junction temperature of the output characteristic curve corresponding to the preset collector current value is obtained.

[0084] That is, when the collector current is constant, the relationship between the output characteristic tangent slope K and the junction temperature T j is analyzed to obtain a function relationship f(K, T j ); similarly, when the collector current is constant, the relationship between the output characteristic tangent intercept B and the junction temperature T j is analyzed to obtain a second relationship f(B, T j ).

[0085] The preset collector current value is updated until the preset collector current value is updated for a preset number of times, and the first relationship and the second relationship corresponding to each preset collector current value are obtained.

[0086] According to the first relationship corresponding to each preset collector current value, a first function expression between the collector current and the first relationship is obtained, and according to the second relationship corresponding to each preset collector current value, a second function expression between the collector current and the second relationship is obtained.

[0087] In one example, the collector current I C is updated, and the steps of obtaining the first relationship and the second relationship when the collector current is constant are performed again until the collector current is updated for a preset number of times, and then based on the first relationship and the second relationship obtained each time, the function relationship between the collector current I C and the functions f(K,T j ) and f(B,T j ) is further analyzed, the corresponding coefficients are solved, and the tangent slope K and the tangent intercept B of the output characteristic curve are expressed as a function relationship related to the collector current I C , i.e. in the form of f(K,T j ,I C ) and f(B,T j ,I C ). That is, the first function expression and the second function expression.

[0088] Finally, the electrical characteristic information of the power device is obtained according to the first function expression and the second function expression.

[0089] Since the tangent slope K of the output characteristic curve represents the instantaneous on-resistance of the power device after removing the diode, multiplying the collector current by the function f(K,Tj,IC) can obtain the instantaneous on-voltage drop of the power device after removing the influence of the diode, and therefore the saturation voltage drop of the power device can be expressed as:

[0090] V CE (sat)=f(K,T j ,I C )·I C +f(B,T j ,I C )

[0091] In one example, the embodiment obtains V CE (sat)=f(K,T j ,IC )·I C +f(B,T j ,I C ), to obtain the electrical characteristic information of the power device; wherein, V CE (sat) is a theoretical value of the saturation voltage drop of the power device, f(K,T j ,I C ) is a first function expression, f(B,T j ,I C ) is a second function expression, I C is the collector current, T j is the junction temperature, K is the tangent slope, and B is the tangent intercept.

[0092] In step 204, based on the electrical characteristic information, a theoretical value of the saturation voltage drop corresponding to the collector current signal and the junction temperature signal is obtained.

[0093] Exemplarily, the converted digital signal corresponding to the collector current signal of the power device and the digital information corresponding to the junction temperature signal are substituted into V CE (sat)=f(K,T j ,I C )·I C +f(B,T j ,I C ), to obtain the theoretical value of the saturation voltage drop.

[0094] In step 205, according to the theoretical value of the saturation voltage drop and the digital signal corresponding to the actual saturation voltage drop signal, a state monitoring result of the power device is obtained; wherein, the state monitoring result is used to represent the degradation state of the package-level bonding wire of the power device.

[0095] In an available implementation, step 205 includes the following steps:

[0096] The digital signal corresponding to the theoretical value of the saturation voltage drop and the actual saturation voltage drop signal is compared to obtain a voltage increment corresponding to the power device; wherein, the voltage increment is the voltage increment caused by the failure of the package-level bonding wire.

[0097] According to the voltage increment and the pre-stored voltage increment threshold condition, the state monitoring result of the power device is obtained; wherein, the voltage increment threshold condition is used to indicate the corresponding relationship between the degradation state of the package-level bonding wire of the power device and the voltage increment.

[0098] Exemplarily, the difference between the digital signal corresponding to the actual saturation voltage drop signal and the theoretical value of the saturation voltage drop is calculated to obtain the voltage increment after temperature and current correction, which represents the voltage increment caused by the failure of the package-level bonding wire of the power device.

[0099] In one example, the embodiment calculates the voltage increment ΔV according to ΔV = V (sat) - V (sat) CE CE CE * CE V (sat) * is the actual measured value of the power device collector-emitter saturation voltage drop collected by the FPGA, V (sat) is the theoretical value of the saturation voltage drop, and ΔV is the voltage increment. CE CE

[0100] In another possible implementation, the voltage increment percentage of the voltage increment relative to the theoretical value of the saturation voltage drop can also be obtained based on the calculated voltage increment, and the state monitoring result of the power device can be determined according to the corresponding relationship between the degradation state of the power device package level bonding wire and the voltage increment percentage.

[0101] For example, according to the preset, if the percentage is less than 1%, the power device is in a healthy state, between 1% and 5% is in a sub-healthy state, and more than 5% indicates that the failure threshold has been reached.

[0102] Step 206, display the state monitoring result and give a warning when the state monitoring result meets the failure warning condition.

[0103] For example, if the failure warning condition indicates that a warning should be given when the device state is in a sub-healthy state, a failure warning can be given when the power device state is in a sub-healthy state, i.e., before the failure threshold, to remind timely replacement of the power device to ensure reliable operation of the system.

[0104] ​​​​​​To sum up, by means of the output characteristic curve cluster of the power device acquired, the electrical characteristic information of the power device is analyzed, including the relationship among the theoretical value of the saturation voltage drop, the junction temperature and the collector current corresponding to the power device, and the information is stored in the FPGA, so that the electrical characteristic of the power device is accurately analyzed, and the response speed and the accuracy of the subsequent device state evaluation are improved. Then, after the analog signal of the power device in the working state is acquired, the theoretical value of the saturation voltage drop corresponding to the current power device is obtained based on the pre-stored electrical characteristic information, and is compared with the actual value of the saturation voltage drop acquired, so that the voltage increment caused by the failure of the packaging level bonding wire is obtained, and then based on the corresponding relationship between the voltage increment and the degradation state of the packaging level bonding wire of the power device, the degradation state of the packaging level bonding wire of the power device is obtained, so that the response speed of the device state evaluation is further improved. Finally, the state monitoring result is displayed, and timely warning is given. The failure of the power device can be timely warned, and the stability and reliability of the power electronic system are enhanced. In addition, for different types of power devices, the corresponding output characteristic curve cluster needs to be acquired, the corresponding electrical characteristic information is obtained by corresponding analysis, and is pre-stored, so that the monitoring demand of different power devices can be met.

[0105] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the application.

[0106] The following is a device embodiment of the application, and for details not described in detail, reference can be made to the corresponding method embodiments described above.

[0107] Figure 4 The structure schematic diagram of the FPGA-based power device state monitoring device provided by the embodiment of the application is shown, the device is applied to the FPGA, only the parts related to the embodiment of the application are shown for the convenience of description, and the details are described as follows:

[0108] As shown in Figure 4 The FPGA-based power device state monitoring device 4 comprises:

[0109] The signal processing module 41 is configured to collect the analog signal of the power device in the working state, and convert the analog signal into a digital signal; wherein the analog signal comprises the actual saturation voltage drop signal, the collector current signal and the junction temperature signal of the power device.

[0110] The FPGA processing module 42 is configured to obtain the state monitoring result of the power device according to the preset electrical characteristic information of the power device and the digital signal; wherein the state monitoring result is used to represent the degradation state of the packaging level bonding wire of the power device.

[0111] The display module 43 is configured to display the state monitoring result and give an early warning when the state monitoring result meets the failure early warning condition.

[0112] In a possible implementation, before the FPGA processing module 42, the device further comprises:

[0113] The first processing module is configured to obtain an output characteristic curve cluster of the power device; wherein the output characteristic curve cluster comprises output characteristic curves of the power device at different junction temperatures, and the output characteristic curve is used to represent the relationship between the collector-emitter saturation voltage drop and the collector current of the power device.

[0114] The second processing module is configured to obtain electrical characteristic information of the power device based on the output characteristic curve cluster; wherein the electrical characteristic information is used to represent the relationship among the corresponding saturation voltage drop theoretical value, the junction temperature and the collector current of the power device.

[0115] In a possible implementation, the second processing module is specifically configured to:

[0116] obtain a preset collector current value, and obtain a curve parameter of each output characteristic curve at the preset collector current value; wherein the curve parameter comprises a tangent slope and a tangent intercept of the output characteristic curve at the preset collector current value.

[0117] obtain a first relationship between the tangent slope of the output characteristic curve corresponding to the preset collector current value and the junction temperature based on the curve parameter of each output characteristic curve at the preset collector current value and the junction temperature corresponding to the output characteristic curve, and obtain a second relationship between the tangent intercept of the output characteristic curve corresponding to the preset collector current value and the junction temperature.

[0118] obtain an update number of the preset collector current value, if the update number does not reach a preset update number, update the preset collector current value, and repeat the step of “obtaining the preset collector current value, and obtaining the curve parameter of each output characteristic curve at the preset collector current value” until the preset update number is reached, to obtain the first relationship and the second relationship corresponding to each preset collector current value.

[0119] obtain a first function expression between the collector current and the first relationship based on the first relationship corresponding to each preset collector current value, and obtain a second function expression between the collector current and the second relationship based on the second relationship corresponding to each preset collector current value.

[0120] obtain the electrical characteristic information of the power device based on the first function expression and the second function expression.

[0121] In a possible implementation, the second processing module is specifically configured to:

[0122] According to V CE (sat)=f(K,T j ,I C )·I C +f(B,T j ,I C ), the electrical characteristic information of the power device is obtained; wherein, V CE (sat) is a theoretical value of the saturation voltage drop of the power device, f(K,T j ,I C ) is a first function expression, f(B,Tj,I C ) is a second function expression, I C is the collector current, T j is the junction temperature, K is the tangent slope, and B is the tangent intercept.

[0123] In a possible implementation, the FPGA processing module 42 is specifically configured to:

[0124] Based on the electrical characteristic information, the theoretical value of the saturation voltage drop corresponding to the collector current signal and the junction temperature signal is obtained.

[0125] According to the digital signal corresponding to the theoretical value of the saturation voltage drop and the actual saturation voltage drop signal, the state monitoring result of the power device is obtained.

[0126] In a possible implementation, the FPGA processing module 42 is specifically configured to:

[0127] The digital signal corresponding to the theoretical value of the saturation voltage drop and the actual saturation voltage drop signal is compared, and the voltage increment corresponding to the power device is obtained; wherein, the voltage increment is the voltage increment caused by the failure of the package-level bonding wire.

[0128] According to the voltage increment and the pre-stored voltage increment threshold condition, the state monitoring result of the power device is obtained; wherein, the voltage increment threshold condition is used to indicate the corresponding relationship between the degradation state of the package-level bonding wire of the power device and the voltage increment.

[0129] In a possible implementation, the apparatus further includes a third processing module configured to:

[0130] Obtain the resistance value of the thermistor built in the power device.

[0131] Determine the junction temperature of the power device according to the resistance value.

[0132] In a possible implementation, the signal processing module 41 is specifically configured to:

[0133] Apply a driving voltage to the gate of the power device to make the power device fully conduct.

[0134] A preset current is applied on the collector of the fully on power device to collect an actual saturation voltage drop signal.

[0135] Figure 5 The structure diagram of the FPGA provided by the embodiment of the application is shown in the figure. Figure 5 As shown in the figure, the FPGA 5 comprises a processor 51 and a communication interface 52, and the communication interface provides information input and / or output for the processor 51. Further, the FPGA can also comprise a memory 53, and the memory 53 is used for storing computer instructions. The processor 51 is used for calling and running the computer instructions 54 to execute the above-mentioned FPGA-based power device state monitoring method provided by the application. Wherein, the processor 51 and the memory 53 can be one or more.

[0136] The embodiment is designed by integration, the FPGA of the application has small size, is easy to install, has low maintenance cost, and can effectively monitor the state of the power device to ensure the stable operation of the power electronic system.

[0137] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0138] Those skilled in the art can realize that the templates, units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software mode depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the application.

[0139] If the modules / units are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on such understanding, the computer program can instruct the related hardware to complete all or part of the processes of the above-mentioned embodiment methods, and the computer program can be stored in a computer readable storage medium, and the computer program can realize the steps of each FPGA-based power device state monitoring method embodiment when executed by a processor. Wherein, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory, random access memory, electric carrier signal, telecommunication signal and software distribution medium, etc.

[0140] The above examples are only used to illustrate the technical solutions of the present application, but not to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those ordinarily skilled in the art should understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for monitoring the state of power devices based on FPGA, characterized in that, The method is applied to an FPGA, and the method comprises: collecting an analog signal when the power device is in a working state and converting the analog signal into a digital signal; wherein the analog signal comprises an actual saturation voltage drop signal, a collector current signal and a junction temperature signal of the power device; obtaining a state monitoring result of the power device according to preset electrical characteristic information of the power device and the digital signal; wherein the state monitoring result is used to represent a deterioration state of a package-level bonding wire of the power device; displaying the state monitoring result and giving a warning when the state monitoring result meets a failure warning condition.

2. The FPGA-based power device condition monitoring method of claim 1, wherein, Before the step of obtaining the state monitoring result of the power device according to the preset electrical characteristic information of the power device and the digital signal, the method further comprises: obtaining an output characteristic curve cluster of the power device; wherein the output characteristic curve cluster comprises output characteristic curves of the power device at different junction temperatures, and an output characteristic curve is used to represent a relationship between a collector-emitter saturation voltage drop and a collector current of the power device; obtaining the electrical characteristic information of the power device based on the output characteristic curve cluster; wherein the electrical characteristic information is used to represent a relationship among a corresponding saturation voltage drop theoretical value, a junction temperature and a collector current of the power device.

3. The FPGA-based power device condition monitoring method of claim 2, wherein, The step of obtaining the electrical characteristic information of the power device based on the output characteristic curve cluster comprises: obtaining a preset collector current value and obtaining a curve parameter of each output characteristic curve at the preset collector current value; wherein the curve parameter comprises a tangent slope and a tangent intercept of the output characteristic curve at the preset collector current value; obtaining a first relationship formula between a tangent slope and a junction temperature of an output characteristic curve corresponding to the preset collector current value and a second relationship formula between a tangent intercept and the junction temperature of the output characteristic curve according to the curve parameter of each output characteristic curve at the preset collector current value and the junction temperature corresponding to the output characteristic curve; obtaining an update number of the preset collector current value, and if the update number does not reach a preset update number, updating the preset collector current value and repeatedly executing the step of obtaining the preset collector current value and obtaining the curve parameter of each output characteristic curve at the preset collector current value until the preset update number is reached, and obtaining the first relationship formula and the second relationship formula corresponding to each preset collector current value; obtaining a first function expression between a collector current and the first relationship formula according to the first relationship formula corresponding to each preset collector current value, and obtaining a second function expression between the collector current and the second relationship formula according to the second relationship formula corresponding to each preset collector current value; obtaining the electrical characteristic information of the power device according to the first function expression and the second function expression.

4. The FPGA-based power device condition monitoring method of claim 3, wherein, The step of obtaining the electrical characteristic information of the power device according to the first function expression and the second function expression comprises: According to V CE (sat) = f(K, T j ,I C ) · I C + f(B, T j ,I C ), obtain the electrical characteristic information of the power device; wherein, V CE (sat) is a theoretical value of the saturation voltage drop of the power device, f(K, T j ,I C ) is the first function expression, f(B, T j ,I C ) is the second function expression, I C is the collector current, T j is the junction temperature, K is the tangent slope, and B is the tangent intercept.

5. The FPGA-based power device condition monitoring method according to any one of claims 1-4, characterized in that, The state monitoring result of the power device is obtained according to the preset electrical characteristic information of the power device and the digital signal, and the state monitoring result of the power device comprises: The saturation voltage drop theoretical value corresponding to the collector current signal and the junction temperature signal is obtained based on the electrical characteristic information; The state monitoring result of the power device is obtained according to the digital signal corresponding to the saturation voltage drop theoretical value and the actual saturation voltage drop signal.

6. The FPGA-based power device condition monitoring method of claim 5, wherein, The state monitoring result of the power device is obtained according to the digital signal corresponding to the saturation voltage drop theoretical value and the actual saturation voltage drop signal, and the state monitoring result of the power device comprises: The voltage increment corresponding to the power device is obtained by comparing the digital signal corresponding to the saturation voltage drop theoretical value and the actual saturation voltage drop signal; wherein the voltage increment is the voltage increment caused by the failure of the package-level bonding wire; The state monitoring result of the power device is obtained according to the voltage increment and the pre-stored voltage increment threshold condition; wherein the voltage increment threshold condition is used to indicate the corresponding relationship between the degradation state of the package-level bonding wire of the power device and the voltage increment.

7. The FPGA-based power device condition monitoring method according to any one of claims 1-4, wherein, The method further comprises: The resistance value of the thermistor built-in in the power device is obtained; The junction temperature of the power device is determined according to the resistance value.

8. The FPGA-based power device condition monitoring method according to any one of claims 1-4, wherein, The analog signal of the power device in the working state comprises: The driving voltage is applied to the gate of the power device to make the power device fully conductive; The preset current is applied to the collector of the fully conductive power device to collect the actual saturation voltage drop signal.

9. An FPGA-based power device condition monitoring apparatus, characterized by, The method is arranged in the FPGA, and the device comprises: The signal processing module is used to collect the analog signal of the power device in the working state and convert the analog signal into a digital signal; wherein the analog signal comprises the actual saturation voltage drop signal, the collector current signal and the junction temperature signal of the power device; The FPGA processing module is used to obtain the state monitoring result of the power device according to the preset electrical characteristic information of the power device and the digital signal; wherein the state monitoring result is used to represent the degradation state of the package-level bonding wire of the power device; The display module is used to display the state monitoring result and give an early warning when the state monitoring result meets the failure early warning condition.

10. An FPGA comprising at least one processor and a communication interface, the communication interface providing information input and / or output for the at least one processor; further comprising at least one memory, the memory being used to store computer instructions, the at least one processor being used to call and run the computer instructions to execute the FPGA-based power device state monitoring method of any one of claims 1 to 8.

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