On-chip calibration device parasitic parameter determining and tracing method based on inversion algorithm

Abstract

The invention discloses an on-chip calibration device parasitic parameter determination and traceability method based on an inversion algorithm, and the method comprises the steps: determining eight error terms through TRL calibration which employs three calibration standard components: a straight-through calibration standard component, a reflection calibration standard component and a transmission line calibration standard component; the method comprises the following steps of: acquiring a relation between error terms in TRL calibration and SOLT calibration according to a signal flow graph, acquiring an expression for extracting a true value of a reflection coefficient of a calibration sheet through inversion according to a 12-item error correction model algorithm, substituting scattering parameters acquired by testing into an error term analytical solution of TRL calibration, solving a TRL calibration error term, and calculating the true value of the reflection coefficient of the calibration sheet according to the error term analytical solution of the TRL calibration. The reflection coefficient truth values of the open circuit and short circuit of the calibration piece and the load piece are extracted; according to the method, the extraction process of the parasitic parameters of the calibration piece is simplified, error sources introduced in the extraction process of the parasitic parameters of the calibration piece are reduced, and the extracted parasitic parameters of the calibration piece have a good effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wafer-level semiconductor device microwave characteristic measurement, and particularly relates to a method for determining and tracing parasitic parameters of on-chip calibration pieces based on an inversion algorithm. BACKGROUND

[0002] With the development of high-frequency integrated circuits towards wafer-level multifunctional chips, the related manufacturing processes and measurement technologies are also constantly improving. Accurate measurement of scattering parameters (S parameters) is a key basis for performance evaluation, model extraction and circuit design of high-frequency integrated circuits. In engineering applications, SOLT calibration is widely used for calibration of on-chip S parameter measurement systems, but its calibration accuracy is heavily dependent on the accuracy of calibration piece definitions. Definition errors of calibration pieces will directly affect the final accuracy of system calibration, and therefore, improving the accuracy of calibration piece definitions is of great significance for improving the reliability of high-frequency integrated circuit on-chip testing.

[0003] Currently, common types of calibration pieces include open, short and load calibration pieces, and their performances are usually characterized by lumped parameter models (such as capacitance, inductance or resistance values). However, in the process of value tracing, definition errors of calibration pieces will be transmitted to the final measurement results through error terms in the traditional method based on impedance parameter extraction (such as SOLT calibration), thereby affecting the overall accuracy of the test system. In contrast, TRL calibration has become a recognized calibration standard in the field of high-frequency on-chip testing due to its high calibration accuracy and low dependence on calibration piece definition values. Traditional methods usually use TRL calibration to preliminarily calibrate the test system, and then extract impedance parameters by measuring on-chip open, short and load calibration pieces. However, this method still has the problem of error transmission in value tracing, which limits the accuracy of the measurement results.

[0004] Therefore, there is an urgent need for a new method that can reduce the influence of calibration piece definition errors and improve the accuracy of on-chip S parameter measurement to meet the higher requirements of high-frequency integrated circuit development on testing technology. Therefore, a method for determining and tracing parasitic parameters of on-chip calibration pieces based on an inversion algorithm is needed. SUMMARY

[0005] The purpose of the present application is to provide a method for determining and tracing parasitic parameters of on-chip calibration pieces based on an inversion algorithm, which can reduce the propagation path of errors in the extraction of calibration piece parasitic parameters and improve the measurement accuracy of on-chip S parameters.

[0006] To achieve the above purpose, the present application is implemented according to the following technical solutions:

[0007] The present application provides a method for determining and tracing parasitic parameters of on-chip calibration pieces based on an inversion algorithm, comprising the following steps:

[0008] Step S01, eight error terms are determined by TRL calibration, which uses three calibration standards of straight-through, reflection and transmission line;

[0009] Step S02, according to the signal flow diagram, the 8 error models of TRL calibration are derived to the 12 error models of SOLT, to obtain the relationship between each error term in TRL calibration and SOLT calibration, wherein the error terms of TRL calibration correspond to 6 error terms in the forward propagation model and 6 error terms in the backward propagation model of SOLT calibration;

[0010] Step S03, according to the 12 error correction model algorithm, the expression for extracting the true value of the reflection coefficient of the calibration chip is obtained, and the extraction calibration chip includes open circuit, short circuit and load calibration;

[0011] Step S04, the on-chip straight-through and scattering parameters, the reflection coefficient value when the two-port open circuit, and the reflection coefficient measurement value of the open circuit, short circuit and load of the extraction calibration chip are tested under 20-40GHz in the chip scattering parameter test system;

[0012] Step S05, the scattering parameters obtained in step S04 are substituted into the analytical solution of the error terms of TRL calibration, to obtain the TRL calibration error terms and the SOLT calibration error terms, and all error terms are characterized in complex form within the frequency range of 20-40GHz;

[0013] Step S06, the reflection coefficient measurement value obtained in step S04 and the error term obtained in step S05 are substituted into the expression in step S03, to obtain the true value of the reflection coefficient of the open circuit, short circuit and load of the extraction calibration chip;

[0014] Step S07, the reflection coefficient true value obtained in step S06 is used to obtain the equivalent capacitance of the open circuit calibration, the equivalent inductance of the short circuit calibration, the equivalent resistance and the equivalent inductance of the load calibration, combined with the equivalent model of the on-chip calibration.

[0015] Step S08, according to the above steps, the error traceability is determined to the amplitude and phase accuracy of the measurement receiver of the vector network analyzer and the physical parameters of the coplanar waveguide transmission line.

[0016] Further, in step S02, the 8 error models of TRL calibration are converted into the forward and backward error models of SOLT calibration by Mason formula.

[0017] Further, in step S03, the open circuit calibration is in the form of GSG coplanar waveguide; the short circuit calibration is in the form of GSG coplanar waveguide; and the load calibration is in the form of GSG coplanar waveguide.

[0018] Further, in step S07, the correctness of the extraction of the parasitic parameters is verified by using the extracted parasitic parameters of the calibration chip as the true value of the calibration chip to substitute into the SOLT calibration algorithm to correct the error of the uncalibrated DUT, and the corrected result is compared with the correction result of the same uncalibrated DUT using the TRL calibration algorithm.

[0019] Further, in step S03, the reflection coefficient true value of the ideal open calibration piece is 1; the reflection coefficient true value of the ideal short calibration piece is 1, and the reflection coefficient true value of the ideal resistance calibration piece is 0.

[0020] Further, the analytical expression of the error term is as follows:

[0021]

[0022] Wherein:

[0023]

[0024] Wherein γ is the propagation constant of the transmission line, and l is the length of the transmission line.

[0025] Further, the true value of the calibration piece is solved by the measured value and the error term, and the expression is as follows:

[0026]

[0027] Wherein Γ AO , Γ AS , Γ AL are the reflection coefficient true values of the open circuit, the short circuit and the load of the extracted calibration chip respectively. Γ AO , Γ AS , Γ AL are the measured values of the reflection coefficients of the open circuit, the short circuit and the load respectively.

[0028] Compared with the prior art, the embodiments of the present application have at least the following advantages or beneficial effects:

[0029] The present application improves the efficiency of the extraction of the parasitic parameters of the single-port on-chip calibration piece, finds the relationship between the true value of the calibration piece and the measured value and the error term by studying the mutual conversion relationship between the error models, further reduces the error sources of the single-port parasitic parameter extraction, traces the error sources of the impedance parameters to the basic quantities, verifies the effectiveness of the proposed method through actual test and comparative analysis, and the quantity value traceability approach is reasonable. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 The key step flowchart of the embodiments of the present application;

[0031] Figure 2The conversion flow chart of 8th and 12th error models in the embodiment of the present application;

[0032] Figure 3 The equivalent resistance value diagram of the resistance calibration element on the alumina sheet actually extracted in the embodiment of the present application;

[0033] Figure 4 The equivalent inductance value diagram of the resistance calibration element on the alumina sheet actually extracted in the embodiment of the present application;

[0034] Figure 5 The equivalent inductance value diagram of the short circuit calibration element on the alumina sheet actually extracted in the embodiment of the present application;

[0035] Figure 6 The equivalent capacitance value diagram of the open circuit calibration element on the alumina sheet actually extracted in the embodiment of the present application;

[0036] Figure 7 The reflection coefficient result comparison diagram of the same on-chip mismatch load subjected to SOLT calibration by using the parasitic parameter values extracted by TRL calibration in the embodiment of the present application;

[0037] wherein, Figure 7 (a) is the amplitude diagram of the reflection coefficient of the same on-chip mismatch load subjected to SOLT calibration by using the parasitic parameter values extracted by TRL calibration in the embodiment of the present application; Figure 7 (b) is the phase diagram of the reflection coefficient of the same on-chip mismatch load subjected to SOLT calibration by using the parasitic parameter values extracted by TRL calibration in the embodiment of the present application;

[0038] Figure 8 The transmission coefficient result comparison diagram of the same on-chip attenuator subjected to SOLT calibration by using the parasitic parameter values extracted by TRL calibration in the embodiment of the present application;

[0039] wherein, Figure 8 (a) is the amplitude diagram of the transmission coefficient of the same on-chip attenuator subjected to SOLT calibration by using the parasitic parameter values extracted by TRL calibration in the embodiment of the present application; Figure 8 (b) is the phase diagram of the transmission coefficient of the same on-chip attenuator subjected to SOLT calibration by using the parasitic parameter values extracted by TRL calibration in the embodiment of the present application;

[0040] Figure 9 The error transfer flow chart in the embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0042] Reference Figure 1 As shown, this invention provides a method for determining and tracing parasitic parameters of on-chip calibration components based on an inversion algorithm, including the following steps:

[0043] Step S01: Eight error terms are determined through TRL calibration. The TRL calibration uses three calibration standards: through-pass, reflection, and transmission line. The TRL calibration includes eight error terms, which are solved and eliminated using these three standards. In this embodiment, the through-pass calibration standard is 200µm long, the transmission calibration standard is 900µm long, and the reflection calibration standard is implemented by lifting a dual-port probe more than 200µm away from the calibration plate.

[0044] TRL calibration includes 8 error terms, namely e 00 ,e 01 ,e 11 ,e 10 ,e 22 ,e 23 ,e 33 ,e 32 By sequentially measuring the reflection coefficients of the through-hole, transmission line, and through-hole component. The analytical expression for the error terms is obtained, in which there are four error terms related to the inversion extraction of parasitic parameters of port 1, namely e 00 ,e 01 ,e 11 ,e 10 Solving for e yields the result. 00 ,e 11 and e 10 e 01 The analytical expression for the error term is as follows:

[0045]

[0046] in:

[0047]

[0048] Where γ is the propagation constant of the transmission line, l is the length of the transmission line, and the following formula is given by e. -γl From the two linear equations in two variables, we can obtain information about e. -γl The two solutions are determined by comparison, and the solution when |α| is much less than 1 is ultimately chosen.

[0049]

[0050] Step S02, according to the signal flow diagram, the 8 error models of TRL calibration are derived to the 12 error models of SOLT, and the relationship between each error term in TRL calibration and SOLT calibration is obtained.

[0051] The signal flow diagram of the 8 error models of TRL calibration is derived to the 12 error models of SOLT calibration, and the error terms e 00 ,e 01 ,e 11 ,e 10 respectively correspond to the error terms e 00 ,1,e′ 11 ,e′ 10 e′ 01 . Figure 2 The flowchart for converting the 8 error models of TRL calibration into the forward error model of SOLT calibration by using Mason formula is shown in the figure, wherein:

[0052]

[0053] From the derivation of the signal flow diagram, the relationship between the error terms of TRL calibration and the error terms of SOLT calibration can be found, in particular, the error terms e 00 ,e 01 ,e 11 ,e 10 respectively correspond to the error terms e 00 ,1,e′ 11 ,e′ 10 e' 01 .

[0054] Step S03, according to the 12 error correction model algorithm, the expression for extracting the true value of the reflection coefficient of the calibration chip is as follows:

[0055]

[0056] wherein Γ AO ,Γ AS ,Γ AL are the true values of the open circuit, short circuit and load reflection coefficients of the extracted calibration chip. Γ AO ,Γ AS ,Γ ALThe measured values of the reflection coefficients of open circuit, short circuit and load, respectively. Optionally, the open circuit, short circuit and load calibration pieces are on-chip calibration pieces in the form of GSG coplanar waveguide. The true value of the reflection coefficient of the ideal open circuit calibration piece is 1, but due to the electromagnetic field edge effect, an equivalent capacitance Co is introduced, causing the reflection coefficient phase to deviate from 0° at high frequencies, so the equivalent capacitance needs to be extracted and its frequency-varying phase response is compensated in the calibration algorithm; the true value of the reflection coefficient of the ideal short circuit calibration piece is 1, but there is an equivalent inductance L S , causing the reflection coefficient phase to deviate from 180° at high frequencies; the true value of the reflection coefficient of the ideal resistance calibration piece is 0, but due to the thin film resistance process error and the parasitic inductance L R introduced at the connection between the resistance and the transmission line, load impedance mismatch is caused.

[0057] Step S04, the scattering parameters of the on-chip through piece and the 900um transmission line at 20-40GHz and the reflection coefficient value of the open circuit of the two-port are directly tested by the on-chip scattering parameter test system (i,j=1,2); the reflection coefficient measurement values (Γ MO ,Γ MS ,Γ ML ) of the open circuit, short circuit and load of the calibration piece are directly tested by the on-chip scattering parameter test system at 20-40GHz.

[0058] The on-chip scattering parameter test system comprises a vector network analyzer, a probe station, a microscope and a GSG probe with a pitch of 150um. The tested on-chip through piece and transmission line are coplanar waveguide structures of an alumina substrate. The open circuit, short circuit and load of the calibration piece are GSG structures processed by a thin film processing process, and the dielectric substrate is an alumina with a thickness of 625um.

[0059] Step S05, substituting the test obtained into the analytical solution of the TRL calibration error term, to obtain the TRL calibration error terms e 00 ,e 11 ,e 10 e 01 , and the SOLT calibration error terms e′ 00 ,e′ 11 ,e′ 10 e′ 01 are obtained. All the error terms are characterized in the form of complex numbers in the frequency band of 20-40GHz.

[0060] Step S06, substituting the test obtained Γ MO ,Γ MS ,Γ ML in step S04 and the error terms e′ 00,e′ 11 ,e′ 10 e′ 01 Substituting into step S03, the true values ​​Γ of the reflection coefficients of the open-circuit, short-circuit, and load components of the extracted calibration sheet are obtained. AO ,Γ AS ,Γ AL .

[0061] Step S07: Using the true values ​​Γ of the reflection coefficients of the open circuit, short circuit, and load components of the extraction calibration sheet obtained in step S06. AO ,Γ AS ,Γ AL Based on the equivalent model of the on-chip calibration component, the equivalent capacitance of the open-circuit calibration component, the equivalent inductance of the short-circuit calibration component, and the equivalent resistance and equivalent inductance of the load calibration component are obtained. The parasitic parameter of the open-circuit component of the calibration chip is extracted as capacitance Co; the parasitic parameter of the inductor component is extracted as inductance L. S The parasitic parameter of the load component is resistance R. L With inductor L L Parasitic parameters and impedance parameters of open circuit, short circuit and load components (Z) O Z S Z L The relationship is as follows:

[0062]

[0063] Z S =jωL S

[0064] Z L =R L +jωL L

[0065] Impedance parameter Z of the calibration piece CS The true value of the calibration piece Г A and the characteristic impedance Z of the system C The relationship is as follows:

[0066]

[0067] like Figures 3-6As shown in the figure, the equivalent resistance value of the actual extracted resistance calibration piece on the alumina sheet in the embodiment of the application is shown, the equivalent resistance value of the load varies with the frequency, the resistance value ranges from 50.6 to 51.4 Ω, the equivalent inductance value of the actual extracted short-circuit calibration piece on the alumina sheet in the embodiment of the application, the equivalent inductance value of the open circuit varies with the frequency, the inductance ranges from -24.5 to -21.7 pH, the equivalent capacitance value of the actual extracted open-circuit calibration piece on the alumina sheet in the embodiment of the application, the equivalent capacitance value of the short circuit varies with the frequency, the inductance ranges from -5.6 to -5.1 fF.

[0068] In step S08, according to the extraction step of the parasitic parameter extraction described above, the final error can be traced back to the amplitude and phase accuracy of the vector network analyzer measuring the receiver and the physical parameters of the co-planar waveguide transmission line. Compared with the traditional method of directly obtaining the true value of the open-circuit, short-circuit and load calibration pieces of the extraction calibration sheet after TRL calibration, the method proposed in the application simplifies the extraction process and reduces the transmission of redundant error terms in the extraction process, and only three error terms e 00 ,e 11 ,e 10 e 01 participate in the error transmission process.

[0069] In order to verify the correctness of the on-chip calibration piece impedance parameter extraction in step S07, the on-chip mismatch load and the 10 dB on-chip attenuator are selected as the to-be-tested pieces for performance verification. The verification steps are as follows: the extracted parasitic parameters of the calibration sheet are used as the true value of the calibration sheet to substitute into the SOLT calibration algorithm to correct the uncalibrated to-be-tested piece, and the corrected result is compared with the correction result of the same to-be-tested piece using the TRL calibration algorithm.

[0070] As Figure 7 and 8 shown, the linear value of the amplitude difference is converted into logarithmic value, which is less than -66.2 dB, and the phase difference is less than 0.02°, the linear value of the amplitude difference is converted into logarithmic value, which is less than -55.8 dB, and the phase difference is less than 0.26°, the comparison results show that when the same to-be-tested piece is subjected to SOLT calibration using TRL calibration and the extracted parasitic parameter value, the transmission coefficient and the reflection coefficient are in good agreement, which verifies the correctness of the method for extracting parasitic parameters proposed in the application.

[0071] The above merely illustrates and describes the structure of the present application, and those skilled in the art can make various modifications or supplements to the described specific embodiments or adopt similar ways to replace, as long as the modifications or supplements do not deviate from the structure of the present application or exceed the scope defined by the present claims, and should belong to the protection scope of the present application.

Claims

1. An on-chip calibration phantom parasitic parameter determination and tracing method based on inversion algorithm, characterized in that, The method comprises the following steps: Step S01, eight error terms are determined by TRL calibration, and the TRL calibration adopts three calibration standards of straight-through, reflection and transmission line; Step S02, according to a signal flow diagram, the eight error models of TRL calibration are derived to the twelve error models of SOLT, to obtain the relationship between each error term in TRL calibration and SOLT calibration, wherein the error terms of TRL calibration correspond to six error terms in the forward propagation model and six error terms in the backward propagation model of SOLT calibration respectively; Step S03, according to the twelve error correction model algorithm, an expression for extracting the true value of the reflection coefficient of the calibration chip is obtained by inversion, and the calibration chip comprises open circuit, short circuit and load calibration standards; Step S04, the on-chip straight-through and scattering parameters, the reflection coefficient value when the two-port open circuit and the reflection coefficient measurement value of the open circuit, short circuit and load of the extraction calibration chip are tested under 20-40GHz in the chip scattering parameter test system; Step S05, the scattering parameters obtained in step S04 are substituted into the analytical solution of the error terms of TRL calibration, to obtain the TRL calibration error terms and the SOLT calibration error terms, and all the error terms are characterized in the form of complex numbers in the frequency range of 20-40GHz; Step S06, the reflection coefficient measurement value of the extraction calibration chip obtained in step S04 and the error terms obtained in step S05 are substituted into the expression in step S03, to obtain the true value of the reflection coefficient of the open circuit, short circuit and load of the extraction calibration chip; Step S07, the reflection coefficient true value obtained in step S06 is used to obtain the equivalent capacitance of the open circuit calibration standard, the equivalent inductance of the short circuit calibration standard, the equivalent resistance and the equivalent inductance of the load calibration standard, in combination with the equivalent model of the on-chip calibration standard; Step S08, according to the above steps, the error traceability is determined to the amplitude and phase accuracy of the measurement receiver of the vector network analyzer and the physical parameters of the co-planar waveguide transmission line.

2. The on-chip calibration parasitic parameter determination and tracing method based on inversion algorithm according to claim 1, characterized in that, In step S02, the eight error models of TRL calibration are converted into the forward error model and the backward error model of SOLT calibration by Mason formula.

3. The on-chip calibration parasitic parameter determination and tracing method based on inversion algorithm according to claim 1, characterized in that, In step S03, the open circuit calibration standard is in the form of GSG co-planar waveguide; the short circuit calibration standard is in the form of GSG co-planar waveguide; and the load calibration standard is in the form of GSG co-planar waveguide.

4. The on-chip calibration parasitic parameter determination and tracing method based on inversion algorithm according to claim 1, characterized in that, In step S07, the correctness of the extracted parasitic parameters is verified by substituting the parasitic parameters of the extracted calibration chip into the SOLT calibration algorithm as the true value of the calibration chip to correct the uncalibrated test piece, and the corrected result is compared with the correction result of the same uncalibrated test piece obtained by using the TRL calibration algorithm.

5. The on-chip calibration parasitic parameter determination and tracing method based on inversion algorithm according to claim 1, characterized in that, In step S03, the true value of the reflection coefficient of the ideal open circuit calibration standard is 1; the true value of the reflection coefficient of the ideal short circuit calibration standard is 1; and the true value of the reflection coefficient of the ideal resistance calibration standard is 0.

6. The on-chip calibration parasitic parameter determination and tracing method based on inversion algorithm according to claim 1, characterized in that, The analytical expression of the error term is as follows: Wherein: Wherein γ is the propagation constant of the transmission line, and l is the length of the transmission line.

7. The on-chip calibration parasitic parameter determination and tracing method based on inversion algorithm according to claim 1, characterized in that, The true value of the calibration standard is solved by the measurement value and the error term as follows: where Γ AO , Γ AS , Γ AL are the true values of the reflection coefficients of the open, short and load of the extraction calibration piece, respectively. Γ AO , Γ AS , Γ AL are the measured values of the reflection coefficients of the open, short and load, respectively.

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