Integer divider and method for realizing Radix-16 operation, chip and electronic equipment

Abstract

The invention discloses an integer divider and method for realizing Radix-16 operation, a chip and electronic equipment, and belongs to the technical field of electronics. The integer divider comprises a preprocessing module, an iterative calculation module and a post-processing module, wherein the iterative calculation module comprises four levels of Radix-2 sub-operation modules which are connected in sequence; the step of generating the 1-bit quotient and the remainder update by the current-level Radix-2 in the primary iteration Radix-16 comprises the following steps of: obtaining an initialized divisor d and a partial remainder wj; determining a 1-bit quotient qj of the current level Radix-2 according to the partial remainder wj; obtaining an updated partial remainder wj + 1 according to a preset iteration recursion rule, and outputting the updated partial remainder wj + 1 to a next-level Radix-2 sub-operation module; and the post-processing module combines the 1-bit quotients generated by each level of Radix-2 to generate 4-bit quotients, and combines the 4-bit quotients as a final quotient value of Radix-16 division operation.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and particularly relate to an integer divider, method, chip and electronic device for implementing Radix-16 operation. BACKGROUND

[0002] In the design of arithmetic operation units of computer architecture, division and remainder operations constitute the most complex calculation module in the basic operation subsystem due to their nonlinear numerical characteristics. Compared with adders, multipliers and other operation units that can be implemented through combinatorial logic or tree structure to achieve single-cycle / short-pipeline delay, traditional division hardware implementation (such as restoration remainder method, non-restoration remainder method) relies on linear iteration mechanism, and the operation throughput is limited by the linear expansion characteristics of the operand bit width, which is difficult to meet the requirements of modern superscalar processors for instruction-level parallelism.

[0003] As a theoretical breakthrough of iterative division algorithm, SRT (Sweeney, Robertson, and Tocher) algorithm reconstructs the iteration paradigm by introducing a quotient bit prediction mechanism in the redundant number system. The classic SRT-2 algorithm uses base 2, and only generates 1-bit quotient value in a single cycle. In the context of 64-bit and wider bit operations, the linear growth of iteration times leads to a throughput bottleneck of the critical calculation path, which significantly affects the Instructions Per Cycle (IPC) index of the processor. To break through the performance limit of base 2 architecture, high-base SRT algorithm (Radix-2k SRT) achieves parallel generation of k-bit quotient values in a single cycle by expanding the redundancy threshold of the redundant number system. However, the increase of base number k will cause super-linear growth of hardware complexity. How to simplify the hardware complexity and ensure the high performance of high-base SRT unit is a technical problem to be solved in the field. SUMMARY

[0004] Embodiments of the present application provide an integer divider, method, chip and electronic device for implementing Radix-16 operation, which can solve the problem of how to simplify the hardware complexity of high-base SRT unit and ensure its high performance.

[0005] To solve the above technical problems, the present application is implemented as follows: In a first aspect, an integer divider for implementing Radix-16 operation is provided, comprising a preprocessing module, an iteration calculation module and a post-processing module connected in sequence, wherein: The iteration calculation module comprises four Radix-2 sub-operation modules connected in sequence, wherein the output end of each Radix-2 sub-operation module is connected with the input end of the next Radix-2 sub-operation module, and the output end of each Radix-2 sub-operation module is connected with the post-processing module respectively; In the Radix-16 division operation of one iteration, the Radix-2 sub-operation module of the current stage generates one-bit quotient and updates the remainder by the following way, wherein the Radix-2 sub-operation module of the current stage is any one of the four Radix-2 sub-operation modules connected in sequence: Obtain an initialization divisor d and a partial remainder w j The initialization divisor d is generated after the initialization of the divisor by the pre-processing module; According to the partial remainder w j Determine one-bit quotient of the Radix-2 sub-operation module of the current stage according to a preset quotient selection rule q j , wherein, q j ∈{+1, 0, -1}, j=0,1,2,3 ; According to a preset iteration recursion rule, the partial remainder w j , the initialization divisor d and the quotient q j are operated to obtain an updated partial remainder w j+1 The updated partial remainder w j+1 is output to the Radix-2 sub-operation module of the next stage, wherein, in the case that the Radix-2 sub-operation module of the current stage is the first Radix-2 sub-operation module, j=0 , the partial remainder w j is an initialization partial remainder generated after the initialization of the dividend; The post-processing module is used for combining one-bit quotient generated by each Radix-2 sub-operation module as four-bit quotient generated by the Radix-16 division operation of one iteration, combining four-bit quotient generated by each Radix-16 division operation of one iteration as the final quotient value of the Radix-16 division operation, and processing the partial remainder output by the fourth Radix-2 sub-operation module of the Radix-16 division operation of the last iteration as the final remainder of the Radix-16 division operation.

[0006] In a second aspect, a method for implementing Radix-16 operation is provided, which is applied to the integer divider as described above, and the method comprises: dividing the Radix-16 operation of one iteration into four Radix-2 sub-operations; generating one-bit quotient and updating the remainder in each Radix-2 sub-operation of the Radix-16 operation of one iteration by the following way: the current Radix-2 sub-operation obtains an initialized divisor d and a partial remainder w j , wherein the initialized divisor d is generated after the initialization of the divisor; according to the partial remainder w j determining one-bit quotient of the current Radix-2 sub-operation according to a preset quotient selection rule q j , wherein q j ∈{+1, 0, -1}, j=0,1,2,3 ; updating the partial remainder w j , the initialized divisor d and the quotient q j by operation to obtain an updated partial remainder w j+1 , wherein the updated partial remainder w j+1 is taken as the partial remainder inputted by the next Radix-2 sub-operation w j+1 , wherein, in the case that the current Radix-2 sub-operation is the first Radix-2 sub-operation, j=0 , the partial remainder w j is an initialized partial remainder generated after the initialization of the dividend; combining one-bit quotient generated by each Radix-2 sub-operation as four-bit quotient generated by the Radix-16 operation of one iteration, combining four-bit quotient generated by each Radix-16 operation of one iteration as the final quotient value of the Radix-16 operation, and processing the partial remainder outputted by the fourth Radix-2 sub-operation of the last Radix-16 operation of one iteration as the final remainder of the Radix-16 operation.

[0007] In a third aspect, a chip is provided, the chip comprising the integer divider as described above, and the chip is configured to perform the method of implementing Radix-16 operation as described above.

[0008] In a fourth aspect, an electronic device is provided, comprising: the chip as described above; and a memory connected with the processor; wherein the memory stores a program or instructions executable on the processor, and the program or instructions, when executed by the chip, implement the steps of the method of implementing Radix-16 operation as described above.

[0009] The integer divider, the method, the chip and the electronic device for implementing Radix-16 operation provided by the embodiments of the present application adopt a multi-stage decomposition structure, and implement efficient Radix-16 operation through a composite iteration system constructed by four Radix-2 sub-operation modules, which simplifies the hardware complexity of the high-base SRT unit, significantly reduces the operation period of the RISC-V division and remainder instructions, improves the operation speed, and ensures the high performance of the high-base SRT unit; and supports 64-bit and 32-bit RISC-V unsigned and signed integer division and remainder operation, and is applicable to different application scenarios.

[0010] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of the specification illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0012] Figure 1 a structure block diagram of the integer divider for implementing Radix-16 operation provided by an exemplary embodiment of the present application is shown; Figure 2 a 2-bit leading zero count schematic diagram provided by an exemplary embodiment of the present application is shown; Figure 3 a 4-bit leading zero count schematic diagram provided by an exemplary embodiment of the present application is shown; Figure 4 a combination logic schematic diagram of the barrel shifter provided by an exemplary embodiment of the present application is shown; Figure 5 an SRT-2 quotient selection truth representation diagram provided by an exemplary embodiment of the present application is shown; Figure 6 a flowchart of the method for implementing Radix-16 operation provided by an exemplary embodiment of the present application is shown; Figure 7 A flow chart is shown for converting the value of the 1-bit quotient generated by each Radix-2 sub-operation module into the corresponding canonical complement quotient value according to an example embodiment of the present application. Figure 8 A structural block diagram of an electronic device according to an example embodiment of the present application is shown. DETAILED DESCRIPTION

[0013] The example embodiments will be described in detail herein with reference to the drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following example embodiments are not meant to represent all implementations consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0014] To solve the problem of super-linear growth of hardware complexity of high-base SRT unit caused by the increase of base k in the prior art, an integer divider and method for implementing Radix-16 operation are provided in the embodiments of the present application.

[0015] The following will be described in conjunction with Figure 1 The integer divider for implementing Radix-16 operation provided in the embodiments of the present application will be explained and described in detail. These embodiments are only used to explain the present application and do not constitute a limitation on the present application.

[0016] Figure 1 A structural block diagram of the integer divider for implementing Radix-16 operation according to an example embodiment of the present application is shown. As Figure 1 shown, the integer divider for implementing Radix-16 operation provided in the embodiments of the present application includes a pre-processing module 10, an iterative calculation module 20 and a post-processing module 30 connected in sequence, corresponding to a pre-processing stage (S1), an iterative calculation stage (S2) and a post-processing stage (S3) respectively.

[0017] In the conventional division operation, the quotient and the remainder are calculated by the way of trying quotient bit by bit. The Radix-16 algorithm is a division algorithm based on a higher base. In order to realize the hardware optimization of the algorithm, a multi-level decomposition structure is adopted in the embodiments of the present application, and a composite iterative system is constructed by 4-level Radix-2 sub-operation modules to simplify the hardware complexity of the high-base SRT unit. As Figure 1As shown, the iteration calculation module 20 comprises 4 stages of Radix-2 sub-operation modules 200 connected in sequence, wherein the output end of each stage of Radix-2 sub-operation modules 200 is connected to the input end of the next stage of Radix-2 sub-operation modules 200, and the output end of each stage of Radix-2 sub-operation modules 200 is respectively connected to the post-processing module 30.

[0018] Each stage of Radix-2 sub-operation modules generates a 1-bit quotient, and each iteration of Radix-16 division operation runs the 4 stages of Radix-2 sub-operation modules once, generating a 4-bit quotient in one iteration of Radix-16 division operation. According to this iteration mode, the final quotient value and the final remainder are generated after N times of iteration of Radix-16 division operation. In the following, the current stage of Radix-2 sub-operation modules 200 in one iteration of Radix-16 division operation is taken as an example to describe the way of generating a 1-bit quotient and updating the remainder by the Radix-2 sub-operation modules 200. In this embodiment, the current stage of Radix-2 sub-operation modules 200 is any Radix-2 sub-operation module in the 4 stages of Radix-2 sub-operation modules 200 connected in sequence, and each stage of Radix-2 sub-operation modules 200 operates according to this mode.

[0019] In some embodiments, the current stage of Radix-2 sub-operation modules 200 in one iteration of Radix-16 division operation generates a 1-bit quotient and updates the remainder by the following way: a1. obtaining the initialized divisor d and the partial remainder w j The initialized divisor d is generated after the initialization of the divisor by the preprocessing module; a2. determining the 1-bit quotient of the current stage of Radix-2 sub-operation modules according to the partial remainder w j according to the preset quotient selection rule q j , wherein, q j ∈{+1, 0, -1}, j=0,1,2,3 ; a3. updating the partial remainder w j , the initialized divisor d and the quotient q j according to the preset iteration recursion rule to obtain the updated partial remainder w j+1 ; a4. outputting the updated partial remainder w j+1 to the next stage of Radix-2 sub-operation modules, wherein, in the case that the current stage of Radix-2 sub-operation modules is the first stage of Radix-2 sub-operation modules, j=0 , the partial remainder wj For the initialization part remainder generated after the initialization of the dividend, in the embodiment, the current stage Radix-2 sub-operation module 200 is any Radix-2 sub-operation module in the four-stage Radix-2 sub-operation modules 200 connected in sequence.

[0020] The post-processing module 30 is configured to combine the 1-bit quotient generated by each stage Radix-2 sub-operation module as a 4-bit quotient generated by one iteration of Radix-16 division operation, combine the 4-bit quotient generated by each iteration of Radix-16 division operation as the final quotient value of the Radix-16 division operation, and process the partial remainder output by the fourth stage Radix-2 sub-operation module of the last iteration of Radix-16 division operation as the final remainder of the Radix-16 division operation.

[0021] The integer divider for implementing Radix-16 operation provided in the embodiment overcomes the problem of super-linear growth of hardware complexity caused by the promotion of the radix k in the prior art, simplifies the hardware complexity, reduces the power consumption, and is suitable for low-power devices; significantly reduces the operation period of the RISC-V division and remainder instructions, improves the operation speed, ensures the high performance of the high-radix SRT unit; and supports 64-bit and 32-bit RISC-V unsigned and signed integer division and remainder operation, and is suitable for different application scenarios.

[0022] In some embodiments, the preprocessing stage (S1) prepares for the subsequent iteration operation, preprocesses the input dividend and divisor, for example, bit width adaptation, absolute value removal, leading zero counting, and the like, and performs normalization and other normalization processing; (S2) the iteration calculation stage performs multiple iteration calculations of the quotient and the remainder through a multi-stage decomposition structure, divides one iteration of Radix-16 division operation into four stages of Radix-2 sub-operation, obtains a 4-bit quotient of one iteration of Radix-16 division operation through Radix-2 sub-operation, and completes multiple iteration calculations of Radix-16 division operation; (S3) the post-processing stage corrects and converts the quotient and the remainder obtained through iteration calculation to conform to the binary coded standard.

[0023] In the embodiment, the divisor and the dividend input into the iteration calculation module 20 are generated after the initialization by the preprocessing module 10. Hereinafter, the operation of the preprocessing module 10 in the preprocessing stage is explained and described.

[0024] In some embodiments, the pre-processing module 10 is configured to perform shift compensation and zero padding extension to obtain an initial partial remainder based on a dividend, and to perform shift compensation and zero padding extension to obtain an initial divisor d based on a divisor, wherein the dividend is a normalized value after being extended to 64-bit and taking absolute value and removing leading zeros, and wherein the divisor is a normalized value after being extended to 64-bit and taking absolute value and removing leading zeros.

[0025] In some embodiments, the pre-processing module 10 receives the following parameters at an input thereof: a dividend (dividend[63:0]), a divisor (divisor[63:0]), a control signal (div_ctl[2:0]), and an instruction and source operand enable signal.

[0026] In some embodiments, the pre-processing module 10 is further configured to decode the control signal to determine an operation mode. In this embodiment, div_ctl[0] is a sign identification bit, wherein 1 indicates a signed operation and 0 indicates an unsigned operation; div_ctl[1] is a data width identification bit, wherein 1 indicates a 64-bit operation and 0 indicates a 32-bit operation; and div_ctl[2] is an operation mode identification bit, wherein 1 indicates a remainder operation and 0 indicates a division operation. By combining the control signal, the system supports eight operation modes: 64-bit signed division, 64-bit unsigned division, 32-bit signed division, 32-bit unsigned division, 64-bit signed remainder, 64-bit unsigned remainder, 32-bit signed remainder, and 32-bit unsigned remainder. For example, when div_ctl[2:0] is “110”, it indicates a 64-bit signed remainder operation.

[0027] In some embodiments, the preprocessing module 10 is further configured to perform sign bit extension on the operands of signed operation based on the decoding result of the control signal div ctl [2:0]. For 32-bit operation mode (div ctl [1] = 0), if it is a signed number (div ctl [0] = 1), the low 32 bits of the dividend and the divisor (dividend [31:0], divisor [31:0]) are extended to 64 bits by sign bit; if it is an unsigned number (div ctl [0] = 0), zero extension to 64 bits is performed. For 64-bit operation mode (div ctl [1] = 1), no sign or zero extension is needed, and the 64-bit source operand is directly taken as the dividend and the divisor. In some embodiments, a multiplexer (MUX) array can be used to implement dynamic bit width selection to support 32 / 64-bit mode switching. For example, if div ctl [1] = 0 (32-bit operation mode) and div ctl [0] = 1 (signed number), the low 32 bits of the dividend and the divisor are extended to 64 bits by sign bit. Thus, the integer divider for Radix-16 operation provided by the embodiments of the present application can support 64-bit, 32-bit RISC-V unsigned and signed integer division and remainder operations, and is suitable for different application scenarios.

[0028] In some embodiments, the preprocessing module 10 is further configured to take the absolute value of the operands of signed operation according to the two's complement mechanism, that is, when the dividend or the divisor is the operand of signed operation, the absolute value of the dividend and the divisor also needs to be further taken.

[0029] In some embodiments, the preprocessing module 10 is further configured to use a parallel binary tree structure to quickly calculate the number of leading zeros of the dividend and the divisor. Specifically, the following method is used: after the absolute value of the dividend and the divisor is calculated, the 64-bit number is first divided into 32 2-bit numbers, and the number of leading zeros of the 2-bit number is calculated, which has 4 cases, and then the number of leading zeros is calculated to obtain the values of z2 and c2, as shown in Figure 2 . Then the 64-bit number is divided into 16 4-bit numbers to calculate the number of leading zeros, which has 5 cases, as shown in Figure 3 . In this way, the value of the leading zeros of the 64-bit number is calculated. For example, for a 64-bit number 0x0000000012345678, the number of leading zeros is 32.

[0030] In some embodiments, the preprocessing module 10 is further configured to normalize the dividend and the divisor by left-shifting the leading zeros of the dividend and the divisor by the number of leading zeros. The shifting algorithm is implemented according to a barrel shifter, and the low 2 bits of the shift control signal control the shifting of 0-3 bits, the middle 2 bits control the shifting of 4-12 bits, and the high 2 bits control the shifting of 16-48 bits. The final shifting result is obtained through three iterations, and the combination logic is implemented as shown in Figure 4 For example, if the number of leading zeros of the dividend is 8, the dividend is left-shifted by 8 bits.

[0031] Thus, the preprocessing module 10 obtains the dividend and the divisor that are normalized after being extended to 64-bit width and taking absolute values and eliminating leading zeros.

[0032] In some embodiments, the preprocessing module 10 is further configured to calculate the number of iterations of the Radix-16 division operation according to the difference in the number of leading zeros. The difference in the number of leading zeros is the number of leading zeros of the dividend minus the number of leading zeros of the divisor; and the number of iterations iter_num can be calculated by the following formula: ; wherein, represents the difference in the number of leading zeros, , represents the number of leading zeros of the dividend, represents the number of leading zeros of the divisor.

[0033] In some embodiments, the preprocessing module 10 is further configured to perform an exception judgment on the divisor and the dividend. In this embodiment, the preprocessing module 10 judges whether the divisor is zero by detecting the number of leading zeros of the absolute value of the divisor. If the number of leading zeros of the absolute value of the divisor is 64, it means that the divisor is 0. For example, when the binary representation of the divisor is 64-bit all zeros (i.e., `64'h0000_0000_0000_0000`), the number of leading zeros is 64, and the preprocessing module 10 recognizes that this is a division by zero exception. The preprocessing module 10 can output an error flag signal to notify the external controller that the current operation is abnormal, and at the same time stop the subsequent iteration operation to avoid invalid calculation and possible damage to the hardware. In mathematical operations, it is meaningless to divide by zero, and performing a division by zero operation in a hardware circuit may cause the circuit to enter an abnormal state, produce unpredictable results, or even damage the hardware. Therefore, judging whether the divisor is zero can effectively avoid such situations.

[0034] In addition, in the embodiment, the preprocessing module 10 is also used to judge whether the dividend is less than the divisor. If the leading zero count of the dividend is greater than the leading zero count of the divisor, the dividend is less than the divisor. For example, the leading zero count of the dividend is 40, and the leading zero count of the divisor is 30, so it can be judged that the dividend is less than the divisor. When it is judged that the dividend is less than the divisor, the divider can directly output the result that the quotient is 0 and the remainder is the dividend, without subsequent iterative operation. In this way, a large number of meaningless calculation steps can be avoided, and the performance of the divider can be improved.

[0035] In the embodiment, the Radix-16 operation of one iteration is cascaded with four SRT2 division operations in a single cycle, and the CSA structure is used to realize parallel calculation of the 69-bit partial remainder carry chain (rem_carry) and the 69-bit partial remainder sum (rem_sum) in order to optimize the critical path timing.

[0036] In order to eliminate the iteration phase deviation, a shift compensation mechanism is introduced in the embodiment, that is, the preprocessing module 10 performs shift compensation and 69-bit zero padding expansion on the dividend to obtain the initialized partial remainder, and performs shift compensation and 69-bit zero padding expansion on the divisor to obtain the initialized divisor d.

[0037] In some embodiments, the preprocessing module 10 performs shift compensation and 69-bit zero padding expansion on the dividend to obtain the initialized partial remainder in the following manner: b1. The shift parameter is obtained by performing modulo 4 operation on the leading zero count difference value, where the leading zero count difference value is the value obtained by subtracting the leading zero count of the divisor from the leading zero count of the dividend; Since the leading zero count difference value may cause phase deviation in the iteration process, the shift parameter is constructed by performing modulo 4 operation, and the normalized dividend is subjected to a shift operation to eliminate the deviation. For example, the shift parameter may be obtained by the following formula: For example, the leading zero count of the dividend is 10, and the leading zero count of the divisor is 6, so . Then, = 4, .

[0038] b2. The least significant bit (LSB) of the dividend is expanded by 3-bit zero padding to construct the intermediate operand of the dividend; The LSB of the normalized dividend is expanded by 3-bit zero padding to construct the intermediate operand , which can meet the needs of subsequent shift and calculation.

[0039] For example, the intermediate operand may be obtained by the following formula: In this embodiment, denotes the value of the dividend after being extended to 64-bit width and taking absolute value by the preprocessing module 10, and then being normalized by leading zero elimination. For example, the normalized dividend is 10101010...1010 (64 bits in total), then the extended intermediate operand = {2'b0, 10101010...1010, 3'b0}, that is, 00101010...1010000 (69 bits).

[0040] b3. The intermediate operand of the dividend is right-shifted according to the shift parameter to obtain the initialization part of the remainder.

[0041] For example, the initialization part of the remainder can be generated by an arithmetic right-shift unit . In this embodiment, the number of bits of right-shift is determined by the shift parameter , and the current bit of the initialization part of the remainder is obtained, and the carry is initialized to 0, that is, .

[0042] Meanwhile, in some embodiments, the preprocessing module 10 performs shift compensation and 69-bit zero padding extension on the divisor to obtain the initialization divisor d by the following method: 3-bit zero padding is extended to the least significant bit of the divisor to obtain the initialization divisor d.

[0043] In this embodiment, in order to ensure the consistency of the dividend and the divisor in the subsequent calculation, the same zero padding extension of the same bit width is performed on the divisor to obtain the initialization divisor d. For example, the initialization divisor d can be obtained by the following formula: , wherein denotes the value of the divisor after being extended to 64-bit width and taking absolute value by the preprocessing module 10, and then being normalized by leading zero elimination, that is, the normalized divisor.

[0044] Through the above series of operations, the dividend and the divisor are initialized, the critical path timing is optimized by using the CSA structure, the shift compensation mechanism is introduced to eliminate the iteration phase deviation, and the preparation for the subsequent iteration operation stage is made. In actual hardware design, these operations can improve the performance and stability of the divider.

[0045] In the following, the operations of the iteration calculation module 20 in the iteration calculation stage are explained and described in detail in combination with the accompanying Figure 1 .

[0046] For example, the intermediate operand of the dividend is right-shifted according to the shift parameter to obtain the initialization part of the remainder. Figure 1To realize hardware optimization of Radix-16 division operation, the application adopts a multi-stage decomposition structure, and constructs a composite iteration system in a cascading manner of four-stage Radix-2 sub-operation modules. Each stage of Radix-2 sub-operation module generates one-bit quotient, and each iteration of Radix-16 division operation runs four-stage Radix-2 sub-operation module once, and generates four-bit quotient in one iteration of Radix-16 division operation. According to this iteration mode, the final quotient value and the final remainder are generated after iter_num iterations of Radix-16 division operation. Thus, the hardware complexity of the high-base SRT unit is simplified, the four-stage Radix-2 pipelined sub-operation significantly reduces the operation period of the RISC-V division and remainder instructions, improves the operation speed, and ensures the high performance of the high-base SRT unit.

[0047] Each stage of Radix-2 sub-operation module operates according to the preset iteration recursion rule. In some embodiments, the current stage of Radix-2 sub-operation module updates the partial remainder w j , initializes the divisor d and quotient q j , and performs operation to obtain the updated partial remainder w j+1 : w j+1 = 2 w j -dq j In this embodiment, w j denotes the partial remainder of the jth iteration, d is the initialized divisor after the above series of processing of the preprocessing module, q j denotes the quotient digit of one-bit quotient of this iteration, and in this embodiment, the quotient digit set is defined as q j ∈{+1, 0, -1}, which is to facilitate calculation and control in hardware implementation. One iteration of Radix-16 division operation is four-stage Radix-2 sub-operation, so j The value of 0,1,2,3。

[0048] In this embodiment, the current stage of Radix-2 sub-operation module 200 updates the partial remainder w j according to the preset quotient selection rule to determine the one-bit quotient of the current stage of Radix-2 sub-operation q j : updates the partial remainder w jLogical left shift by one bit, and the remainder of the shifted part is truncated w j The high 3 bits of the remainder of the shifted part w j Select quotient according to the high 3 bits of the remainder of the shifted part w q j .

[0049] In some embodiments, the post-processing module combines the 1-bit quotient generated by each Radix-2 sub-operation module as a 4-bit quotient of a Radix-16 division operation in one iteration by generating the 4-bit quotient of the Radix-16 division operation according to the following formula : .

[0050] The following is an exemplary description of the operation iteration process of the 4-stage Radix-2 sub-operation module of the Radix-16 division operation in one iteration in an application example. Taking the dividend w0=600 (the initialized dividend) and the divisor d=37 (the initialized divisor) as an example, the Radix-2 sub-operation in each stage performs quotient bit selection and remainder update, and the operation iteration process of the 4-stage Radix-2 sub-operation module is as follows: 1st stage Radix-2 sub-operation (j=0): The quotient bit selection is performed according to the high 3 bits of w0=600, i.e., w0=600→binary high 3 bits=1002→q0=+1; The remainder update is performed according to the following formula: w1=2×600−37×(+1)=1200−37=1163; 2nd stage Radix-2 sub-operation (j=1): The quotient bit selection is performed according to the high 3 bits of w1=1163, i.e., w1=1163→binary high 3 bits=1000→q1=+1 The remainder update is performed according to the following formula: w2=2×1163−37×(+1)=2326−37=2289 3rd stage Radix-2 sub-operation (j=2): The quotient bit selection is performed according to the high 3 bits of w2=2289, i.e., w2=2289→binary high 3 bits=1001→q2=+1 The remainder update is performed according to the following formula: w3=2×2289−37×(+1)=4578−37=4541 4th stage Radix-2 sub-operation (j=3): The quotient is selected as follows: Based on the high 3 bits of w3=2289, select q3, w3=4541 → high 3 bits of binary = 1000 → q3=+1 The partial remainder is updated as follows: w4 = 2 × 4541 − 37 × (+1) = 9082 − 37 = 9045 Generate a 4-digit quotient for one iteration of Radix-16 division using the following formula. : .

[0051] In this embodiment, the operation cycle of RISC-V division and modulo instructions is significantly reduced by the four-level Radix-2 pipelined subprocessing, which improves the operation speed and ensures the high performance of the high-radix SRT unit.

[0052] In this embodiment, a CSA structure is used to implement the sum of the 69-bit partial remainders. j ) and carry chain j Parallel computation. In some embodiments, the current-level Radix-2 sub-operation module is also used to utilize CSA to perform partial remainder computation. w j Decompose into local and sum j With carry chain j , among which, j=0 In the case of the base and sum j To initialize some remainders, carry chain. j =0.

[0053] In some embodiments, the current-level Radix-2 sub-operation module determines the remainder based on the partial remainder in the following manner. w j The 1-digit quotient of the current level Radix-2 suboperation is determined according to the preset quotient selection rules. q j : c1. The current-level Radix-2 sub-operation module uses CSA to combine the local sum. j With carry chain j Perform a logical left shift operation by one bit each; During the quotient iteration process, the carry-over form of some remainders (sum) must first be preserved. j carry j Perform a logical left shift operation. The purpose of the left shift is to construct a suitable input base for the next iteration cycle, because in binary arithmetic, shifting left by one bit is equivalent to multiplying by 2, which meets the requirements of remainder updates in iterative operations.

[0054] For example, a logical left shift can be performed in the following way: ShiftLeft( sum j-1 , carry j-1 ,1)→( rem_sum j , rem_ carry j This indicates that the remainder of the previous period is used as the basis for the sum. sum j-1 and carry chain carry j-1 Shift left by 1 bit to obtain the input for the current iteration cycle. rem_sum j and rem_ carry j In this embodiment, initially, ( sum 0, carry 0) = ( sum init , carry init ), sum init and carry init It is the sum of the original remainders and the carry chain of the initial partial remainders obtained by the preprocessing module 10 after initializing the dividend and divisor.

[0055] c2. Extract the original value after the shift. rem_sum j The high 3 bits and the carry chain after shifting rem_carry j The high 3 bits; In the SRT-2 algorithm, a suitable quotient value {+1, 0, −1} needs to be dynamically selected based on the magnitude of the partial remainder. This is achieved by truncating and shifting the result. rem_sum j and rem_carry j The high 3 bits form the input signal. QDS in = { carry j [68:66] , sum j [68:66]} serves as the input for subsequent queries of the SRT-2 quotient selection truth table, thereby determining the appropriate quotient value.

[0056] c3. Based on the shifted position and... rem_sum j The high 3 bits and the carry chain after shifting rem_carry j The high 3 bits are used to query the quotient and select the truth table to obtain the quotient. q j .

[0057] Exemplarily, according to the input signal QDS in , based on Figure 5 the SRT-2 quotient selection truth table shown in the figure, the quotient is calculated in real time by using a combination logic circuit q j . As shown in the figure, the row of the SRT-2 quotient selection truth table represents Figure 5 rem_sum j high 3 bits of rem_sum _ msb_i [2:0], and the column of the SRT-2 quotient selection truth table represents rem_carry j high 3 bits of rem_ carry _ msb_i [2:0], for example, the initial partial remainder: (high 3 bits are filled with 0, and low 3 bits are discarded), , rem_sum 0=30,720,000 (0x01D4C0000), rem_carry 0=0, and rem_sum 0 high 3 bits (0x01D, whose high 3 bits are 01 in binary), according to the SRT-2 quotient selection truth table, the quotient q 0=+1.

[0058] In the embodiment, each Radix-2 sub-operation is implemented by a triple-operand carry-save adder (3:2 CSA) to update the partial remainder. In some embodiments, the Radix-2 sub-operation module of the current stage updates the partial remainder w j , the divisor d and the quotient q j according to the preset iterative recursion rule by performing the following operation: w j+1 : The Radix-2 sub-operation module of the current stage updates the partial remainder w j+1 by using the CSA to perform the following operation according to the following formula: j+1 j+1 : sum j+1 = rem_sum j ⊕ rem_carry j ⊕ ( q j · ​​d ), carry j+1 = Majority ( rem_sum j , rem_carry j , q j · d ), where ⊕ denotes XOR operation, rem_sum j denotes the base and sum j of the number left shifted by one bit, rem_carry j denotes the carry chain j of the number left shifted by one bit; Majority ( a , b , c ) = ( a ∧ b )∨( b ∧ c )∨( c ∧ a ), a= rem_sum j , b= rem_carry j , c= q j · d， denotes AND operation, ∨ denotes OR operation. Majority The function denotes the value that appears more frequently among the three inputs.

[0059] In the following application example, the Radix-2 sub-operation module uses CSA to decompose the partial remainder w j into the base and sum j and the carry chain j , and to perform the quotient bit selection and partial remainder update process. Taking the dividend w0=0x12345678 and the divisor d=0x123 as an example, the process of quotient bit selection and partial remainder update in the first stage of Radix-2 sub-operation for 64-bit unsigned integer division is as follows: After preprocessing and normalization of the dividend w0, the initial partial remainder is obtained sum init =0x2468ACF0, the carry chain carry init =0x0, and the initialized divisor d=0x246.

[0060] Partial remainder left shift: rem_sum j = sum init <<1 = 0x48D159E0 rem_ carry j = carry init <<1 = 0x0 Quotient calculation: Truncation rem_sum j and rem_ carry j the high 3 bits of QDS in = 0x3, according to the SRT-2 quotient selection truth table, the calculation is obtained q j =-1.

[0061] Remainder update:

[0062] = 0x48D1579A;

[0063] = 0x0 Repeat the above steps for subsequent Radix-2 sub-operations until 4 times of Radix-2 sub-operations (one iteration of Radix-16 division operation) are completed. After the end of the 4th sub-operation, the quotient obtained by 4 times of sub-operations is integrated by the phase synchronization circuit to obtain the 4-bit quotient value of this iteration of Radix-16 division operation. Then, according to the remainder update formula, the partial remainder is continuously updated, and the next Radix-16 Radix-16 division operation iteration is performed until the required precision is reached or the entire division operation is completed.

[0064] In this embodiment, the CSA can be used to calculate the carry and the place separately, avoiding the delay problem of carry propagation in the traditional adder, thereby optimizing the critical path timing. In this way, by using the quotient iteration and the iterative remainder update based on the CSA, the efficient operation of the Radix-16 integer divider is realized.

[0065] In some embodiments, the post-processing module 30 is further configured to store the 1-bit quotient generated by each Radix-2 sub-operation module into a register corresponding to the level. For example, in this embodiment, a 4-level deep and 2-bit wide register array quo_dig[3:0][1:0] is used to temporarily store the quotient. Each register corresponds to the operation result of a Radix-2 sub-operation module. The first dimension [3:0] indicates that there are 4 storage units, for example, quo_dig[0] stores the quotient generated by the first Radix-2 iteration, quo_dig[1] stores the quotient information generated by the second Radix-2 iteration, quo_dig[2] stores the quotient information generated by the third Radix-2 iteration, and quo_dig[3] stores the quotient information generated by the fourth Radix-2 iteration. The second dimension [1:0] indicates that each storage unit is 2 bits wide. Since the quotient set is defined as q j ∈{+1, 0, -1}, 2 bits are used to represent different values of the quotient: the 0th bit (LSB, least significant bit) is the +1 enable flag. When quo_dig[i][0]=1, it indicates that the quotient selected by this level iteration is +1. The 1st bit (MSB, most significant bit) is the -1 enable flag. When quo_dig[i][1]=1, it indicates that the quotient selected by this level iteration is -1. If quo_dig[i][0]=0 and quo_dig[i][1]=0, it indicates that the quotient selected by this level iteration is 0. Thus, the register array can conveniently store and manage the quotient obtained by each Radix-2 sub-operation module, and the phase synchronization circuit ensures that the results of the four iterations are synchronized and output in the fourth cycle, meeting the quotient set integration requirements of Radix-16.

[0066] Next, the operation of the post-processing module 30 in the post-processing stage is explained and described in detail.

[0067] In the iteration calculation process, the quotient is generated in the redundant signed digit (RSD) representation, and the symbol set is defined as q j ∈{+1, 0, -1}. In some embodiments, the post-processing module 30 is further configured to convert the 1-bit quotient generated by each Radix-2 sub-operation module into a corresponding standard complement quotient value, to achieve seamless compatibility with the binary complement standard.

[0068] This application employs an on-the-fly conversion architecture to implement a canonical two's complement quotient. The integer divider for Radix-16 operations provided in this embodiment further includes: a main quotient register and a candidate quotient register connected to the post-processing module 30; wherein, the main quotient register stores the main quotient canonical two's complement quotient value of the 1-bit quotient generated by each Radix-2 sub-operation module; the candidate quotient register stores the candidate quotient canonical two's complement quotient value of each Radix-2 sub-operation module. For example, the main quotient register (Q) is a 64-bit dynamic shift register, storing the canonical two's complement quotient value generated based on the current valid quotient digital stream; the candidate quotient register (Q) stores the candidate quotient value of the canonical two's complement quotient ... ): Maintains potential candidate values ​​for corrective paths to handle borrowing scenarios.

[0069] Post-processing module 30 converts the 1-bit quotient value generated by the current-level Radix-2 sub-operation module into the corresponding canonical two's complement quotient value in the following manner: Post-processing module 30 obtains the base-prime complement quotient value from the prime quotient register. The base candidate quotient canonical two's complement quotient value in the candidate quotient register In this embodiment, when the current-level Radix-2 sub-operation module is the first-level Radix-2 sub-operation module, j=0 Base main merchant standard complement merchant value And cardinal candidate quotient canonical complement quotient value Initialize to zero. ; The quotient generated by the current level Radix-2 sub-operation module q j+1 When the value is +1, the base primary quotient is normalized with complement quotient value. Shift left by one bit and fill the lower bit with 1 to get the quotient q j+1 Main Merchant Standard Supplement Code Merchant Value And write it into the master quotient register, and set the master quotient's two's complement quotient value. Shift left by one bit and fill the lower bits with 0 to get the quotient q j+1 Candidate Merchant Standard Complement Merchant Value And write it into the candidate quotient register; The quotient generated by the current level Radix-2 sub-operation module q j+1 When the base is 0, the complement quotient value will be determined by the base quotient. Shift left by one bit and fill the lower bits with 0 to get the quotient q j+1 Main Merchant Standard Supplement Code Merchant Value And write it into the master quotient register, and set the radix candidate canonical two's complement quotient value. Left shift one bit and low bit complement 1 to get quotient q j+1 candidate quotient normed complement quotient value and write into the candidate quotient register. quotient generated by the current stage Radix-2 sub-operation module q j+1 candidate quotient normed complement quotient value Left shift one bit and low bit complement 1 to get quotient q j+1 main quotient normed complement quotient value candidate quotient normed complement quotient value Left shift one bit and low bit complement 0 to get quotient q j+1 candidate quotient normed complement quotient value ; main quotient normed complement quotient value q j+1 main quotient normed complement quotient value candidate quotient normed complement quotient value q j+1 candidate quotient normed complement quotient value main quotient normed complement quotient value and candidate quotient normed complement quotient value of the base number obtained when the value of the 1-bit quotient generated by the next stage Radix-2 sub-operation module is converted into the corresponding normed complement quotient value.

[0070] Specifically, the conversion logic of converting the quotient value into the corresponding normed complement quotient can be simply understood as follows: every time a 1-bit quotient q j+1 is generated, the values of Q and are updated in real time according to the value. Let the quotient value generated by the j+1th iteration be q j+1 then the conversion logic of converting the quotient value into the corresponding normed complement quotient can be recursively generated by the following formula:

[0071]

[0072] The conversion logic of converting the quotient value into the corresponding normed complement quotient is exemplarily explained in an application example as follows. Taking the quotient bit sequence: q= [-1, 0, +1], main quotient normed complement quotient value and candidate quotient normed complement quotient value initialized to zero, i.e. Q=0000, =0000 as an example, the process of converting the value of the 1-bit quotient generated by the 4-stage Radix-2 sub-operation module into the corresponding normed complement quotient value is as follows: The quotient value generated by the 1st Radix-2 sub-operation is q1 = +1, Q left shifts 1 bit and fills 1, Q is updated to 0001; left shifts 1 bit and fills 0, updated to 0000; The quotient generated by the second Radix-2 sub-operation is q 2 = -1, Q is replaced by left shifts 1 bit and fills 1; Q is updated to 0001; left shifts 1 bit and fills 1, updated to 0001; The quotient generated by the third Radix-2 sub-operation is q 3 = 0, Q left shifts 1 bit and fills 0, Q is updated to 0010; left shifts 1 bit and fills 1, updated to 0011; The quotient generated by the fourth Radix-2 sub-operation is q 4 = +1, Q left shifts 1 bit and fills 1, Q is updated to 00101; left shifts 1 bit and fills 0, updated to 00110; Final quotient: Q = 00101 (decimal 5). Through dynamic borrow correction, even if the quotient bit sequence contains negative values, the final result is still correct.

[0073] In this embodiment, by adopting the On-the-fly quotient conversion technology, and the LUT scale is 25% of the traditional Radix-16 scheme, the hardware design is optimized, the power consumption is reduced, and it is suitable for low-power devices.

[0074] In the remainder correction phase of the division operation, when the final iteration partial remainder appears a negative value, a numerical correction operation needs to be performed. In some embodiments, in the case that the partial remainder output by the fourth Radix-2 sub-operation of the fourth iteration Radix-16 division operation is negative, the post-processing module processes the partial remainder output by the fourth Radix-2 sub-operation module of the last iteration Radix-16 division operation as the final remainder of the Radix-16 division operation in the following manner: performing numerical correction on the partial remainder output by the fourth Radix-2 sub-operation module of the last iteration Radix-16 division operation to obtain a corrected remainder, wherein the corrected remainder satisfies |corrected remainder| < |initialized divisor d|; taking the corrected remainder as the final remainder of the Radix-16 division operation.

[0075] In some embodiments, the post-processing module corrects the partial remainder output by the 4th stage Radix-2 sub-operation module of the last iteration of the Radix-16 division operation to obtain a corrected remainder by adding the initialized divisor d to the partial remainder output by the 4th stage Radix-2 sub-operation module to obtain the corrected remainder. And the quotient value is modified by subtracting 1 synchronously. In this way, the non-negative property of the remainder is ensured while the accuracy of the quotient value is maintained.

[0076] In some embodiments, in the case that the partial remainder output by the 4th stage Radix-2 sub-operation of the last iteration of the Radix-16 division operation is negative, the post-processing module 30 merges the 4-bit quotient generated by each iteration of the Radix-16 division operation as the final quotient value of the Radix-16 division operation by: obtaining the candidate quotient canonical complement value of the 1-bit quotient generated by each stage Radix-2 sub-operation module in each iteration of the Radix-16 division operation from the candidate quotient register and merging the candidate quotient canonical complement value as the final quotient value of the Radix-16 division operation. In the case that the partial remainder output by the 4th stage Radix-2 sub-operation of the last iteration of the Radix-16 division operation is positive, the post-processing module merges the 4-bit quotient generated by each iteration of the Radix-16 division operation as the final quotient value of the Radix-16 division operation by: obtaining the main quotient canonical complement value of the 1-bit quotient generated by each stage Radix-2 sub-operation module in each iteration of the Radix-16 division operation from the main quotient register and merging the main quotient canonical complement value as the final quotient value of the Radix-16 division operation.

[0077] For example, the dividend is -50, the absolute value is normalized to 50, the divisor is 7, the iteration result is quotient value = -7, partial remainder = 6. The correction operation is as follows: The partial remainder is negative, triggering correction, the corrected remainder = -1 + 7 = 6, the corrected quotient = -7 - 1 = -8. By verification, (-8) * 7 + 6 = -56 + 6 = -50, which is equal to the dividend, and it can be seen that the accuracy of the remainder and the quotient value is maintained through correction.

[0078] ​In some embodiments, the remainder symbol processing follows the dividend sign precedence principle, and the final remainder symbol flag rem_sign is determined by performing a logical AND operation between div_ctl[0] (a symbol identification bit, 1 represents signed operation, and 0 represents unsigned operation) and the sign bit of the dividend (located at dividend

[63] ). The flag will participate in the remainder correction process to ensure that the remainder symbol is strictly consistent with the dividend. If rem_sign is negative, the remainder symbol is different from the dividend. The negative value of the corrected remainder is taken. In some embodiments, the post-processing module 30 takes the corrected remainder as the final remainder of the Radix-16 division operation by the following method: according to the dividend sign precedence principle, the sign of the corrected remainder is determined to be negative; the negative value of the corrected remainder is taken, and the final remainder of the Radix-16 division operation is obtained by right shifting the value by a corresponding number of bits according to the value of the leading zero count of the divisor. Finally, the partial remainder is right shifted by the leading zero bits of the absolute value of the divisor to obtain the final calculated remainder value.

[0079] In some embodiments, the post-processing module 30 is also used for quotient value symbol adjustment. By comparing the sign bits of the dividend and the divisor (dividend

[63] and divisor

[63] ), if the signs of the two are different, the quotient value is set to negative, otherwise it is kept positive. Specifically, quotient sign = dividend sign ⊕ divisor sign. In one application example, the dividend (-50) and the divisor (+7) have different signs, quotient sign = 1 ⊕ 0 = 1, and the quotient is negative. The operation result is -8, which is directly represented in two's complement. In another application example, the dividend (+30) and the divisor (+5) have the same sign. Quotient sign = 0 ⊕ 0 = 0, and the quotient is positive. The result is +6, which is stored in original code.

[0080] The integer divider for implementing Radix-16 operation provided in the present application can be widely applied in various environments such as high-performance computing, embedded systems and Internet of Things, artificial intelligence and deep learning, financial computing, communication systems and scientific computing. By being integrated into hardware platforms such as processors, AI accelerators and embedded devices, the operation efficiency can be significantly improved, the power consumption can be reduced, and compatibility with existing network environments and technical frameworks can be achieved, which has wide application prospects and market potential.

[0081] The integer divider for implementing Radix-16 operation provided in the present application is suitable for the following application environments: 1. High-performance processor: used to accelerate integer division and remainder operation in CPU, to improve the performance of scientific computing, encryption algorithm and other scenes; 2. Digital signal processing (Digital Signal Processing, DSP): in real-time computing scenes such as image processing and audio processing, to provide efficient division and remainder operation support.

[0082] 3. Application Specific Integrated Circuit (ASIC): Integrated into specialized hardware for accelerating specific domain computing tasks, such as deep learning, cryptography, etc.

[0083] 4. Field-Programmable Gate Array (FPGA) implementation: Rapid deployment through programmable logic devices, suitable for prototype verification and customized hardware acceleration.

[0084] The integer divider for implementing Radix-16 operation provided by the embodiments of the present application adopts a multi-stage decomposition structure, and a composite iteration system is constructed by four Radix-2 sub-operation modules to realize efficient Radix-16 operation, which simplifies the hardware complexity of the high-base SRT unit, significantly reduces the operation period of the RISC-V division and remainder instructions, improves the operation speed, and ensures the high performance of the high-base SRT unit; and supports 64-bit and 32-bit RISC-V unsigned and signed integer division and remainder operations, and is suitable for different application scenarios.

[0085] An embodiment of the present application provides a method for implementing Radix-16 operation. Figure 6 A flowchart of the method for implementing Radix-16 operation is shown, which is applied to the integer divider in any of the embodiments of the present application. Figure 1 to Figure 5 The method for implementing Radix-16 operation is only briefly described below, and other details can be referred to the related description in the above integer divider for implementing Radix-16 operation. The embodiments of the method for implementing Radix-16 operation correspond to the above embodiments of the integer divider for implementing Radix-16 operation, and each implementation process and implementation manner of the above embodiments of the integer divider for implementing Radix-16 operation can be applied to the embodiments of the method for implementing Radix-16 operation, and the same technical effects can be achieved.

[0086] As shown in Figure 6 The method for implementing Radix-16 operation mainly includes the following steps (S101-S103): S101, divide the one-iteration Radix-16 division operation into four Radix-2 sub-operations; S102, in the one-iteration Radix-16 division operation, each Radix-2 sub-operation generates a one-bit quotient and updates the remainder in the following way: S1021, the current Radix-2 sub-operation obtains the initialized divisor d and the partial remainder wj , the divisor d is initialized to be generated after the initialization of the divisor; S1022, according to the partial remainder w j determine the 1-bit quotient of the current stage Radix-2 sub-operation according to the preset quotient selection rule q j , wherein, q j ∈{+1, 0, -1}, j=0,1,2,3 ; S1023, according to the preset iteration recursion rule, the partial remainder w j , initialize the divisor d and the quotient q j , and perform operations to obtain an updated partial remainder w j+1 , the updated partial remainder w j+1 , the updated partial remainder w j+1 , wherein, in the case that the current stage Radix-2 sub-operation is the first stage Radix-2 sub-operation, j=0 , the partial remainder w j is an initialization partial remainder generated after the initialization of the dividend; S103, the 1-bit quotient generated by each stage Radix-2 sub-operation is combined as a 4-bit quotient generated by one iteration Radix-16 division operation, and the 4-bit quotient generated by each iteration Radix-16 division operation is combined as the final quotient value of the Radix-16 division operation, and the partial remainder output by the fourth stage Radix-2 sub-operation of the last iteration Radix-16 division operation is processed as the final remainder of the Radix-16 division operation.

[0087] The method for implementing Radix-16 operation provided by the embodiment of the application implements Radix-16 operation by using four cascaded Radix-2 sub-operation modules, overcomes the problem of super-linear growth of hardware complexity caused by the promotion of the base k in the prior art, simplifies the hardware complexity, reduces the power consumption, and is suitable for low-power devices; significantly reduces the operation period of the RISC-V division and remainder instructions, improves the operation speed, ensures the high performance of the high-base SRT unit; and supports 64-bit, 32-bit RISC-V unsigned and signed integer division and remainder operation, and is suitable for different application scenarios.

[0088] The method for implementing Radix-16 operation provided in the embodiments of the present application mainly includes three stages: a preprocessing stage (S1), an iterative calculation stage (S2) and a post-processing stage (S3). In some embodiments, the preprocessing stage (S1) prepares for the subsequent iterative operation, and performs preprocessing on the input dividend and divisor, for example, bit width adaptation, absolute value removal, leading zero count and the like, and performs normalization and other standardization processing; the iterative calculation stage (S2) performs multiple iterative calculation of quotient and remainder through a multi-level decomposition structure, divides the Radix-16 division operation of one iteration into four levels of Radix-2 sub-operation, obtains a 4-bit quotient of the Radix-16 division operation of one iteration through the Radix-2 sub-operation, and completes the multiple iterative calculation of the Radix-16 division operation; and the post-processing stage (S3) corrects and converts the quotient and remainder obtained through the iterative calculation, so as to conform to the binary complement standard.

[0089] In the embodiments, before step S101, the method for implementing Radix-16 operation provided in the embodiments of the present application further includes preprocessing operation in the preprocessing stage. Hereinafter, the preprocessing operation in the preprocessing stage is explained and described.

[0090] In some embodiments, before step S101, the method for implementing Radix-16 operation provided in the embodiments of the present application further includes calculating the iteration number of the Radix-16 division operation according to the leading zero count difference. The leading zero count difference is the value of the leading zero count of the dividend minus the leading zero count of the divisor; specifically, the iteration number iter_num can be calculated through the following formula: ; wherein, represents the leading zero count difference, , represents the leading zero count of the dividend, represents the leading zero count of the divisor.

[0091] In the embodiments, the 4-time SRT2 division operation in a single cycle of one iteration of Radix-16 operation is cascaded, and in order to optimize the critical path timing, the CSA structure is used to realize parallel calculation of the current bit (rem_sum) and the carry chain (rem_carry) of the 69-bit partial remainder. In order to eliminate the iteration phase deviation, a shift compensation mechanism is introduced in the embodiments of the present application, that is, the preprocessing module 10 performs shift compensation on the dividend and zero padding expansion of 69-bit width to obtain the initialized partial remainder, and performs shift compensation on the divisor and zero padding expansion of 69-bit width to obtain the initialized divisor d.

[0092] In some embodiments, before step S101, the method for implementing Radix-16 operation provided by the embodiments of the present application further includes: performing shift compensation and 69-bit zero padding extension on the dividend to obtain an initial partial remainder, wherein the dividend is a value after 64-bit extension, absolute value taking, and leading zero elimination normalization; and performing shift compensation and 69-bit zero padding extension on the divisor to obtain an initial divisor d, wherein the divisor is a value after 64-bit extension, absolute value taking, and leading zero elimination normalization. In some embodiments, the input end of the preprocessing module 10 receives parameters including: a dividend (dividend[63:0]), a divisor (divisor[63:0]), a control signal (div_ctl[2:0]), and an instruction and source operand enable signal. The preprocessing module 10 performs leading zero elimination normalization on the dividend and the divisor after 64-bit extension and absolute value taking. For a specific implementation of the preprocessing module 10, refer to the above-mentioned embodiment of the integer divider for implementing Radix-16 operation, which will not be repeated here.

[0093] In some embodiments, performing shift compensation and 69-bit zero padding extension on the dividend to obtain an initial partial remainder includes: b1. obtaining a shift parameter by performing modulo 4 operation on a leading zero count difference value, wherein the leading zero count difference value is a value obtained by subtracting the leading zero count of the divisor from the leading zero count of the dividend; b2. extending 3-bit zero padding on the least significant bit of the dividend to construct a dividend intermediate operand; and b3. performing right shift operation on the dividend intermediate operand according to the shift parameter to obtain the initial partial remainder. Meanwhile, in some embodiments, performing shift compensation and 69-bit zero padding extension on the divisor to obtain an initial divisor d includes: extending 3-bit zero padding on the least significant bit of the divisor to obtain the initial divisor d. For specific application examples, refer to the above-mentioned embodiment of the integer divider for implementing Radix-16 operation, which will not be repeated here.

[0094] Through the above series of operations, the dividend and the divisor are initialized, the critical path timing is optimized by using the CSA structure, and the shift compensation mechanism is introduced to eliminate the iteration phase deviation, thereby preparing for the subsequent iteration operation stage. In actual hardware design, these operations can improve the performance and stability of the divider.

[0095] In the following, the embodiments of the present application will be described in detail with reference to the accompanying drawings. Figure 6 The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0096] To realize hardware optimization of Radix-16 division operation, the application adopts a multi-stage decomposition structure, and constructs a composite iteration system in a cascading manner of four-stage Radix-2 sub-operation modules. Each stage of Radix-2 sub-operation module generates one-bit quotient, and each iteration of Radix-16 division operation runs four-stage Radix-2 sub-operation modules once, generating four-bit quotient in one iteration of Radix-16 division operation. According to this iteration method, the final quotient value and the final remainder are generated after iter_num iterations of Radix-16 division operation. Thus, the hardware complexity of the high-base SRT unit is simplified, the four-stage Radix-2 pipelined sub-operation significantly reduces the operation period of the RISC-V division and remainder instructions, improves the operation speed, and ensures the high performance of the high-base SRT unit.

[0097] Each stage of Radix-2 sub-operation module operates according to a preset iteration recursion rule. In some embodiments, in S1023, the partial remainder w w j , the divisor d and the quotient q q j are operated to obtain the updated partial remainder w w j+1 . w j+1 = 2 w j -dq j .

[0098] In some embodiments, in S1022, according to the partial remainder w w j , the one-bit quotient q q j of the current stage of Radix-2 sub-operation is determined according to a preset quotient selection rule. w j , the partial remainder w w j is subjected to a logical left shift operation by one bit, and the high 3 bits of the shifted partial remainder w j are intercepted; and the quotient q q j is selected according to the high 3 bits of the shifted partial remainder w j .

[0099] In some embodiments, the method for realizing Radix-16 operation provided in the application further includes: decomposing the partial remainder w w j into the base sum and the carry chain carry j , wherein, in the decomposition, the partial remainder w j is subjected to a logical left shift operation by one bit, and the high 3 bits of the shifted partial remainder w j=0In the case of the base and sum j To initialize some remainders, carry chain. j =0.

[0100] In some embodiments, in step S1022, based on the partial remainder w j The 1-digit quotient of the current level Radix-2 suboperation is determined according to the preset quotient selection rules. q j Includes: The current-level Radix-2 sub-operation module uses CSA to combine the local and sum values. j With carry chain j Perform a logical left shift operation by one bit; extract the high 3 bits of the shifted sum and the high 3 bits of the shifted carry chain; based on the high 3 bits of the shifted sum and the high 3 bits of the shifted carry chain, look up the quotient in the truth table to obtain the quotient. q j .

[0101] In some embodiments, in step S1023, the partial remainder is processed according to a preset iterative recursion rule. w j Initialize the divisor d and the quotient q j Perform the calculation to obtain the updated partial remainder w j+1 include: The updated partial remainder is obtained using CSA by calculating the following formula. w j+1 The standard and sum j+1 With carry chain j+1 : sum j+1 = rem_sum j ⊕ rem_carry j ⊕ ( q j · d ), carry j+1 = Majority ( rem_sum j , rem_carry j , q j · d ), Where ⊕ represents the XOR operation, rem_sum j Indicates the base and sum j The value after shifting left by one bit,rem_carry j carry chain j left shift one bit; Majority a b c a b b c c a a= rem_sum j, b= rem_carry j c= q j · d，

[0102] In this embodiment, the CSA can be used to separate the calculation of the carry and the bit, avoiding the delay problem of the carry propagation in the traditional adder, thereby optimizing the critical path timing. In this way, the Radix-16 integer divider is realized by using the quotient value iteration and the iterative remainder update based on the CSA.

[0103] In the following, the embodiments of the application will be described in detail with reference to the accompanying drawings. Figure 6 The implementation of the post-processing stage in step S103 will be explained and described in detail.

[0104] In some embodiments, before step S103, the method for realizing Radix-16 operation provided by the embodiments of the application further includes: storing the 1-bit quotient generated by each level of Radix-2 sub-operation module into the register of the corresponding level. Exemplarily, in this embodiment, a 4-level depth, 2-bit width register array quo_dig[3:0][1:0] is used to realize the temporary storage of the quotient, and each register corresponds to the operation result of one level of Radix-2 sub-operation module. Thus, the quotient obtained by each level of Radix-2 sub-operation module can be conveniently stored and managed by the register array, and the phase synchronization circuit is used to ensure that the iteration results of the four levels are synchronized and output in the fourth cycle, thereby meeting the integration requirement of the quotient of Radix-16.

[0105] In the iteration calculation process, the quotient value is generated in the form of redundant signed digit (RSD), and the symbol set is defined as q j ​​​​​​​​​​​​∈ {+1, 0, -1}. In some embodiments, the method for implementing Radix-16 operation further comprises: converting the value of the 1-bit quotient generated by each Radix-2 sub-operation module into a corresponding normal complement quotient value, so as to achieve seamless compatibility with the binary complement standard.

[0106] In some embodiments, the method for implementing Radix-16 operation further comprises: converting the value of the 1-bit quotient generated by each Radix-2 sub-operation module into a corresponding normal complement quotient value, so as to achieve seamless compatibility with the binary complement standard. S201, obtaining the radix main quotient normal complement quotient value in the main quotient register and the radix candidate quotient normal complement quotient value in the candidate quotient register ; In some embodiments, the main quotient register is used to store the main quotient normal complement quotient value of the 1-bit quotient generated by each Radix-2 sub-operation module; the candidate quotient register is used to store the candidate quotient normal complement quotient value of each Radix-2 sub-operation module; for example, the main quotient register (Q) is a 64-bit dynamic shift register, which stores the normal complement quotient value generated based on the current effective quotient digit stream; the candidate quotient value register (Q ): maintains the potential candidate value of the correction path, which is used to handle the borrow scenario.

[0107] In some embodiments, when the current Radix-2 sub-operation module is the first Radix-2 sub-operation module, j=0 the radix main quotient normal complement quotient value and the radix candidate quotient normal complement quotient value are initialized to zero, .

[0108] S202, obtaining the quotient generated by the current Radix-2 sub-operation module q j+1 when the quotient is +1, shifting the radix main quotient normal complement quotient value one bit to the left and filling the low bit with 1 to obtain the main quotient normal complement quotient value q j+1 of the quotient , and writing it into the main quotient register; shifting the main quotient normal complement quotient value one bit to the left and filling the low bit with 0 to obtain the candidate quotient value in the candidate quotient value register q j+1 of the quotient , and writing it into the candidate quotient register; S203, obtaining the quotient generated by the current Radix-2 sub-operation module q j+1When the base is 0, the complement quotient value will be determined by the base quotient. Shift left by one bit and fill the lower bits with 0 to get the quotient q j+1 Main Merchant Standard Supplement Code Merchant Value And write it into the master quotient register, and set the radix candidate canonical two's complement quotient value. Shift left by one bit and fill the lower bit with 1 to get the quotient q j+1 Candidate Merchant Standard Complement Merchant Value And write it into the candidate quotient register; S204, the quotient generated by the current level Radix-2 sub-operation module q j+1 When the value is -1, the quotient value of the candidate canonical complement of the cardinality is... Shift left by one bit and fill the lower bit with 1 to get the quotient q j+1 Main Merchant Standard Supplement Code Merchant Value quotient of cardinality candidate canonical complement Shift left by one bit and fill the lower bits with 0 to get the quotient q j+1 Candidate Merchant Standard Complement Merchant Value ; S205, Jiang Shang q j+1 Main Merchant Standard Supplement Code Merchant Value and business q j+1 Candidate Merchant Standard Complement Merchant Value These are the radix primary quotient and radix candidate quotient obtained when converting the 1-bit quotient generated by the next-level Radix-2 sub-operation module into the corresponding canonical two's complement quotient.

[0109] For specific implementation details, please refer to the above embodiment of the integer divider implementing Radix-16 operations, which will not be repeated here.

[0110] In this embodiment, by adopting on-the-fly quotient conversion technology and using a LUT size that is 25% of the traditional Radix-16 solution, the hardware design is optimized, power consumption is reduced, and it is suitable for low-power devices.

[0111] In some embodiments, step S103, merging the 1-digit quotients generated by each Radix-2 sub-operation into a 4-digit quotient generated by one iteration of Radix-16 division, includes: generating the 4-digit quotient of the Radix-16 division operation using the following formula. : The implementation is described above in the integer divider embodiment implementing Radix-16 operation, which will not be repeated here. In this embodiment, the operation period of the RISC-V division and remainder instructions is significantly reduced by four-stage Radix-2 pipelined sub-operation, the operation speed is improved, and the high performance of the high-base SRT unit is ensured.

[0112] In this embodiment, in the remainder correction stage of the division operation, when the final iteration partial remainder appears negative, a numerical correction operation needs to be performed. In some embodiments, in the case that the partial remainder output by the fourth-stage Radix-2 sub-operation of the last iteration Radix-16 division operation is negative, the processing of the partial remainder output by the fourth-stage Radix-2 sub-operation module of the last iteration Radix-16 division operation in step S103 as the final remainder of the Radix-16 division operation includes: performing numerical correction on the partial remainder output by the fourth-stage Radix-2 sub-operation module of the last iteration Radix-16 division operation to obtain a corrected remainder, wherein the corrected remainder satisfies |corrected remainder| < |initial divisor d|; and taking the corrected remainder as the final remainder of the Radix-16 division operation. In some embodiments, the numerical correction on the partial remainder output by the fourth-stage Radix-2 sub-operation module of the last iteration Radix-16 division operation to obtain a corrected remainder includes: adding the partial remainder output by the fourth-stage Radix-2 sub-operation module to the initial divisor d to obtain the corrected remainder. And the quotient value is corrected by 1 at the same time. In this way, the non-negative property of the remainder is ensured, and the accuracy of the quotient value is maintained.

[0113] In some embodiments, in the case that the partial remainder output by the fourth-stage Radix-2 sub-operation of the last iteration Radix-16 division operation is negative, the merging of the 4-bit quotient generated by each iteration Radix-16 division operation as the final quotient value of the Radix-16 division operation in step S103 includes: merging the candidate quotient canonical complement quotient value of the 1-bit quotient generated by each stage Radix-2 sub-operation module in each iteration Radix-16 division operation from the candidate quotient register as the final quotient value of the Radix-16 division operation. In some embodiments, in the case that the partial remainder output by the fourth-stage Radix-2 sub-operation of the last iteration Radix-16 division operation is positive, the merging of the 4-bit quotient generated by each iteration Radix-16 division operation as the final quotient value of the Radix-16 division operation in step S103 includes: merging the main quotient canonical complement quotient value of the 1-bit quotient generated by each stage Radix-2 sub-operation module in each iteration Radix-16 division operation from the main quotient register as the final quotient value of the Radix-16 division operation. Through correction, the accuracy of the remainder and the quotient value is maintained.

[0114] In some embodiments, in step S103, the corrected remainder is taken as the final remainder of the Radix-16 division operation, including: determining the sign of the corrected remainder as negative according to the principle of dividend sign first; taking the negative value of the corrected remainder and right shifting the corresponding number of bits according to the value of the leading zero count of the divisor to obtain the final remainder of the Radix-16 division operation. In the embodiment, the remainder sign processing follows the principle of dividend sign first, and the final remainder sign rem_sign is determined by performing a logical AND operation between div_ctl[0] (a sign identification bit, 1 indicating signed operation and 0 indicating unsigned operation) and the sign bit of the dividend (located at dividend

[63] ). The flag will participate in the remainder correction process to ensure that the remainder sign is strictly consistent with the dividend. If rem_sign is negative, the sign of the remainder is different from that of the dividend, and the negative value of the corrected remainder is taken. In some embodiments, the post-processing module 30 takes the corrected remainder as the final remainder of the Radix-16 division operation by: determining the sign of the corrected remainder as negative according to the principle of dividend sign first; taking the negative value of the corrected remainder and right shifting the corresponding number of bits according to the value of the leading zero count of the divisor to obtain the final remainder of the Radix-16 division operation. Finally, the partial remainder is right shifted by the leading zero bits of the absolute value of the divisor to obtain the final calculation remainder value.

[0115] In the following, in an application example, the implementation of the Radix-16 operation is explained and described in detail in combination with Figure 7 and embodiments. The embodiment is only used to explain the present application and does not constitute a limitation of the present application.

[0116] As shown in Figure 7 , the method for implementing Radix-16 operation mainly includes the following steps (S101-S103): initial stage (DILE_ABS): S301, input the dividend (dividend[63:0]) and the divisor (divisor[63:0]); S302, calculate the absolute values of the divisor and the dividend; pre-processing stage PRE_0: S303, calculate the leading zero count dividend_lzc of the dividend and the leading zero count ddivisor_lzc of the divisor respectively, and left shift the number of leading zero bits for normalization; pre-processing stage PRE_1: S304, calculate the iteration number iter_num of the Radix-16 division operation according to the difference between the leading zero counts of the dividend and the divisor; S305, shift compensation and 69-bit zero padding extension are performed on the normalized dividend to obtain an initial partial remainder (current and sum and carry chain), and shift compensation and 69-bit zero padding extension are performed on the normalized divisor to obtain an initial divisor norm_d; The iterative calculation stage (SRT_ITER) includes the following steps: S306, a composite iteration system is constructed by cascading four Radix-2 sub-operation modules SRT2, each Radix-2 sub-operation module generates 1-bit quotient quo_dig and partial remainder update (sum and carry), and each Radix-16 division operation iteration runs four Radix-2 sub-operation modules, and 4-bit quotient is generated in one Radix-16 division operation iteration. The post-processing stage POST_0 includes the following steps: S307, an on-the-fly quotient real-time conversion strategy is adopted to convert each bit of quotient quo_dig into a standard complement quotient, and the quotient digits quo_dig obtained in each iteration are collected and combined to form the final quotient.

[0117] S308, it is judged whether it is a final iteration (final_iter), if yes, the partial remainder output by the fourth Radix-2 sub-operation module in the last iteration of Radix-16 division operation is corrected as the final remainder (add and shift) of Radix-16 division operation, otherwise, the step S306 is returned. The post-processing stage POST_1 includes the following steps: S309, according to the signs of the initially input divisor and dividend, the final signs of quotient and remainder are determined according to the sign rules of division, and the final division result div_res_w1 is output.

[0118] The method for implementing Radix-16 operation provided in the embodiments of the present application constructs a composite iteration system by four Radix-2 sub-operation modules to implement efficient Radix-16 operation, simplifies the hardware complexity of the high-base SRT unit, significantly reduces the operation period of the RISC-V division and remainder operation instruction, improves the operation speed, ensures the high performance of the high-base SRT unit, and supports 64-bit and 32-bit RISC-V unsigned and signed integer division and remainder operation, and is suitable for different application scenarios.

[0119] The chip provided in the embodiments of the present application includes the integer divider described above Figure 1 to Figure 5 The integer divider shown in any embodiment, and the chip is used for performing the above Figure 6 to Figure 7The method for implementing Radix-16 operation shown in any embodiment.

[0120] Figure 8 A structural block diagram of an electronic device 100 is shown in an example embodiment of the present application. The electronic device 100 can be implemented as the integer divider for implementing Radix-16 operation described above, which can be configured in an electronic device such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a smart watch, a television, or a server.

[0121] Generally, the electronic device 100 includes a chip 1000, a processor 1001, and a memory 1002 connected with the chip 1000 and the processor 1001.

[0122] The memory 1002 can include one or more computer-readable storage media that can be non-transitory. The memory 1002 can also include high-speed random access memory and nonvolatile, computer-readable storage media such as one or more magnetic disk storage devices, flash memory devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 1002 is used to store at least one instruction for being executed by the chip to implement all or part of the steps in the method for implementing Radix-16 operation shown in the method embodiments of the present application.

[0123] Those skilled in the art can understand that, Figure 8 The structure shown in the above description does not constitute a limitation on the electronic device 1000, and can include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0124] In an example embodiment, a readable storage medium is also provided, in which a program or instruction is stored, which, when executed by a processor, implements all or part of the steps in the above method for implementing Radix-16 operation. For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0125] In an example embodiment, a computer program product is also provided, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions, which, when executed by a computer, cause the computer to perform all or part of the steps in the above method for implementing Radix-16 operation. Figure 6 to Figure 7All or part of the steps of the method of implementing Radix-16 operations shown in any of the embodiments.

[0126] Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0127] It is to be understood that the application is not limited to the precise structures hereinabove described and shown in the drawings for carrying out the application and that changes can be made to the exact construction and arrangement of parts thereof without departing from the scope of the present application. The scope of the application is to be indicated by the appended claims rather than the description and drawings.

Claims

1. An integer divider implementing Radix-16 operations, comprising: The integer divider comprises a preprocessing module, an iterative calculation module and a post-processing module connected in sequence, wherein: The iterative calculation module comprises four Radix-2 sub-operation modules connected in sequence, wherein the output end of each Radix-2 sub-operation module is connected with the input end of the next Radix-2 sub-operation module, and the output end of each Radix-2 sub-operation module is connected with the post-processing module respectively; In a Radix-16 division operation in one iteration, a current Radix-2 sub-operation module generates a one-bit quotient and updates a remainder by the following method, wherein the current Radix-2 sub-operation module is any one of the four Radix-2 sub-operation modules connected in sequence: The post-processing module combines the one-bit quotient generated by each Radix-2 sub-operation module as a four-bit quotient generated by the Radix-16 division operation in one iteration, combines the four-bit quotient generated by the Radix-16 division operation in each iteration as a final quotient value of the Radix-16 division operation, and processes the partial remainder output by the fourth Radix-2 sub-operation module in the last iteration of the Radix-16 division operation as a final remainder of the Radix-16 division operation. obtaining an initialization divisor d and a partial remainder w j , the initialization divisor d being generated after the initialization of the divisor by the preprocessing module; According to the partial remainder w j According to the preset quotient selection rule, a 1-bit quotient of the current stage Radix-2 sub-operation module is determined q j wherein, q j ∈{+1, 0, -1}, j=0,1,2,3 ; According to a preset iterative recursion rule, the partial remainder is updated to obtain an updated partial remainder w j , the initialization divisor d and the quotient q j According to a preset iterative recursion rule, the partial remainder is updated to obtain an updated partial remainder w j+1 , the initialization divisor d and the quotient w j+1 output to a next Radix-2 sub-operation module, wherein, in the case that the current Radix-2 sub-operation module is a first Radix-2 sub-operation module, j=0 , the partial remainder w j is an initialization partial remainder generated after initialization of the dividend 2. The integer divider according to claim 1, wherein: The preprocessing module performs shift compensation and zero padding extension of 69-bit width on the dividend to obtain the initial partial remainder, wherein the dividend is a value after being extended to 64-bit width, taking absolute value and performing leading zero elimination normalization. The preprocessing module also performs shift compensation and zero padding extension of 69-bit width on the divisor to obtain the initial divisor d, wherein the divisor is a value after being extended to 64-bit width, taking absolute value and performing leading zero elimination normalization.

3. The integer divider according to claim 2, wherein: The preprocessing module performs shift compensation and zero padding extension of 69-bit width on the dividend to obtain the initial partial remainder by the following method: The shift parameter is obtained by performing modulo 4 operation on the leading zero count difference, wherein the leading zero count difference is a value obtained by subtracting the leading zero count of the divisor from the leading zero count of the dividend. The least significant bit of the dividend is extended by 3-bit zero padding to construct a dividend intermediate operand. The dividend intermediate operand is right-shifted by the shift parameter to obtain the initial partial remainder.

4. The integer divider according to claim 3, wherein: The preprocessing module performs shift compensation and zero padding extension of 69-bit width on the divisor to obtain the initial divisor d by the following method: The least significant bit of the divisor is extended by 3-bit zero padding to obtain the initial divisor d. -dq 5. The integer divider of claim 1, wherein, The current stage Radix-2 sub-operation module carries out the operation on the partial remainder w j , the initialization divisor d and the quotient q j to obtain the updated partial remainder w j+1 : w j+1 = 2 w j 7. The integer divider according to claim 1, wherein: j .

6. The integer divider of claim 1, wherein, The current stage Radix-2 sub-operation module determines the 1-bit quotient of the current stage Radix-2 sub-operation according to the partial remainder and the quotient selection rule w j The quotient selection rule is preset. q j : the partial remainder w j performing a logical left shift by one bit operation, truncating the partial remainder after the shift w j the high 3 bits of According to the shifted partial remainder w j of the quotient q j .

8. The integer divider according to claim 7, wherein: The current stage Radix-2 sub-operation module is further configured to utilize a carry-save adder (CSA) to add the partial remainders w j to the base and sum j and the carry chain carry j , wherein, in the case that the base and sum j=0 is equal to the initialization partial remainder, the carry chain carry j is equal to 0. j . ​ The current stage Radix-2 sub-operation module determines the 1-bit quotient of the current stage Radix-2 sub-operation according to the partial remainder and the quotient selection rule w j according to a preset quotient selection rule q j : The current stage Radix-2 sub-operation module utilizes the CSA to perform a logical left shift operation by one bit on the base and sum j and the carry chain carry j respectively; the upper 3 bits of the shifted sum and the upper 3 bits of the shifted carry chain; The quotient is obtained from a quotient select truth table according to the shifted sum and high 3 bits and the shifted carry chain high 3 bits q j .

9. The integer divider of claim 8, wherein, The current stage Radix-2 sub-operation module updates the partial remainder according to a preset iteration recursion rule by the following manner w j , the initialization divisor d and the quotient q j to obtain an updated partial remainder w j+1 : The current stage Radix-2 sub-operation module utilizes the CSA to obtain the updated partial remainder through the following formula w j+1 The native and sum j+1 And the carry chain carry j+1 : sum j+1 = rem_sum j ⊕ rem_carry j ⊕ ( q j · d )， carry j+1 = Majority ( rem_sum j ， rem_carry j ， q j · d )， wherein denotes an exclusive OR operation, rem_sum j denotes the native and sum j the value after left shifting by one bit, rem_carry j denotes the carry chain carry j the value after left shifting by one bit; Majority a , b , c ) = ( a ∧ b ) ∨ ( b ∧ c ) ∨ ( c ∧ a ), a=rem_sum j, b= rem_carry j , c= q j · d， denotes an AND operation and ∨ denotes an OR operation.​ 10. The integer divider of claim 1, wherein, the post-processing module is further configured to store the 1-bit quotient generated by each Radix-2 sub-operation module into a corresponding register; and convert the value of the 1-bit quotient generated by each Radix-2 sub-operation module into a corresponding normal-complement quotient value.

11. The integer divider of claim 10, wherein Further comprising: a main quotient register and a candidate quotient register; wherein the main quotient register is configured to store the main normal-complement quotient value of the 1-bit quotient generated by each Radix-2 sub-operation module; and the candidate quotient register is configured to store the candidate normal-complement quotient value of each Radix-2 sub-operation module; the post-processing module is configured to convert the value of the 1-bit quotient generated by the current Radix-2 sub-operation module into a corresponding normal-complement quotient value in the following manner: The post-processing module acquires a radix main quotient normal complement quotient value in the main quotient register and a radix candidate quotient normal complement quotient value in the candidate quotient register , wherein, in the case that the current stage Radix-2 sub-operation module is a first stage Radix-2 sub-operation module, j=0 the radix main quotient normal complement quotient value and the radix candidate quotient normal complement quotient value are initialized to zero; the quotient generated by the current stage Radix-2 sub-operation module q j+1 the main quotient norm-complement quotient value of the quotient left shift one bit and low bit fill 1 to obtain the quotient q j+1 the main quotient norm-complement quotient value of the quotient and write into the main quotient register, the main quotient norm-complement quotient value of the quotient left shift one bit and low bit fill 0 to obtain the quotient q j+1 the candidate quotient norm-complement quotient value of the quotient and write into the candidate quotient register; the quotient generated by the current stage Radix-2 sub-operation module q j+1 the main quotient norm-complement quotient value of the base left shift one bit and low bit fill 0 to get the quotient q j+1 the main quotient norm-complement quotient value of the base and write into the main quotient register, the base candidate norm-complement quotient value left shift one bit and low bit fill 1 to get the quotient q j+1 the candidate quotient norm-complement quotient value of the base and write into the candidate quotient register; the quotient generated by the current stage Radix-2 sub-operation module q j+1 the quotient of the radix candidate normal complement value left shift one bit and low bit complement 1 to obtain the quotient q j+1 the main quotient normal complement value of the quotient of the radix candidate normal complement value left shift one bit and low bit complement 0 to obtain the quotient q j+1 the candidate quotient normal complement value of ; the quotient q j+1 the radix main quotient norm-complement quotient value and the quotient q j+1 the radix candidate quotient norm-complement quotient value the radix main quotient norm-complement quotient value and the radix candidate quotient norm-complement quotient value are obtained when converting the value of the 1-bit quotient generated by the next-level Radix-2 sub-operation module into the corresponding norm-complement quotient value.

12. The integer divider of claim 11, wherein, in the case that the partial remainder output by the 4th Radix-2 sub-operation is negative, the post-processing module is configured to process the partial remainder output by the 4th Radix-2 sub-operation module of the last iteration of the Radix-16 division operation as the final remainder of the Radix-16 division operation in the following manner: numerically correct the partial remainder output by the 4th Radix-2 sub-operation module of the last iteration of the Radix-16 division operation to obtain a corrected remainder, wherein the corrected remainder satisfies |the corrected remainder| < |the initialized divisor d|; take the corrected remainder as the final remainder of the Radix-16 division operation.

13. The integer divider of claim 12, wherein, the post-processing module is configured to numerically correct the partial remainder output by the 4th Radix-2 sub-operation module of the last iteration of the Radix-16 division operation to obtain a corrected remainder in the following manner: add the initialized divisor d to the partial remainder output by the 4th Radix-2 sub-operation module to obtain the corrected remainder.

14. The integer divider of any one of claims 11 to 13, wherein, in the case that the partial remainder output by the 4th Radix-2 sub-operation of the last iteration of the Radix-16 division operation is negative, the post-processing module is configured to combine the 4-bit quotient generated by each iteration of the Radix-16 division operation as the final quotient value of the Radix-16 division operation in the following manner: The candidate quotient standard complement quotient value of the 1-bit quotient generated by the Radix-2 sub-operation module in each stage of each iteration of the Radix-16 division operation is obtained from the candidate quotient register and is merged as the final quotient value of the Radix-16 division operation. In the case that the partial remainder output by the fourth stage Radix-2 sub-operation of the last iteration of the Radix-16 division operation is a positive value, the post-processing module generates the 4-bit quotient of each iteration of the Radix-16 division operation in the following manner and merges it as the final quotient value of the Radix-16 division operation: The main quotient standard complement quotient value of the 1-bit quotient generated by the Radix-2 sub-operation module in each stage of each iteration of the Radix-16 division operation is obtained from the main quotient register and is merged as the final quotient value of the Radix-16 division operation.

15. The integer divider of claim 13, wherein, The post-processing module merges the corrected remainder as the final remainder of the Radix-16 division operation in the following manner: The sign of the corrected remainder is determined to be negative according to the rule of dividend sign first; The negative value of the corrected remainder is taken and is right-shifted by a corresponding number of bits according to the value of the leading zero count of the divisor to obtain the final remainder of the Radix-16 division operation.

16. The integer divider of claim 1, wherein, The post-processing module merges the 1-bit quotient generated by each stage Radix-2 sub-operation module as the 4-bit quotient of each iteration of the Radix-16 division operation in the following manner: The 4-bit quotient of the Radix-16 division operation is generated by the following equation : 。 17. The integer divider of claim 3, wherein, The pre-processing module is further configured to calculate the number of iterations of the Radix-16 division operation according to the difference value of the leading zero count.

18. A method of implementing Radix-16 operations, characterized by, The method is applied to the integer divider of any one of claims 1-17, and the method comprises: dividing each iteration of the Radix-16 division operation into four stages of Radix-2 sub-operations; each stage of Radix-2 sub-operation in each iteration of the Radix-16 division operation generates a 1-bit quotient and updates the remainder in the following manner: The current stage Radix-2 sub-operation obtains an initialization divisor d and a partial remainder w j , wherein the initialization divisor d is generated after the initialization of the divisor; According to the partial remainder w j determining the 1-bit quotient of the current stage Radix-2 sub-operation according to the preset quotient selection rule q j wherein, q j ∈{+1, 0, -1}, j=0,1,2,3 ; According to a preset iterative recursion rule, the partial remainder w j , the initialization divisor d and the quotient q j An operation is performed to obtain an updated partial remainder w j+1 , the updated partial remainder w j+1 The partial remainder is input to a next stage Radix-2 sub-operation w j+1 , wherein, in the case that the current stage Radix-2 sub-operation is the first stage Radix-2 sub-operation, j=0 , the partial remainder w j Is an initialization partial remainder generated after the initialization of the dividend the 1-bit quotient generated by each stage of the Radix-2 sub-operation is merged as the 4-bit quotient generated by each iteration of the Radix-16 division operation, the 4-bit quotient generated by each iteration of the Radix-16 division operation is merged as the final quotient value of the Radix-16 division operation, and the partial remainder output by the fourth stage Radix-2 sub-operation of the last iteration of the Radix-16 division operation is processed as the final remainder of the Radix-16 division operation.

19. A chip, the chip comprising the integer divider of any one of claims 1-17, and the chip is configured to execute the method for implementing Radix-16 operation of claim 18.

20. An electronic device, comprising: The electronic device comprises: the chip of claim 19; and a memory connected to the processor. The electronic device comprises: the chip of claim 19; and a memory connected to the processor. The memory stores programs or instructions executable on the processor, and the programs or instructions, when executed by the chip, implement the steps of the method for implementing Radix-16 operation as claimed in claim 18.

Images