Command execution method and device, equipment and storage medium
By sharing a buffer to store timing control scripts across multiple channels of the NAND Flash controller and employing an arbitration mechanism, the problems of wasted storage resources and increased area in multi-channel controllers are solved, achieving efficient resource utilization and cost reduction.
Patent Information
- Application Number
- CN202511079456.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-01
- Publication Date
- 2025-11-07
AI Technical Summary
In traditional NAND Flash controllers, the multi-channel architecture leads to wasted storage resources and increased total area, and the timing control scripts stored in a single timing control module have a lot of complexity and repetitive content.
The timing control script file is stored in a shared buffer for multiple channels, and efficient reuse is achieved through an arbitration mechanism to reduce redundant storage. The timing control instructions are obtained and parsed in an arbitration order.
This reduces storage resource waste and total area of multi-channel NAND Flash controllers, thereby lowering manufacturing costs.
Smart Images
Figure CN120909654A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of command execution, in particular to a command execution method, device, equipment and storage medium. BACKGROUND
[0002] With the rapid development of NAND Flash (Not AND Flash, a kind of flash memory using non-linear macro cell mode), the capacity and performance requirements of storage devices are constantly increasing, and the design of NAND Flash controller also faces new challenges. The traditional NAND Flash controller usually adopts a multi-channel (Channel) architecture, each channel is equipped with an independent timing control module for accurate control of the signal timing of NAND Flash. And each timing control module stores a timing control script, which contains all the timing control instructions required by NAND Flash in the normal working scenario, so that when the NAND Flash controller is working normally, the signal timing of NAND Flash is controlled by parsing and executing these timing control instructions.
[0003] However, with the evolution of NAND Flash, the complexity and storage requirements of the timing control script have increased significantly, and the storage space required by a single timing control module has reached 8K instruction depth. When the NAND Flash controller contains more channels, it can easily cause the total area of the NAND Flash controller to increase significantly, and the timing control script stored in each timing control module may contain a large amount of repetitive content, which can easily cause waste of storage resources of the NAND Flash controller.
[0004] Therefore, how to reduce the storage resource waste and total area of the multi-channel NAND Flash controller is a problem that needs to be solved by those skilled in the art. SUMMARY
[0005] The purpose of the embodiments of the present application is to provide a command execution method, device, equipment and storage medium, which can reduce the storage resource waste of the multi-channel NAND Flash controller and the total area of the multi-channel NAND Flash controller. The specific scheme is as follows:
[0006] In a first aspect, the present application provides a command execution method applied to a NAND Flash controller, the NAND Flash controller comprising a plurality of channels, and each channel being configured with an independent timing control module, the method comprising:
[0007] acquiring, by each timing control module, a target operation command for the NAND Flash, and generating a corresponding instruction acquisition request based on the target operation command acquired by each timing control module.
[0008] arbitrating execution sequences of the instruction acquisition requests to obtain an arbitration sequence;
[0009] acquiring, according to the arbitration sequence, target timing control instructions corresponding to the instruction acquisition requests from script files in the shared cache area in sequence, and returning the target timing control instructions to the corresponding timing control modules; wherein the script files include a plurality of timing control instructions generated based on operation commands for the NAND Flash;
[0010] analyzing, by the timing control modules respectively, the corresponding target timing control instructions, and executing, according to timing control information obtained after the analysis, corresponding target operation commands for the NAND Flash.
[0011] Optionally, the target operation commands for the NAND Flash are acquired by the timing control modules respectively, including:
[0012] monitoring, by any timing control module, whether the command prefetch signal is high in real time; the any timing control module is any one of the timing control modules;
[0013] if the command prefetch signal is high, detecting whether a preset command cache is empty; the preset command cache is used to store operation commands for the NAND Flash acquired through a preset hardware interface;
[0014] if the preset command cache is not empty, acquiring the target operation commands for the NAND Flash from the preset command cache, and pulling down the command prefetch signal;
[0015] if the preset command cache is empty, acquiring the target operation commands for the NAND Flash from a preset command queue according to a command priority, and pulling down the command prefetch signal; the preset command queue is used to store operation commands for the NAND Flash issued by firmware.
[0016] Optionally, the preset command queue includes a first preset command queue used to store first operation commands and a second preset command queue used to store second operation commands; wherein the command priority of the first operation commands is higher than the command priority of the second operation commands.
[0017] Correspondingly, the target operation commands for the NAND Flash acquired from the preset command queue according to the command priority include:
[0018] judging whether the first preset command queue is empty;
[0019] if the first preset command queue is not empty, acquiring the target operation commands for the NAND Flash from the first preset command queue.
[0020] If the first preset command queue is empty, a target operation command for the NAND Flash is obtained from the second preset command queue.
[0021] Optionally, the method further comprises:
[0022] If any channel obtains a current operation command for the NAND Flash issued by the firmware, the current operation command is classified to obtain a classification result; any channel is any one of the plurality of channels;
[0023] If the classification result indicates that the current operation command is a command not involving read / write operation or an execution duration of the current operation command is less than a preset duration threshold, a command priority of the current operation command is set as a high priority, and the current operation command is written into the first preset command queue;
[0024] If the classification result indicates that the current operation command is a command involving read / write operation or the execution duration of the current operation command is not less than the preset duration threshold, the command priority of the current operation command is set as a low priority, and the current operation command is written into the second preset command queue.
[0025] Optionally, according to the arbitration order, a target timing control instruction corresponding to the instruction obtaining request is obtained from the script file in the shared cache area, and the target timing control instruction is returned to the corresponding timing control module, including:
[0026] According to the arbitration order, a current to-be-executed instruction obtaining request is determined from the instruction obtaining requests;
[0027] An instruction start address is parsed from the current to-be-executed instruction obtaining request;
[0028] Based on the instruction start address, a target timing control instruction corresponding to the current to-be-executed instruction obtaining request is obtained from the script file in the shared cache area;
[0029] A start flag bit and an end flag bit are added to a head and a tail of the target timing control instruction respectively to obtain an added target timing control instruction;
[0030] The added target timing control instruction is returned to the corresponding timing control module, so that the timing control module stores the added target timing control instruction into the first preset instruction queue.
[0031] Optionally, the corresponding target timing control instruction is parsed by each timing control module, including:
[0032] The second preset instruction queue is monitored in real time by any timing control module;
[0033] If the second preset instruction queue is empty, a target timing control instruction is read from the first preset instruction queue, and the read target timing control instruction is stored in the second preset instruction queue; wherein, in the process of reading the target timing control instruction from the first preset instruction queue, if an end flag bit or the second preset instruction queue is full, the operation of reading the target timing control instruction from the first preset instruction queue is ended;
[0034] If the second preset instruction queue is not empty, a target timing control instruction is obtained from the second preset instruction queue, and the obtained target timing control instruction is parsed.
[0035] Optionally, the method further comprises:
[0036] If the second preset instruction queue is not empty, the command pre-fetch signal is pulled high, so that any timing control module obtains a next target operation command for the NAND Flash, generates a new instruction obtaining request based on the next target operation command, receives a new target timing control instruction corresponding to the new instruction obtaining request, and stores the new target timing control instruction in the first preset instruction queue.
[0037] In a second aspect, the application provides a command execution device applied to a NAND Flash controller, the NAND Flash controller comprising a plurality of channels, and each channel being configured with an independent timing control module, the device comprising:
[0038] A request generation module, configured to obtain target operation commands for the NAND Flash through the timing control modules respectively, and generate corresponding instruction obtaining requests based on the obtained target operation commands respectively;
[0039] A request arbitration module, configured to arbitrate the execution sequences of the instruction obtaining requests to obtain an arbitration sequence;
[0040] An instruction obtaining module, configured to obtain target timing control instructions corresponding to the instruction obtaining requests from a script file in the shared cache area according to the arbitration sequence, and return the target timing control instructions to the corresponding timing control modules; wherein, the script file comprises a plurality of timing control instructions generated based on the operation commands for the NAND Flash;
[0041] A command execution module, configured to parse the corresponding target timing control instructions through the timing control modules respectively, and execute the corresponding target operation commands on the NAND Flash according to the timing control information obtained after the parsing.
[0042] In a third aspect, the application provides an electronic device, comprising:
[0043] a memory for storing the computer program;
[0044] a processor for executing the computer program to implement the steps of the aforementioned command execution method.
[0045] In a fourth aspect, the present application provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the aforementioned command execution method.
[0046] The method of the present application is applied to a NAND Flash controller, and the NAND Flash controller comprises a plurality of channels, and each channel is configured with an independent timing control module, wherein the method of the present application specifically comprises: obtaining a target operation command for the NAND Flash through each timing control module respectively, and generating a corresponding instruction obtaining request based on the target operation command obtained respectively; arbitrating the execution sequence of each instruction obtaining request to obtain an arbitration sequence; obtaining a target timing control instruction corresponding to the instruction obtaining request from a script file in a shared cache area in turn according to the arbitration sequence, and returning the target timing control instruction to the corresponding timing control module; wherein the script file comprises a plurality of timing control instructions generated based on each operation command for the NAND Flash; each timing control module respectively analyzes the corresponding target timing control instruction, and executes the corresponding target operation command on the NAND Flash according to the timing control information obtained after the analysis.
[0047] Beneficial effects: The present application generates all timing control instructions required by the NAND Flash in a normal working scenario based on all operation commands for the NAND Flash, stores all timing control instructions required by the NAND Flash in the normal working scenario into a script file, then stores the script file in a shared cache area of a plurality of channels, and realizes efficient reuse of the script file through an arbitration mechanism, compared with storing the script file in the timing control modules in the plurality of channels respectively, the present application can obviously reduce a large amount of resource waste caused by repeated storage of the script file, and can reduce the storage resources required by the multi-channel NAND Flash controller and the total area of the multi-channel NAND Flash controller, thereby reducing the manufacturing cost of the NAND Flash controller. BRIEF DESCRIPTION OF DRAWINGS
[0048] In order to more clearly illustrate the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.
[0049] Figure 1 A command execution method flow chart provided for an embodiment of the present application;
[0050] Figure 2 A four-channel NAND Flash controller schematic diagram provided for an embodiment of the present application;
[0051] Figure 3 A specific timing control module structure diagram provided for an embodiment of the present application;
[0052] Figure 4 A command execution device structure schematic diagram provided for an embodiment of the present application;
[0053] Figure 5 An electronic device structure diagram provided for an embodiment of the present application. DETAILED DESCRIPTION
[0054] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.
[0055] The terms “include” and “have” and any variations in the specification and above drawings of the present application, as well as any variations related to “include” and “have”, are intended to cover the inclusions without exclusivity. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can include steps or units not listed.
[0056] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.
[0057] With the evolution of NAND Flash, the complexity of timing control scripts and storage requirements have increased significantly, and the storage space required by a single timing control module has reached 8K instruction depth. When a NAND Flash controller contains a large number of channels, it is easy to cause a significant increase in the total area of the NAND Flash controller, and there may be a large amount of repeated content in the timing control scripts stored in each timing control module, which is easy to cause waste of storage resources of the NAND Flash controller. Therefore, the present application provides a command execution method, which can reduce the waste of storage resources of a multi-channel NAND Flash controller and the total area of the multi-channel NAND Flash controller by storing script files in a shared cache area of multiple channels and implementing efficient reuse of the script files through an arbitration mechanism.
[0058] Referring to Figure 1 As shown in the figure, the embodiment of the application provides a command execution method, which is applied to a NAND Flash controller, the NAND Flash controller comprises a plurality of channels, and each channel is configured with an independent timing control module, and the method of the application comprises the following steps:
[0059] In step S11, the target operation command for the NAND Flash is acquired by each timing control module respectively, and the corresponding instruction acquisition request is generated based on the target operation instruction acquired by each timing control module.
[0060] The NAND Flash controller in the embodiment comprises a plurality of channels, and the structures of the plurality of channels are completely same, which can execute the operation command for the NAND Flash in parallel, and each channel is configured with an independent timing control module for accurately controlling the execution time of the operation command for the NAND Flash. It should be noted that the plurality of channels in the NAND Flash controller are connected with the plurality of NAND Flash one by one, that is, different channels are connected with different NAND Flash.
[0061] In the embodiment, the NAND Flash controller acquires the target operation command for the NAND Flash by the timing control module in the plurality of channels respectively, and generates the corresponding instruction acquisition request based on the target operation instruction acquired by each timing control module. It should be noted that the target operation command for the NAND Flash includes but is not limited to the write operation command, the read operation command, the erase operation command, etc.
[0062] Specifically, in the process of acquiring the target operation command for the NAND Flash by each timing control module, for any one of the timing control modules, denoted as any timing control module, it is monitored by the any timing control module whether the command prefetch signal is high; if the command prefetch signal is low, it is continuously monitored whether the command prefetch signal is high. If the command prefetch signal is high, it is detected whether the preset command cache is empty; wherein the preset command cache is used to store the operation command for the NAND Flash acquired through the preset hardware interface; if the preset command cache is not empty, the target operation command for the NAND Flash is acquired from the preset command cache, and the command prefetch signal is pulled low; if the preset command cache is empty, the target operation command for the NAND Flash is acquired from the preset command queue according to the command priority, and the command prefetch signal is pulled low; wherein the preset command queue is used to store the operation command for the NAND Flash issued by the firmware.
[0063] It should be noted that each timing control module includes a preset command cache and a preset command queue. The preset command cache is used to store the operation command for the NAND Flash obtained through the preset hardware interface, and the preset hardware interface can be an APB (Advanced Peripheral Bus) interface. The operation command for the NAND Flash obtained through the preset hardware interface is generally an initialization command for the NAND Flash, such as a Reset (reset) command, a Hard Reset (forced reset) command, a Reset LUN (reset logical unit number) command, etc. The preset command queue is used to store the operation command for the NAND Flash issued by the firmware (FW, FirmWare).
[0064] It should also be noted that each timing control module includes a timing control parameter configuration unit. The timing control parameter configuration unit provides an APB interface to the outside, so as to customize the parameters of the timing control module through the APB interface, and provide flexible configuration function. In addition, the preset command cache in each timing control module is located in the timing control parameter configuration unit.
[0065] In addition, the command prefetch signal is set to high level by default when the NAND Flash controller is initialized; the high level and the low level can be represented by 1 and 0.
[0066] In an example, the preset command queue can include a first preset command queue for storing a first operation command and a second preset command queue for storing a second operation command; wherein the command priority of the first operation command is higher than the command priority of the second operation command.
[0067] At this time, in the process of obtaining the target operation command for the NAND Flash from the preset command queue according to the command priority, it is judged by any timing control module whether the first preset command queue is empty; if the first preset command queue is not empty, the target operation command for the NAND Flash is obtained from the first preset command queue; if the first preset command queue is empty, the target operation command for the NAND Flash is obtained from the second preset command queue.
[0068] Further, if any channel obtains the current operation command for the NAND Flash issued by the firmware, the current operation command is classified to obtain a classification result; wherein any channel is any one of the plurality of channels; if the classification result indicates that the current operation command is a command not involving read / write operation or the execution duration of the current operation command is less than a preset duration threshold, the command priority of the current operation command is set to high priority, and the current operation command is written into the first preset command queue; if the classification result indicates that the current operation command is a command involving read / write operation or the execution duration of the current operation command is not less than the preset duration threshold, the command priority of the current operation command is set to low priority, and the current operation command is written into the second preset command queue.
[0069] It should be noted that, in addition to being configured with a timing control module, each channel is also configured with a command data processing module. For any one of the plurality of channels, denoted as any channel, if the command data processing module in any channel obtains the current operation command for the NAND Flash issued by the firmware, the current operation command is classified to obtain a classification result, and the classification result and the current operation command are sent to the timing control module in any channel. The timing control module in any channel will set the corresponding command priority for the current operation command according to the classification result, and write the current operation command into the corresponding preset command queue according to the command priority of the current operation command; wherein if the classification result indicates that the current operation command is a command not involving read / write operation or the execution duration of the current operation command is less than a preset duration threshold, the timing control module in any channel will set the command priority of the current operation command to high priority, and write the current operation command into the first preset command queue; if the classification result indicates that the current operation command is a command involving read / write operation or the execution duration of the current operation command is not less than the preset duration threshold, the timing control module in any channel will set the command priority of the current operation command to low priority, and write the current operation command into the second preset command queue.
[0070] Step S12, arbitration of execution order is performed on each instruction acquisition request to obtain an arbitration order.
[0071] In the embodiment of the application, in addition to containing a plurality of channels, the NAND Flash controller also contains a multi-channel arbitration module. Specifically, the NAND Flash controller sends the instruction acquisition requests of the respective channels to the multi-channel arbitration module through the timing control modules in the plurality of channels, so that the multi-channel arbitration module arbitrates the execution order of the received instruction acquisition requests to obtain an arbitration order. It should be noted that the arbitration order reflects the execution order of the instruction acquisition requests.
[0072] For the arbitration mechanism of the instruction obtaining requests, in one case, the arbitration mechanism can include: arbitrating the instruction obtaining requests according to the preset multi-channel execution sequence, to sort the instruction obtaining requests according to the multi-channel execution sequence, thereby obtaining the arbitration sequence; in another case, the arbitration mechanism can include: configuring the channel priority for each of the plurality of channels in the NAND Flash controller in advance, arbitrating the execution sequence of the instruction obtaining requests according to the channel priority from high to low, to sort the instruction obtaining requests according to the channel priority from high to low, thereby obtaining the arbitration sequence. Of course, there are other cases, which will not be described in detail here.
[0073] Taking the NAND Flash controller containing four channels as an example, if the preset multi-channel execution sequence is: the second channel→the first channel→the fourth channel→the third channel, then the arbitration sequence obtained after arbitrating the instruction obtaining requests according to the preset multi-channel execution sequence is: the instruction obtaining request of the second channel→the instruction obtaining request of the first channel→the instruction obtaining request of the fourth channel→the instruction obtaining request of the third channel.
[0074] Taking the NAND Flash controller containing four channels as an example, if the channel priority from high to low is: the priority of the second channel>the priority of the first channel>the priority of the fourth channel>the priority of the third channel, then the arbitration sequence obtained after arbitrating the instruction obtaining requests according to the channel priority from high to low is: the instruction obtaining request of the second channel→the instruction obtaining request of the first channel→the instruction obtaining request of the fourth channel→the instruction obtaining request of the third channel.
[0075] Step S13: obtaining the target timing control instruction corresponding to the instruction obtaining request from the script file in the shared cache area according to the arbitration sequence, and returning the target timing control instruction to the corresponding timing control module; wherein the script file includes a plurality of timing control instructions generated based on each operation command for the NAND Flash.
[0076] In the embodiment of the present application, in the initialization stage, the NAND Flash controller generates all timing control instructions required by the NAND Flash in the normal working scenario, such as the timing control instructions of read, write, erase and other operations, through a script generation tool such as Python, according to the timing requirements provided by the NAND Flash manufacturer and all operation commands for the NAND Flash, and then stores all timing control instructions required by the NAND Flash in the normal working scenario in the same script file, and writes the script file into the shared buffer area in the NAND Flash controller through the APB interface. The shared buffer area can be SRAM (Static Random-Access Memory).
[0077] Specifically, the NAND Flash controller can sequentially obtain the target timing control instruction corresponding to the instruction acquisition request from the script file in the shared buffer area according to the arbitration order, and return the target timing control instruction to the timing control module corresponding to the instruction acquisition request, so that each timing control module can receive the target timing control instruction corresponding to the respective instruction acquisition request.
[0078] More specifically, the NAND Flash controller determines the current to-be-executed instruction acquisition request from the arbitration order among the instruction acquisition requests, parses the instruction start address from the current to-be-executed instruction acquisition request, obtains the target timing control instruction corresponding to the current to-be-executed instruction acquisition request from the script file in the shared buffer area based on the instruction start address, and adds a start flag and an end flag to the head and tail of the target timing control instruction respectively to obtain the added target timing control instruction, and returns the added target timing control instruction to the timing control module corresponding to the current to-be-executed instruction acquisition request, so that the timing control module receives the added target timing control instruction and stores the added target timing control instruction into the first preset instruction queue.
[0079] It should be noted that the NAND Flash controller also includes a timing instruction buffer control module, and the timing instruction buffer control module includes a shared buffer area for storing a script file containing a plurality of timing control instructions.
[0080] Specifically, after the multi-channel arbitration module in the NAND Flash controller arbitrates the execution sequence of each instruction acquisition request to obtain an arbitration sequence, the multi-channel arbitration module determines a current instruction acquisition request to be executed from each instruction acquisition request according to the arbitration sequence, and sends the current instruction acquisition request to be executed to a timing instruction cache control module in the NAND Flash controller, so that the timing instruction cache control module parses an instruction start address from the current instruction acquisition request to be executed, and based on the instruction start address, acquires a target timing control instruction corresponding to the current instruction acquisition request to be executed from a script file in the shared cache area, and adds a start flag bit and an end flag bit to the head and tail of the target timing control instruction, respectively, and then returns the target timing control instruction after the addition to the timing control module corresponding to the current instruction acquisition request to be executed via the multi-channel arbitration module.
[0081] In step S14, each timing control module respectively parses the corresponding target timing control instruction, and executes a corresponding target operation command on the NAND Flash according to timing control information obtained after the parsing.
[0082] In the embodiment of the application, after each timing control module receives a target timing control instruction corresponding to a respective instruction acquisition request, each timing control module respectively parses the respective target timing control instruction to obtain corresponding timing control information, and executes a target operation command acquired by the respective timing control module on the NAND Flash according to the respective timing control information.
[0083] Specifically, for any timing control module in the timing control module, the second preset instruction queue is monitored in real time by any timing control module. If the second preset instruction queue is empty, the target timing control instruction is read from the first preset instruction queue, and the read target timing control instruction is stored in the second preset instruction queue; wherein, in the process of reading the target timing control instruction from the first preset instruction queue, if the end flag bit is read or the second preset instruction queue is full, the operation of reading the target timing control instruction from the first preset instruction queue is ended. If the second preset instruction queue is not empty, the target timing control instruction is acquired from the second preset instruction queue, the acquired target timing control instruction is parsed, and a corresponding target operation command on the NAND Flash is executed according to the timing control information obtained after the parsing.
[0084] Meanwhile, if any of the timing control modules monitors that the second preset instruction queue is not empty, the command prefetch signal is pulled high, so that any of the timing control modules obtains the next target operation command for the NAND Flash, generates a new instruction obtaining request based on the next target operation command, receives a new target timing control instruction corresponding to the new instruction obtaining request, and stores the new target timing control instruction into the first preset instruction queue.
[0085] In this way, when the second preset instruction queue is not empty, the embodiment of the present application not only executes the target operation command for the NAND Flash based on the target timing control instruction corresponding to the target operation command in the second preset instruction queue, but also simultaneously obtains the next target operation command for the NAND Flash and the target timing control instruction corresponding to the next target operation command, and stores them in the first preset instruction queue in advance. Compared with obtaining the next target operation command and the target timing control instruction corresponding to the next target operation command after executing the target operation command, the embodiment of the present application can obviously improve the efficiency of command execution and ensure the real-time performance of command execution.
[0086] It should be noted that the first preset command queue, the second preset command queue, the first preset instruction queue and the second preset instruction queue in the embodiment of the present application are all FIFO (First Input First Output) queues, which need to follow the rule of first-in first-out, and follow the rule of head-out and tail-in.
[0087] In the process that any of the timing control modules executes the corresponding target operation command for the NAND Flash according to the timing control information, if the target operation command is a write operation instruction, the timing control information indicates when to execute the write operation instruction to enter the write operation phase, and after entering the write operation phase, any of the timing control modules obtains the to-be-written data from the write data queue and writes the to-be-written data into the NAND Flash; wherein the write data queue provides a preset writing interface to the outside, so as to write the to-be-written data into the write data queue through the preset writing interface.
[0088] In the process that any of the timing control modules executes the corresponding target operation command for the NAND Flash according to the timing control information, if the target operation command is a read operation instruction, the timing control information indicates when to execute the read operation instruction to enter the read operation phase, and after entering the read operation phase, any of the timing control modules reads data from the NAND Flash and writes the read data into the read data queue, and the read data queue provides a preset reading interface to the outside, so as to read the data in the read data queue to an external module or device through the preset reading interface.
[0089] Further, in the process that any timing control module executes corresponding target operation command of the NAND Flash according to the timing control information, any timing control module will monitor the running state of the NAND Flash in real time, and write the state information into the preset state queue; wherein, the running state includes but is not limited to idle state, preparation state and busy state, etc. And the preset state queue provides a preset transmission interface to the outside, so as to read the state information in the preset state queue to the external module or device through the preset transmission interface, so that the external module or device can know the running state of the NAND Flash in time.
[0090] It should be noted that, in order to ensure that the NAND Flash can correctly identify and respond to the signals or data sent by the timing control module, the embodiment of the application also needs to format convert the signals or data output by the timing control module, and send it to the NAND Flash after format conversion, so that the NAND Flash can correctly identify and respond, ensure the effective communication between the timing control module and the NAND Flash, that is, ensure the effective communication between the NAND Flash controller and the NAND Flash.
[0091] Beneficial effect: the application generates all timing control instructions required by the NAND Flash in the normal working scenario based on all operation commands for the NAND Flash, stores all timing control instructions required by the NAND Flash in the normal working scenario into a script file, then stores the script file in the shared buffer area of multiple channels, and realizes efficient reuse of the script file through arbitration mechanism, compared with storing the script file in the timing control module in multiple channels respectively, the application can obviously reduce the large resource waste caused by repeated storage of the script file, and can reduce the storage resources required by the multi-channel NAND Flash controller and the total area of the multi-channel NAND Flash controller, thereby reducing the manufacturing cost of the NAND Flash controller.
[0092] Reference Figure 2As shown in the figure, the embodiment of the present application provides a four-channel NAND Flash controller; wherein the four-channel NAND Flash controller comprises a timing instruction cache control module, a multi-channel arbitration module and four channels (channel 0, channel 1, channel 2 and channel 3); the timing instruction cache control module comprises a shared cache area, and the shared cache area is used to store a script file, and the script file comprises all timing control instructions required by the NAND Flash in a normal working scenario; each channel comprises a command data processing module and a timing control module, and each channel is respectively connected with a corresponding NAND Flash.
[0093] Referring to Figure 3 As shown in the figure, the embodiment of the present application provides a specific timing control module, wherein the timing control module comprises a timing control parameter configuration unit, a command control submodule and an instruction execution submodule; the command control submodule comprises a first preset command queue, a second preset command queue, a control unit, a first preset instruction queue and an instruction transfer unit; the instruction execution submodule comprises a second preset instruction queue, an instruction execution unit, a format conversion unit, a write data queue, a read data queue and a preset state queue.
[0094] In the initialization phase, the NAND Flash controller sets the command prefetch signal to high level, and generates all timing control instructions required by the NAND Flash in a normal working scenario according to the timing requirements provided by the NAND Flash manufacturer and all operation commands for the NAND Flash by using a script generation tool such as Python, and stores all timing control instructions in a script file, and writes the script file into the shared cache area in the timing instruction cache control module through the APB interface.
[0095] In the running phase, the command data processing module in each channel of the NAND Flash controller obtains the current operation command for the NAND Flash issued by the firmware, classifies the current operation command to obtain a classification result, and then sends the classification result and the current operation command to the timing control module in the same channel. The timing control module in the same channel sets a corresponding command priority for the current operation command according to the classification result, and writes the current operation command into a corresponding preset command queue, such as the first preset command queue or the second preset command queue, according to the command priority of the current operation command.
[0096] Meanwhile, the control unit in the timing control module monitors whether the command prefetch signal is high in real time; if the command prefetch signal is low, the command prefetch signal is continuously monitored; if the command prefetch signal is high, it is detected whether the preset command cache in the timing control parameter configuration unit is empty; wherein the preset command cache is used to store the operation command for the NAND Flash obtained through the APB interface; if the preset command cache is not empty, the target operation command for the NAND Flash is obtained from the preset command cache, and the command prefetch signal is pulled low; if the preset command cache is empty, the target operation command for the NAND Flash is obtained from the preset command queue according to the command priority.
[0097] After obtaining the target operation command for the NAND Flash, the control unit generates an instruction obtaining request based on the target operation instruction, and sends the instruction obtaining request to the multi-channel arbitration module.
[0098] The multi-channel arbitration module arbitrates the execution order of each received instruction obtaining request to obtain an arbitration order, determines the current instruction obtaining request to be executed from each instruction obtaining request according to the arbitration order, and sends the current instruction obtaining request to be executed to the timing instruction cache control module.
[0099] The timing instruction cache control module parses the instruction start address from the current instruction obtaining request to be executed, obtains the target timing control instruction corresponding to the current instruction obtaining request to be executed from the script file of the shared cache area based on the instruction start address, adds a start flag bit and an end flag bit to the head and tail of the target timing control instruction respectively, and then returns the added target timing control instruction to the timing control module corresponding to the current instruction obtaining request to be executed through the multi-channel arbitration module, so that the control unit in the timing control module receives the added target timing control instruction and stores the added target timing control instruction in the first preset instruction queue.
[0100] Meanwhile, the instruction execution submodule in the timing control module monitors whether the second preset instruction queue is empty in real time; if the second preset instruction queue is empty, the instruction transfer signal is pulled high. The instruction transfer unit in the timing control module reads the target timing control instruction from the first preset instruction queue when the instruction transfer signal is high, and stores the read target timing control instruction in the second preset instruction queue; wherein, in the process of reading the target timing control instruction from the first preset instruction queue, if the start flag bit is read, the target operation command is sent to the instruction execution submodule; if the end flag bit is read or it is monitored that the second preset instruction queue is full, the instruction transfer signal is pulled low to end the operation of reading the target timing control instruction from the first preset instruction queue.
[0101] If the second preset instruction queue is not empty, the instruction execution unit in the instruction execution submodule obtains a target timing control instruction from the second preset instruction queue, analyzes the obtained target timing control instruction, and executes a corresponding target operation command on the NAND Flash according to the timing control information obtained after the analysis.
[0102] Meanwhile, if the second preset instruction queue is not empty, the instruction execution submodule pulls up the command pre-fetch signal, so that the control unit obtains the next target operation command for the NAND Flash when it detects that the command pre-fetch signal is at a high level, generates a new instruction obtaining request based on the next target operation command, receives a new target timing control instruction corresponding to the new instruction obtaining request, and stores the new target timing control instruction in the first preset instruction queue, thereby realizing pre-fetching of the next target operation command and the target timing control instruction corresponding to the next target operation command.
[0103] In the process of executing the corresponding target operation command on the NAND Flash according to the timing control information, if the target operation command is a write operation instruction, the instruction execution unit obtains the data to be written from the write data queue and writes the data to be written into the NAND Flash after format conversion by the format conversion unit; wherein the write data queue provides a preset write interface to the outside, so that the data to be written is written into the write data queue through the preset write interface. If the target operation command is a read operation instruction, the instruction execution unit reads data from the NAND Flash through the format conversion unit and writes the read data into the read data queue, so that the data in the read data queue is read to the external module or device through the preset read interface.
[0104] Meanwhile, in the process of executing the corresponding target operation command on the NAND Flash according to the timing control information, the instruction execution unit obtains the running state of the NAND Flash in real time through the format conversion unit and writes the state information into the preset state queue, so as to read the state information in the preset state queue to the external module or device through the preset transmission interface.
[0105] Beneficial effects: The application generates all timing control instructions required by the NAND Flash in the normal working scenario based on all operation commands for the NAND Flash, stores all timing control instructions required by the NAND Flash in the normal working scenario into a script file, then stores the script file in a shared buffer area of multiple channels, and realizes efficient reuse of the script file through an arbitration mechanism. Compared with storing the script file in the timing control modules in the multiple channels respectively, the application can obviously reduce the large resource waste caused by repeated storage of the script file, and can reduce the storage resources required by the multi-channel NAND Flash controller and the total area of the multi-channel NAND Flash controller, thereby reducing the manufacturing cost of the NAND Flash controller.
[0106] Referring to Figure 4 As shown in the figure, the embodiment of the application provides a command execution device applied to a NAND Flash controller, the NAND Flash controller comprising multiple channels, and each channel being configured with an independent timing control module, the device of the application comprising:
[0107] The request generation module 11 is configured to acquire target operation commands for the NAND Flash through each timing control module respectively, and generate corresponding instruction acquisition requests based on the target operation commands acquired respectively;
[0108] The request arbitration module 12 is configured to arbitrate the execution sequence of each instruction acquisition request to obtain an arbitration sequence;
[0109] The instruction acquisition module 13 is configured to acquire target timing control instructions corresponding to the instruction acquisition requests from the script file in the shared buffer area in turn according to the arbitration sequence, and return the target timing control instructions to the corresponding timing control module; wherein the script file comprises a plurality of timing control instructions generated based on each operation command for the NAND Flash;
[0110] The command execution module 14 is configured to analyze the corresponding target timing control instructions through each timing control module respectively, and execute the corresponding target operation commands on the NAND Flash according to the timing control information obtained after the analysis.
[0111] Since the embodiments of the device part correspond to the above-mentioned embodiments, the embodiments of the device part are described with reference to the above-mentioned embodiments of the method part, and will not be described here.
[0112] Beneficial effects: The present application generates all timing control instructions required by the NAND Flash in the normal working scenario based on all operation commands of the NAND Flash, stores all timing control instructions required by the NAND Flash in the normal working scenario into a script file, then stores the script file in a shared buffer area of multiple channels, and realizes efficient reuse of the script file through an arbitration mechanism. Compared with storing the script file in the timing control modules in the multiple channels respectively, the present application can obviously reduce the large resource waste caused by repeated storage of the script file, and can reduce the storage resources required by the multi-channel NAND Flash controller and the total area of the multi-channel NAND Flash controller, thereby reducing the manufacturing cost of the NAND Flash controller.
[0113] Further, the embodiment of the present application further discloses an electronic device, Figure 5 is an electronic device structure diagram according to an exemplary embodiment, the contents in the figure cannot be considered as any limitation on the use range of the present application. The electronic device, specifically can include: at least one processor 21, at least one memory 22, power supply 23, communication interface 24, input output interface 25 and communication bus 26. Wherein, the memory 22 is used for storing computer program, the computer program is loaded and executed by the processor 21, to realize the related steps in the command execution method disclosed by any preceding embodiment. In addition, the electronic device in the embodiment specifically can be electronic computer.
[0114] In the embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create data transmission channel between the electronic device and the external device, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the present application, which is not limited specifically herein; the input output interface 25 is used to obtain external input data or output data to the outside world, and the specific interface type can be selected according to the specific application needs, which is not limited specifically herein.
[0115] In addition, the memory 22 as the carrier of resource storage can be read-only memory, random access memory, disk or optical disk, etc., and the resources stored thereon can include operating system 221, computer program 222, etc., and the storage mode can be temporary storage or permanent storage.
[0116] The operating system 221 is configured to manage and control the various hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program capable of completing the command execution method executed by the electronic device disclosed in any of the preceding embodiments, the computer program 222 can further include a computer program capable of completing other specific work.
[0117] Further, the present application also discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to implement the command execution method disclosed above. The specific steps of the method can refer to the corresponding content disclosed in the preceding embodiments, which will not be repeated here.
[0118] Further, the present application also discloses a computer program product comprising computer programs / instructions; wherein the computer programs / instructions are executed by a processor to implement the command execution method disclosed above. The specific steps of the method can refer to the corresponding content disclosed in the preceding embodiments, which will not be repeated here.
[0119] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can refer to the method part.
[0120] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of the two. In order to clearly show the interchangeability of hardware and software, the components and steps of each example have been described in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.
[0121] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0122] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be intended to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the element.
[0123] The above describes the technical solutions provided by the present application in detail, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the examples is only for helping to understand the method and core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges can be changed, and the content of the specification should not be understood as limiting the present application.
Claims
1. A method of command execution, characterized by, The method is applied to a NAND Flash controller, the NAND Flash controller includes multiple channels, and each channel is configured with an independent timing control module, and the method includes: Each timing control module respectively acquires a target operation command for a NAND Flash, and generates a corresponding instruction acquisition request based on the target operation command acquired by each timing control module; Each instruction acquisition request is arbitrated in execution order to obtain an arbitration order; According to the arbitration order, a target timing control instruction corresponding to the instruction acquisition request is acquired from a script file of a shared cache area in sequence, and the target timing control instruction is returned to the corresponding timing control module; wherein the script file includes a plurality of timing control instructions generated based on each operation command for the NAND Flash; Each timing control module respectively analyzes the corresponding target timing control instruction, and executes the corresponding target operation command on the NAND Flash according to the timing control information obtained after the analysis.
2. The command execution method according to claim 1, wherein The method of acquiring a target operation command for a NAND Flash by each timing control module includes: Any timing control module monitors whether a command prefetch signal is high in real time; the any timing control module is any one of the timing control modules; If the command prefetch signal is high, it is detected whether a preset command cache is empty; the preset command cache is used to store operation commands for the NAND Flash acquired through a preset hardware interface; If the preset command cache is not empty, a target operation command for the NAND Flash is acquired from the preset command cache, and the command prefetch signal is pulled low; If the preset command cache is empty, a target operation command for the NAND Flash is acquired from a preset command queue according to a command priority, and the command prefetch signal is pulled low; the preset command queue is used to store operation commands for the NAND Flash issued by firmware.
3. The command execution method according to claim 2, wherein The preset command queue includes a first preset command queue used to store first operation commands and a second preset command queue used to store second operation commands; wherein the command priority of the first operation commands is higher than the command priority of the second operation commands; Correspondingly, the method of acquiring a target operation command for the NAND Flash from the preset command queue according to a command priority includes: It is judged whether the first preset command queue is empty; If the first preset command queue is not empty, a target operation command for the NAND Flash is acquired from the first preset command queue; If the first preset command queue is empty, a target operation command for the NAND Flash is acquired from the second preset command queue.
4. The command execution method according to claim 3, wherein Further comprising: If any channel acquires a current operation command for the NAND Flash issued by the firmware, the current operation command is classified to obtain a classification result; Any one of the channels is any one of the plurality of channels; If the classification result represents that the current operation command is a command not involving read-write operation or the execution duration of the current operation command is less than a preset duration threshold, a command priority of the current operation command is set as a high priority, and the current operation command is written into the first preset command queue; If the classification result represents that the current operation command is a command involving read-write operation or the execution duration of the current operation command is not less than a preset duration threshold, a command priority of the current operation command is set as a low priority, and the current operation command is written into the second preset command queue.
5. The command execution method according to claim 2, wherein The obtaining, according to the arbitration sequence, the target timing control instruction corresponding to the instruction obtaining request from the script file of the shared cache area, and returning the target timing control instruction to the corresponding timing control module, comprises: determining, from the instruction obtaining requests according to the arbitration sequence, the current instruction obtaining request to be executed; parsing an instruction start address from the current instruction obtaining request to be executed; obtaining, based on the instruction start address, the target timing control instruction corresponding to the current instruction obtaining request to be executed from the script file of the shared cache area; adding a start flag bit and an end flag bit to the head and tail of the target timing control instruction respectively to obtain the added target timing control instruction; returning the added target timing control instruction to the corresponding timing control module, so that the timing control module stores the added target timing control instruction into a first preset instruction queue.
6. The command execution method according to claim 5, wherein The parsing, by each timing control module, of the corresponding target timing control instruction, comprises: monitoring, by the any timing control module, whether a second preset instruction queue is empty in real time; if the second preset instruction queue is empty, reading the target timing control instruction from the first preset instruction queue and storing the read target timing control instruction into the second preset instruction queue; wherein, in the process of reading the target timing control instruction from the first preset instruction queue, if the end flag bit is read or the second preset instruction queue is full, the operation of reading the target timing control instruction from the first preset instruction queue is ended; if the second preset instruction queue is not empty, obtaining the target timing control instruction from the second preset instruction queue and parsing the obtained target timing control instruction.
7. The command execution method according to claim 6, wherein Further comprising: if the second preset instruction queue is not empty, pulling up the command prefetch signal, so that the any timing control module obtains a next target operation command for the NAND Flash, generates a new instruction obtaining request based on the next target operation command, receives a new target timing control instruction corresponding to the new instruction obtaining request, and stores the new target timing control instruction into the first preset instruction queue.
8. A command execution apparatus characterized by comprising: The application is applied to a NAND Flash controller, the NAND Flash controller includes multiple channels, and each channel is configured with an independent timing control module, and the device comprises: a request generation module, configured to acquire target operation commands for the NAND Flash through each timing control module respectively, and generate corresponding instruction acquisition requests based on the target operation commands acquired respectively; a request arbitration module, configured to arbitrate the execution sequence of each instruction acquisition request to obtain an arbitration sequence; an instruction acquisition module, configured to acquire target timing control instructions corresponding to the instruction acquisition requests from a script file in a shared cache area in sequence according to the arbitration sequence, and return the target timing control instructions to the corresponding timing control modules; wherein the script file includes a plurality of timing control instructions generated based on each operation command for the NAND Flash; a command execution module, configured to analyze the target timing control instructions corresponding to the timing control modules respectively, and execute the target operation commands on the NAND Flash according to the timing control information obtained after the analysis.
9. An electronic device, comprising: comprise: a memory, configured to store a computer program; a processor, configured to execute the computer program to implement the steps of the command execution method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium, and the computer program is executed by the processor to implement the steps of the command execution method according to any one of claims 1 to 7.