Data transmission method, receiving and sending unit, chip, storage medium, program

Abstract

The present disclosure provides a data transmission method, a receiving unit, a sending unit, a chip, a computer readable medium and a computer program product, and belongs to the technical field of die-to-die data transmission, which can at least partially solve the problem of large delay in existing die-to-die data transmission. The data transmission method for the receiving unit comprises the following steps: detecting an offset between a write clock and a read clock of an RX FIFO; the read clock of the RX FIFO is a local clock of the receiving unit, and the write clock is a feedforward clock generated according to a read clock of a TX FIFO; sending the offset to a sending unit; and determining a read enable of a data signal according to a valid signal.

Description

Technical Field

[0001] This disclosure relates to the field of cross-die data transmission technology, and in particular to a data transmission method, receiving unit, transmitting unit, chip, computer-readable medium, and computer program product. Background Technology

[0002] The data transmission method between different dies within a chip has a relatively large delay. Summary of the Invention

[0003] This disclosure provides a data transmission method, a receiving unit, a transmitting unit, a chip, a computer-readable medium, and a computer program product.

[0004] In a first aspect, embodiments of this disclosure provide a data transmission method for a receiving unit, wherein the receiving unit and a transmitting unit are packaged in the same chip and connected via a bare die interconnect. The receiving unit receives a data signal and a valid signal from a transmitting unit's ...

[0005] The offset between the write clock and read clock of the RX FIFO is detected; the read clock of the RX FIFO is the local clock of the receiving unit, and the write clock is a feedforward clock generated based on the read clock of the TX FIFO;

[0006] The offset is sent to the sending unit;

[0007] Based on the valid signal, the read enable of the data signal is determined.

[0008] In some embodiments, detecting the offset between the write clock and the read clock of the RX FIFO includes:

[0009] Determine the standard edge of the write clock for the RX FIFO;

[0010] The offset is defined as the difference between the standard edge and the reference edge of the read clock of the RX FIFO; the reference edge is the edge of the read clock of the RX FIFO that is closest to the standard edge.

[0011] In some embodiments, determining the read enable of the data signal based on the valid signal includes:

[0012] The valid signal is detected at the reference edge;

[0013] In response to the detected valid signal being in a valid state, the read enable of the data signal is activated;

[0014] In response to the detected valid signal changing from a valid state to an invalid state, the read enable of the data signal is turned off after a preset enable delay.

[0015] In some embodiments, the method of this disclosure further includes:

[0016] In response to the RX FIFO reset, the write pointer of the RX FIFO is set to the maximum position, and the read pointer of the RX FIFO is set to the minimum position.

[0017] Secondly, embodiments of this disclosure provide a data transmission method for a transmitting unit, wherein the transmitting unit and a receiving unit are packaged in the same chip and connected via a bare die interconnect. The transmitting unit transmits a data signal and a valid signal to the receiving unit's RX FIFO via a TX FIFO. The local clock of the transmitting unit and the local clock of the receiving unit are generated based on the same reference clock. The method includes:

[0018] The offset is received from the receiving unit; the offset is the offset between the write clock and the read clock of the RX FIFO, the read clock of the RX FIFO is the local clock of the receiving unit, and the write clock is a feedforward clock generated based on the read clock of the TX FIFO.

[0019] The read operation time of the TX FIFO and the valid signal are adjusted according to the offset.

[0020] In some embodiments, adjusting the read operation time of the TX FIFO and the valid signal according to the offset includes:

[0021] In response to A = [-t / 2, t / 2], the read clock of the TX FIFO and the valid signal are delayed by A; where A is the offset and t is the read cycle of the TX FIFO;

[0022] In response to A = (t / 2, t], the position of the read pointer of the TX FIFO is delayed by t, and the read clock of the TX FIFO and the valid signal are delayed by |A|-t;

[0023] In response to A = (-t, -t / 2), advance the position of the read pointer of the TX FIFO by t, and delay the read clock of the TX FIFO and the valid signal by t - |A|.

[0024] In some embodiments, adjusting the read operation time of the TX FIFO according to the offset and the valid signal includes:

[0025] In the initial state, the read operation time of the TX FIFO and the valid signal are adjusted according to the offset.

[0026] In operation, when the offset reaches a preset adjustment threshold, the read operation time of the TX FIFO and the valid signal are adjusted according to the offset.

[0027] In some embodiments, adjusting the read operation time of the TX FIFO and the valid signal according to the offset when the offset reaches a preset adjustment threshold includes:

[0028] In response to the presence of a data signal to be transmitted and the offset reaching a preset first adjustment threshold, the read operation time of the TX FIFO and the valid signal are adjusted according to the offset; the first adjustment threshold is equal to the maximum adjustment amount, which corresponds to the maximum adjustment range that the transmitting unit can achieve for the read clock of the TX FIFO.

[0029] In some embodiments, the method of this disclosure further includes:

[0030] In response to the absence of a data signal to be transmitted, the read clock of the TX FIFO is turned off.

[0031] In some embodiments, turning off the read clock of the TX FIFO in response to the absence of a data signal to be transmitted includes:

[0032] In response to the TX FIFO's read clock being continuously turned off for a preset time threshold, the TX FIFO's read clock is activated to send an analog data signal.

[0033] In some embodiments, adjusting the read operation time of the TX FIFO according to the offset and the valid signal includes:

[0034] In response to the offset when transmitting the analog data signal reaching a preset second adjustment threshold, the read operation time of the TX FIFO and the valid signal are adjusted according to the offset; the second adjustment threshold is less than the maximum adjustment amount, the maximum adjustment amount corresponding to the maximum adjustment range that the transmitting unit can achieve for the read clock of the TX FIFO.

[0035] Thirdly, embodiments of this disclosure provide a receiving unit, including an RX FIFO, a memory, and a processor; the memory stores a computer program executable by the processor, and when the computer program is executed by the processor, it implements any of the data transmission methods of embodiments of this disclosure.

[0036] Fourthly, embodiments of this disclosure provide a transmission unit, including a TX FIFO, a memory, and a processor; the memory stores a computer program executable by the processor, and when the computer program is executed by the processor, it implements any of the data transmission methods of embodiments of this disclosure.

[0037] Fifthly, embodiments of this disclosure provide a chip, comprising:

[0038] Reference clock;

[0039] Any receiving unit according to the embodiments of this disclosure;

[0040] Any of the transmitting units in the embodiments of this disclosure.

[0041] Sixthly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements any of the data transmission methods of embodiments of this disclosure.

[0042] In a seventh aspect, embodiments of this disclosure provide a computer program product, including a computer program that, when executed by a processor, implements any of the data transmission methods of embodiments of this disclosure.

[0043] In this embodiment, the receiving unit can detect the actual offset between the write clock and read clock of the RX FIFO, that is, the difference between the local clock of the transmitting unit and the local clock of the receiving unit, and transmit the offset to the transmitting unit. The transmitting unit can adjust the time of reading the TX FIFO according to the offset, that is, make the read clock and write clock of the RX FIFO "aligned". Therefore, the RX FIFO of this embodiment can work in the manner of "synchronous FIFO" without separate synchronization. Moreover, the above offset is a real-time value that is detected at any time, and is not the maximum drift that may occur in the entire life cycle of the chip. Therefore, it is also significantly smaller than the read and write distance set in related technologies, which can greatly reduce the latency of cross-die data transmission. Attached Figure Description

[0044] In the accompanying drawings of the embodiments disclosed herein:

[0045] Figure 1 This is a block diagram of a chip in related technologies;

[0046] Figure 2 A flowchart illustrating a method for data transmission in a receiving unit, provided as an embodiment of this disclosure;

[0047] Figure 3 A flowchart illustrating a method for data transmission in a transmitting unit, provided as an embodiment of this disclosure;

[0048] Figure 4 A block diagram of a receiving unit provided in an embodiment of this disclosure;

[0049] Figure 5 A block diagram illustrating the composition of a transmitting unit provided in an embodiment of this disclosure;

[0050] Figure 6 A block diagram of a chip provided in an embodiment of this disclosure;

[0051] Figure 7 A block diagram illustrating the composition of a computer-readable medium provided in this disclosure embodiment;

[0052] Figure 8 A system architecture diagram of the data transmission method of Example 1 provided in this disclosure embodiment;

[0053] Figure 9 This is a schematic diagram illustrating the method of determining the offset in another data transmission method according to an embodiment of this disclosure;

[0054] Figure 10 for Figure 8 A schematic diagram of the structure of a phase detector;

[0055] Figure 11 for Figure 8 A schematic diagram of a delay chain calibration circuit for a phase detector;

[0056] Figure 12 for Figure 8 A schematic diagram of the structure of a SER;

[0057] Figure 13 for Figure 8 Read and write timing of the TX FIFO in the middle;

[0058] Figure 14 for Figure 8 A schematic diagram of the structure of a type of DES;

[0059] Figure 15 for Figure 8 A detailed structural diagram of a part;

[0060] Figure 16 The following is a timing diagram for different data transmission methods in Example 1. Detailed Implementation

[0061] To enable those skilled in the art to better understand the technical solutions of this disclosure, the data transmission method, receiving unit, sending unit, chip, computer-readable medium, and computer program product provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0062] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0063] The accompanying drawings are provided to further illustrate this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. These and other features and advantages will become more apparent to those skilled in the art from the description of detailed embodiments with reference to the accompanying drawings.

[0064] Unless otherwise specified, each embodiment and feature of this disclosure may be used individually or in combination with other embodiments and features thereof.

[0065] Those skilled in the art will understand that various changes in form and detail may be made to the embodiments of this disclosure without departing from the scope of this disclosure as set forth by the appended claims.

[0066] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0067] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0068] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0069] A chip is an independent computing device that includes packaged integrated circuits, such as a central processing unit (CPU) or a general-purpose graphics processing unit (GP-GPU).

[0070] As the size of circuit structures in chips continues to shrink, approaching the quantum tunneling limit, further miniaturization becomes extremely difficult from both a technological and cost perspective. Therefore, building large systems from interconnected smaller systems becomes more economical. For this purpose, chiplet technology can be employed, i.e., referring to... Figure 1 Partial integrated circuits are formed on multiple unpackaged dies. Each die can perform some computational functions relatively independently, and die-to-die connections are set between the dies to achieve cross-die data transmission. The multiple dies and their inter-die connections are then packaged into a chip.

[0071] In some related technologies, refer to Figure 1 To enable cross-die data transmission, a first-in-first-out (FIFO) buffer can be set in both the transmitting (TX) die and the receiving (RX) die. The data to be transmitted is first written to the TX FIFO by the TX die, then read from the TX FIFO, and written to the RX FIFO via the die-to-die connection. Finally, it is read from the RX FIFO and processed by the RX die.

[0072] In some related technologies, multiple bare dies can use a "same-source clock," that is, referenced to... Figure 1 Multiple bare dies generate their own local clocks (LCLK) based on the same reference clock (ref) to control various local operations. However, due to uneven circuit layout, process technology, temperature, aging, etc., there is still a certain difference between the local clocks of different bare dies, i.e., drift, and this drift may fluctuate within a certain range as the chip is used.

[0073] Based on the above-mentioned technologies, the data writing of the RX FIFO is essentially controlled by the local clock of the TX die, and the data reading is controlled by the local clock of the RX die. Therefore, there is a drift between the local clocks of the TX die and the RX die, which is equivalent to the read clock and write clock of the RX FIFO being out of sync. Hence, the RX FIFO is an "asynchronous FIFO".

[0074] In some related technologies, to ensure that the local clock of each bare die will not cause data errors regardless of left or right drift throughout the entire life cycle of the chip, the drift buffer technology can be used. That is, after the read enable of the RX FIFO is enabled, it will pause for 2-3 clock cycles to synchronize with the read clock domain, and then pause for another 1-2 clock cycles to convert to Gray code before reading begins; the specific number of clock cycles is determined according to the maximum possible drift range of the clock.

[0075] Therefore, the RX FIFO has a relatively large "read / write distance," which necessitates a large RX FIFO depth to store data during synchronization. Its depth is typically at least 4. Furthermore, the large read / write distance significantly increases the latency of cross-die data transmission. For example, when the local clock is 2GHz, or 500ps per clock cycle, the latency of data transmission within the die is typically 2 clock cycles and 1ns. The RX FIFO's read / write distance is usually 2-4 clock cycles. Adding transmission latency, the latency of cross-die data transmission typically exceeds 10ns, failing to meet the 2ns latency requirement of the Universal Chipplet Interconnect Express (UCIe) protocol.

[0076] Firstly, referring to Figures 2 to 6 This disclosure provides a data transmission method for a receiving unit. The receiving unit and the transmitting unit are packaged in the same chip and connected by a bare die connection. The receiving unit receives data signals and valid signals from the transmitting unit's TX FIFO via an RX FIFO. The local clock of the transmitting unit and the local clock of the receiving unit are generated according to the same reference clock.

[0077] Reference Figure 6 The method disclosed in this embodiment is used in a receiving unit, which is packaged together with a transmitting unit within a chip. The receiving unit includes an RX FIFO, which is connected to the TX FIFO of the transmitting unit via a die-to-die connection. Thus, the transmitting unit can transmit data signals to the receiving unit through the TX FIFO, the die-to-die connection, and the RX FIFO. Simultaneously, the receiving unit and the transmitting unit are also connected to the same reference clock and generate their respective local clocks based on the reference clock.

[0078] According to the UCIe protocol, the transmitting unit also needs to generate a valid signal based on the local clock and send it to the receiving unit through the TXFIFO, the bare crystal connection, and the RX FIFO. The receiving unit can determine the read enable of the RX FIFO, that is, the read enable of the received data signal, based on the valid signal.

[0079] The receiving unit can be an RX bare crystal or a module within an RX bare crystal used for cross-die data transmission; the transmitting unit can be a TX bare crystal or a module within a TX bare crystal used for cross-die data transmission.

[0080] It should be understood that the TX and RX bare crystals mentioned above are determined by the direction of data transmission; however, the same bare crystal may both send data to other bare crystals and receive data from other bare crystals. Therefore, the bare crystal can be both a TX bare crystal and an RX bare crystal, and it can include both a transmitting unit and a receiving unit.

[0081] Reference Figure 2 The data transmission method in this embodiment includes:

[0082] S101. Detect the offset between the write clock and read clock of the RX FIFO.

[0083] The read clock of the RX FIFO is the local clock of the receiving unit, and the write clock is a feedforward clock generated based on the read clock of the TX FIFO.

[0084] S102, Send the offset to the sending unit.

[0085] S103. Determine the read enable of the data signal based on the valid signal.

[0086] Reference Figure 6 In this embodiment of the disclosure, the read clock of the RX FIFO is the local clock of the receiving unit, while its write clock is the feedforward clock (FWD CLK) from the transmitting unit. The feedforward clock is generated based on the read clock of the TX FIFO, that is, based on the local clock of the transmitting unit.

[0087] The local clocks of the transmitting unit and the receiving unit are generated based on the same reference clock, and their frequencies can be the same, such as 2GHz. However, the frequencies of the read clock of the TX FIFO, the write clock of the RX FIFO, and the feedforward clock can be higher than the local clock frequency, such as 8GHz.

[0088] Therefore, the difference between the write clock and read clock of the RX FIFO represents the difference between the local clock of the transmitting unit and the local clock of the receiving unit. Thus, the receiving unit can detect the offset between the write clock and read clock of the RX FIFO at any time and transmit the offset to the transmitting unit through sideband messages, etc. The transmitting unit can adjust the time of the TX FIFO's read operation and the valid signal according to the received offset, that is, adjust the time of the RX FIFO's write operation, so that the read clock and write clock of the RX FIFO are "aligned", that is, the above offset is "reset to zero". Thus, when the receiving unit generates read enable according to the valid signal, it is "equivalent" that the read operation and write operation of the RX FIFO are performed under the synchronous clock. The RX FIFO can work in the manner of "synchronous FIFO", spanning the clock domains of the TX die and the RX die.

[0089] In this embodiment, the receiving unit can detect the actual offset between the write clock and read clock of the RX FIFO, that is, the difference between the local clock of the transmitting unit and the local clock of the receiving unit, and transmit the offset to the transmitting unit. The transmitting unit can adjust the time of reading the TX FIFO according to the offset, that is, make the read clock and write clock of the RX FIFO "aligned". Therefore, the RX FIFO of this embodiment can work in the manner of "synchronous FIFO" without separate synchronization. Moreover, the above offset is a real-time value that is detected at any time, and is not the maximum drift that may occur in the entire life cycle of the chip. Therefore, it is also significantly smaller than the read and write distance set in related technologies, which can greatly reduce the latency of cross-die data transmission.

[0090] In some embodiments, detecting the offset between the write clock and read clock of the RX FIFO (S101) includes:

[0091] S1011. Determine the standard edge of the write clock for the RX FIFO.

[0092] S1012. Determine the difference between the standard edge and the reference edge of the read clock of the RX FIFO as the offset.

[0093] Among them, the reference edge is the edge that is closest to the standard edge in the read clock of the RX FIFO.

[0094] As one embodiment of this disclosure, when detecting the above offset, reference can be made to... Figure 9 First, a certain edge of the write clock of the RX FIFO, such as the falling edge, is taken as the standard edge; and the edge of the read clock of the RX FIFO that is closest to the standard edge, which may be either the rising edge or the falling edge, is taken as the reference edge; then, the difference between the reference edge and the standard edge can be detected as the offset.

[0095] For example, you can refer to Figure 9 When the reference edge is "after" the standard edge, the offset is considered positive; when the reference edge is "before" the standard edge, the offset is considered negative.

[0096] In some embodiments, determining the read enable of the data signal based on the valid signal (S103) includes:

[0097] S1031. Detect the valid signal at the reference edge.

[0098] S1032A: In response to the detected valid signal being in a valid state, enable the read signal of the data signal.

[0099] S1032B: In response to the detected valid signal changing from a valid state to an invalid state, after a preset enable delay, the read enable of the data signal is turned off.

[0100] As one embodiment of this disclosure, whenever the read clock of the RX FIFO reaches the above reference edge, a valid signal is detected, and when the valid signal is in a valid state, such as changing to valid=1, the read enable of the data signal is activated, and the read pointer of the RX FIFO begins to increment; when the valid signal is detected to change from a valid state to an invalid state, such as changing from valid=1 to valid=0, a predetermined enable delay is waited for, such as 2 local clock cycles, and the read enable of the data signal is turned off, and the read pointer no longer changes.

[0101] The valid signal is used to indicate the validity of the TX FIFO output data. It can indicate different states based on the level of different unit intervals (UI). For example, among the eight UIs of the valid signal, if the first four UIs are high or a 1 signal, it indicates a valid state; while if the last five or more UIs are low or a 0 signal, it indicates an invalid state.

[0102] In some embodiments, the data transmission method of this disclosure further includes:

[0103] S100: In response to RX FIFO reset, set the write pointer of RX FIFO to the maximum position and the read pointer of RX FIFO to the minimum position.

[0104] As one embodiment of this disclosure, when the RX FIFO is reset, such as during a power-on reset, only the read pointer can be set to the minimum position, i.e., "read pointer = 0"; the write pointer is not set to zero, but is set to the maximum position, i.e., "write pointer = max"; thus, the RX FIFO can directly read the data at position 0, instead of having to wait for the write pointer to be 1 to read the data at position 0, as is the case with asynchronous FIFOs in related technologies, which can reduce the delay by one clock cycle.

[0105] Secondly, referring to Figures 2 to 6 This disclosure provides a data transmission method for a transmitting unit. The transmitting unit and the receiving unit are packaged in the same chip and connected through a bare die connection. The transmitting unit sends a data signal and a valid signal to the receiving unit's RX FIFO through a TXFIFO. The local clock of the transmitting unit and the local clock of the receiving unit are generated based on the same reference clock.

[0106] Reference Figure 6 The method disclosed in this embodiment is used in a transmitting unit, which is packaged together with a receiving unit within a chip. The receiving unit includes an RX FIFO, which is connected to the TX FIFO of the transmitting unit via a die-to-die connection. Thus, the transmitting unit can transmit data signals to the receiving unit through the TX FIFO, the die-to-die connection, and the RX FIFO. Simultaneously, both the receiving and transmitting units are connected to the same reference clock and generate their respective local clocks based on this reference clock.

[0107] According to the UCIe protocol, the transmitting unit also needs to generate a valid signal based on the local clock and send it to the receiving unit. The receiving unit can determine the read enable of the RX FIFO, that is, the read enable of the received data signal, based on the valid signal.

[0108] The receiving unit can be an RX bare crystal or a module within an RX bare crystal used for cross-die data transmission; the transmitting unit can be a TX bare crystal or a module within a TX bare crystal used for cross-die data transmission.

[0109] It should be understood that the TX and RX bare crystals mentioned above are determined by the direction of data transmission; however, the same bare crystal may both send data to other bare crystals and receive data from other bare crystals. Therefore, the bare crystal can be both a TX bare crystal and an RX bare crystal, and it can include both a transmitting unit and a receiving unit.

[0110] Reference Figure 3 The data transmission method of this disclosure includes:

[0111] S201, Receive the offset from the receiving unit.

[0112] Here, the offset is the offset between the write clock and the read clock of the RX FIFO. The read clock of the RX FIFO is the local clock of the receiving unit, and the write clock is the feedforward clock generated based on the read clock of the TX FIFO.

[0113] S202. Adjust the read operation time and valid signal of TX FIFO according to the offset.

[0114] In this embodiment of the disclosure, after the transmitting unit receives the offset detected by the receiving unit through sideband messages or other means, it can adjust the time of the TX FIFO for reading operations and the valid signal according to the offset, that is, change the time of the RX FIFO for writing operations, so that the reading clock of the RX FIFO is "aligned" with the writing clock, that is, make the above offset "zero".

[0115] In some embodiments, adjusting the read operation time and valid signal of the TX FIFO according to the offset (S202) includes:

[0116] S2021A, in response to A=[-t / 2, t / 2], delays the read clock and valid signal of the TX FIFO by A.

[0117] Where A is the offset and t is the read cycle of the TX FIFO.

[0118] S2021B, in response to A = (t / 2, t], delay the position of the read pointer of the TX FIFO by t, and delay the read clock and valid signal of the TX FIFO by |A|-t.

[0119] S2021C, in response to A = (-t, -t / 2), advance the position of the read pointer of the TX FIFO by t, and delay the read clock and valid signal of the TX FIFO by t - |A|.

[0120] As one embodiment of this disclosure, the offset value can be recorded as A, and the read cycle of the TX FIFO can be set to t, then:

[0121] (1) When the value of A is in the range of [-t / 2, t / 2], the read clock and valid signal of TX FIFO can be delayed by A directly, such as by using a delay loop (DLL) to delay the read clock and valid signal of TX FIFO by A.

[0122] (2) When the value of A is in the range of (t / 2, t], the position of the read pointer of TX FIFO can be delayed by t, and the read clock and valid signal of TX FIFO can be delayed by |A|-t.

[0123] (3) When A is in the interval (-t, -t / 2), the position of the read pointer of TX FIFO can be advanced by t, and the read clock and valid signal of TXFIFO can be delayed by t-|A|.

[0124] It should be understood that the delay amounts for the read clock and valid signal mentioned above may be negative. Delaying the read clock and valid signal by a negative value is equivalent to advancing the read clock by the absolute value of that negative value.

[0125] Based on the above method, the maximum range of "direct delay" adjustment for the read clock and valid signal of the TX FIFO is t. However, by changing the read pointer of the TX FIFO and then "reversing" the delay of the read clock, it is possible to adjust the offset fluctuating within a larger range. That is, the fluctuation range of the offset can be 2t. For example, as long as a DLL with a maximum delay of 2t is set and its initial delay is set to t, the offset fluctuating within the range of (-t, t] can be adjusted.

[0126] In some embodiments, adjusting the read operation time and valid signal of the TX FIFO according to the offset (S202) includes:

[0127] S2022A. In the initial state, adjust the read operation time and valid signal of the TX FIFO according to the offset.

[0128] S2022B: In the working state, when the offset reaches the preset adjustment threshold, the read operation time and valid signal of TXFIFO are adjusted according to the offset.

[0129] As one embodiment of this disclosure, in the initial state, such as when the chip is powered on, the offset can be directly detected, for example, by detecting the offset based on the test data signal; and the transmitting unit can directly adjust the read operation time and valid signal of the TX FIFO based on the offset detected by the receiving unit "for the first time", that is, in the "initial adjustment", the read clock and write clock of the RX FIFO are directly "aligned".

[0130] After the chip starts working, the offset, which has already reached zero, will continue to change over time due to changes in temperature, aging, etc. After the chip enters the working state, the receiving unit can continue to detect the offset in real time, that is, to "track" the offset; however, the transmitting unit does not adjust the clock according to the offset at all times, but only when the offset is "too large", such as reaching a preset adjustment threshold, will it adjust the read operation time of the TX FIFO and the valid signal according to the offset, and re-align the read clock and write clock of the RX FIFO.

[0131] The chip's clock may oscillate within a small range, but this oscillation is small, so the resulting offset is also small and will not cause data errors, so there is no need to adjust it. According to the above method, in the working state, adjustment is only made when the offset exceeds the adjustment threshold, which can avoid unnecessary adjustments to the clock due to small-range oscillations.

[0132] In some embodiments, when the offset reaches a preset adjustment threshold, the read operation time and valid signal of the TX FIFO are adjusted according to the offset (S2022B), including:

[0133] S2022B1: In response to the presence of a data signal to be transmitted and the offset reaching a preset first adjustment threshold, adjust the read operation time and valid signal of the TX FIFO according to the offset.

[0134] The first adjustment threshold is equal to the maximum adjustment amount, which corresponds to the maximum adjustment range that the transmitting unit can achieve for the read clock time of the TX FIFO.

[0135] For an actual transmitting unit, it is impossible to adjust the clock "infinitely", but only within a certain range, which is called the "maximum adjustment amount".

[0136] As one embodiment of this disclosure, in the working state, if the transmitting unit has a data signal to transmit, the adjustment threshold of the "triggered" offset, i.e. the first adjustment threshold, can be equal to the above maximum adjustment amount, such as t and -t.

[0137] When adjusting the read operation time of the TX FIFO, it is necessary to "pause" the transmission of data signals. Therefore, when there is a data signal that is about to be transmitted, the number of adjustments should be "reduced" as much as possible. Thus, when the system is in operation and there is a data signal to be transmitted, the first adjustment threshold that triggers the adjustment can be the maximum adjustment amount mentioned above.

[0138] In some embodiments, the data transmission method of this disclosure further includes:

[0139] S204. In response to the absence of a data signal to be transmitted, turn off the read clock of the TX FIFO.

[0140] In some related technologies, the RX FIFO adopts a constant read and write mode, that is, the read clock and write clock of the RX FIFO are always on regardless of whether there is data to be transmitted, which results in high power consumption and cannot meet the power saving requirements of the UCIe protocol's dynamic acquisition (gating).

[0141] As one embodiment of this disclosure, when there is no data signal to be sent to the receiving unit, the transmitting unit can turn off the read clock of the TX FIFO, that is, turn off the feedforward clock and the write clock of the RX FIFO; and when there is a data signal to be sent again, the transmitting unit turns on the read clock of the TX FIFO, that is, turns on the feedforward clock and the write clock of the RX FIFO.

[0142] Therefore, in this embodiment of the present disclosure, the clock can be turned off when there is no actual data to be transmitted, thereby reducing energy consumption and meeting the power saving requirements of the UCIe protocol.

[0143] In some embodiments, in response to the absence of a data signal to be transmitted, the read clock of the TX FIFO is turned off (S204), including:

[0144] S2041. In response to the TX FIFO read clock being continuously turned off for a preset time threshold, the TX FIFO read clock is started and an analog data signal is sent.

[0145] When the read clock of the TX FIFO is turned off, the receiving unit will not receive the feedforward clock, and therefore cannot track the "offset". However, during this period, the local clocks of the transmitting and receiving units may still drift. If the actual offset caused by the drift during this period is too large, such as exceeding the maximum adjustment amount mentioned above, the transmitting unit may not be able to align the read clock and write clock of the RX FIFO after the read clock of the TX FIFO is turned on again, causing data errors.

[0146] Therefore, a "time threshold" can be preset. The setting of this time threshold should ensure that the drift generated by the local clock within its range will not cause an excessive offset, such as an offset exceeding the maximum adjustment amount. Therefore, the time threshold can be set according to the chip's performance, such as 1ms.

[0147] Therefore, when the duration for which no data signal needs to be transmitted reaches the above time threshold, that is, when the duration for which the read clock of the TX FIFO is continuously turned off reaches the time threshold, the read clock of the TX FIFO can be started and an analog data signal for detecting the offset can be sent. Thus, the receiving unit can detect the offset according to the restarted feedforward clock, and the transmitting unit can then adjust the read operation time and valid signal of the TX FIFO according to the offset.

[0148] In some embodiments, adjusting the read operation time and valid signal of the TX FIFO according to the offset (S202) includes:

[0149] S2023. In response to the offset reaching a preset second adjustment threshold when transmitting analog data signals, adjust the read operation time and valid signal of the TX FIFO according to the offset.

[0150] The second adjustment threshold is less than the maximum adjustment amount, which corresponds to the maximum adjustment range that the transmitting unit can achieve for the read clock of the TX FIFO.

[0151] As one embodiment of this disclosure, when restarting the read clock of the TX FIFO and sending analog data signals, the adjustment can be "triggered" only when the offset exceeds a certain adjustment threshold, such as the second adjustment threshold, thereby avoiding unnecessary frequent adjustments. However, since there is no actual data signal to be sent in this case, even if data transmission is "paused" for clock adjustment, it will not have any actual impact. Therefore, the second adjustment threshold can be smaller than the maximum adjustment amount or the first adjustment threshold, such as t / 2.

[0152] Thirdly, referring to Figure 4 This disclosure provides a receiving unit, including an RX FIFO, a memory, and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements any of the data transmission methods of this disclosure.

[0153] Fourthly, refer to Figure 5 This disclosure provides a transmission unit, including a TX FIFO, a memory, and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements any of the data transmission methods of this disclosure.

[0154] Fifthly, refer to Figure 6 This disclosure provides a chip, including:

[0155] Reference clock;

[0156] Any receiving unit according to the embodiments of this disclosure;

[0157] Any of the transmitting units in the embodiments of this disclosure.

[0158] Sixthly, refer to Figure 7 This disclosure provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements any of the data transmission methods of this disclosure.

[0159] In a seventh aspect, embodiments of this disclosure provide a computer program product, including a computer program, which, when executed by a processor, implements any of the data transmission methods of embodiments of this disclosure.

[0160] Among them, the processor is a circuit structure with data processing capabilities, and the memory is a circuit structure with data storage capabilities, including but not limited to random access memory (RAM), more specifically such as SDRAM, DDR, etc., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH).

[0161] Example 1:

[0162] Reference Figures 8 to 16 Example 1 provides an exemplary description of a specific data transmission method according to an embodiment of this disclosure.

[0163] Reference Figure 8 Example 1 is used for the transmitting unit to transmit data signals to the receiving unit, wherein the transmitting unit may be a TX bare crystal, the receiving unit may be an RX bare crystal, and there is a bare crystal connection between the transmitting unit and the receiving unit.

[0164] Reference Figure 8 The transmitting and receiving units use the same 100MHz reference clock (ref).

[0165] In the transmitting unit, the reference clock is generated at 8 GHz via a phase-locked loop (PLL). This 8 GHz clock serves as the read clock and valid signal for the TX FIFO, and is also used to process sequence data (01010101) to generate the transmit-side clock polarity signal (TXCKP), which is transmitted to the receiving unit to obtain the receive-side clock polarity signal (RXCKP), which is the feedforward clock (FWD CLK) for the receiving unit. Simultaneously, the 8 GHz clock from the transmitting unit is further divided by 4 (DIV4) to generate a 2 GHz local clock (LCLK), which serves as the write clock for the TX FIFO.

[0166] In the receiving unit, the reference clock is generated into an 8GHz clock by a PLL, and then into a 2GHz LCLK by a 4-divider (DIV4), which serves as the read clock for the RX FIFO.

[0167] Reference Figure 8 The receiving unit also includes a phase detector (PD), which compares its own LCLK with the FWD CLK from the transmitting unit, that is, compares the read clock and write clock of the RX FIFO to determine the offset between them, and then... Figure 8 The dashed lines in the text indicate that the offset is returned to the sending unit via sideband messages or other means.

[0168] Since the FWD CLK is 8GHz and the receiver unit's LCLK is 2GHz, therefore, refer to... Figure 8 The FWD CLK can be converted into a 2GHz signal by a 4-divider (DIV4) and then compared with the LCLK of the receiving unit in the PD.

[0169] For example, refer to Figure 9 When the falling edge of the write clock of the RX FIFO is taken as the standard edge, the PD can find the edge in the read clock of the RX FIFO that is closest to the standard edge as the reference edge, and compare the difference between the reference edge and the standard edge as the offset; for example, it can refer to... Figure 9 When the reference edge is "after" the standard edge, the offset is considered positive, and when the reference edge is "before" the standard edge, the offset is considered negative.

[0170] It should be understood that it is also feasible to compare the FWD CLK directly with the read clock of the RX FIFO without going through a 4 divider, but the standard edge needs to be a specific falling edge, rather than all falling edges.

[0171] The specific form of PD can be determined according to the required offset accuracy. For example, for a 2GHz clock, a reference can be used. Figure 10 The 64-level phase detector corresponds to an offset accuracy of 500ps / 64.

[0172] The delay units that form the delay chain in the PD (Power Delay Unit) may experience delay changes due to factors such as temperature and aging, thus requiring calibration. For example, a reference unit can be set up near the PD. Figure 11 The calibration circuit has the same delay unit form as the delay unit in the PD, so it will produce a delay change similar to the delay unit in the PD. Thus, the calibration circuit can determine how many delay units correspond to 2 UIs to calibrate the delay chain of the PD. For example, for an 8GHz clock, 2UI = 125ps. If it is found that it corresponds to k delay units, the delay value of the PD can be set to N × 125ps / k, where N is the number of delay units in the PD.

[0173] The transmitting unit includes multiple 8-to-1 data serializers (SERs), each SER containing a TX FIFO, which is connected to the receiving unit via bare crystal interconnection.

[0174] For example, refer to Figure 8 The sending unit may include:

[0175] SER1 is used to transmit 8-bit data signals (TX data), which includes TX FIFO1, corresponding to the data channel;

[0176] SER2 is used to transmit the 8-bit valid signal (TX valid), which includes TX FIFO2;

[0177] SER2 is used to transmit the feedforward clock (FWD CLK), which includes TX FIFO2.

[0178] The specific structure of the SER in the sending unit can be found in [reference]. Figure 12 The read / write timing of its TX FIFO can be referenced. Figure 13 .

[0179] Reference Figure 12 Upstream data is written to a TX FIFO with a depth of 2 using a 2GHz LCLK as the write clock, while an 8GHz read clock (PCLK) reads 2 bits of data from the TX FIFO each time and sends them to the next part for parallel-to-serial conversion (2 to 1); then, 1 bit of serial data is output and sent through the TX driver (TX drv).

[0180] Reference Figure 13 The distance between the read pointer (RDPTR) and write pointer (WRPTR) of the TX FIFO should be at least one 8GHz clock cycle (t), which is at least 125ps. When the distance between the read pointer and the write pointer is different, the read starting point of the RDPTR is at different positions and corresponds to different TX FIFO depths. For example, when the distance is 9t, the TX FIFO depth needs to be 3. In Example 1, to cope with possible clock drift, the distance can be selected as 2t.

[0181] Correspondingly, the receiving unit includes multiple 1-to-8 data deserializers (DES), each DES having an RX FIFO, which is connected to the TX FIFO of the receiving unit's SER via a bare crystal connection.

[0182] For example, refer to Figure 8 The receiving unit may include:

[0183] DES1 is used to receive data signals, and includes RX FIFO1;

[0184] DES2 is used to receive valid signals, and it includes TX FIFO2.

[0185] Since the FWD CLK signal is a clock signal, the receiving unit can directly receive the signal from SER3 without setting the corresponding DES.

[0186] The specific structure of the DES in the receiving unit can be found in [reference]. Figure 14 .

[0187] Reference Figure 14 For serial data input via RX drv, an 8GHz FWD CLK can be used as the write clock. Even-numbered bits and odd-numbered bits are sampled on the rising and falling edges respectively, and converted from serial to parallel (1 to 2). On the next rising edge, the converted 2-bit data is written to positions 0 and 1 of the first row of the RX FIFO. Then, on the next rising edge, positions 2 and 3 of the first row of the RX FIFO can be written, and this process is repeated until the first row of the RX FIFO is filled in four cycles of the 8GHz clock, and then the next row is written. For example, the depth of the RX FIFO can be 4, and the data read from it can first enter a register (reg).

[0188] Reference Figure 8 In the transmitting unit, corresponding to SER1 and SER2, small delay lines (Deskew) can also be provided respectively, which are used to make small delay adjustments, such as a delay of about 0.04UI, which corresponds to about 5ps of an 8GHz clock.

[0189] Reference Figure 8 In the receiving unit, a delay matching unit can be provided for DES1 and DES2 respectively to compensate for the delay of the RX path.

[0190] Reference Figure 15 DES2 can be equipped with a corresponding RX valid module, which is used to generate read enable rd_en based on the valid signal.

[0191] The input to RX valid is the 8-bit valid signal after serial-to-parallel conversion. It can decode the received 8'b1111_000 signal to obtain 1 bit valid=1, which is a valid state, and decode the received 8'bxx00_000 signal to obtain 1 bit valid=0, which is an invalid state.

[0192] Reference Figure 15The valid signal is sampled at the reference edge of the LCLK defined above; reference Figure 16 If the sampled result is valid=1, which means it is in a valid state, then the read enable is started, i.e., rd_en=1 is set; until the sampled result is valid=0, which means it changes from a valid state to an invalid state, and after a preset enable delay, the read enable is turned off, i.e., rd_en=0 is set; where the enable delay can be two 2GHz LCLK clock cycles (T).

[0193] When rd_en=1, the read pointers (RDPTR) of RX FIFO1 and RX FIFO2 can be incremented and the data in the corresponding FIFO can be read. Since FWD CLK is aligned with the valid signal and the data signal, and skew<4ps, it can be assumed that the writes of each RX FIFO are consistent.

[0194] The transmitting unit also includes a delay loop (DLL), which delays the elapsed clock signal. The delay range is 0~250ps (0~2t), and the delay accuracy, i.e., the delay per step, can be 0.3~1ps. The initial value of the DLL can be set to 125ps, thus enabling a delay range of -t to t, and therefore the maximum adjustment is t.

[0195] For example, refer to Figure 8 The transmitting unit may have DLL1 and DLL2. DLL1 is used to delay the valid signal and the read clock of TX FIFO, that is, to delay the data channel (lane); while DLL2 is used to delay FWD CLK, that is, to delay the TXCKP lane.

[0196] The delay based on the offset should be adjusted synchronously for DLL1 and DLL2; while the eye adjustment of the FWD CLK sampling data can be achieved by controlling DLL2 separately.

[0197] Therefore, the data transmission method in Example 1 may include the following stages:

[0198] (1) Power-on reset

[0199] When the chip is powered on, the write pointer of the RX FIFO is reset to the maximum position max, and the read pointer is reset to 0.

[0200] Since the size of the RX FIFO is 4, the maximum value is 3.

[0201] (2) TX FIFO calibration

[0202] As before, the distance between the read pointer and the write pointer of the RX FIFO is set to 2t.

[0203] (3) Scan eye diagram

[0204] The initial delay values ​​of DLL1 and DLL2 are set to 125ps. The SER1 and SER2 of the transmitting unit send a random number sequence. The DES of the receiving unit samples the data in front of each RX FIFO and converts it into 8-bit parallel data, which is then compared with the set golden sequence.

[0205] The process involves continuously increasing the delay of DLL2 and repeating the above detection multiple times to determine the eye diagram, and then setting the delay of DLL2 at the center of the eye diagram.

[0206] Among them, the sampling structure used for eye diagram scanning is Figure 8 Not shown in the image.

[0207] (4) Initial state

[0208] Before actual data signal transmission begins, the transmitting unit sends a test data signal to the receiving unit. The transmitting unit's 8GHz clock is transmitted to the receiving unit's RXCKP port via the UCIe protocol's TXCKP port, obtaining the receiving unit's FWDCLK, which is then converted to 2GHz via 4DIV frequency conversion, as shown in the reference. Figure 9 The receiving unit's PD then compares LCLK with the converted FWD CLK to obtain the offset A, and transmits A to the transmitting unit via a sideband message.

[0209] The transmitting unit adjusts the delay according to the offset A as follows:

[0210] When A = [-62.5, 62.5]ps, that is, when [-t / 2, t / 2], the delay of DLL1 and DLL2 is directly adjusted to 125ps + A, so that the reference edge of the read clock of RX FIFO is aligned with the standard edge of the real clock; where 125ps represents the initial delay of DLL1 and DLL2, and the actual amount of delay adjusted is A.

[0211] When A = (62.5, 125]ps, that is, at (t / 2, t], the read pointer position of TX FIFO is increased by t, and the delay of DLL1 and DLL2 is adjusted to 125ps - (125ps - |A|), that is, the actual adjustment of the delay is |A| - t, so that the reference edge of the read clock of RX FIFO is aligned with the standard edge of the real clock;

[0212] When A = (-125, -62.5) ps, that is, when (-t, -t / 2), the read pointer position of TX FIFO is set to -t, and the delay of DLL1 and DLL2 is adjusted to 125ps + (125ps - |A|), that is, the actual adjustment of the delay is t - |A|, so that the reference edge of the read clock of RX FIFO is aligned with the standard edge of the real clock.

[0213] (5) Working status

[0214] (5-1) After entering the normal working state, if there is a continuous need to transmit data signals, the receiving unit tracks the offset A and transmits A to the transmitting unit through the sideband message.

[0215] The transmitting unit adjusts the delay according to the offset A as follows:

[0216] Only when |A|=125ps, the delay is adjusted in the manner described in (1) above. The difference is that when making the adjustment, the transmission of the data signal needs to be paused.

[0217] The 125ps mentioned above is the preset first adjustment threshold, which is equal to the maximum adjustment amount t.

[0218] (5-2) After entering the normal working state, if there is no data signal to be transmitted, the read clock of TX FIFO is turned off, that is, the FWD CLK of the receiving unit is turned off, so the PD of the receiving unit cannot compare to obtain the offset A, and the transmitting unit does not make any adjustment.

[0219] (5-3) When there is no data signal to be transmitted for 1ms, the receiving unit turns on the read clock of the TX FIFO and sends an analog data signal, so that the PD of the receiving unit can detect the offset A and transmit A to the transmitting unit.

[0220] The transmitting unit adjusts the delay according to the offset A as follows:

[0221] The delay is adjusted in the manner described in (1) above only when |A|>62.5ps, which is greater than t / 2.

[0222] The 1ms mentioned above is a predetermined time threshold, determined based on clock drift. It should be ensured that the clock offset within this time threshold does not exceed the maximum adjustment amount. It should be understood that the time threshold can also be other values ​​such as 100μs, 10μs, or 1μs.

[0223] The 62.5ps mentioned above is a preset second adjustment threshold, which should be less than the maximum adjustment amount. It should be understood that the second adjustment threshold can also be other values ​​less than the maximum adjustment amount, such as t / 8 or t / 16.

[0224] Reference Figure 16 Based on the method in Example 1 above:

[0225] If the standard edge of the write clock of the RX FIFO is aligned with the rising edge of the read clock, that is, when the reference edge is the rising edge, the data signal Pl_data finally read by the receiving unit corresponds to the group of LCLK, Valid, rd_en, Pl_data in the upper part of the figure, and its delay is 1T, that is, 500ps.

[0226] If the standard edge of the write clock of the RX FIFO is aligned with the falling edge of the read clock, that is, when the reference edge is the falling edge, the data signal Pl_data finally read by the receiving unit corresponds to the lower set of LCLK, Valid, rd_en, Pl_data in the figure, and its delay is 1.5T, or 750ps.

[0227] Among them, the related technology uses RX FIFO as an asynchronous FIFO management method. Its synchronization requires 2 to 3 cycles (T), and the conversion to Gray code requires 1 to 2 T, with a total data signal readout delay of about 4 T.

[0228] And reference Figure 16 According to the embodiments of this disclosure, the RX FIFO can operate in the manner of a synchronous FIFO, and its maximum data signal readout delay is only 1~1.5T, which is much smaller than the delay of related technologies.

[0229] Furthermore, in this embodiment of the present disclosure, the total data transmission time from the transmitting unit to the receiving unit is approximately 1582.5ps < 2ns, which meets the requirements of the UCIe protocol.

[0230] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0231] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0232] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media and communication media. In embodiments of this disclosure, computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, and any other media that can be used to store desired information and can be accessed by a computer. In embodiments of this disclosure, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A method of data transmission, characterized by, A method for a receiving unit, the receiving unit and a sending unit are packaged in the same chip and connected through an inter-die connection, the receiving unit receives a data signal and a valid signal from a sending side first-in-first-out (FIFO) buffer (TX FIFO) of the sending unit through a receiving side FIFO buffer (RX FIFO), and a local clock of the sending unit and a local clock of the receiving unit are generated based on a same reference clock; the method comprises: detecting an offset between a write clock and a read clock of the RX FIFO; the detecting the offset between the write clock and the read clock of the RX FIFO comprises: determining a standard edge of the write clock of the RX FIFO; determining a difference between the standard edge and a reference edge of the read clock of the RX FIFO as the offset; the read clock of the RX FIFO is the local clock of the receiving unit, the write clock is a feedforward clock generated based on a read clock of the TX FIFO, and the reference edge is an edge of the read clock of the RX FIFO that is closest to the standard edge; sending the offset to the sending unit; the sending unit adjusts a read operation time of the TX FIFO and the valid signal based on the offset; the adjusting the read operation time of the TX FIFO and the valid signal based on the offset comprises: in response to A=[-t / 2, t / 2], delaying the read clock of the TX FIFO and the valid signal by A; wherein A is the offset, and t is a read period of the TX FIFO; in response to A=(t / 2, t], delaying a position of a read pointer of the TX FIFO by t, and delaying the read clock of the TX FIFO and the valid signal by |A|-t; in response to A=(-t, -t / 2), advancing the position of the read pointer of the TX FIFO by t, and delaying the read clock of the TX FIFO and the valid signal by t-|A|; and determining a read enable of the data signal based on the valid signal.

2. The method of claim 1, wherein, The determining the read enable of the data signal based on the valid signal comprises: detecting the valid signal at the reference edge; in response to the detected valid signal being in a valid state, starting the read enable of the data signal; in response to the detected valid signal changing from the valid state to an invalid state, closing the read enable of the data signal after a preset enable delay.

3. The method of claim 1, wherein, Further comprising: in response to the RX FIFO being reset, setting a write pointer of the RX FIFO to a maximum position, and setting a read pointer of the RX FIFO to a minimum position.

4. A method of data transmission, characterized by A method for a sending unit, the sending unit and a receiving unit are packaged in the same chip and connected through an inter-die connection, the sending unit sends a data signal and a valid signal to a RX FIFO of the receiving unit through a TX FIFO, and a local clock of the sending unit and a local clock of the receiving unit are generated based on a same reference clock; the method comprises: receiving an offset from the receiving unit; the offset is an offset between a write clock and a read clock of the RX FIFO detected by the receiving unit; the detecting the offset between the write clock and the read clock of the RX FIFO comprises: determining a standard edge of the write clock of the RX FIFO; determining a difference between the standard edge and a reference edge of the read clock of the RX FIFO as the offset; the read clock of the RX FIFO is a local clock of the receiving unit, the write clock is a feed-forward clock generated according to the read clock of the TX FIFO, and the reference edge is an edge of the read clock of the RX FIFO that is closest to the standard edge; adjusting a read operation time of the TX FIFO and the valid signal according to the offset; the receiving unit determines a read enable of the data signal according to the valid signal; the adjusting the read operation time of the TX FIFO and the valid signal according to the offset comprises: in response to A=[-t / 2, t / 2], delaying the read clock of the TX FIFO and the valid signal by A; wherein A is the offset, and t is a read period of the TX FIFO; in response to A=(t / 2, t], delaying a position of a read pointer of the TX FIFO by t, and delaying the read clock of the TX FIFO and the valid signal by |A|-t; in response to A=(-t, -t / 2), advancing the position of the read pointer of the TX FIFO by t, and delaying the read clock of the TX FIFO and the valid signal by t-|A|.

5. The method of claim 4, wherein, the adjusting the read operation time of the TX FIFO and the valid signal according to the offset comprises: in an initial state, adjusting the read operation time of the TX FIFO and the valid signal according to the offset; in a working state, adjusting the read operation time of the TX FIFO and the valid signal according to the offset when the offset reaches a preset adjustment threshold.

6. The method of claim 5, wherein, the adjusting the read operation time of the TX FIFO and the valid signal according to the offset when the offset reaches the preset adjustment threshold comprises: in response to the existence of the data signal to be sent and the offset reaching a preset first adjustment threshold, adjusting the read operation time of the TX FIFO and the valid signal according to the offset; the first adjustment threshold is equal to a maximum adjustment amount, and the maximum adjustment amount corresponds to a maximum adjustment range that can be achieved by the sending unit on the read clock of the TX FIFO.

7. The method of claim 4, wherein, further comprising: in response to the absence of the data signal to be sent, stopping the read clock of the TX FIFO.

8. The method of claim 7, wherein, the stopping the read clock of the TX FIFO in response to the absence of the data signal to be sent comprises: in response to a continuous stopping time of the read clock of the TX FIFO reaching a preset time threshold, starting the read clock of the TX FIFO and sending an analog data signal.

9. The method of claim 8, wherein, The adjusting the read operation time of the TX FIFO and the valid signal according to the offset comprises: adjusting the read operation time of the TX FIFO and the valid signal according to the offset in response to the offset reaching a preset second adjustment threshold when the analog data signal is transmitted; the second adjustment threshold is smaller than a maximum adjustment amount, and the maximum adjustment amount corresponds to a maximum adjustment range that can be achieved by the transmitting unit on the read clock of the TX FIFO.

10. A receiving unit, characterized by The RX FIFO, a memory, and a processor are included; the memory stores a computer program that can be executed by the processor; and the computer program, when executed by the processor, implements the method for data transmission of any one of claims 1 to 3.

11. A transmitting unit, characterized by The TX FIFO, a memory, and a processor are included; the memory stores a computer program that can be executed by the processor; and the computer program, when executed by the processor, implements the method for data transmission of any one of claims 4 to 9.

12. A chip, characterized by The TX FIFO, a memory, and a processor are included; the memory stores a computer program that can be executed by the processor; and the computer program, when executed by the processor, implements the method for data transmission of any one of claims 4 to 9. a reference clock; the receiving unit of claim 10; the transmitting unit of claim 11.

13. A computer readable medium characterized by A computer program is stored thereon, and the computer program, when executed by a processor, implements the method for data transmission of any one of claims 1 to 9.

14. A computer program product, characterised in that, A computer program is stored thereon, and the computer program, when executed by a processor, implements the method for data transmission of any one of claims 1 to 9.

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