Storage management interface and sharing method oriented to multi-chip interconnection

Abstract

The invention discloses a storage management interface oriented to multi-chip interconnection and a sharing method. The storage management interface comprises a storage management module and a protocol adaptation module. The protocol adaptation module comprises a packet analysis channel, a packet generation channel, an output control channel and an AXI sending and receiving channel; the access information extraction module is used for extracting access information in a defined request type, executing legal operation and rejecting illegal operation; the storage management module comprises a storage division module, a storage block information caching module and a memory access verification module; and the storage management module is used for dividing and managing the storage blocks, querying and checking the access information arriving in the protocol adaptation module, and determining the legality of the operation. The storage management module adopted by the invention has the advantages of low memory access delay and low cache overhead.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit communication, and particularly relates to a storage management interface and sharing method for multi-core particle interconnection. BACKGROUND

[0002] Integrated circuit technology develops rapidly according to Moore's law, but as the integrated circuit size continues to decrease in recent years, Moore's law approaches the physical limit, and the cost and period of developing application-specific integrated circuits gradually increase. A multi-core heterogeneous integrated system based on core particle technology breaks the bottleneck of chip performance growth, but poses new challenges in multi-core particle data sharing. For example, under the traditional processor-centered storage architecture, when a host core particle accesses a remote storage medium, the host core particle needs to first access the host corresponding to the storage medium, and then access the storage medium, so that the access path is long and there is high latency. SUMMARY

[0003] The application aims to solve the problem of long access path and high latency in the background art, and provides a storage management interface and sharing method for multi-core particle interconnection.

[0004] In order to achieve the purpose of the application, the application provides a storage management interface and sharing method for multi-core particle interconnection.

[0005] The storage management interface for multi-core particle interconnection provided by the application is used to connect an on-chip network and a storage medium controller, manage storage blocks, receive and analyze data packets of various request types of the on-chip network and check the operation authority, authorize and execute legal operations and reject illegal operations, and then return response data packets of the response type corresponding to the legal operations or error codes corresponding to the illegal operations to the on-chip network.

[0006] The application provides a storage management interface for multi-core particle interconnection, which is located between a storage medium controller and an on-chip network; the storage management interface comprises a storage management module and a protocol adaptation module;

[0007] The protocol adaptation module comprises packet analysis, packet generation, output control, and AXI sending and receiving channels, and is used to extract memory access information in the defined request type, execute legal operations, and reject illegal operations; the request type includes reading and writing, application, release, and sharing;

[0008] The storage management module comprises a storage division module, a storage block information cache module, and a memory access verification module; the storage management is used to divide and manage storage blocks, and query and verify the memory access information from the protocol adaptation module to determine the legality of the operation;

[0009] Specifically, the protocol adaptation module includes packet analysis, packet generation, output control, and AXI read-write channels; wherein, the packet analysis is used for receiving the request packet of the on-chip network input port, and sending the operation information carried by the request packet to the storage division module; the packet generation is used for receiving the error coding sent from the storage management module or the response sent from the AXI receiving port; the AXI sending port receives the storage block operation information initiated by the previous stage, and performs the sending of AXI W channel, AXI W channel and AXI AR channel; the AXI receiving port receives the response of AXI B channel and AXI R channel, and sends the information to the output control; the output control module is responsible for receiving the check result of the operation, and selects the AXI response or error coding to send to the packet generation module.

[0010] The storage management module includes a storage division module, a storage information cache module, and a memory access verification module; wherein, the storage division module is the main module for realizing the function, and is used for marking and managing whether the storage block is idle; the storage information cache module is used for saving the additional information allocated to the corresponding storage block, including the master node of the corresponding storage block; the memory access verification module executes the application, release, read-write operation according to the storage division module and the storage information cache module.

[0011] Compared with the existing storage management mode based on multi-level page table, the storage management module has the advantages of low memory access delay and small cache overhead.

[0012] Further, as shown in Figure 3 , the storage block uses a tree structure composed of a plurality of nodes, each node maps a storage block and records the allocation state of the storage block, and the parent node corresponds to two child nodes mapping the combination of the storage block; it is specified that the size of the storage block mapped by the leaf node is 64MB, and the number of layers of the tree structure is obtained according to the storage capacity. The number of layers of the storage block also corresponds to the bit width of the base address of the storage block (for example, a 4GB DDR contains 2 6 64MB storage blocks, which requires a 6-layer binary tree mapping and a 6-bit base address for indexing); it is specified that the base address of the node corresponding to the storage block is the position of the node in the tree, and the base address of the parent node is the base address of the left child node.

[0013] The existing storage management mode based on multi-level page table locates the information of the storage resource block by accessing the sub-tables level by level; while the storage hierarchy relationship of the present application is directly mapped in the tree structure realized by hardware, and the storage block information can be obtained by single query, so that the memory access delay is more optimal.

[0014] Further, the storage block information cache module is specifically used for saving the storage block state information, and in the storage information cache module, information other than the allocation state is recorded for each storage block, as shown in Table 1:

[0015] Table 1 Storage block information

[0016]

[0017] Designing storage information cache based on the concept of spatial multiplexing: for a state management module implemented by a h-layer binary tree, a total of 2 ^h -1 nodes, the storage information cache module only saves the allocation state of 2 ^ h-1 ) rows of nodes, corresponding to all leaf nodes in the tree. For intermediate nodes that are not leaf nodes, if they have been allocated, all leaf nodes in the subtree rooted at them are also allocated, and the information storage row of the lowest leaf node is used to store the allocation information of the entire subtree. Figure 4 A 4-level binary tree node information saving method is shown, using 8 cache rows to save the state of 16 nodes.

[0018] Further, the memory access verification module is used to judge legal requests, illegal requests, illegal operations, and legal operations.

[0019] The judgment method of legal requests and illegal requests is as follows: in addition to storage application operations, according to the maintained storage block information, memory access requests from hosts in the holding host list and access addresses falling within the storage block address space are legal requests, and vice versa. Illegal requests; wherein, the memory access operation from the host is divided into read operation, write operation, storage block application operation, storage block release operation, and storage block sharing operation.

[0020] The judgment method of illegal operations and legal operations is as follows: the host is the holder, sharer or irrelevant of the storage block; the holder of the storage block directly executes the read and write, release and sharing operations of the corresponding storage block; the first read operation of the sharer is directly executed; all operations of the sharer other than the first read operation and all operations of the irrelevant are illegal operations.

[0021] Further, the storage block operation is to dynamically allocate the idle storage block according to the size of the applied storage block and give the base address; when the storage block application operation is executed, the application operation containing the size information of the application is broadcasted to the idle nodes in the entire binary tree from the root node; the nodes receiving the broadcast will judge whether the application operation can be executed according to their own state and the state of their child nodes, and make an application; when there are multiple nodes that can be allocated, an arbitrator is used to authorize one of the nodes and reject the allocation response of other nodes, and the base address of the allocated storage block is generated according to the position of the node; after confirming the node to be allocated, the node will change its allocation state, and the change of the state and the success or failure information of the application will be propagated back to the root node, updating the state of the entire binary tree.

[0022] ​The storage block release operation is to find and modify the allocation state of the corresponding node according to the base address of the released storage block; when the storage block release operation is executed, one bit of the base address is used as the index of the first-level binary tree, and the release operation is transmitted on the search path according to the index information; the node receiving the release operation judges whether the release operation can be executed according to the state of the node itself and the state of the child nodes of the node itself, and the node capable of executing the release operation is the deepest node allocated in the release path; after the node to be released is confirmed, the node and the application are changed, the allocation state of the node itself is changed, and the change of the state and the success or failure information of the release are transmitted to the root node in reverse, so as to update the state of the entire binary tree;

[0023] The storage block sharing operation is to find the allocation state of the corresponding node according to the base address of the queried storage block; when the storage block query operation is executed, one bit of the base address is used as the index of the first-level binary tree, and the query operation is transmitted on the search path according to the index information; the search process of the node in the query process is the same as that of the storage block release, and after the search is completed, the state of the target node is not modified, and the state of the entire binary tree is not updated.

[0024] Further, the packet analysis is used to parse the memory access information in the defined read-write, application, release and sharing requests and process the information by the storage management module: the host number, read-write address and length in the read-write request are extracted; the host number and the application storage block size in the application request are extracted; the host number and the release storage block base address in the release request are extracted; the host number, the shared storage block base address and the shared object host number list in the sharing request are extracted; after the extraction, the information is sent to the storage management module for verification and execution;

[0025] The AXI sending and receiving channel is used to interact with the storage device in the form of AXI protocol for the read-write request verified, and send the read-write response returned by the storage device to the packet generation module;

[0026] The packet generation module is used to package various responses corresponding to the returned request: for the request determined to be illegal, the packet generation module generates an illegal response carrying an error code; for the legal read-write request, the read-write response returned by the AXI sending and receiving channel is packaged; for the legal application request, the storage block base address newly allocated by the storage management module is packaged; for the legal release and sharing request, the success or failure of the release and sharing is packaged.

[0027] The application also provides a sharing method of a storage management interface for multi-core particle interconnection, and the sharing method is realized based on the storage management interface provided by the application, and the sharing method comprises the following steps:

[0028] The storage medium is managed in blocks, receives various request type data packets of the on-chip network and parses into different types of operations, authorizes and executes legal operations and rejects illegal operations, and then returns response data packets corresponding to the legal operations or error codes corresponding to the illegal operations to the on-chip network.

[0029] Compared with the prior art, the significant progress of the present application is that:

[0030] Compared with the prior art, the significant progress of the present application is that:

[0031] The prior art based on a multi-level page table accesses a sub-table level by level to finally locate the information of a storage resource block; while the storage hierarchy relationship of the present application is directly mapped in a tree structure realized by hardware, and the storage block information can be obtained by a single query, so that the memory access delay is more optimal.

[0032] To more clearly illustrate the functional characteristics and structural parameters of the present application, the following further describes the present application in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a storage management interface structure diagram for multi-core particle interconnection provided by the present application;

[0034] Figure 2 is a use scenario diagram of the storage management interface provided by the present application;

[0035] Figure 3 is a storage block mapping method schematic diagram provided by the present application;

[0036] Figure 4 is a storage block information cache structure schematic diagram provided by the present application;

[0037] Figure 5 is a storage division module execution application example diagram provided by the present application;

[0038] Figure 6 is a storage division module execution release example diagram provided by the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0040] The multi-core interconnection-oriented storage management interface and sharing method based on the storage center-oriented storage architecture can shorten the access path, reduce the access delay, greatly improve the access efficiency, and improve the system performance.

[0041] The application provides a multi-core interconnection-oriented storage management interface and sharing method.

[0042] The multi-core interconnection-oriented storage management interface includes a storage management module and a protocol adaptation module.

[0043] The storage management module includes a storage division module, a storage block information cache, and an access verification module.

[0044] The protocol adaptation module is described below.

[0045] The protocol adaptation module includes packet analysis, packet generation, and AXI sending and receiving channels.

[0046] The packet analysis is used to analyze the access information in the defined read-write, application, release, and sharing requests and process the access information by the storage management module.

[0047] The AXI sending and receiving channel is used to interact with the storage device in the form of the AXI protocol for the read-write request that passes the verification and send the read-write response returned by the storage device to the packet generation module.

[0048] The package generation module is configured to generate various responses corresponding to the return request: for a request determined to be illegal, the package generation module generates an illegal response carrying an error code; in addition, for a legal read / write request, the read / write response returned by the AXI sending and receiving channel is packaged; for a legal application request, the storage block base address newly allocated by the storage management module is packaged; for a legal release and sharing request, the package is packaged according to whether the release and sharing are successful.

[0049] The storage management module includes a storage division module, a storage block information cache, and a memory access verification module. The three sub-modules will be introduced below.

[0050] The storage division module is configured to map the storage blocks.

[0051] The storage division module is configured to map the storage blocks.

[0052] Specifically, a tree structure composed of a plurality of nodes is used, each node mapping a storage block; the parent node corresponds to the combination of the storage blocks mapped by its two child nodes. Two storage block allocation states, occupied and idle, are defined. The storage block size, host identifier, shared host list, sharing state, and base address information are maintained for each storage block, and the base address is directly mapped through the tree structure coordinates, and the left child node information space is reused by the parent node to reduce information storage overhead. The storage division module is configured to divide the storage resources according to a size of 64 MB, distinguish the storage blocks by base addresses, and maintain the allocation and idle states of the storage blocks. As shown in Figure 3 The storage division module uses a full binary tree to divide the storage resources; each node in the binary tree stores 1 bit of information, which is used to determine whether the storage block mapped by the node has been allocated; the height of the binary tree is h, and it contains 2 h -1 nodes, and the number of nodes on each layer is the maximum number of nodes; all leaf nodes are on the last layer, and the number of leaf nodes is 2 h-1 The leaf nodes are used to divide the storage resources into 64 MB storage blocks, and the number of layers of the binary tree depends on the capacity of the storage device. For example, for a 4 GB DDR, a 7-layer binary tree is used, so that the leaf nodes correspond to a storage resource size of 64 MB. Since the binary tree used is a full tree, all non-leaf nodes contain a pair of child nodes; from the leaf nodes upwards, the storage resource mapped by each level of nodes is the combination of the storage resources mapped by its pair of child nodes, and the parent node of the leaf node maps 128 MB of resources, and so on. The root node of the binary tree maps the storage resources in the entire storage device.

[0053] After the mapping of the binary tree and the storage resource is established, due to the binary structure of the binary tree, the position relationship of the node in the binary tree can also be used as the high address of the mapped storage block resource. Define h-1 bits to represent the position of the node in the binary tree of h layers. From the root node, if the target node belongs to the left subtree of the root node, record "1", otherwise record "0". Then, if there is a subtree containing the target node, the base address corresponding to the target node is not completed, and the subtree is used as input to continue searching; if there is no subtree containing the target node, the base address corresponding to the target node has been completed, and the right subtree is directly used as input until the leaf node is searched to complete the generation of the base address.

[0054] Execution of the request

[0055] The storage management module obtains the request type and the request information from the package analysis module, and performs a response operation. The application request executes the storage block application; the release request executes the storage block release; the read-write and sharing request executes the storage block information query.

[0056] The storage block application will dynamically allocate the idle storage block according to the size of the applied storage block and give its base address. When the storage block application operation is executed, the application operation containing the size information of the application will be broadcasted to the idle nodes in the entire binary tree from the root node. The nodes receiving the broadcast will determine whether the application operation can be executed according to their own state and the state of their own child nodes, and propose the application. When there are multiple nodes that can be allocated, an arbitrator is used to authorize one of the nodes, and the allocation response of the other nodes is rejected, and the base address of the allocated storage block is generated according to the position of the node. After confirming the node to be allocated, the node will change its allocation state, and the success or failure information of the application will be propagated back to the root node to update the state of the entire binary tree. Figure 5 A binary tree with 4 layers is shown, and the processing flow when allocating a storage block of 256MB size is shown. The red nodes in the figure are allocated nodes, the yellow nodes are nodes broadcasting the application operation, the green nodes are nodes winning the arbitration, and the remaining nodes are idle nodes.

[0057] The storage block release searches and modifies the allocation state of the corresponding node according to the base address of the released storage block. When the storage block release operation is executed, one bit of the base address is used as the index of the one-level binary tree, and the release operation is transmitted on the search path according to the index information. The node receiving the release operation determines whether the release operation can be executed according to its own state and the state of its own child nodes. The node that can execute the release operation is the deepest node that has been allocated in the release path. After confirming the node to be released, the node changes its allocation state, and the success or failure information of the release is propagated back to the root node to update the state of the entire binary tree, which is the same as the application. Figure 6The figure shows the process of releasing a 256MB memory block, the red nodes are allocated nodes, the green nodes are the nodes that win the arbitration, and the rest are free nodes.

[0058] The memory block information query looks up the allocation state of the corresponding node according to the queried memory block base address. When performing the memory block query operation, one bit of the base address is used as the index of the first level of the binary tree, and the query operation is transmitted on the search path according to the index information. The node search process in the query process is the same as the memory block release, and after the search is completed, the state of the target node is not modified, and the state of the entire binary tree is not updated.

Claims

1. A storage management interface oriented to multi-core interconnection, characterized in that, The storage management interface is located between a storage medium controller and an on-chip network; the storage management interface comprises a storage management module and a protocol adaptation module; The protocol adaptation module comprises packet analysis, packet generation, output control, and AXI sending and receiving channels; The request type comprises reading and writing, application, release, and sharing, and is used to extract memory access information in the defined request type, perform legal operations, and reject illegal operations; The storage management module comprises a storage division module, a storage block information cache module, and a memory access verification module; the storage management module is used for dividing and managing storage blocks, and querying and verifying memory access information from the protocol adaptation module to determine the legality of operations; The storage division module is a main module for implementing functions, and is used for marking and managing whether storage blocks are idle; the storage information cache module is used for saving additional information allocated to corresponding storage blocks, including a master node of the corresponding storage block; the memory access verification module performs application, release, and read-write operations according to the storage division module and the storage information cache module.

2. The storage management interface of claim 1, wherein, The storage division module is specifically used for using a tree structure composed of a plurality of nodes, each node mapping a storage block and recording an allocation state of the storage block, and a parent node corresponding to two child nodes mapping a combination of storage blocks; It is specified that the size of a storage block mapped by a leaf node is 64 MB, and the number of layers of the tree structure is obtained according to the storage capacity; the number of layers of the storage block corresponds to the bit width of the base address of the storage block; It is specified that the base address of a storage block corresponding to a node is the position of the node in the tree, and the base address of a parent node is the base address of the left child node of the parent node.

3. The storage management interface of claim 2, wherein, The storage block information cache module is specifically used for saving storage block state information, as shown in Table 1: Table 1 Storage block information Table 1 is specific storage block information; For a state management module implemented by a h-layer binary tree, there are 2 ^h -1 nodes in total, and the information storage cache module only stores the allocation status of 2 ^ ( h-1 ) rows of nodes, corresponding to all leaf nodes in the tree; for non-leaf intermediate nodes, if they have been allocated, all leaf nodes in the subtree rooted at the intermediate node are also allocated, and the information storage row of the leaf node with the lowest base is used to store the allocation information of the entire subtree.

4. The storage management interface of claim 2, wherein, The memory access verification module is used for judging legal requests, illegal requests, illegal operations, and legal operations; The judgment method of the legal request and the illegal request is as follows: except for the storage application operation, according to the maintained storage block information, a memory access request from a host in the holding host list and accessing an address within the storage block address space is a legal request, and otherwise, it is an illegal request; wherein, the memory access operation from the host is divided into a read operation, a write operation, a storage block application operation, a storage block release operation, and a storage block sharing operation; The judgment method of the illegal operation and the legal operation is as follows: a host is a holder, a sharer, or an irrelevant of a storage block; a holder host directly performs read and write operations, release operations, and sharing operations on a corresponding storage block; a sharer directly performs a first read operation on a corresponding storage block; all operations of the sharer except the first read operation and all operations of the irrelevant are illegal operations.

5. The storage management interface according to claim 4, wherein The storage block operation is to dynamically allocate the free storage block according to the storage block size of the application and give the base address; when the storage block application operation is executed, the application operation containing the size information of the application is broadcasted to the free nodes in the whole binary tree from the root node; the nodes receiving the broadcast will determine whether the application operation can be executed according to the state of the nodes themselves and the state of the child nodes, and make the application; when there are multiple nodes that can be allocated, an arbitrator is used to authorize one of the nodes, and the allocation response of the other nodes is rejected, and the base address of the allocated storage block is generated according to the position of the node; after confirming the node to be allocated, the node changes the allocation state, and the change of the state and the success or failure information of the application are propagated reversely to the root node to update the state of the whole binary tree; The storage block release operation is to find and modify the allocation state of the corresponding node according to the base address of the released storage block; when the storage block release operation is executed, one bit of the base address is used as the index of the first-level binary tree, and the release operation is transmitted on the search path according to the index information; the nodes receiving the release operation determine whether the release operation can be executed according to the state of the nodes themselves and the state of the child nodes, and the node that can execute the release operation is the deepest node that has been allocated in the release path; after confirming the node to be released, the node changes the allocation state, and the change of the state and the success or failure information of the release are propagated reversely to the root node to update the state of the whole binary tree; The storage block sharing operation is to find the allocation state of the corresponding node according to the base address of the queried storage block; when the storage block query operation is executed, one bit of the base address is used as the index of the first-level binary tree, and the query operation is transmitted on the search path according to the index information; the search process of the nodes in the query process is the same as that in the storage block release, and after the search is completed, the state of the target node is not modified, and the state of the whole binary tree is not updated.

6. The storage management interface of claim 1, wherein, The packet analysis is used to parse the memory access information in the defined read-write, application, release and sharing requests and process the information by the storage management module: the host number, read-write address and length in the read-write request are extracted; The host number, application storage block size in the application request are extracted; the host number, release storage block base address in the release request are extracted; the host number, shared storage block base address and shared object host number list in the sharing request are extracted; after the extraction, the information is sent to the storage management module for verification and execution; The AXI sending and receiving channel is used to interact with the storage device in the form of AXI protocol for the read-write request that passes the verification, and send the read-write response returned by the storage device to the packet generation module; The packet generation module is used to package various responses corresponding to the returned requests: for the illegal request, the packet generation module generates an illegal response carrying an error code; for the legal read-write request, the read-write response returned by the AXI sending and receiving channel is packaged; for the legal application request, the newly allocated storage block base address of the storage management module is packaged; for the legal release and sharing requests, the release and sharing success or failure are packaged.

7. A sharing method of a storage management interface oriented to multi-core interconnection, the method is implemented based on the storage management interface provided in claims 1 to 6, and the sharing method comprises: performing block management on a storage medium, receiving data packets of various request types of an on-chip network and parsing into different types of operations, authorizing and executing legal operations and rejecting illegal operations, and then returning response data packets corresponding to the legal operations or error codes corresponding to the illegal operations to the on-chip network.

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