Super junction and SiC integrated efficient heat dissipation method and system

Abstract

The invention relates to the technical field of power semiconductors, in particular to a super junction and SiC integrated efficient heat dissipation method and system, and the method comprises the steps: carrying out the transition layer deposition of a super junction silicon epitaxial wafer, obtaining a transition super crystal circle, carrying out the low-temperature bonding through the transition super crystal circle, obtaining a heterogeneous integrated wafer, carrying out the thinning activation of the heterogeneous integrated wafer, and obtaining a thinned heterogeneous wafer. Constructing a micro-channel by using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel, detecting the cooling performance of the sealed micro-channel, obtaining an optimal heat dissipation path, cooling the optimal heat dissipation path, recording the output power of the device, obtaining an output power set, and obtaining an optimal flow rate based on the gradient flow rate and the output power set. And obtaining a plurality of heat dissipation wafers based on the optimal heat dissipation path and the optimal flow velocity, and carrying out reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers. According to the invention, the problems of performance degradation and reliability reduction caused by heat accumulation of super junction and SiC integration can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductors, and in particular to a high-efficiency heat dissipation method and system for super junction and SiC integration. BACKGROUND

[0002] With the rapid development of the power semiconductor industry, the heat dissipation method for super junction and SiC integration is facing new challenges. The performance degradation and reliability decline caused by heat accumulation in super junction and SiC integration can be solved by preparing super junction silicon carbide hetero-wafers through low-temperature bonding, and then screening and optimizing the flow rate of the micro-channel heat dissipation path.

[0003] Currently, the heat dissipation of semiconductor devices is mainly achieved by thermal interface materials and metal heat sinks. Although the original heat dissipation method has a certain heat dissipation effect, it has the problems of low heat dissipation efficiency, high energy consumption and inability to accurately dissipate heat. Therefore, optimizing the heat dissipation method for super junction and SiC integration is of great significance to improve the working efficiency of super junction and SiC integration. SUMMARY

[0004] The present application provides a high-efficiency heat dissipation method for super junction and SiC integration, and a computer readable storage medium, which mainly aims to solve the problem of performance degradation and reliability decline caused by heat accumulation in super junction and SiC integration.

[0005] To achieve the above-mentioned purpose, the present application provides a high-efficiency heat dissipation method for super junction and SiC integration, comprising: obtaining a plurality of super junction silicon epitaxial wafers, and performing the following operations on each super junction silicon epitaxial wafer in the plurality of super junction silicon epitaxial wafers: depositing a transition layer on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; performing low-temperature bonding on the transition super junction wafer under pre-confirmed activation conditions to obtain a hetero-integrated wafer; thinning and activating the hetero-integrated wafer to obtain a thinned hetero wafer, wherein the thinned hetero wafer comprises an activated silicon carbide layer; obtaining three heat dissipation paths, and performing the following operations on each heat dissipation path in the three heat dissipation paths: constructing a micro-channel using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; detecting the cooling performance of the sealed micro-channel to obtain a cooling performance score; summarizing the cooling performance scores to obtain three cooling performance scores, and obtaining an optimal heat dissipation path based on the three cooling performance scores; cooling at a plurality of gradient flow rates according to the optimal heat dissipation path, and recording the device output power to obtain an output power set; Obtaining the optimal flow rate based on the gradient flow rate and the output power set; Obtaining the heat dissipation wafer based on the optimal heat dissipation path, the optimal flow rate and the thinned heterogeneous wafer, and collecting the heat dissipation wafer to obtain a plurality of heat dissipation wafers; Performing reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers.

[0006] Optionally, the transition layer deposition on the super junction silicon epitaxial wafer to obtain a transition super junction wafer comprises: Temporarily bonding the super junction silicon epitaxial wafer and the pre-confirmed glass carrier to obtain a bonded wafer; Mechanically grinding the bonded wafer to obtain a ground bonded wafer; Detecting the thickness of the ground bonded wafer to obtain a silicon thickness, comparing the silicon thickness with a preset silicon thickness threshold, if the silicon thickness is greater than or equal to the silicon thickness threshold, taking the ground bonded wafer as the bonded wafer, returning to the step of mechanically grinding the bonded wafer until the silicon thickness is less than the silicon thickness threshold, and taking the ground bonded wafer as a qualified bonded wafer; If the silicon thickness is less than the silicon thickness threshold, taking the ground bonded wafer as a qualified bonded wafer; Mechanically polishing the qualified bonded wafer to obtain a polished bonded wafer; Back plating transition on the polished bonded wafer to obtain a transition layer wafer; Unbonding and cleaning the transition layer wafer to obtain a transition super junction wafer.

[0007] Optionally, the low-temperature bonding of the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer comprises: Obtaining a silicon carbide substrate; Polishing the silicon carbide substrate to obtain a polished silicon carbide substrate; Detecting the roughness of the polished silicon carbide substrate to obtain a roughness; Comparing the roughness with a preset roughness threshold, if the roughness is greater than or equal to the roughness threshold, taking the polished silicon carbide substrate as the silicon carbide substrate, returning to the step of polishing the silicon carbide substrate to obtain a polished silicon carbide substrate until the roughness is less than the roughness threshold, and taking the polished silicon carbide substrate as a qualified polished substrate; If the roughness is less than the roughness threshold, taking the polished silicon carbide substrate as a qualified polished substrate; Performing deoxidation treatment on the qualified polished substrate to obtain a deoxidized substrate; Activating bonding of the transition super junction wafer and the deoxidized substrate to obtain a heterogeneous integrated wafer.

[0008] Optionally, the three heat dissipation paths comprise: applying a preset electric power on the thinned heterogeneous wafer, and collecting a thermal image to obtain a high-heat map; mapping the high-heat map into a grid thermal flux matrix, and obtaining a plurality of high-heat unit coordinates by using the grid thermal flux matrix; planning a plurality of heat dissipation paths by using the plurality of high-heat unit coordinates and a pre-confirmed historical heat dissipation path, to obtain the plurality of heat dissipation paths; performing fast heat-flow coupling simulation on the plurality of heat dissipation paths to obtain a plurality of heat data sets, wherein the heat data sets correspond to the heat dissipation paths one by one, and the heat data sets include maximum temperatures and average temperatures; confirming three heat dissipation paths based on the plurality of heat data sets.

[0009] Optionally, the confirming three heat dissipation paths based on the plurality of heat data sets comprises: obtaining a maximum maximum temperature, a minimum maximum temperature and a comprehensive average temperature based on a plurality of maximum temperatures and a plurality of average temperatures in the plurality of heat data sets; performing the following operations on each heat data set in the plurality of heat data sets: calculating a heat dissipation score by using the maximum temperature, the average temperature, the maximum maximum temperature, the minimum maximum temperature and the comprehensive average temperature in the heat data set, wherein the calculation formula is as follows: , wherein, represents the heat dissipation score, represents a preset heat peak weight coefficient, represents the maximum maximum temperature, represents the minimum maximum temperature, represents the maximum temperature, represents a preset average temperature weight coefficient, represents the comprehensive average temperature, represents the average temperature; obtaining a plurality of heat dissipation scores by summarizing the heat dissipation scores; sorting the plurality of heat dissipation scores in descending order to obtain a heat dissipation score sequence, and obtaining the three heat dissipation paths by summarizing heat dissipation paths corresponding to the first three heat dissipation scores in the heat dissipation score sequence.

[0010] Optionally, the micro-channel construction by using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel comprises: obtaining a plurality of groups of combination parameters; performing etching standard tests on the pre-confirmed test silicon layer by using the plurality of groups of combination parameters respectively to obtain a plurality of etching grooves; obtaining a plurality of groove parameter sets based on a plurality of etching grooves, wherein the groove parameter set comprises a groove depth, a groove width and a bottom surface roughness; performing the following operations on each groove parameter set in the plurality of groove parameter sets: calculating an etching score by using the groove depth, the groove width and the bottom surface roughness in the groove parameter set; summarizing the etching scores to obtain a plurality of etching scores; obtaining a maximum etching score based on the plurality of etching scores, and taking a combination parameter corresponding to the maximum etching score as a final processing parameter; performing laser etching on the activated silicon carbide layer by using the heat dissipation path and the final processing parameter to obtain a micro-channel groove; bonding the pre-confirmed silicon cover plate with the micro-channel groove to obtain a sealed micro-channel.

[0011] Optionally, the sealed micro-channel is subjected to cooling performance detection to obtain a cooling performance score, comprising: performing a steady-state heat dissipation test on the sealed micro-channel to obtain a thermal steady-state micro-channel; obtaining an inlet temperature, an outlet temperature, a port pressure difference and a cooling liquid flow rate based on the thermal steady-state micro-channel; calculating the cooling performance score by using the inlet temperature, the outlet temperature, the port pressure difference and the cooling liquid flow rate, wherein the calculation formula is as follows: , wherein, represents the cooling performance score, represents a preset constant power, represents the cooling liquid flow rate, represents the inlet temperature, represents the outlet temperature, represents the port pressure difference.

[0012] Optionally, the optimal flow rate is obtained based on the gradient flow rate and the output power set, comprising: performing curve fitting on the gradient flow rate and the output power set to obtain a flow rate-power relationship curve; calculating a plurality of unit flow rate power gains based on the flow rate-power relationship curve and a preset flow rate interval; constructing a power gain curve by using the plurality of unit flow rate power gains; obtaining a peak gain based on the plurality of unit flow rate power gains; obtaining a gain threshold based on the peak gain; confirming the optimal flow rate based on the gain threshold and the power gain curve.

[0013] Optionally, the reliability verification is performed on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers, and the method comprises the following steps of: The following operations are performed on each of the plurality of heat dissipation wafers: The heat dissipation wafer is subjected to a thermal cycle test to obtain a tested wafer; The interface image of the tested wafer is collected to obtain an interface image; The interface image is subjected to delamination detection to obtain a delamination area; The delamination areas are summarized to obtain a plurality of delamination areas; The heat dissipation wafer corresponding to the delamination area less than or equal to the delamination area threshold value is taken as a qualified heat dissipation wafer, and the qualified heat dissipation wafers are summarized to obtain a plurality of qualified heat dissipation wafers.

[0014] To achieve the above object, the application further provides a high-efficiency heat dissipation system integrated with super junction and SiC, comprising: A device bonding activation module is configured to obtain a plurality of super junction silicon epitaxial wafers, and perform the following operations on each of the plurality of super junction silicon epitaxial wafers: A transition layer is deposited on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; The transition super junction wafer is subjected to low-temperature bonding under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer; The heterogeneous integrated wafer is thinned and activated to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer comprises an activated silicon carbide layer; A heat dissipation path planning module is configured to obtain three heat dissipation paths, and perform the following operations on each of the three heat dissipation paths: A micro-channel is constructed by using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; The sealed micro-channel is subjected to cooling performance detection to obtain a cooling performance score; The cooling performance scores are summarized to obtain three cooling performance scores, and the optimal heat dissipation path is obtained based on the three cooling performance scores; An optimal flow rate confirmation module is configured to cool the device by using the optimal heat dissipation path at a plurality of gradient flow rates, and record the output power of the device to obtain an output power set; The optimal flow rate is obtained based on the gradient flow rate and the output power set; A sample quality detection module is configured to obtain a heat dissipation wafer based on the optimal heat dissipation path, the optimal flow rate and the thinned heterogeneous wafer, and summarize the heat dissipation wafers to obtain a plurality of heat dissipation wafers; The reliability verification is performed on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers.

[0015] To solve the above problems, the application further provides an electronic device, which comprises: Memory, storing at least one instruction; and The processor executes the instructions stored in the memory to implement the high-efficiency heat dissipation method for superjunction and SiC integration described above.

[0016] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the aforementioned efficient heat dissipation method for superjunction and SiC integration.

[0017] The present application is to solve the problems described in the background art. The present application obtains a plurality of super junction silicon epitaxial wafers, and performs the following operations on each super junction silicon epitaxial wafer: transition layer deposition is performed on the super junction silicon epitaxial wafer to obtain a transition super junction wafer, low-temperature bonding is performed on the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer, and thinning activation is performed on the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer. The present application embodiment forms a high-quality, low-defect activated silicon carbide layer by transition layer deposition and low-temperature bonding of super junction silicon and silicon carbide hetero-integration and thinning activation, providing a reliable heterogeneous wafer foundation for subsequent direct construction of high-efficiency heat dissipation micro-channels thereon. Based on this, the present application obtains three heat dissipation paths, and performs the following operations on each heat dissipation path: micro-channel construction is performed on the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel, cooling performance detection is performed on the sealed micro-channel to obtain a cooling performance score, the cooling performance scores are summarized to obtain three cooling performance scores, and the optimal heat dissipation path is obtained based on the three cooling performance scores. The present application embodiment can quickly lock the optimal heat dissipation path by constructing and measuring three sealed micro-channels in parallel on the activated silicon carbide layer, quantitatively comparing the cooling performance scores, and providing a reliable basis for subsequent flow rate optimization, thereby avoiding blind trial and error. Further, the present application cools the device output power by using the optimal heat dissipation path at a plurality of gradient flow rates, records the output power to obtain an output power set, and obtains the optimal flow rate based on the gradient flow rate and the output power set. The present application embodiment can accurately lock the best balance point of heat dissipation and energy consumption by gradient scanning the flow rate and recording the output power in real time under the optimal heat dissipation path, thereby obtaining the optimal flow rate that guarantees device output and avoids energy waste. Next, the present application obtains a heat dissipation wafer based on the optimal heat dissipation path, the optimal flow rate, and the thinned heterogeneous wafer, summarizes the heat dissipation wafers to obtain a plurality of heat dissipation wafers, and performs reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers. The present application embodiment can batch produce and uniformly verify the heat dissipation wafers under the optimal heat dissipation path and the optimal flow rate, thereby one-time screening a plurality of qualified heat dissipation wafers to ensure that the heat dissipation performance and reliability are highly consistent within the batch. Therefore, the present application can solve the problems of performance degradation and reliability decline caused by heat accumulation in super junction and SiC integration. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A flowchart of a super junction and SiC integrated high-efficiency heat dissipation method provided by an embodiment of the present application is shown in the figure. Figure 2 A functional module diagram of a super junction and SiC integrated high-efficiency heat dissipation system provided by an embodiment of the present application is shown in the figure. Figure 3A structural schematic diagram of an electronic device for implementing the high-efficiency heat dissipation method of integrating super junction with SiC is provided in an embodiment of the present application.

[0019] Legend of reference signs: 1, electronic device; 10, processor; 11, memory; 12, bus.

[0020] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0021] It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0022] An embodiment of the present application provides a high-efficiency heat dissipation method of integrating super junction with SiC. The execution subject of the high-efficiency heat dissipation method of integrating super junction with SiC includes but is not limited to at least one of electronic devices capable of being configured to execute the method provided by the present application, such as a server and a terminal. In other words, the high-efficiency heat dissipation method of integrating super junction with SiC can be executed by software or hardware installed in a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0023] Reference Figure 1 As shown in the figure, a flowchart of the high-efficiency heat dissipation method of integrating super junction with SiC provided by an embodiment of the present application. In the present embodiment, the high-efficiency heat dissipation method of integrating super junction with SiC includes: S1, obtaining a plurality of super junction silicon epitaxial wafers, and performing the following operations on each super junction silicon epitaxial wafer in the plurality of super junction silicon epitaxial wafers: depositing a transition layer on the super junction silicon epitaxial wafer to obtain a transition super junction wafer.

[0024] It should be explained that the depositing a transition layer on the super junction silicon epitaxial wafer to obtain a transition super junction wafer includes: temporarily bonding the super junction silicon epitaxial wafer and the pre-identified glass carrier to obtain a bonded wafer; mechanically grinding the bonded wafer to obtain a ground bonded wafer; detecting the thickness of the ground bonded wafer, comparing the silicon thickness with a pre-set silicon thickness threshold, if the silicon thickness is greater than or equal to the silicon thickness threshold, the ground bonded wafer is used as the bonded wafer, and the step of mechanically grinding the bonded wafer is returned until the silicon thickness is less than the silicon thickness threshold, and the ground bonded wafer is used as a qualified bonded wafer; if the silicon thickness is less than the silicon thickness threshold, the ground bonded wafer is used as a qualified bonded wafer; mechanically polishing the qualified bonded wafer to obtain a polished bonded wafer; back plating transition is performed on the polished bonding wafer to obtain a wafer with a transition layer; a wafer with a transition layer is obtained by back plating transition on the polished bonding wafer;

[0025] Further, the super junction silicon epitaxial wafer is an epitaxial wafer with a super junction charge balance structure, which is used for subsequent integration with silicon carbide. The glass carrier is a glass substrate used as a temporary support in semiconductor processes. The purpose of using the glass carrier is to provide mechanical support for the super junction silicon epitaxial wafer during subsequent processing to prevent warping or breakage. Optionally, a borosilicate glass substrate is used as the glass carrier. Temporary bonding is a process of bonding the super junction silicon epitaxial wafer glass carrier under vacuum and UV curing. The bonding wafer is a composite structure obtained after temporary bonding, which is composed of a super junction silicon epitaxial wafer and a glass carrier. Mechanical grinding is a process of grinding the substrate on the back of the bonding wafer. The ground bonding wafer is the bonding wafer after mechanical grinding. Optionally, a grinding process is used as the method of mechanical grinding.

[0026] Understandably, thickness detection is a process of measuring the thickness of the silicon layer of the ground bonding wafer using a thickness measuring instrument. Optionally, a laser thickness gauge is used as the method of thickness detection. The silicon thickness is the thickness of the silicon layer obtained by thickness detection. The silicon thickness threshold is a preset target thickness value, for example, 20 microns. The qualified bonding wafer is the ground bonding wafer with a silicon thickness less than or equal to the silicon thickness threshold. Mechanical polishing is a process of using chemical mechanical polishing to planarize the silicon back of the qualified bonding wafer. The purpose is to eliminate the surface damage layer, micro cracks and stress caused by grinding, to obtain a smooth and defect-free silicon surface. The polished bonding wafer is the qualified bonding wafer after mechanical polishing. Back plating transition is a process of sputtering a transition layer of 20nm titanium, 100nm tantalum and 50nm nickel on the silicon back of the qualified bonding wafer to obtain a wafer with a transition layer. The wafer with a transition layer is a wafer structure after the deposition of the transition layer on the silicon back. The wafer cleaning is a process of separating the glass carrier from the wafer with a transition layer and removing the colloid to obtain an independent transition super junction wafer. The transition super junction wafer is a silicon wafer obtained by wafer cleaning.

[0027] S2, low temperature bonding is performed on the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer.

[0028] It should be explained that the low temperature bonding of the transition super junction wafer under the pre-confirmed activation conditions to obtain a heterogeneous integrated wafer includes: obtaining a silicon carbide substrate; polishing the silicon carbide substrate to obtain a polished silicon carbide substrate; roughness detection is performed on the polished silicon carbide substrate to obtain roughness; The roughness is compared with a preset roughness threshold value, if the roughness is greater than or equal to the roughness threshold value, the polished silicon carbide substrate is taken as a silicon carbide substrate, and the step of polishing the silicon carbide substrate is returned, to obtain a polished silicon carbide substrate, until the roughness is less than the roughness threshold value, the polished silicon carbide substrate is taken as a qualified polished substrate; If the roughness is less than the roughness threshold value, the polished silicon carbide substrate is taken as a qualified polished substrate. The qualified polished substrate is subjected to deoxidation treatment to obtain a deoxidized substrate. The transition super junction wafer and the deoxidized substrate are subjected to activated bonding to obtain a hetero-integrated wafer.

[0029] Further, the silicon carbide substrate is a 6H-SiC single wafer used as an integrated substrate. The polished silicon carbide substrate is a silicon carbide substrate with reduced roughness after chemical mechanical polishing. Roughness detection is a process of quantitatively measuring the flatness of the surface of the polished silicon carbide substrate. Optionally, an optical profiler is used as the instrument for roughness detection. Roughness is the surface roughness of the polished silicon carbide substrate obtained by roughness detection. The roughness threshold value is the upper limit of the surface roughness preset for successful bonding, for example, 0.5 nm. The roughness threshold value is determined based on a large number of process experiments. If the roughness is higher than the roughness threshold value, too many gaps will be generated at the bonding interface, resulting in a sharp increase in thermal resistance and a decrease in bonding strength. The qualified polished substrate is a polished silicon carbide substrate with a roughness lower than the roughness threshold value. Deoxidation treatment is a process of removing silicon dioxide generated by oxidation on the surface of the qualified polished substrate. Optionally, soaking in a diluted hydrofluoric acid solution is used as the deoxidation treatment method. The deoxidized substrate is the qualified polished substrate after deoxidation treatment. Activated bonding is a process of activating the surface of the deoxidized substrate and the transition layer surface of the transition super junction wafer, so that the surfaces have dangling bonds and hydrophilicity, and then bonding the surfaces of the deoxidized substrate and the transition layer surface of the transition super junction wafer at room temperature (for example, 26 ), and finally annealing at a low annealing temperature (for example, 400 ) to enhance the bonding strength. The hetero-integrated wafer is a composite wafer structure obtained by activated bonding.

[0030] S3, thinning and activating the hetero-integrated wafer to obtain a thinned hetero-integrated wafer, wherein the thinned hetero-integrated wafer includes an activated silicon carbide layer.

[0031] It should be explained that the thinning and activation is a composite processing process for the silicon carbide substrate in the hetero-integrated wafer. Specifically, the silicon carbide substrate is thinned to a target thickness (for example, 50 ±5 ), to obtain a thinned heterogeneous integrated wafer; annealing the silicon carbide substrate of the thinned heterogeneous integrated wafer under pre-confirmed environmental conditions (under the protection of argon atmosphere, at a temperature of 380 ±10 ), to obtain an annealed heterogeneous integrated wafer; performing oxygen plasma treatment (power 300W, time 60 seconds) on the silicon carbide substrate of the annealed heterogeneous integrated wafer, to obtain a thinned heterogeneous wafer. The thinned heterogeneous wafer is a wafer structure obtained after the thinning activation is completed. The activated silicon carbide layer is the silicon carbide substrate that has undergone thinning activation in the thinned heterogeneous wafer.

[0032] S4, obtain three heat dissipation paths, and perform the following operations on each of the three heat dissipation paths: use the activated silicon carbide layer and the heat dissipation path to construct a microfluid channel, to obtain a sealed microfluid channel.

[0033] It should be explained that the obtaining of the three heat dissipation paths includes: applying a preset electrical power to the thinned heterogeneous wafer and performing heat image acquisition to obtain a high-heat map; mapping the high-heat map to a grid thermal flux matrix, and using the grid thermal flux matrix to obtain a plurality of high-heat unit coordinates; using the plurality of high-heat unit coordinates and pre-confirmed historical heat dissipation paths to plan heat dissipation paths, to obtain a plurality of planned heat dissipation paths; performing fast heat-flow coupling simulation on the plurality of planned heat dissipation paths to obtain a plurality of heat data sets, wherein the heat data sets correspond one-to-one to the planned heat dissipation paths, and the heat data sets include the highest temperature and the average temperature; confirming the three heat dissipation paths based on the plurality of heat data sets.

[0034] Further, the electrical power is the product of a constant operating voltage and current (for example, 100W) applied to excite the super-junction device in the thinned heterogeneous wafer to generate heat, which is used to simulate the heat source distribution under actual working conditions. The heat image acquisition is a process of scanning and recording the temperature field distribution on the surface of the thinned heterogeneous wafer after the electrical power is applied and reaches a thermal steady state. Optionally, an infrared thermal imager is used as the instrument for the heat image acquisition. The thermal steady state is that the temperature of any point on the thinned heterogeneous wafer changes at a rate less than a preset change threshold (for example, within 60 consecutive seconds, the temperature fluctuation of all measurement points does not exceed ±0.1 ). The high heat map is a heat distribution map obtained by heat image acquisition, wherein the temperature of each region of the thinned heterogeneous wafer surface is visually displayed in different colors, and is used to identify the hotspot region with high heat flux density. The gridded heat flux matrix is to divide the high heat map into N×M uniform grid cells, and to obtain a numerical matrix that can quantitatively describe the heat flow distribution of the entire wafer surface according to the center temperature value of each grid cell. For example, (2, 3, 40) represents that the temperature of the grid cell in the second row and the third column of the high heat map is 40 . The high heat cell coordinates are the index coordinates of the grid cells in the gridded heat flux matrix whose center temperature values exceed a preset temperature threshold (for example, 90 . For example, (2, 3) represents the grid cell in the second row and the third column of the high heat map. The historical heat dissipation path is a micro-channel geometric layout mode with high heat dissipation effect summarized from historical device designs, such as a snake-shaped, grid-shaped, back-shaped or bionic fractal structure. The heat dissipation path planning is a process of using a path optimization algorithm (such as a genetic algorithm) to obtain a micro-channel center line trajectory connecting the regions corresponding to the multiple high heat cell coordinates, in combination with the micro-channel geometric layout mode in the historical heat dissipation path library. Optionally, the genetic algorithm is used as the method of heat dissipation path planning. The planned heat dissipation path is a spatial geometric trajectory of the micro-channel center line obtained by heat dissipation path planning.

[0035] It can be understood that the fast heat-flow coupling simulation is a numerical simulation of the planned heat dissipation path on the three-dimensional model, which quickly calculates the temperature field distribution of the thinned heterogeneous wafer and the fluid pressure drop in the micro-channel corresponding to the planned heat dissipation path when the cooling liquid flows through the micro-channel corresponding to the planned heat dissipation path. Optionally, the CFD simulation is used as the method of fast heat-flow coupling simulation. The heat data set is a data set of the fast heat-flow coupling simulation result corresponding to the planned heat dissipation path.

[0036] It should be explained that the three heat dissipation paths are confirmed based on the multiple heat data sets, including: Based on the multiple highest temperatures and the multiple average temperatures in the multiple heat data sets, the maximum highest temperature, the minimum highest temperature and the comprehensive average temperature are obtained. For each heat data set in the multiple heat data sets, the following operations are performed: The heat dissipation score is calculated using the highest temperature, the average temperature, the maximum highest temperature, the minimum highest temperature and the comprehensive average temperature in the heat data set, and the calculation formula is as follows: , wherein, represents the heat dissipation score, represents a preset thermal peak weight coefficient, represents a maximum value of the highest temperature, represents a minimum value of the highest temperature, represents the highest temperature, represents a preset uniform temperature weight coefficient, represents a comprehensive average temperature, represents an average temperature; aggregate the heat dissipation scores to obtain a plurality of heat dissipation scores; sort the plurality of heat dissipation scores in descending order to obtain a heat dissipation score sequence, and aggregate the heat dissipation paths corresponding to the first three heat dissipation scores in the heat dissipation score sequence to obtain three heat dissipation paths.

[0037] Further, the maximum value of the highest temperature is the highest temperature with the largest value among the plurality of highest temperatures. The minimum value of the highest temperature is the highest temperature with the smallest value among the plurality of highest temperatures. The comprehensive average temperature is the average value of the plurality of highest temperatures. The thermal peak weight coefficient is a weight factor representing the influence degree of the highest temperature on the heat dissipation performance, for example, 0.6. The uniform temperature weight coefficient is a weight factor representing the influence degree of the average temperature on the heat dissipation performance, for example, 0.4. The heat dissipation score is a numerical value calculated using the highest temperature, the average temperature, the maximum value of the highest temperature, the minimum value of the highest temperature, and the comprehensive average temperature in the heat data set, for quantitatively evaluating the heat dissipation effect of the corresponding heat dissipation path. Among them, the higher the heat dissipation score, the better the heat dissipation effect of the corresponding heat dissipation path. The heat dissipation score sequence is a sequence obtained by sorting the plurality of heat dissipation scores in descending order. The three heat dissipation paths are the heat dissipation paths corresponding to the first three heat dissipation scores in the heat dissipation score sequence.

[0038] It should be explained that the microfluid channel is constructed by using the activated silicon carbide layer and the heat dissipation path to obtain a sealed microfluid channel, which comprises: obtain a plurality of sets of combination parameters; perform etching standard tests on the pre-confirmed test silicon layer using the plurality of sets of combination parameters to obtain a plurality of etching grooves; obtain a plurality of groove parameter sets based on the plurality of etching grooves, wherein the groove parameter set includes groove depth, groove width, and bottom surface roughness; perform the following operations on each groove parameter set in the plurality of groove parameter sets: calculate an etching score using the groove depth, the groove width, and the bottom surface roughness in the groove parameter set; aggregate the etching scores to obtain a plurality of etching scores; obtain a maximum etching score based on the plurality of etching scores, and use the combination parameter corresponding to the maximum etching score as the final processing parameter; The activated silicon carbide layer is laser etched by using the heat dissipation path and the final machining parameter to obtain a micro-channel groove. The pre-confirmed silicon cover plate is bonded with the micro-channel groove to obtain a sealed micro-channel.

[0039] Further, the combined parameter is a combination of adjustable parameters in the laser etching process, including laser single pulse energy, scanning speed, repetition frequency and processing times. The test silicon layer is a single crystal silicon wafer with similar laser absorption rate and thermal physical properties as the activated silicon carbide layer, which is used for etching process parameter exploration without consuming valuable formal product wafers. The etching standard test on the test silicon layer is a process of etching a straight groove with a standard length and direction using a specific set of combined parameters. The etched groove is a groove formed on the test silicon layer by the etching standard test. The groove parameter set is a set of key parameters for characterizing the etched groove geometry and surface quality, including groove depth, groove width and bottom roughness. The groove depth is the vertical distance from the bottom of the etched groove to the surface of the test silicon layer. The groove width is the distance between the two side edges of the opening of the etched groove. The bottom roughness is a quantitative indicator of the flatness of the bottom surface of the etched groove. The techniques for obtaining the groove parameter set are all prior art and will not be described here. The etching score is an index value for quantitatively evaluating the etching effect of a single set of combined parameters, wherein the etching score calculation formula is as follows: , wherein, represents the etching score, represents the depth weight coefficient, represents the width weight coefficient, represents the roughness weight coefficient, represents the etching depth, represents the target etching depth, represents the etching width, represents the target etching width, represents the target bottom roughness, represents the bottom roughness.

[0040] It can be understood that the depth weight coefficient is the weight coefficient of the groove depth relative to the target depth ratio, for example, 0.4. The width weight coefficient is the weight coefficient of the groove width relative to the target width ratio, for example, 0.3. The roughness weight coefficient is the weight coefficient of the target roughness relative to the actual roughness ratio, for example, 0.3. The target etching depth is the etching depth target value, for example, 150 . The target etching width is the etching width target value, for example, 100 . The target bottom roughness is the bottom roughness target value, for example, 0.5 The maximum etching score is the maximum value among the plurality of etching scores. The final processing parameter is a combination parameter corresponding to the maximum etching score. The laser etching is a process of processing a required micro-channel groove on the back of the activated silicon carbide layer by using the final processing parameter and the heat dissipation path. The micro-channel groove is an open groove with a specific cross-sectional shape and path formed on the activated silicon carbide layer by laser etching. The silicon cover plate is a silicon wafer pre-processed with cooling liquid inlet and outlet through holes, used to seal the micro-channel groove. The sealed micro-channel is a micro-channel system for cooling liquid flow obtained by bonding the silicon cover plate with the activated silicon carbide layer with the micro-channel groove.

[0041] S5, detecting the cooling performance of the sealed micro-channel to obtain a cooling performance score.

[0042] It should be explained that the detection of the cooling performance of the sealed micro-channel to obtain a cooling performance score includes: conducting a steady-state heat dissipation test on the sealed micro-channel to obtain a thermal steady-state micro-channel; obtaining an inlet temperature, an outlet temperature, a port pressure difference and a cooling liquid flow based on the thermal steady-state micro-channel; calculating the cooling performance score by using the inlet temperature, the outlet temperature, the port pressure difference and the cooling liquid flow, wherein the calculation formula is as follows: , wherein, represents the cooling performance score, represents a preset constant power, represents the cooling liquid flow, represents the inlet temperature, represents the outlet temperature, represents the port pressure difference.

[0043] Further, the steady-state heat dissipation test is a process of supplying a constant flow of cooling liquid (for example, deionized water) to the sealed micro-channel, while applying a constant electric power to the thinned heterogeneous wafer and maintaining it in a thermal equilibrium state. The thermal steady-state micro-channel is the sealed micro-channel in a thermal equilibrium state. The inlet temperature is the measured temperature of the cooling liquid entering the sealed micro-channel. The outlet temperature is the measured temperature of the cooling liquid flowing out of the sealed micro-channel. Optionally, a temperature sensor is used as the instrument for obtaining the inlet temperature and the outlet temperature. The port pressure difference is the measured static pressure difference of the cooling liquid between the inlet and the outlet of the sealed micro-channel. Optionally, a pressure gauge is used as the instrument for obtaining the port pressure difference. The cooling liquid flow is the volume of the cooling liquid flowing through the sealed micro-channel per unit time. The cooling performance score is a quantitative index for comprehensively evaluating the heat dissipation efficiency of the sealed micro-channel. The constant power is the electric power value applied to the thinned heterogeneous wafer, for example, 100 W.

[0044] S6, aggregate the cooling performance scores to obtain three cooling performance scores, and obtain an optimal heat dissipation path based on the three cooling performance scores.

[0045] It should be explained that obtaining an optimal heat dissipation path based on the three cooling performance scores means that the heat dissipation path corresponding to the cooling performance score with the maximum value among the three cooling performance scores is taken as the optimal heat dissipation path.

[0046] S7, cooling is performed at a plurality of gradient flow rates using the optimal heat dissipation path, and a device output power is recorded to obtain an output power set, and an optimal flow rate is obtained based on the gradient flow rates and the output power set.

[0047] It should be explained that the optimal flow rate is obtained based on the gradient flow rates and the output power set, including: curve fitting is performed on the gradient flow rates and the output power set to obtain a flow rate-power relationship curve; a plurality of unit flow rate power gains are calculated based on the flow rate-power relationship curve and a preset flow rate interval; a power gain curve is constructed using the plurality of unit flow rate power gains; a peak gain is obtained based on the plurality of unit flow rate power gains; a gain threshold is obtained based on the peak gain; the optimal flow rate is determined based on the gain threshold and the power gain curve.

[0048] Further, the gradient flow rates are a set of pre-set cooling liquid flow rate values, for example, 10, 20, 30, 40, 50, 60, 70 . The device output power is the maximum electrical power that can be stably output by the super-junction device under the cooling condition of a certain gradient flow rate. It is used to represent the actual working ability of the thinned heterogeneous wafer under the cooling effect corresponding to the gradient flow rate. The output power set is a collection of device output powers corresponding to a plurality of gradient flow rates. Curve fitting is a process of fitting a plurality of device output powers in the output power set to obtain a continuous and smooth function curve. Optionally, the least squares method is used as the curve fitting method. The flow rate-power relationship curve is a curve drawn by taking the gradient flow rate as the horizontal coordinate and the corresponding unit flow rate power gain as the vertical coordinate through curve fitting. It is used to represent the change trend between the gradient flow rate and the device output power. The flow rate interval is a flow rate change range set for calculating the unit flow rate power gain, for example, 5 . The unit flow rate power gain is the change amount of the device output power corresponding to the unit flow rate change within a certain flow rate interval on the flow rate-power relationship curve, wherein the unit flow rate power gain calculation formula is as follows: , wherein, a unit flow rate power gain, a flow rate interval, a change in output power in the flow rate interval.

[0049] It can be understood that the power gain curve is a curve drawn with the gradient flow rate as the abscissa and the unit flow rate power gain as the ordinate. The peak gain is the maximum unit flow rate power gain in the plurality of unit flow rate power gains. The gain threshold is a threshold set based on the peak gain, for example, 10% of the peak gain, and the peak gain is 6, then the gain threshold is 0.6. The optimal flow rate is the gradient flow rate corresponding to the first time when the unit flow rate power gain drops to equal to or below the gain threshold in the direction of the gradient flow rate from large to small on the power gain curve.

[0050] S8, based on the optimal heat dissipation path, the optimal flow rate and the thinned heterogeneous wafer, obtaining a heat dissipation wafer, collecting the heat dissipation wafers to obtain a plurality of heat dissipation wafers, and performing reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers.

[0051] It should be explained that the reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers includes: performing the following operations on each of the plurality of heat dissipation wafers; performing a thermal cycle test on the heat dissipation wafer to obtain a tested wafer; performing interface image acquisition on the tested wafer to obtain an interface image; performing delamination detection on the interface image to obtain a delamination area; collecting the delamination areas to obtain a plurality of delamination areas; the heat dissipation wafer corresponding to the delamination area less than or equal to the delamination area threshold is regarded as a qualified heat dissipation wafer, and the qualified heat dissipation wafers are collected to obtain a plurality of qualified heat dissipation wafers.

[0052] It can be understood that based on the optimal heat dissipation path, the optimal flow rate and the thinned heterogeneous wafer, the heat dissipation wafer is obtained by constructing a micro-flow channel on the thinned heterogeneous wafer based on the optimal heat dissipation path, and the cooling liquid is transported at the optimal flow rate to obtain the heat dissipation wafer. The heat dissipation wafer is applied to the thinned heterogeneous wafer cooled by the optimal heat dissipation path and the optimal flow rate.

[0053] Further, the thermal cycle test is to make the environment temperature of the heat dissipation wafer at a high temperature (for example, 125 ) and a low temperature (for example, 40 ) between the two temperatures. The process is repeated for multiple cycles (e.g., 1000 times). The process is used to simulate the thermal stress impact of environmental temperature changes in actual use to examine the durability of the structure. The wafer after testing is a heat dissipation wafer after thermal cycle testing. The interface image acquisition is a process of scanning and imaging the key interface (the bonding interface between the super-junction device layer and the silicon carbide substrate) of the wafer after testing. Optionally, an ultrasonic scanning microscope is used as the method of interface image acquisition. The interface image is an image obtained by interface image acquisition for subsequent delamination detection, wherein different material layers in the interface image exhibit different gray scales. The delamination detection is a process of analyzing the interface image, automatically identifying and extracting the separation area (i.e., the delamination area) of the bonding interface due to thermal stress failure. Optionally, an edge detection algorithm is used as the method of delamination detection. The delamination area is the total area of all delamination areas obtained by delamination detection, expressed as a percentage of the entire bonding interface area. The delamination area threshold is an upper limit value of a reliability qualification standard, for example, 1%. If the delamination area is greater than the delamination area threshold, the contact thermal resistance will significantly increase, resulting in a sharp degradation of heat dissipation performance and an inability to guarantee the service life of the device. The qualified heat dissipation wafer is a heat dissipation wafer with an interface delamination area less than or equal to the delamination area threshold.

[0054] The present application is to solve the problems in the background art. The present application obtains a plurality of super junction silicon epitaxial wafers, and performs the following operations on each super junction silicon epitaxial wafer: transition layer deposition is performed on the super junction silicon epitaxial wafer to obtain a transition super junction wafer, low-temperature bonding is performed on the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer, and thinning activation is performed on the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer. The present application embodiment forms a high-quality, low-defect activated silicon carbide layer by transition layer deposition and low-temperature bonding of super junction silicon and silicon carbide hetero-integration and thinning activation, providing a reliable heterogeneous wafer foundation for subsequent direct construction of high-efficiency heat dissipation microchannels thereon. Based on this, the present application obtains three heat dissipation paths, and performs the following operations on each heat dissipation path: microchannel construction is performed on the activated silicon carbide layer and the heat dissipation path to obtain a sealed microchannel, cooling performance detection is performed on the sealed microchannel to obtain a cooling performance score, the cooling performance scores are summarized to obtain three cooling performance scores, and the optimal heat dissipation path is obtained based on the three cooling performance scores. The present application embodiment can quickly lock the optimal heat dissipation path by constructing and measuring three sealed microchannels in parallel on the activated silicon carbide layer, quantitatively comparing the cooling performance scores, and providing a reliable basis for subsequent flow rate optimization, thereby avoiding blind trial and error. Further, the present application cools the device output power by using the optimal heat dissipation path at a plurality of gradient flow rates, records the output power to obtain an output power set, and obtains the optimal flow rate based on the gradient flow rate and the output power set. The present application embodiment can accurately lock the best balance point of heat dissipation and energy consumption by gradient scanning the flow rate and recording the output power in real time under the optimal heat dissipation path, thereby obtaining the optimal flow rate that guarantees device output and avoids energy waste. Next, the present application obtains a heat dissipation wafer based on the optimal heat dissipation path, the optimal flow rate, and the thinned heterogeneous wafer, summarizes the heat dissipation wafers to obtain a plurality of heat dissipation wafers, and performs reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers. The present application embodiment can batch produce and uniformly verify the heat dissipation wafers under the optimal heat dissipation path and the optimal flow rate, thereby one-time screening a plurality of qualified heat dissipation wafers to ensure that the heat dissipation performance and reliability are highly consistent within the batch. Therefore, the present application can solve the problems of performance degradation and reliability decline caused by heat accumulation in super junction and SiC integration.

[0055] As Figure 2 shown is a functional module diagram of the high-efficiency heat dissipation system for super junction and SiC integration provided by an embodiment of the present application.

[0056] The super junction and SiC integrated high-efficiency heat dissipation system 100 can be installed in an electronic device. According to the functions implemented, the super junction and SiC integrated high-efficiency heat dissipation system 100 can include a device bonding activation module 101, a heat dissipation path planning module 102, an optimal flow rate confirmation module 103, and a sample quality detection module 104. The modules described in the present application can also be referred to as units, which refer to a series of computer program segments that can be executed by an electronic device processor and can complete a fixed function, which are stored in the memory of the electronic device.

[0057] The device bonding activation module 101 is configured to obtain a plurality of super junction silicon epitaxial wafers, and perform the following operations on each of the plurality of super junction silicon epitaxial wafers: Performing transition layer deposition on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; Performing low-temperature bonding on the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer; Performing thinning activation on the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer; The heat dissipation path planning module 102 is configured to obtain three heat dissipation paths, and perform the following operations on each of the three heat dissipation paths: Performing micro-channel construction using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; Performing cooling performance detection on the sealed micro-channel to obtain a cooling performance score; Summarizing the cooling performance scores to obtain three cooling performance scores, and obtaining an optimal heat dissipation path based on the three cooling performance scores; The optimal flow rate confirmation module 103 is configured to cool using the optimal heat dissipation path at a plurality of gradient flow rates, and record the device output power to obtain an output power set; Obtaining an optimal flow rate based on the gradient flow rate and the output power set; The sample quality detection module 104 is configured to obtain a heat dissipation wafer based on the optimal heat dissipation path, the optimal flow rate, and the thinned heterogeneous wafer, and summarize the heat dissipation wafers to obtain a plurality of heat dissipation wafers; Performing reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers.

[0058] In detail, the modules in the super junction and SiC integrated high-efficiency heat dissipation system 100 in the embodiments of the present application use the same technical means as the super junction and SiC integrated high-efficiency heat dissipation method described in the above Figure 1 , and can produce the same technical effects, which will not be described here.

[0059] As Figure 3As shown is a structural schematic diagram of an electronic device provided by an embodiment of the present application, which realizes the high-efficiency heat dissipation method of super junction and SiC integration.

[0060] The electronic device 1 can include a processor 10, a memory 11 and a bus 12, and can further include a computer program stored in the memory 11 and executable on the processor 10, such as the high-efficiency heat dissipation method of super junction and SiC integration program.

[0061] The memory 11 includes at least one type of readable storage medium, such as flash memory, mobile hard disk, multimedia card, card-type memory (for example, SD or DX memory, etc.), magnetic memory, disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 11 can also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. equipped on the electronic device 1. Further, the memory 11 includes not only the internal storage unit of the electronic device 1, but also the external storage device. The memory 11 can be used not only to store application software and various data installed on the electronic device 1, such as the code of the high-efficiency heat dissipation method of super junction and SiC integration program, but also to temporarily store data that has been output or will be output.

[0062] The processor 10 can be composed of integrated circuits in some embodiments, such as a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same function or different functions, including one or more combinations of central processing unit (CPU), microprocessor, digital processing chip, graphics processor and various control chips, etc. The processor 10 is the control unit of the electronic device, which connects various components of the entire electronic device through various interfaces and lines, executes or runs the program or module stored in the memory 11 (such as the high-efficiency heat dissipation method of super junction and SiC integration program, etc.), and calls the data stored in the memory 11, to perform various functions and process data of the electronic device 1.

[0063] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to enable connection and communication between the memory 11, the at least one processor 10, etc.

[0064] Figure 3 Only the electronic device with components is shown, and those skilled in the art can understand that, Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and can include fewer or more components than shown, or combine certain components, or different component arrangements.

[0065] For example, although not shown, the electronic device 1 can also include a power supply (such as a battery) to power each component. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management system, so that the power management system can realize functions such as charge management, discharge management, and power consumption management. The power supply can also include one or more direct current or alternating current power supplies, a recharging system, a power supply fault detection circuit, a power supply converter or inverter, a power supply status indicator, etc. The electronic device 1 can also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which are not described here.

[0066] Further, the electronic device 1 can also include a network interface, which can optionally include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), and is typically used to establish a communication connection between the electronic device 1 and other electronic devices.

[0067] Optionally, the electronic device 1 can also include a user interface, which can be a display (Display), an input unit (such as a keyboard (Keyboard)), and optionally a standard wired interface, a wireless interface. Optionally, in some embodiments, the display can be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch, etc. The display can also be appropriately referred to as a display screen or a display unit, and is used to display information processed in the electronic device 1 and to display a visualized user interface.

[0068] It should be understood that the embodiments are only for illustration and are not limited in the scope of the patent application by this structure.

[0069] The super junction and SiC integrated high-efficiency heat dissipation method program stored in the memory 11 in the electronic device 1 is a combination of multiple instructions, which can realize the following when running in the processor 10: Obtain a plurality of super junction silicon epitaxial wafers, and perform the following operations on each of the plurality of super junction silicon epitaxial wafers: Depositing a transition layer on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; Performing low-temperature bonding on the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer; Thinning and activating the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer; Obtaining three heat dissipation paths, and performing the following operations on each of the three heat dissipation paths: Constructing a micro-channel using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; Performing cooling performance detection on the sealed micro-channel to obtain a cooling performance score; Summarizing the cooling performance scores to obtain three cooling performance scores, and obtaining an optimal heat dissipation path based on the three cooling performance scores; Cooling using the optimal heat dissipation path at a plurality of preset gradient flow rates, and recording the device output power to obtain an output power set; Obtaining an optimal flow rate based on the gradient flow rate and the output power set; Obtaining a heat dissipation wafer based on the optimal heat dissipation path, the optimal flow rate, and the thinned heterogeneous wafer, and summarizing the heat dissipation wafers to obtain a plurality of heat dissipation wafers; Performing reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers.

[0070] Specifically, the specific implementation method of the processor 10 on the above instructions can refer to Figures 1 to 3 The description of related steps in the corresponding embodiments is omitted here.

[0071] Further, the modules / units integrated in the electronic device 1, if realized in the form of software function units and sold or used as independent products, can be stored in a computer readable storage medium. The computer readable storage medium can be volatile or non-volatile. For example, the computer readable medium can include any entity or system capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory).

[0072] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program can realize the following steps when executed by a processor of an electronic device: A plurality of super junction silicon epitaxial wafers are obtained, and the following operations are performed on each super junction silicon epitaxial wafer in the plurality of super junction silicon epitaxial wafers: Transition layer deposition is performed on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; Low-temperature bonding is performed on the transition super junction wafer under pre-confirmed activation conditions to obtain a hetero-integrated wafer; Thinning activation is performed on the hetero-integrated wafer to obtain a thinned hetero wafer, wherein the thinned hetero wafer comprises an activated silicon carbide layer; Three heat dissipation paths are obtained, and the following operations are performed on each heat dissipation path in the three heat dissipation paths: Micro-channel construction is performed on the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; Cooling performance detection is performed on the sealed micro-channel to obtain a cooling performance score; The cooling performance scores are summarized to obtain three cooling performance scores, and an optimal heat dissipation path is obtained based on the three cooling performance scores; Cooling is performed on the optimal heat dissipation path at a plurality of preset gradient flow rates, and a device output power is recorded to obtain an output power set; An optimal flow rate is obtained based on the gradient flow rate and the output power set; A heat dissipation wafer is obtained based on the optimal heat dissipation path, the optimal flow rate and the thinned hetero wafer, and the heat dissipation wafers are summarized to obtain a plurality of heat dissipation wafers; Reliability verification is performed on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers.

[0073] In several embodiments provided in the application, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative, and actual implementation can have another division way.

[0074] The modules described as separate components can or can not be physically separated, and the components displayed as modules can or can not be physical units, that is, they can be located in one place or distributed on multiple network units. According to actual needs, part or all of the modules can be selected to achieve the purpose of the embodiment scheme.

[0075] In addition, each function module in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of hardware plus software function module.

[0076] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be realized in other specific forms without departing from the spirit or essential characteristics of the present application.

[0077] Furthermore, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or systems stated in a system claim can also be implemented by one unit or system through software or hardware. The word "comprise" is used to indicate names, and does not indicate any specific order.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A high-efficiency heat dissipation method integrating super junction with SiC, characterized in that, The method comprises: obtaining a plurality of super junction silicon epitaxial wafers, and performing the following operations on each of the plurality of super junction silicon epitaxial wafers: depositing a transition layer on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; performing low-temperature bonding on the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer; performing thinning activation on the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer comprises an activated silicon carbide layer; obtaining three heat dissipation paths, and performing the following operations on each of the three heat dissipation paths: constructing a micro-channel using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; performing cooling performance detection on the sealed micro-channel to obtain a cooling performance score; obtaining three cooling performance scores by aggregating the cooling performance scores, and obtaining an optimal heat dissipation path based on the three cooling performance scores; cooling at a plurality of gradient flow rates according to the optimal heat dissipation path, and recording device output power to obtain an output power set; obtaining an optimal flow rate based on the gradient flow rate and the output power set; obtaining a heat dissipation wafer based on the optimal heat dissipation path, the optimal flow rate, and the thinned heterogeneous wafer, and aggregating the heat dissipation wafers to obtain a plurality of heat dissipation wafers; performing reliability verification on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers.

2. The method of claim 1, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The method comprises: temporarily bonding the super junction silicon epitaxial wafer and a pre-confirmed glass carrier to obtain a bonded wafer; mechanically grinding the bonded wafer to obtain a ground bonded wafer; performing thickness detection on the ground bonded wafer to obtain a silicon thickness, comparing the silicon thickness with a pre-set silicon thickness threshold, and if the silicon thickness is greater than or equal to the silicon thickness threshold, regarding the ground bonded wafer as a bonded wafer and returning to the step of mechanically grinding the bonded wafer until the silicon thickness is less than the silicon thickness threshold, and regarding the ground bonded wafer as a qualified bonded wafer; if the silicon thickness is less than the silicon thickness threshold, regarding the ground bonded wafer as a qualified bonded wafer; mechanically polishing the qualified bonded wafer to obtain a polished bonded wafer; back plating the transition layer on the polished bonded wafer to obtain a wafer with a transition layer; peeling and cleaning the wafer with the transition layer to obtain a transition super junction wafer.

3. The method of claim 2, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The method comprises: obtaining a silicon carbide substrate; performing polishing treatment on the silicon carbide substrate to obtain a polished silicon carbide substrate; performing roughness detection on the polished silicon carbide substrate to obtain a roughness; comparing the roughness with a pre-set roughness threshold, and if the roughness is greater than or equal to the roughness threshold, regarding the polished silicon carbide substrate as a silicon carbide substrate and returning to the step of polishing the silicon carbide substrate to obtain a polished silicon carbide substrate until the roughness is less than the roughness threshold, and regarding the polished silicon carbide substrate as a qualified polished substrate; if the roughness is less than the roughness threshold, regarding the polished silicon carbide substrate as a qualified polished substrate; performing deoxidation treatment on the qualified polished substrate to obtain a deoxidized substrate; activating bonding the transition super junction wafer and the deoxidized substrate to obtain a heterogeneous integrated wafer.

4. The method of claim 3, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The method comprises: Applying a preset electric power on the thinned heterogeneous wafer, and collecting a thermal image to obtain a high-heat map; Mapping the high-heat map into a grid thermal flux matrix, and obtaining a plurality of high-heat unit coordinates by using the grid thermal flux matrix; Planning a plurality of heat dissipation paths by using the plurality of high-heat unit coordinates and a pre-confirmed historical heat dissipation path, to obtain the plurality of planned heat dissipation paths; Performing fast heat-flow coupling simulation on the plurality of planned heat dissipation paths to obtain a plurality of heat data sets, wherein the heat data sets correspond to the planned heat dissipation paths one by one, and each heat data set includes a maximum temperature and an average temperature; Confirming three heat dissipation paths based on the plurality of heat data sets.

5. The method of claim 4, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The confirming three heat dissipation paths based on the plurality of heat data sets includes: Obtaining a maximum value of the maximum temperature, a minimum value of the maximum temperature and a comprehensive average temperature based on a plurality of maximum temperatures and a plurality of average temperatures in the plurality of heat data sets; For each heat data set in the plurality of heat data sets, performing the following operations: Calculating a heat dissipation score by using the maximum temperature, the average temperature, the maximum value of the maximum temperature, the minimum value of the maximum temperature and the comprehensive average temperature in the heat data set, wherein the calculation formula is as follows: ， wherein, represents a heat dissipation score, represents a preset heat peak weight coefficient, represents a maximum value of the highest temperature, represents a minimum value of the highest temperature, represents the highest temperature, represents a preset uniform temperature weight coefficient, represents a comprehensive average temperature, represents an average temperature; Summarizing the heat dissipation scores to obtain a plurality of heat dissipation scores; Sorting the plurality of heat dissipation scores in descending order to obtain a heat dissipation score sequence, and summarizing the heat dissipation paths corresponding to the first three heat dissipation scores in the heat dissipation score sequence to obtain the three heat dissipation paths.

6. The method of claim 5, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The micro-channel construction by using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel includes: Obtaining a plurality of groups of combination parameters; Performing etching standard tests on the pre-confirmed test silicon layer by using the plurality of groups of combination parameters to obtain a plurality of etching grooves; Obtaining a plurality of groove parameter sets based on the plurality of etching grooves, wherein each groove parameter set includes a groove depth, a groove width and a bottom surface roughness; For each groove parameter set in the plurality of groove parameter sets, performing the following operations: Calculating an etching score by using the groove depth, the groove width and the bottom surface roughness in the groove parameter set; Summarizing the etching scores to obtain a plurality of etching scores; Obtaining a maximum etching score based on the plurality of etching scores, and taking the combination parameters corresponding to the maximum etching score as final machining parameters; Performing laser etching on the activated silicon carbide layer by using the heat dissipation path and the final machining parameters to obtain a micro-channel groove; Bonding the pre-confirmed silicon cover plate with the micro-channel groove to obtain a sealed micro-channel.

7. The method of claim 6, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The cooling performance detection on the sealed micro-channel to obtain a cooling performance score includes: Performing a steady-state heat dissipation test on the sealed micro-channel to obtain a thermal steady-state micro-channel; Obtaining an inlet temperature, an outlet temperature, a port pressure difference and a cooling liquid flow rate based on the thermal steady-state micro-channel; Calculating a cooling performance score by using the inlet temperature, the outlet temperature, the port pressure difference and the cooling liquid flow rate, wherein the calculation formula is as follows: ， wherein, represents a cooling performance score, represents a preset constant power, represents a coolant flow rate, represents an inlet temperature, represents an outlet temperature, represents a port differential pressure.

8. The method of claim 7, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The obtaining an optimal flow rate based on the gradient flow rate and the output power set includes: Performing curve fitting on the gradient flow rate and the output power set to obtain a flow rate-power relationship curve; Calculating a plurality of unit flow rate power gains based on the flow rate-power relationship curve and a preset flow rate interval; Constructing a power gain curve by using the plurality of unit flow rate power gains; Obtaining a peak gain based on the power gain of the plurality of unit flow rates; Obtaining a gain threshold based on the peak gain; Confirming an optimal flow rate based on the gain threshold and the power gain curve.

9. The method of claim 8, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The reliability verification of the plurality of heat dissipation wafers obtains a plurality of qualified heat dissipation wafers, which comprises: The following operations are performed on each of the plurality of heat dissipation wafers: Performing a thermal cycle test on the heat dissipation wafer to obtain a tested wafer; Performing interface image acquisition on the tested wafer to obtain an interface image; Performing delamination detection on the interface image to obtain a delamination area; Summarizing the delamination areas to obtain a plurality of delamination areas; The heat dissipation wafers corresponding to the delamination areas less than or equal to the delamination area threshold are regarded as qualified heat dissipation wafers, and the qualified heat dissipation wafers are summarized to obtain a plurality of qualified heat dissipation wafers.

10. A high-efficiency heat dissipation system integrated with super junction and SiC, characterized in that, The system comprises: A device bonding activation module for obtaining a plurality of super junction silicon epitaxial wafers, and performing the following operations on each of the plurality of super junction silicon epitaxial wafers: Performing transition layer deposition on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; Performing low-temperature bonding on the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer; Performing thinning activation on the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer comprises an activated silicon carbide layer; A heat dissipation path planning module for obtaining three heat dissipation paths, and performing the following operations on each of the three heat dissipation paths: Performing micro-channel construction using the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; Performing cooling performance detection on the sealed micro-channel to obtain a cooling performance score; Summarizing the cooling performance scores to obtain three cooling performance scores, and obtaining an optimal heat dissipation path based on the three cooling performance scores; An optimal flow rate confirmation module for cooling the device using the optimal heat dissipation path at a plurality of gradient flow rates, and recording the output power of the device to obtain an output power set; Obtaining an optimal flow rate based on the gradient flow rates and the output power set; A sample quality detection module for obtaining heat dissipation wafers based on the optimal heat dissipation path, the optimal flow rate, and the thinned heterogeneous wafer, and summarizing the heat dissipation wafers to obtain a plurality of heat dissipation wafers; The reliability verification of the plurality of heat dissipation wafers obtains a plurality of qualified heat dissipation wafers.

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