Display panel

Abstract

The invention provides a display panel, the display panel is provided with a plurality of display areas, each display area is provided with a plurality of rows of pixels, the display panel comprises a gate drive circuit and a selection control circuit, and the selection control circuit is configured to generate a first initial signal and a second initial signal according to a frame inversion signal, a stage transmission signal and a level signal. Corresponding to an Nth frame of the display panel, the gate driving circuit is configured to generate a plurality of first gate signals in response to one of a first start signal and a second start signal, and generate a plurality of second gate signals in response to a frame start signal, the plurality of first gate signals and the plurality of second gate signals are respectively used for controlling multiple rows of pixels of two adjacent display areas to be turned on, and the display areas corresponding to the turned-on pixels in two adjacent frames are partially overlapped, so that the pixels of only two display areas in the plurality of display areas are charged during a frame period, and the display effect is improved. Therefore, the power consumption of the display panel during one frame is reduced.

Description

[0001] This divisional application is based on a Chinese patent application No. 202311869857.2 filed on December 29, 2023, with the title of “Display panel”. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0003] The existing display panel generally outputs a plurality of clock signals to the gate driving circuit through the level converter electrically connected with the control chip, and the gate driving circuit generates a voltage for controlling the on-off of the transistors of the pixels of the plurality of rows of pixels of the display panel according to the plurality of clock signals, so as to control the pixels to be opened row by row, and the data signal is transmitted to each pixel in the pixel row whose gate is opened by the plurality of data lines.

[0004] Since the gate driving circuit of the conventional display panel needs to open the pixels row by row from the first row of pixels to the last row of pixels during a frame period until the charging of all the pixels of the display panel is completed, so as to realize the display of one frame of picture, therefore, for the high-resolution display panel with a large number of rows of pixels, the amount of data signal that needs to be transmitted by the display panel during a frame period is large, which leads to high power consumption of the display panel.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. SUMMARY

[0006] The purpose of the present application is to provide a display panel to reduce the power consumption of the display panel.

[0007] To solve the above problems, the technical solution of the present application is as follows:

[0008] The present application provides a display panel, the display panel has a plurality of display areas, each of the display areas is provided with a plurality of rows of pixels; the display panel comprises a gate driving circuit and a selection control circuit. The gate driving circuit is electrically connected with the plurality of rows of pixels of the plurality of display areas; the selection control circuit is electrically connected with the gate driving circuit, and the selection control circuit is configured to generate a first start signal and a second start signal according to a received frame inversion signal, a level signal input by a level signal input terminal and a stage transmission signal. Wherein, in the Nth frame of the display panel, the gate driving circuit is configured to generate a plurality of first gate signals in response to one of the first start signal and the second start signal, and generate a plurality of second gate signals in response to a frame start signal, the plurality of first gate signals and the plurality of second gate signals are respectively used for controlling a plurality of rows of pixels of two adjacent display areas to be opened, and the display areas corresponding to the pixels opened in adjacent two frames have a partial overlap, N≥1, and N is a positive integer.

[0009] Optionally, in some embodiments of the present application, in the N+1th frame of the display panel, the gate drive circuit is configured to generate a plurality of third gate signals in response to the other one of the first start signal and the second start signal, and generate a plurality of the second gate signals in response to the frame start signal, the plurality of third gate signals and the plurality of second gate signals being used to control a plurality of rows of pixels of two adjacent display areas to be turned on, respectively. The display area corresponding to the plurality of rows of pixels turned on in the Nth frame in response to the plurality of first gate signals and the display area corresponding to the plurality of rows of pixels turned on in the N+1th frame in response to the plurality of third gate signals are different display areas.

[0010] Optionally, in some embodiments of the present application, one of the first start signal and the second start signal has a corresponding active pulse in the Nth frame for causing the gate drive circuit to generate the plurality of first gate signals. The other one of the first start signal and the second start signal has a corresponding active pulse in the N+1th frame for causing the gate drive circuit to generate the plurality of third gate signals.

[0011] Optionally, in some embodiments of the present application, in the Nth frame, the first start signal has an active pulse, and the active pulse of the first start signal lags behind the active pulse of the frame start signal. In the N+1th frame, the second start signal has an active pulse, and the active pulse of the second start signal lags behind the active pulse of the frame start signal.

[0012] Optionally, in some embodiments of the present application, the frame inversion signal has a jump between a high level and a low level in a switching period corresponding to two adjacent frames.

[0013] Optionally, in some embodiments of the present application, the gate drive circuit comprises a plurality of shift register units, and an output terminal of a shift register unit is electrically connected to a row of pixels. Among the display areas corresponding to the plurality of rows of pixels turned on in the Nth frame and the N+1th frame in response to the plurality of second gate signals, a signal output by the shift register unit corresponding to the last row of pixels is used as the stage transmission signal transmitted to the selection control circuit.

[0014] Optionally, in some embodiments of the present application, in the Nth frame, the first start signal has an active pulse, and the active pulse of the first start signal overlaps with a period in which the stage transmission signal has an active pulse. In the N+1th frame, the second start signal has an active pulse, and the active pulse of the second start signal overlaps with a period in which the stage transmission signal has an active pulse.

[0015] Optionally, in some embodiments of the present application, the selection control circuit includes a first selection control circuit and a second selection control circuit. In one frame, the gate drive circuit is configured to generate a plurality of the second gate signals in response to the frame start signal to control a plurality of rows of the pixels in one of the display areas to turn on, and to output a plurality of signals to control a plurality of rows of the pixels in another of the display areas to turn on in response to one of the first start signal and the second start signal generated by the first selection control circuit and one of the first start signal and the second start signal generated by the second selection control circuit.

[0016] Optionally, in some embodiments of the present application, in a part of the frame, the gate drive circuit is configured to generate a plurality of the second gate control signals in response to the frame start signal to control a plurality of rows of the pixels in one of the display areas to turn on. In another part of the frame, the gate drive circuit is configured to output a plurality of signals to control a plurality of rows of the pixels in another of the display areas to turn on in response to one of the first start signal and the second start signal generated by the first selection control circuit and one of the first start signal and the second start signal generated by the second selection control circuit.

[0017] Optionally, in some embodiments of the present application, in the another part of the frame, the gate drive circuit is configured to output a plurality of signals in response to one of the first start signal and the second start signal generated by the first selection control circuit to control the pixels in odd rows in the corresponding display area to turn on, and to output a plurality of signals in response to one of the first start signal and the second start signal generated by the second selection control circuit to control the pixels in even rows in the corresponding display area to turn on.

[0018] Optionally, in some embodiments of the present application, in the display area for receiving a plurality of the second gate signals, the last row of the pixels correspond to receive the second gate signal as the stage transmission signal transmitted to the first selection control circuit, and the last row of the pixels correspond to receive the second gate signal as the stage transmission signal transmitted to the second selection control circuit.

[0019] Optionally, in some embodiments of the present application, the level signal input end comprises a first low level signal input end and a second low level signal input end. The selection control circuit comprises a first control unit and a second control unit. The first control unit is configured to generate the first start signal according to one of the high level and the low level of the frame inversion signal, the corresponding stage transmission signal and the level signal supplied by the first low level signal input end. The second control unit is configured to generate the second start signal according to the other of the high level and the low level of the frame inversion signal, the corresponding stage transmission signal and the level signal supplied by the second low level signal input end.

[0020] In the present application, by making the display panel comprise a gate drive circuit and a selection control circuit, and the selection control circuit is configured to generate a first start signal and a second start signal according to a frame inversion signal, a stage transmission signal and a level signal, the gate drive circuit is configured to generate a plurality of first gate signals in response to one of the first start signal and the second start signal in the Nth frame, and generate a plurality of second gate signals in response to a frame start signal, the plurality of first gate signals and the plurality of second gate signals are respectively used to control a plurality of rows of pixels of two adjacent display areas to be turned on, and the display areas corresponding to the pixels turned on in the adjacent two frames have a partial overlap, so that during a frame, only the pixels of two display areas in a plurality of display areas are charged, thereby reducing the power consumption of the display panel during a frame. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a schematic diagram of the selection control circuit provided by Embodiment One of the present application;

[0022] Figure 2 is a circuit diagram of the selection control circuit shown in Figure 1

[0023] Figure 3 is a schematic diagram of the display panel provided by Embodiment One of the present application;

[0024] Figure 4 is a schematic diagram of the connection relationship between the gate drive circuit and the selection control circuit shown in Figure 3

[0025] Figure 5 is a timing diagram of the gate drive circuit and the selection control circuit shown in Figure 4

[0026] Figure 6 is a schematic diagram of the display panel provided by Embodiment Two of the present application;

[0027] Figure 7 is a schematic diagram of the connection relationship between the gate drive circuit and the selection control circuit of the present application. DETAILED DESCRIPTION​​​

[0028] The meanings of the terms used in the specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which the present application pertains. The terms used in the specification and claims are only for the purpose of facilitating the description and understanding of the present application, and are not intended to limit the present application to the narrow interpretation of the specific terms used in the specification and claims.

[0029] Referring to Figures 1 to 7 The present application provides a display panel, which comprises a first display area 101, a second display area 102 and a third display area 103, wherein the first display area 101, the second display area 102 and the third display area 103 are arranged in sequence along a first direction Y. The present application divides the display panel into at least three display areas along the first direction Y, so as to control the three display areas respectively.

[0030] In the present application, the display panel further comprises a plurality of rows of pixels arranged in sequence along the first direction Y, a gate driving circuit and a selection control circuit 200.

[0031] The gate driving circuit comprises a plurality of stages of shift register units, and the output end of a stage of shift register units is electrically connected with a row of pixels.

[0032] The selection control circuit 200 comprises a frame inversion signal input end FHL, a stage transmission signal input end Gm1_IN, a first start signal output end STV2 and a second start signal output end STV3. The stage transmission signal input end Gm1_IN is electrically connected with the stage transmission signal output end of the shift register unit Gm1 located in the last row of pixels in the second display area 102. The first start signal output end STV2 is electrically connected with the input end of the shift register unit Gm1+1 located in the first row of pixels in the first display area 101. The second start signal output end STV3 is electrically connected with the input end of the shift register unit Gm1+m2+1 located in the first row of pixels in the third display area 103. The selection control circuit 200 is configured to select the start signal output by one of the first start signal output end STV2 and the second start signal output end STV3 according to the frame inversion signal transmitted by the frame inversion signal input end FHL and the stage transmission signal transmitted by the stage transmission signal input end Gm1_IN during the Nth frame, and select the start signal output by the other of the first start signal output end STV2 and the second start signal output end STV3 according to the frame inversion signal input by the frame inversion signal input end FHL and the stage transmission signal transmitted by the stage transmission signal input end Gm1_IN during the N+1th frame, wherein N is a non-zero positive integer.

[0033] In the present application, the first-stage shift register unit G1 electrically connected with the first row of pixels in the second display area 102 is the first-stage shift register unit of the display panel. The start signal input end of the first-stage shift register unit G1 electrically connected with the first row of pixels in the second display area 102 is electrically connected with the control chip to receive the frame start signal STV from the control chip.

[0034] In the present application, by sequentially dividing the display panel into the first display area 101, the second display area 102 and the third display area 103 in the arrangement direction of the rows of pixels, and by setting the selection control circuit 200 in the gate driving circuit, the selection control circuit 200 selects the output of the start signal from the first start signal output end STV2 to the shift register unit electrically connected with the first row of pixels in the first display area 101 according to the frame inversion signal FHL after the stage transmission signal output of the shift register unit Gm1 electrically connected with the last row of pixels in the second display area 102, so that the gate of the pixel in the first display area 101 is opened and starts to charge, or selects the output of the start signal STV3 from the second start signal output end STV3 to the shift register unit Gm1+m2+1 electrically connected with the first row of pixels in the third display area 103, so that the gate of the pixel in the third display area 103 is opened and starts to charge, that is, during a frame period, after the gate of the row of pixels in the second display area 102 is opened in sequence row by row, the gate of only one of the pixel in the first display area 101 and the pixel in the third display area 103 is opened in sequence row by row and charges, so that during each frame period, only the pixels in two of the three display areas charge, thereby reducing the power consumption of the display panel during each frame period, and during the next frame period, the selection control circuit 200 selects the output of the start signal from the other of the first start signal output end STV2 and the second start signal output end STV3, that is, during the adjacent two frame periods, the charging of the pixel in the first display area 101 and the charging of the pixel in the third display area 103 are alternately performed, so as to ensure that the pixels in all the display areas of the display panel can charge at least once during the adjacent two frame periods, to ensure that the display panel can perform high-resolution display, and during the adjacent two frame periods, the pixels in the second display area 102 between the first display area 101 and the third display area 103 can maintain a relatively high refresh frequency, which is beneficial to ensure the high refresh frequency of the display panel.

[0035] In the present application, the selection control circuit 200 controls the sequence of the partition display, and the refresh frequencies of different display areas are different, so that the display panel has lower power consumption and transmission bandwidth requirement.

[0036] As shown in FIG. 1, Figures 1 to 5 As shown in FIG. 1, Figure 5As shown, during the Nth frame, the frame inversion signal input end FHL transmits a continuous high level signal, when the last stage shift register unit Gm electrically connected with the pixels in the second display area 102 outputs a stage transmission signal to the stage transmission signal input end Gm1_IN of the selection control circuit 200, the selection control circuit 200 selects to output a start signal from the first start signal output end STV2 according to the high level signal transmitted by the frame inversion signal input end FHL and the stage transmission signal of the stage transmission signal input end Gm1_IN, the first stage shift register unit Gm+1 electrically connected with the pixels in the first display area 101 opens the gate of the first row of pixels in the first display area 101 according to the start signal output by the first start signal output end STV2, and then opens the gate of the pixels in the second row of pixels in the first display area 101, until all the pixels in the first display area 101 complete a scanning, thereby completing the scanning of the display panel in the Nth frame. During the N+1th frame, the frame inversion signal input end FHL transmits a continuous low level signal, when the first stage shift register unit Gm1 electrically connected with the pixels in the third display area 103 outputs a stage transmission signal to the stage transmission signal input end Gm1_IN of the selection control circuit 200, the selection control circuit 200 selects to output a start signal from the second start signal output end STV3 according to the low level signal transmitted by the frame inversion signal input end FHL and the stage transmission signal of the stage transmission signal input end Gm1_IN, the first stage shift register unit Gm1+m2+1 electrically connected with the pixels in the third display area 103 opens the gate of the first row of pixels in the third display area 103 according to the start signal output by the second start signal output end STV3, and then opens the gate of the pixels in the second row of pixels in the third display area 103, until all the pixels in the third display area 103 complete a scanning, thereby completing the scanning of the display panel in the N+1th frame.

[0037] Alternatively, during the Nth frame, the frame inversion signal input end FHL transmits a continuous low level signal, the selection control circuit 200 selects to output a start signal from the first start signal output end STV2 according to the low level signal transmitted by the frame inversion signal input end FHL and the stage transmission signal of the stage transmission signal input end Gm1_IN, during the N+1th frame, the frame inversion signal input end FHL transmits a continuous high level signal, the selection control circuit 200 selects to output a start signal from the second start signal output end STV3 according to the high level signal transmitted by the frame inversion signal input end FHL and the stage transmission signal of the stage transmission signal input end Gm1_IN.

[0038] In the embodiment, the frame inversion signal input end FHL is electrically connected with the control chip.

[0039] As Figures 1 to 3As shown, in this embodiment, the selection control circuit 200 further includes a first control unit 210 and a second control unit 220. The control terminal of the first control unit 210 is electrically connected to the frame inversion signal input terminal FHL, the input terminal of the first control unit 210 is electrically connected to the cascade signal input terminal Gm1_IN, and the output terminal of the first control unit 210 is electrically connected to the first start signal output terminal STV2. The first control unit 210 is configured to turn on the cascade signal input terminal Gm1_IN and the first start signal output terminal STV2 when the frame inversion signal transmitted by the frame inversion signal input terminal FHL is either high or low, and to turn off the cascade signal input terminal Gm1_IN and the first start signal output terminal STV2 when the frame inversion signal transmitted by the frame inversion signal input terminal FHL is either high or low.

[0040] The control terminal of the second control unit 220 is electrically connected to the frame inversion signal input terminal FHL. The input terminal of the second control unit 220 is electrically connected to the stage transmission signal input terminal Gm1_IN. The output terminal of the second control unit is electrically connected to the second start signal output terminal STV3. The second control unit 220 is configured to turn on the stage transmission signal input terminal Gm1_IN and the second start signal output terminal STV3 when the frame inversion signal input terminal FHL is either high or low. When the frame inversion signal input terminal FHL is either high or low, the control stage transmission signal input terminal Gm1_IN and the second start signal output terminal STV3 are disconnected.

[0041] like Figure 2 As shown, in this embodiment, the first control unit 210 includes a first input control module 211, a first output module 212, and a first pull-down module 213.

[0042] The input terminal of the first input control module 211 is electrically connected to the frame inversion signal input terminal FHL, and the output terminal of the first input control module 211 is electrically connected to the first control node Q1. The first input control module 211 is configured to control the level of the first control node Q1 according to the signal of the frame inversion signal input terminal FHL.

[0043] The input terminal of the first output module 212 is electrically connected to the first control node Q1 and the transmission signal input terminal Gm1_IN. The output terminal of the first output module 212 is electrically connected to the first output node K1. The first output node K1 is electrically connected to the first start signal output terminal STV2. The first output module 212 is configured to control the on / off state of the transmission signal input terminal Gm1_IN and the first start signal output terminal STV2 according to the level of the first control node Q1.

[0044] An input end of the first pull-down module 213 is electrically connected with a frame inversion signal input end FHL, a first high-level signal input end VGH1 and a first low-level signal input end VGL1, an output end of the first pull-down module 213 is electrically connected with a first output node K1 and a first control node Q1, the first pull-down module 213 is configured to pull down the level of the first output node K1 and the first control node Q1 according to the signals of the frame inversion signal input end FHL, the first high-level signal input end VGH1 and the first low-level signal input end VGL1, so that the first start signal output end STV2 is disconnected from the stage transmission signal input end Gm1_IN, and the first start signal output end STV2 continuously outputs a low level.

[0045] The second control unit 220 includes a second input control module 221, a third input control module 222, a second output module 223 and a second pull-down module 224.

[0046] An input end of the second input control module 221 is electrically connected with the frame inversion signal input end FHL, a second high-level signal input end VGH2 and a second low-level signal input end VGL2, an output end of the second input control module 221 is electrically connected with a second control node Q2, and the second input control module 221 is configured to control the level of the second control node Q2 according to the signals of the frame inversion signal input end FHL, the second high-level signal input end VGH2 and the second low-level signal input end VGL2.

[0047] An input end of the third input control module 222 is electrically connected with the second control node Q2, an output end of the third input control module 222 is electrically connected with a third control node Q3, and the third input control module 222 is configured to control the level of the third control node Q3 according to the level of the second control node Q2.

[0048] An input end of the second output module 223 is electrically connected with the third control node Q3 and the stage transmission signal input end Gm1_IN, an output end of the second output module 223 is electrically connected with a second output node K2, the second output node K2 is electrically connected with a second start signal output end STV3, and the second output module 223 is configured to control the on-off of the stage transmission signal input end Gm1_IN and the second start signal output end STV3 according to the level of the third control node Q3.

[0049] The input end of the second pull-down module 224 is electrically connected with the second control node Q2, the third high-level signal input end VGH3 and the second low-level signal input end VGL2, the output end of the second pull-down module 224 is electrically connected with the third control node Q3 and the second output node K2, and the second pull-down module 224 is configured to pull down the levels of the third control node Q3 and the second output node K2 according to the level of the second control node Q2, the signal of the third high-level signal input end VGH3 and the signal of the second low-level signal input end VGL2.

[0050] In the embodiment, the first input control module 211 includes a first switch element T1, the control end and the input end of the first switch element T1 are electrically connected with the frame inversion signal input end FHL, and the output end of the first switch element T1 is electrically connected with the first control node Q1. The first switch element T1 is a first transistor, one of the source and the drain of the first transistor and the gate are electrically connected with the frame inversion signal input end FHL, and the other of the source and the drain of the first transistor is electrically connected with the first control node Q1. When the high-level signal transmitted by the frame inversion signal input end FHL, the gate of the first transistor is at a high point, the first transistor transmits a high level to the first control node Q1, and the first control node Q1 is kept at a high potential.

[0051] The first output module 212 includes a second switch element T2 and a first capacitor C1, the control end of the second switch element T2 is electrically connected with the first control node Q1, the input end of the second switch element T2 is electrically connected with the stage transmission signal input end Gm1_IN, the output end of the second switch element T2 is electrically connected with the first output node K1, the first output node K1 is electrically connected with the first start signal output end STV2, and the first capacitor C1 is electrically connected with the first control node Q1 and the first output node K1. The second switch element T2 is a second transistor, when the first control node Q1 is at a high potential, the gate of the second transistor is at a high potential, the first capacitor C1 is charged, and the stage transmission signal input end Gm1_IN and the first start signal output end STV2 are turned on.

[0052] In the embodiment, the first pull-down module 213 includes a third switch element T3, a fourth switch element T4, a fifth switch element T5 and a sixth switch element T6.

[0053] The control end of the third switch element T3 is electrically connected with the frame inversion signal input end FHL, the input end of the third switch element T3 is electrically connected with the first low level signal input end VGL1, and the output end of the third switch element T3 is connected with the fourth control node P1. The third switch element T3 is a third transistor, one of the source and the drain of the third transistor is electrically connected with the fourth control node P1, and the other of the source and the drain of the third transistor is electrically connected with the first low level signal input end VGL1. The first low level signal input end VGL1 is electrically connected with a first voltage source, and the first voltage source is used for outputting a low level signal.

[0054] The control end and the input end of the fourth switch element T4 are both electrically connected with the first high level signal input end VGH1, and the output end of the fourth switch element T4 is electrically connected with the fourth control node P1. The fourth switch element T4 is a fourth transistor, one of the source and the drain of the fourth transistor and the gate are electrically connected with the first high level signal input end VGH1, and the other of the source and the drain of the fourth transistor is electrically connected with the fourth control node P1. The first high level signal input end VGH1 is electrically connected with a second voltage source.

[0055] The control end of the fifth switch element T5 is electrically connected with the fourth control node P1, the input end of the fifth switch element T5 is electrically connected with the first low level signal input end VGL1, and the output end of the fifth switch element T5 is connected with the first control node Q1. The fifth switch element T5 is a fifth transistor, the gate of the fifth transistor is electrically connected with the fourth control node P1, one of the source and the drain of the fifth transistor is electrically connected with the first low level signal input end VGL1, and the other of the source and the drain of the fifth transistor is electrically connected with the first control node Q1.

[0056] The control end of the sixth switch element T6 is electrically connected with the fourth control node P1, the input end of the sixth switch element T6 is electrically connected with the first low level signal input end VGL1, and the output end of the sixth switch element T6 is electrically connected with the first output node K1. The sixth switch element T6 is a sixth transistor, the gate of the sixth transistor is electrically connected with the fourth control node P1, one of the source and the drain of the sixth transistor is electrically connected with the first low level signal input end VGL1, and the other of the source and the drain of the sixth transistor is electrically connected with the first output node K1.

[0057] When the frame inversion signal output end transmits a low level signal, the potential of the fourth control node P1 rises, the fifth transistor and the sixth transistor open, after the fifth transistor opens, the potential of the first control node Q1 is pulled low, the second transistor is closed, the stage transmission signal input end Gm1_IN is disconnected with the first start signal output end STV2, after the sixth transistor opens, the potential of the first output node K1 is pulled low, the first start signal output end STV2 outputs a low level signal, so that the shift register electrically connected with the pixel row located in the first display area does not perform stage transmission, and the pixel row located in the first display area does not charge.

[0058] When the frame inversion signal input end FHL transmits a high level signal, the source and the drain of the third transistor are turned on, thereby pulling down the potential of the fourth control node P1, and the fifth transistor and the sixth transistor are in a closed state, so that the levels of the first control node Q1 and the first output node K1 are not affected by the signal of the first low level signal input end VGL1.

[0059] In the embodiment, the second input control module 221 includes a seventh switch element T7 and an eighth switch element T8.

[0060] The control end of the seventh switch element T7 is electrically connected with the frame inversion signal input end FHL, the input end of the seventh switch element T7 is electrically connected with the second low level signal input end VGL2, and the output end of the seventh switch element T7 is connected with the second control node Q2. The seventh switch element T7 is a seventh transistor, the gate of the seventh transistor is electrically connected with the frame inversion signal input end FHL, one of the source and the drain of the seventh transistor is electrically connected with the second low level signal input end VGL2, and the other of the source and the drain of the seventh transistor is electrically connected with the second control node Q2. The second low level signal input end VGL2 is electrically connected with the first voltage source.

[0061] The control end and the input end of the eighth switch element T8 are connected with the second high level signal input end VGH2, and the output end of the eighth switch element T8 is connected with the second control node Q2. The eighth switch element T8 is an eighth transistor, the gate of the eighth transistor and one of the source and the drain of the eighth transistor are electrically connected with the second high level signal input end VGH2, and the other of the source and the drain of the eighth transistor is electrically connected with the second control node Q2.

[0062] When the frame inversion signal input end FHL transmits a high level signal, the seventh transistor opens, so that the level of the second control node Q2 is pulled low. When the frame inversion signal input end FHL transmits a low level signal, the seventh transistor is closed, and the second control node Q2 maintains a high potential.

[0063] In this embodiment, the third input control module 222 includes a ninth switching element T9. The control end and the input end of the ninth switching element T9 are electrically connected with the second control node Q2, and the output end of the ninth switching element T9 is electrically connected with the third control node Q3. Specifically, the ninth switching element T9 is a ninth transistor, one of the gate and one of the source and the drain of the ninth transistor is electrically connected with the second control node Q2, and the other of the source and the drain of the ninth transistor is electrically connected with the third control node Q3. When the second control node Q2 is at a high potential, the ninth transistor is turned on, thereby pulling up the potential of the third control node Q3.

[0064] The second output module 223 includes a tenth switching element T10 and a second capacitor C2. The control end of the tenth switching element T10 is electrically connected with the third control node Q3, the input end of the tenth switching element T10 is electrically connected with the stage transmission signal input end Gm1_IN, the output end of the tenth switching element T10 is electrically connected with the second output node K2, and the second capacitor C2 is electrically connected with the third control node Q3 and the second output node K2. The tenth switching element T10 is a tenth transistor, the gate of the tenth transistor is electrically connected with the third control node Q3, one of the source and the drain of the tenth transistor is electrically connected with the stage transmission signal input end Gm1_IN, and the other of the source and the drain of the tenth transistor is electrically connected with the second output node K2. When the third control node Q3 is at a high potential, the tenth transistor is turned on, thereby making the stage transmission signal input end Gm1_IN and the second start signal output end STV3 conductive.

[0065] The second pull-down module 224 includes an eleventh switching element T11, a twelfth switching element T12, a thirteenth switching element T13 and a fourteenth switching element T14.

[0066] The control end of the eleventh switching element T11 is electrically connected with the second control node Q2, the input end of the eleventh switching element T11 is electrically connected with the second low potential signal input end VGL2, and the output end of the eleventh switching element T11 is electrically connected with the fifth control node P2. The eleventh switching element T11 is an eleventh transistor, the gate of the eleventh transistor is electrically connected with the second control node Q2, one of the source and the drain of the eleventh transistor is electrically connected with the second low potential signal input end VGL2, and the other of the source and the drain of the eleventh transistor is electrically connected with the fifth control node P2.

[0067] The control end and the input end of the twelfth switching element T12 are electrically connected with the third high potential signal input end VGH3, and the output end of the twelfth switching element T12 is electrically connected with the fifth control node P2. The gate of the twelfth switching element T12 and one of the source and the drain of the twelfth switching element T12 are electrically connected with the third high potential signal input end VGH3, and the other of the source and the drain of the twelfth switching element T12 is electrically connected with the fifth control node P2.

[0068] The control end of the thirteenth switch element T13 is electrically connected with the fifth control node P2, the input end of the thirteenth switch element T13 is electrically connected with the second low-level signal input end VGL2, and the output end of the thirteenth switch element T13 is electrically connected with the third control node Q3. The thirteenth switch element T13 is a thirteenth transistor, the gate of the thirteenth transistor is electrically connected with the fifth control node P2, one of the source and the drain of the thirteenth transistor is electrically connected with the second low-level signal input end VGL2, and the other of the source and the drain of the thirteenth transistor is electrically connected with the third control node Q3.

[0069] The control end of the fourteenth switch element T14 is electrically connected with the fifth control node P2, the input end of the fourteenth switch element T14 is electrically connected with the second low-level signal input end VGL2, and the output end of the fourteenth switch element T14 is electrically connected with the second output node K2. The fourteenth switch element T14 is a fourteenth transistor, the gate of the fourteenth transistor is electrically connected with the fifth control node P2, one of the source and the drain of the fourteenth transistor is electrically connected with the second low-level signal input end VGL2, and the other of the source and the drain of the thirteenth transistor is electrically connected with the second output node K2.

[0070] The second low-level signal input end VGL2 is electrically connected with a first voltage source, and the second high-level signal input end VGH2 and the third high-level signal input end VGH3 are electrically connected with a second voltage source.

[0071] When the frame inversion signal input end FHL transmits a low level, the seventh transistor is closed, the eighth transistor is opened, the level of the second control node Q2 is pulled high, the ninth transistor is opened, the level of the third control node Q3 is pulled high, the tenth transistor is opened, the stage transmission signal input end Gm1_IN is turned on with the second initial signal output end. The eleventh transistor is opened, the level of the fifth control node P2 is pulled low, and the thirteenth transistor and the fourteenth transistor are closed.

[0072] When the frame inversion signal input end FHL transmits a high level, the seventh transistor is opened, the level of the second control node Q2 is pulled low, the ninth transistor is closed, the tenth transistor is closed, the stage transmission signal input end Gm1_IN is disconnected with the second initial signal output end STV3, the eleventh transistor is closed, the potential of the fifth control node P2 is pulled high, the thirteenth transistor is opened, the potential of the third control node Q3 is pulled low, the fourteenth transistor is opened, the potential of the second output node K2 is pulled low, and the second initial signal output end STV3 outputs a low-level signal, so that the shift register electrically connected with the pixel row located in the third display area does not perform stage transmission, and the pixel row located in the third display area is not charged.

[0073] In the embodiment, the number of rows of pixels in the second display area 102 is greater than or equal to the number of rows of pixels in the first display area 101 and greater than or equal to the number of rows of pixels in the third display area 103. Since the refresh frequencies of the first display area 101 and the second display area 102 are different from the refresh frequency of the second display area 102, the number of rows of pixels in the second display area 102 being greater than or equal to the number of rows of pixels in the first display area 101 and greater than or equal to the number of rows of pixels in the third display area 103 can ensure that, in adjacent two frames of images, the pixels in the middle and most of the pixels have a high refresh frequency, so that the high-resolution display panel has a high refresh frequency at the same time, and the display effect is optimized.

[0074] In the embodiment, since the pixels in only two of the three display areas are charged during a frame, the number of pixel rows of the gate to be turned on during a frame is reduced, so that the display panel can be provided with more pixels and the high resolution of the display panel is improved.

[0075] In the embodiment, the second display area 102 includes a first sub-display area 102a and a second sub-display area 102b, the first sub-display area 102a is adjacent to the first display area 101, and the second sub-display area 102b is adjacent to the third display area 103.

[0076] As shown in FIGS. 1 and 2, in the embodiment of the application, the number of rows of pixels in the second display area 102 is greater than or equal to the number of rows of pixels in the first display area 101 and greater than or equal to the number of rows of pixels in the third display area 103. Figure 6 Figure 7 As shown in FIGS. 1 and 2, in the embodiment of the application, the number of rows of pixels in the second display area 102 is greater than or equal to the number of rows of pixels in the first display area 101 and greater than or equal to the number of rows of pixels in the third display area 103.

[0077] In the embodiment, the stage transfer signal output end of the nth-stage shift register electrically connected with the (n-3)th row of pixels is electrically connected with the (n-1)th-stage shift register, and the stage transfer signal output end of the (n-2)th-stage shift register electrically connected with the (n-2)th row of pixels is electrically connected with the nth-stage shift register. The (n-3)th-stage shift register and the (n-1)th-stage shift register are located on one side of the display area, and the (n-2)th-stage shift register and the nth-stage shift register are located on the other side of the display area. n is a non-zero positive integer greater than 3.

[0078] In the embodiment, the selection control circuit 200 includes a first selection control circuit 200 and a second selection control circuit 200, and the first selection control circuit 200 and the second selection control circuit 200 each include a frame inversion signal input end FHL, a stage transfer signal input end Gm1_IN, a first start signal output end STV2, and a second start signal output end STV3.

[0079] In the embodiment, the first display area 101 contains m1 rows of pixels, and the second display area 102 contains m2 rows of pixels. m1 and m2 are both greater than or equal to n. ​

[0080] The stage transmission signal input end Gm1 IN of the first selection control circuit 200 is electrically connected with the stage transmission signal output end of the shift register unit of the last row of pixels in the second display area 102, that is, the stage transmission signal input end Gm1 IN of the first selection control circuit 200 is electrically connected with the stage transmission signal output end of the m1-1th shift register.

[0081] The first start signal output end STV2 of the first selection control circuit 200 is electrically connected with the input end of the shift register unit of the first row of pixels in the first display area 101, that is, the first start signal output end STV2 of the first selection control circuit 200 is electrically connected with the input end of the m1+1th shift register, and the row of pixels electrically connected with the m1+1th shift register is located in the first display area 101.

[0082] The second start signal output end STV3 of the first selection control circuit 200 is electrically connected with the input end of the shift register unit of the first row of pixels in the third display area 103, that is, the second start signal output end STV3 of the first selection control circuit 200 is electrically connected with the input end of the m1+m2+1th shift register unit, and the row of pixels electrically connected with the m1+m2+1th shift register unit is located in the third display area 103.

[0083] The first selection control circuit 200 is configured to output a start signal through one of the first start signal output end STV2 of the first selection control circuit 200 and the second start signal output end STV3 of the first selection control circuit 200 according to the frame inversion signal transmitted by the frame inversion signal input end FHL of the first selection control circuit 200 during the Nth frame, and output a start signal through the other of the first start signal output end STV2 of the first selection control circuit 200 and the second start signal output end STV3 of the first selection control circuit 200 according to the frame inversion signal input by the frame inversion signal input end FHL of the first selection control circuit 200 during the N+1th frame.

[0084] The stage transmission signal input end Gm1 IN of the second selection control circuit 200 is electrically connected with the stage transmission signal output end of the shift register unit of the last row of pixels in the second display area 102, that is, the stage transmission signal input end Gm1 IN of the second selection control circuit 200 is electrically connected with the output end of the m1th shift register, and the row of pixels electrically connected with the m1th shift register is located in the second display area 102.

[0085] The first start signal output end STV2 of the second selection control circuit 200 is electrically connected with the input end of the shift register unit of the second row of pixels located in the first display area 101, that is, the first start signal output end STV2 of the second selection control circuit 200 is electrically connected with the input end of the m1+2th shift register unit, wherein the pixel row electrically connected with the m1+2th shift register unit is located in the first display area 101.

[0086] The second start signal output end STV3 of the second selection control circuit 200 is electrically connected with the input end of the shift register unit of the second row of pixels located in the third display area 103, that is, the second start signal output end STV3 of the second selection control circuit 200 is electrically connected with the m1+m2+2th shift register unit, wherein the pixel row electrically connected with the m1+m2+2th shift register unit is located in the third display area 103.

[0087] The second selection control circuit 200 is configured to output a start signal through one of the first start signal output end STV2 of the second selection control circuit 200 and the second start signal output end STV3 of the second selection control circuit 200 according to the frame inversion signal inputted by the frame inversion signal input end FHL of the second selection control circuit 200 during the Nth frame, and output a start signal through the other of the first start signal output end STV2 of the second selection control circuit 200 and the second start signal output end STV3 of the second selection control circuit 200 according to the frame inversion signal inputted by the frame inversion signal input end FHL of the second selection control circuit 200 during the N+1th frame.

[0088] The first selection control circuit 200 and the second selection control circuit 200 are respectively arranged on the left and right sides of the display area, wherein the shift register units of the odd row pixels in the first display area 101 and the second display area 102 are started by the first selection control circuit 200, and the shift register units of the even row pixels in the first display area 101 and the second display area 102 are started by the second selection control circuit 200, which is beneficial to thinning the frame of the display panel.

[0089] The specific embodiments of the present application are described in detail above. The above-described embodiments disclosed by the present application are only preferred embodiments of the present application. Those skilled in the art can make many modifications and improvements without departing from the concept of the present application. These modifications and improvements fall within the scope of the claims of the present application.

Claims

1. A display panel, characterized by, The display panel has a plurality of display areas, each of which is provided with a plurality of rows of pixels; the display panel comprises: a gate drive circuit electrically connected to a plurality of rows of the pixels of a plurality of the display areas; a selection control circuit electrically connected to the gate drive circuit and configured to generate a first start signal and a second start signal according to a received frame inversion signal, a level signal supplied by a level signal input terminal and a stage transmission signal; wherein in an Nth frame of the display panel, the gate drive circuit is configured to generate a plurality of first gate signals in response to one of the first start signal and the second start signal, and generate a plurality of second gate signals in response to a frame start signal, the plurality of first gate signals and the plurality of second gate signals are respectively used to control a plurality of rows of pixels of two adjacent display areas to be turned on, and the display areas corresponding to the pixels turned on in adjacent two frames have a partial overlap, N≥1, and N is a positive integer.

2. The display panel of claim 1, wherein in an (N+1)th frame of the display panel, the gate drive circuit is configured to generate a plurality of third gate signals in response to the other of the first start signal and the second start signal, and generate a plurality of the second gate signals in response to the frame start signal, the plurality of third gate signals and the plurality of second gate signals are respectively used to control a plurality of rows of pixels of two adjacent display areas to be turned on; wherein the display areas corresponding to the plurality of rows of pixels turned on in the Nth frame in response to the plurality of first gate signals and the display areas corresponding to the plurality of rows of pixels turned on in the (N+1)th frame in response to the plurality of third gate signals are different display areas.

3. The display panel of claim 1 or 2, wherein one of the first start signal and the second start signal has a corresponding active pulse in the Nth frame, for causing the gate drive circuit to generate the plurality of first gate signals; the other of the first start signal and the second start signal has a corresponding active pulse in the (N+1)th frame, for causing the gate drive circuit to generate the plurality of third gate signals.

4. The display panel of claim 3, wherein in the Nth frame, the first start signal has an active pulse, and the active pulse of the first start signal lags behind an active pulse of the frame start signal; in the (N+1)th frame, the second start signal has an active pulse, and the active pulse of the second start signal lags behind the active pulse of the frame start signal.

5. The display panel of claim 3, wherein, in a switching period corresponding to adjacent two frames, the frame inversion signal has a transition between a high level and a low level.

6. The display panel of claim 3, wherein, the gate drive circuit comprises a plurality of stage shift register units, and an output terminal of a stage of the shift register units is electrically connected to a row of the pixels; Among them, in the Nth frame and the N+1 frame, the signal output by the shift register unit corresponding to the last row of pixels in the display area corresponding to the multiple rows of pixels opened in response to the multiple second gate signals is the stage transmission signal transmitted to the selection control circuit.

7. The display panel of claim 6, wherein, In the Nth frame, the first start signal has an effective pulse, and the effective pulse of the first start signal overlaps with the period in which the stage transmission signal has an effective pulse; In the N+1 frame, the second start signal has an effective pulse, and the effective pulse of the second start signal overlaps with the period in which the stage transmission signal has an effective pulse.

8. The display panel of claim 1, wherein, The selection control circuit includes a first selection control circuit and a second selection control circuit; Among them, in a frame, the gate drive circuit is configured to generate multiple second gate signals in response to the frame start signal to control multiple rows of pixels in a display area to be opened, and one of the first start signal and the second start signal generated by the first selection control circuit and one of the first start signal and the second start signal generated by the second selection control circuit output a signal for controlling multiple rows of pixels in another display area to be opened.

9. The display panel of claim 8, wherein, In a part of the frame period, the gate drive circuit is configured to generate multiple second gate control signals in response to the frame start signal to control multiple rows of pixels in a display area to be opened; In another part of the frame period, the gate drive circuit is configured to output multiple signals for controlling multiple rows of pixels in another display area to be opened in response to one of the first start signal and the second start signal generated by the first selection control circuit and one of the first start signal and the second start signal generated by the second selection control circuit.

10. The display panel of claim 9, wherein, In the other part of the frame period, the gate drive circuit is configured to output multiple signals for controlling pixels in odd rows in the corresponding display area to be opened in response to one of the first start signal and the second start signal generated by the first selection control circuit; and output multiple signals for controlling pixels in even rows in the corresponding display area to be opened in response to one of the first start signal and the second start signal generated by the second selection control circuit. In the display area for receiving multiple second gate signals, the second gate signal received by the pixel in the last row corresponds to the stage transmission signal transmitted to the first selection control circuit, and the second gate signal received by the pixel in the last row corresponds to the stage transmission signal transmitted to the second selection control circuit.

11. The display panel of claim 8, wherein, The level signal input end includes a first low-level signal input end and a second low-level signal input end; and the selection control circuit includes:

12. The display panel of claim 1, wherein, ​ The first control unit is configured to generate the first start signal according to one of a high level and a low level of the frame inversion signal, a corresponding stage transmission signal and a level signal supplied by the first low level signal input end; The second control unit is configured to generate the second start signal according to the other of the high level and the low level of the frame inversion signal, the corresponding stage transmission signal and a level signal supplied by the second low level signal input end.

Images