Three-terminal storage module, three-terminal memory and data processing method thereof

Abstract

The invention provides a three-terminal storage module, a three-terminal memory and a data processing method thereof, the three-terminal storage module comprises a first transistor, a second transistor, a third transistor and a storage unit, the first end of the storage unit is connected with the first end of the first transistor, and the second end of the third transistor is connected with the second end of the third transistor; the second end of the storage unit is connected with the first end of the second transistor, and the third end of the storage unit is connected with the first end of the third transistor. According to the three-terminal storage module, the three-terminal memory and the data processing method of the three-terminal memory provided by the embodiment of the invention, multiplexing of a data storage function and a PUF (Physical Unclonable Function) function is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a three-terminal storage module, a three-terminal memory and a data processing method thereof. BACKGROUND

[0002] Physical Unclonable Function (PUF) provides an effective technical means for solving hardware security, identity authentication and anti-counterfeiting, and has wide application prospects in the fields of information security, Internet of Things and intelligent manufacturing.

[0003] In the prior art, the PUF function can be realized by using a three-terminal memory. Two storage modules in the three-terminal memory are needed to perform homomorphic writing, and then the voltage value, current value or logic state of the two storage modules are compared to obtain the response of the PUF. Since the storage module for realizing the PUF function needs to be occupied all the time, the area overhead of the hardware security circuit is increased. SUMMARY

[0004] In view of the problems in the prior art, the embodiments of the present application provide a three-terminal storage module, a three-terminal memory and a data processing method thereof, which can at least partially solve the problems in the prior art.

[0005] In a first aspect, the present application provides a three-terminal storage module, comprising a first transistor, a second transistor, a third transistor and a storage unit, wherein:

[0006] The first end of the storage unit is connected to the first end of the first transistor, the second end of the storage unit is connected to the first end of the second transistor, and the third end of the storage unit is connected to the first end of the third transistor.

[0007] Further, the storage unit adopts a magnetic tunnel junction.

[0008] In a second aspect, the present application provides a three-terminal memory, comprising a plurality of three-terminal storage modules according to any one of the above embodiments, a row decoder, a column decoder and a comparator, wherein:

[0009] Each three-terminal storage module is connected to the row decoder and the column decoder respectively; and the comparator is connected to each three-terminal storage module.

[0010] The comparator obtains a read signal from the three-terminal storage module in a read mode and obtains storage data based on the read signal; the comparator obtains a first output signal and a second output signal from the three-terminal storage module in a PUF mode and obtains a response signal of the PUF mode based on the first output signal and the second output signal; the data storage function and the physically unclonable function of the three-terminal storage module are multiplexed.

[0011] Further, the second end of the first transistor of each three-terminal storage module is connected to the column decoder through a complementary bit line, the second end of the second transistor of each three-terminal storage module is connected to the column decoder through a bit line, and the second end of the third transistor of each three-terminal storage module is connected to the column decoder through a source line; the third end of the first transistor of each three-terminal storage module is connected to the row decoder through a read word line, the third end of the second transistor of each three-terminal storage module is connected to the row decoder through a first write word line, and the third end of the third transistor of each three-terminal storage module is connected to the row decoder through a second write word line.

[0012] Further, the comparator is connected to the second end of the second transistor of each three-terminal storage module through a complementary bit line and is connected to the second end of the third transistor of each three-terminal storage module through a source line.

[0013] Further, the plurality of three-terminal storage modules are arranged in an array.

[0014] In a third aspect, the present application provides a hardware encryption chip comprising the three-terminal storage module according to any one of the above embodiments.

[0015] In a fourth aspect, the present application provides a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor comprises the hardware encryption chip according to the above embodiments.

[0016] In a fifth aspect, the present application provides a data processing method using the three-terminal storage module according to any one of the above embodiments, comprising:

[0017] In a storage mode, the row decoder and the column decoder receive a first external excitation to cause the three-terminal storage module to write data; in a read mode, the row decoder and the column decoder receive a second external excitation to cause the three-terminal storage module to generate a read signal and transmit the read signal to the comparator; the comparator obtains storage data by comparing the read signal and a threshold signal;

[0018] In the PUF mode, the row decoder and the column decoder receive a third external excitation, so that the three-terminal storage module generates a first output signal and a second output signal and transmits the first output signal and the second output signal to the comparator; the comparator obtains a response signal of the PUF mode by comparing the first output signal and the second output signal.

[0019] Further, the row decoder and the column decoder receive a second external excitation, so that the three-terminal storage module generates a reading signal and transmits the reading signal to the comparator.

[0020] After the row decoder and the column decoder receive the second external excitation, the row decoder supplies power to a reading word line and a writing word line corresponding to the three-terminal storage module, and the column decoder supplies power to a complementary bit line corresponding to the three-terminal storage module, so that the three-terminal storage module outputs the reading signal to the comparator through a data output line; if the writing word line is a first writing word line, the data output line is a bit line; if the writing word line is a second writing word line, the data output line is a source line.

[0021] Further, the row decoder and the column decoder receive a third external excitation, so that the three-terminal storage module generates a first output signal and a second output signal and transmits the first output signal and the second output signal to the comparator.

[0022] After the row decoder and the column decoder receive the third external excitation, the row decoder supplies power to a reading word line, a first writing word line and a second writing word line corresponding to the three-terminal storage module, and the column decoder supplies power to a complementary bit line corresponding to the three-terminal storage module, so that the three-terminal storage module outputs the first output signal through a bit line and outputs the second output signal through a source line to the comparator.

[0023] Further, the data processing method provided by the embodiment of the application further comprises:

[0024] In the PUF mode, the row decoder and the column decoder receive a fourth external excitation, so that data stored in the first three-terminal storage module and the second three-terminal storage module are the same, and the first three-terminal storage module generates a third output signal and the second three-terminal storage module generates a fourth output signal and transmits the third output signal and the fourth output signal to the comparator; the comparator obtains a response signal of the PUF mode by comparing the third output signal and the fourth output signal.

[0025] The three-terminal storage module, the three-terminal memory and the data processing method thereof provided by the embodiment of the application comprise a first transistor, a second transistor, a third transistor and a storage unit, a first end of the storage unit is connected with a first end of the first transistor, a second end of the storage unit is connected with a first end of the second transistor, and a third end of the storage unit is connected with a first end of the third transistor, so that the data storage function and the PUF function are multiplexed. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort. In the drawings:

[0027] Figure 1 is a structural schematic diagram of a three-terminal storage module provided by the first embodiment of the present application.

[0028] Figure 2 is a structural schematic diagram of a three-terminal storage module provided by the second embodiment of the present application.

[0029] Figure 3 is a principle schematic diagram of a three-terminal storage module realizing a PUF function provided by the third embodiment of the present application.

[0030] Figure 4 is a structural schematic diagram of a three-terminal storage module provided by the fourth embodiment of the present application.

[0031] Figure 5 is a partial structural schematic diagram of a three-terminal storage module provided by the fifth embodiment of the present application.

[0032] Figure 6 is an entity structural schematic diagram of a computer device provided by the sixth embodiment of the present application.

[0033] Figure 7 is a flow schematic diagram of a data processing method of a three-terminal storage module provided by the seventh embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail below in combination with the drawings. Herein, the illustrative embodiments of the present application and the descriptions thereof are used to explain the present application, but not as a limitation of the present application. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other at will. The acquisition, storage, use, processing, etc. of data in the technical solutions in the present application all conform to the relevant provisions of laws and regulations. The user information in the embodiments of the present application is obtained through a legal and compliant way, and the acquisition, storage, use, processing, etc. of the user information is authorized and agreed by the client.

[0035] In order to facilitate the understanding of the technical solutions provided by the present application, the related contents of the technical solutions of the present application will be described first.

[0036] Physical unclonable function: PUF is a low-cost hardware security primitive that uses internal chip characteristics to achieve high-security hardware protection functions. A certain excitation is input to the PUF circuit, and a unique random output response is obtained. Different excitations will obtain different output responses; due to the existence of physical deviation between chips, different PUF circuits with the same circuit structure will also obtain different output responses for the same input excitation.

[0037] Spin-orbit torque magnetic random access memory (SOT-MRAM): SOT-MRAM is a new generation of magnetic random access memory technology that uses spin-orbit torque effect to realize data writing. Unlike traditional spin transfer torque (STT)-based MRAM, SOT-MRAM passes a face current in a heavy metal layer (such as platinum, tungsten), and uses strong spin-orbit coupling to generate a vertical spin-polarized current, thereby efficiently driving the magnetic moment of the free layer adjacent to the heavy metal layer in the magnetic tunnel junction (MTJ) to flip. This writing mechanism physically separates the read / write path, significantly improves the writing speed (up to sub-nanosecond level) and reduces power consumption, while avoiding the reliability problems of the tunnel junction in the STT-MRAM writing process.

[0038] The three-terminal memory for realizing the PUF function in the prior art cannot be used for data storage any more, and two storage modules are needed to realize the PUF function. The three-terminal storage module provided by the embodiment of the present application can realize the PUF function on a single three-terminal storage module through the application of the internal entropy source of the three-terminal storage module, and the PUF function and the data storage function of the three-terminal storage module are independent of each other, and the change of the stored data does not affect the realization of the PUF function, thereby realizing the multiplexing of the PUF function and the data storage function. For the three-terminal memory, the number of excitation response pairs of the physical unclonable function and the randomness of the output response are increased, the area overhead of the hardware security circuit is greatly reduced, and the response speed of the hardware security module is improved.

[0039] Figure 1 is a structural schematic diagram of the three-terminal storage module provided by the first embodiment of the present application, as Figure 1 shown, the three-terminal storage module provided by the embodiment of the present application comprises a first transistor 1, a second transistor 2, a third transistor 3 and a storage unit 4, wherein:

[0040] The first end of the storage unit 4 is connected with the first end of the first transistor 1, the second end of the storage unit 4 is connected with the first end of the second transistor 2, and the third end of the storage unit 4 is connected with the first end of the third transistor 3.

[0041] Specifically, when the memory function needs to be implemented, when writing data, the second transistor 2 and the third transistor 3 are controlled to be turned on, and the current passes through the second transistor 2, the storage unit 4 and the third transistor 3, and the data is written to the storage unit. The second transistor 2 and the third transistor 3 are used to implement data storage.

[0042] When reading data, the first transistor 1 and the second transistor 2 are controlled to be turned on, and the read data is obtained by comparing the size of the current flowing through the first transistor 1, the storage unit 4 and the second transistor 2 with the preset current, and the first transistor 1 and the second transistor 2 implement data reading. Alternatively, the first transistor 1 and the third transistor 3 are controlled to be turned on, and the read data is obtained by comparing the size of the current flowing through the first transistor 1, the storage unit 4 and the third transistor 3 with the preset current, and the first transistor 1 and the third transistor 3 implement data reading. The size of the preset current is set according to actual needs, and the embodiment of the present application is not limited.

[0043] The asymmetry of the three-terminal storage module caused by process deviation and other factors. When using the internal entropy source of the three-terminal storage module, the current is input from the first terminal of the three-terminal storage module, and the asymmetry of itself will make the resistance value on the current path from the first terminal to the second terminal of the three-terminal storage module different from the resistance value on the current path from the first terminal to the third terminal of the three-terminal storage module, thereby affecting the size and delay of the output current of the second terminal and the third terminal of the three-terminal storage module.

[0044] When the PUF function needs to be implemented, the first transistor 1, the second transistor 2 and the third transistor 3 are controlled to be turned on, the first current flowing through the first transistor 1, the storage unit 4 and the second transistor 2 is obtained, and the second current flowing through the first transistor 1, the storage unit 4 and the third transistor 3 is obtained, and the response signal of the PUF is obtained by comparing the size of the first current and the second current. The first transistor 1, the second transistor 2 and the third transistor 3 implement the PUF function.

[0045] The first transistor 1, the second transistor 2 and the third transistor 3 can be Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs).

[0046] The three-terminal storage module provided by the embodiment of the present application includes a first transistor, a second transistor, a third transistor and a storage unit, the first end of the storage unit is connected with the first end of the first transistor, the second end of the storage unit is connected with the first end of the second transistor, and the third end of the storage unit is connected with the first end of the third transistor, thereby realizing the multiplexing of the data storage function and the PUF function.

[0047] Based on the above embodiments, the storage unit 4 further adopts a magnetic tunnel junction.

[0048] For example, such as Figure 2 As shown, the magnetic tunnel junction 4 includes a free layer A1, a barrier layer A2, a fixed layer A3, and a strong spin-orbit coupling layer A4. The fixed layer A3, barrier layer A2, and free layer A1 are sequentially stacked on the spin-orbit coupling layer A4. The direction of the magnetic moment of the free layer A1 is not fixed, while the direction of the magnetic moment of the fixed layer A3 is fixed. The magnetic tunnel junction exhibits anisotropy, including perpendicular magnetic anisotropy and in-plane magnetic anisotropy. The free layer A1, barrier layer A2, and fixed layer A3 can be circular or square thin films. The strong spin-orbit coupling layer A4 can be a heavy metal strip thin film or an antiferromagnetic strip thin film. The fixed layer A3 is connected to the first terminal of the first transistor 1, one end of the strong spin-orbit coupling layer A4 is connected to the first terminal of the second transistor 2, and the other end of the spin-orbit coupling layer A4 is connected to the first terminal of the third transistor 3.

[0049] During a write operation: The second transistor 2 and the third transistor 3 are turned on. Current flows into the second transistor 2, through the strong spin-orbit coupling layer A4, and out through the third transistor 3. After a preset time, the current flowing through the strong spin-orbit coupling layer A4 causes the magnetic moment in the adjacent free layer A1 to be written in a specific direction, thus writing the memory to a high-resistance state (or a low-resistance state), achieving data writing. When data in the opposite resistance state needs to be written, current flows into the third transistor 3, through the strong spin-orbit coupling layer A4, and out through the third transistor 3. After a preset time, the current flowing through the strong spin-orbit coupling layer A4 causes the magnetic moment in the adjacent free layer A1 to be rewritten in the opposite direction to the specific direction, writing the memory to a low-resistance state (or a high-resistance state).

[0050] During the read operation: First transistor 1 and second transistor 2 are turned on, allowing current to flow into first transistor 1, through fixed layer A3, barrier layer A2, free layer A1, and strong spin-orbit coupling layer A4, and out through second transistor 2. The magnitude of the current flowing out of second transistor 2 is compared with a preset current to obtain the read data. Alternatively, first transistor 1 and third transistor 3 are turned on, allowing current to flow into first transistor 1, through fixed layer A3, barrier layer A2, free layer A1, and strong spin-orbit coupling layer A4, and out through third transistor 3. The magnitude of the current flowing out of third transistor 3 is compared with a preset current to obtain the read data.

[0051] like Figure 3As shown, the current I flows from the fixed layer A3, and there is a difference between the currents I1 and I2 output from the two ends of the strong spin-orbit coupling layer A4. The currents I1 and I2 flow into the comparator (SA), the SA compares the sizes of the currents I1 and I2 and outputs a 1 or 0 value, generating a response signal of the PUF.

[0052] In the implementation of the PUF function, the first transistor 1, the second transistor 2 and the third transistor 3 are controlled to be turned on, the first current flowing through the first transistor 1, the magnetic tunnel junction 4 and the second transistor 2 is obtained, and the second current flowing through the first transistor 1, the magnetic tunnel junction 4 and the third transistor 3 is obtained, and the response signal of the PUF is obtained by comparing the sizes of the first current and the second current.

[0053] Figure 4 is a structural schematic diagram of a three-terminal memory provided by a fourth embodiment of the present application, as shown in Figure 4 The three-terminal memory provided by the embodiment of the present application includes a plurality of three-terminal storage modules 401 described in any of the above embodiments, a row decoder 402, a column decoder 403 and a comparator 404, wherein:

[0054] Each three-terminal storage module 401 is connected to the row decoder 402 and the column decoder 403 respectively; and the comparator 404 is connected to each three-terminal storage module 401.

[0055] The comparator 404 obtains a read signal from the three-terminal storage module 401 in the read mode and obtains storage data based on the read signal; the comparator 404 obtains a first output signal and a second output signal from the three-terminal storage module 401 in the PUF mode and obtains a response signal of the PUF mode based on the first output signal and the second output signal; and the data storage function and the physical unclonable function of the three-terminal storage module 401 are multiplexed.

[0056] Specifically, the plurality of three-terminal storage modules 401 can be arranged in an array. The row decoder 402 is used to control the power supply of the conductive lines in the row where the selected three-terminal storage module 401 is located. The column decoder 403 is used to control the power supply of the conductive lines in the column where the selected three-terminal storage module 401 is located.

[0057] In the read mode, the row decoder 402 and the column decoder 403 make the corresponding three-terminal storage module 401 output a read signal under external excitation, and the comparator 404 compares the read signal with a threshold signal and obtains the data stored in the three-terminal storage module 401 based on the comparison result. The threshold signal is set according to actual needs, which is not limited in the embodiment of the present application.

[0058] In the PUF mode, the row decoder 402 and the column decoder 403 are externally excited to make the corresponding three-terminal storage module 401 generate a first output signal and a second output signal, and the comparator 404 obtains a response signal of the PUF mode by comparing the first output signal and the second output signal.

[0059] The three-terminal storage module 401 can store data and provide the response signal of the PUF mode, and the change of the data storage of the three-terminal storage module 401 does not affect the implementation of the PUF function. The three-terminal storage module 401 realizes the multiplexing of the data storage function and the physical unclonable function.

[0060] The three-terminal storage provided by the embodiment of the present application comprises a plurality of three-terminal storage modules, a row decoder, a column decoder and a comparator, each three-terminal storage module is connected with the row decoder and the column decoder; the comparator is connected with each three-terminal storage module; the comparator obtains a read signal from the three-terminal storage module in the read mode and obtains storage data based on the read signal; the comparator obtains a first output signal and a second output signal from the three-terminal storage module in the PUF mode and obtains a response signal of the PUF mode based on the first output signal and the second output signal; the data storage function and the physical unclonable function of the three-terminal storage module are multiplexed, the multiplexing of the data storage function and the PUF function of the three-terminal storage module is realized, and the area overhead of the storage circuit and the security circuit is reduced.

[0061] Figure 5 is a partial enlarged structure schematic diagram of the three-terminal storage provided by the fifth embodiment of the present application, Figure 5 is Figure 4 is an enlarged view of A in the above-mentioned embodiment, as Figure 4 and Figure 5 shown, on the basis of the above-mentioned embodiments, further, the three-terminal storage module 401 comprises a first transistor 401-1, a second transistor 401-2, a third transistor 401-3 and a storage unit 401-4, the first end of the storage unit 401-4 is connected with the first end of the first transistor 401-1, the second end of the storage unit 401-4 is connected with the first end of the second transistor 401-2, and the third end of the storage unit 401-4 is connected with the first end of the third transistor 401-3.

[0062] The second end of the first transistor 401-1 is connected with the column decoder 403 through a complementary bit line (BLb line), the second end of the second transistor 401-2 is connected with the column decoder 403 through a bit line (BL line), and the second end of the third transistor 401-3 is connected with the column decoder 403 through a source line (SL line); the third end of the first transistor 401-1 is connected with the row decoder 402 through a read word line (RWL line), the third end of the second transistor 401-2 is connected with the row decoder 402 through a first write word line (WWL line), and the third end of the third transistor 401-3 is connected with the row decoder 402 through a second write word line (WWL' line).

[0063] The row decoder 402 is used for controlling the power supply of the RWL line, the WWL line and the WWL' line, and the column decoder 403 is used for controlling the power supply of the BLb line.

[0064] As shown in FIG. 4, on the basis of the above-mentioned embodiments, further, the comparator 404 is connected with the second end of the second transistor 401-2 of each three-terminal storage module 401 through the BLb line, and is connected with the second end of the third transistor 401-3 of each three-terminal storage module 401 through the SL line. Figure 4 As shown in FIG. 5, on the basis of the above-mentioned embodiments, further, a plurality of three-terminal storage modules 401 are arranged in an array.

[0065] Figure 4 As shown in FIG. 6, on the basis of the above-mentioned embodiments, further, a plurality of three-terminal storage modules 401 are arranged in an array.

[0066] The embodiment of the present application provides a hardware encryption chip, which comprises the three-terminal storage module in any of the above-mentioned embodiments.

[0067] The embodiment of the present application provides a computer device, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, and the processor comprises the hardware encryption chip in the above-mentioned embodiment.

[0068] The computer device may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device or a combination of any of these devices.

[0069] Reference is made to FIG. 7, which shows a structural schematic diagram of a computer device suitable for implementing the embodiments of the present application. Figure 6

[0070] As shown in FIG. 8, on the basis of the above-mentioned embodiments, further, a plurality of three-terminal storage modules 401 are arranged in an array. Figure 6 ​​As shown, the computer device includes a central processing unit (CPU) 601 which can perform various appropriate operations and processes according to programs stored in a read only memory (ROM) 602 or programs loaded from a storage section 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the computer device are also stored. The CPU 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0071] Connected to the I / O interface 605 are an input section 606 including a keyboard, a mouse, and the like; an output section 607 including a display device such as a cathode ray tube (CRT), a liquid crystal display (LCD), and the like, and a speaker, and the like; a storage section 608 including a hard disk, and the like; and a communication section 609 including a network interface card such as a LAN card, a modem, and the like. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as necessary. A removable recording medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, and the like is attached to the drive 610 as necessary, so that a computer program read therefrom is installed in the storage section 608 as necessary.

[0072] Figure 7 is a flowchart of a data processing method of a three-terminal memory provided by a seventh embodiment of the present application, as shown, Figure 7 The data processing method of the three-terminal memory provided by the embodiment of the present application can be applied to the three-terminal memory of any of the above embodiments, and includes:

[0073] S701, in the write mode, the row decoder and the column decoder receive the first external excitation, so that the three-terminal memory module writes data; in the read mode, the row decoder and the column decoder receive the second external excitation, so that the three-terminal memory module generates a read signal transmitted to the comparator; the comparator obtains the storage data by comparing the read signal and the threshold signal;

[0074] Specifically, the three-terminal memory has both data storage function and PUF function. In order to realize the data storage function, data writing and reading need to be performed, and the data writing corresponds to the write mode, and the data storage corresponds to the read mode. In the write mode, the row decoder and the column decoder can receive the first external excitation, the row decoder controls the second transistor and the third transistor of the three-terminal memory module to be turned on, and the column decoder supplies power to the second transistor or the third transistor, so that the storage unit of the three-terminal memory module can write data. The first external excitation can be a write signal, including the data to be written and the write address.

[0075] In the read mode, the row decoder and the column decoder can receive a second external excitation, the row decoder controls the first transistor of the three-terminal storage module to be turned on and controls the second transistor or the third transistor of the three-terminal storage module to be turned on, the column decoder supplies power to the first transistor of the three-terminal storage module, the storage unit of the three-terminal storage module outputs a read signal to the comparator through the second transistor or the third transistor, and the comparator obtains data stored in the storage unit of the three-terminal storage module by comparing the read signal with a threshold signal. The second external excitation can be a read signal and can include a read address.

[0076] The first external excitation and the second external excitation can be set according to actual needs, and embodiments of the present application are not limited.

[0077] In the PUF mode, the row decoder and the column decoder receive a third external excitation to make the three-terminal storage module generate a first output signal and a second output signal to be transmitted to the comparator, and the comparator obtains a response signal of the PUF mode by comparing the first output signal with the second output signal.

[0078] Specifically, in the PUF mode, the row decoder and the column decoder can receive a third external excitation, the row decoder controls the first transistor, the second transistor and the third transistor of the three-terminal storage module to be turned on, the column decoder supplies power to the first transistor of the three-terminal storage module, the storage unit of the three-terminal storage module outputs a first output signal to the comparator through the second transistor and outputs a second output signal to the comparator through the third transistor. Due to the asymmetry of the three-terminal storage module caused by process deviation and other factors, the first output signal and the second output signal are different. The comparator obtains a response signal of the PUF mode by comparing the first output signal with the second output signal.

[0079] The third external excitation can be set according to actual needs, and embodiments of the present application are not limited. The three-terminal storage module can further include a controller, and the controller sends the third external excitation to the row decoder and the column decoder. It can be understood that the write mode, the read mode and the PUF mode are independent of each other and have no sequential relationship.

[0080] It is assumed that the data stored in the storage unit of the three-terminal storage module in the high resistance state is 1, and the corresponding current flows from the second transistor to the third transistor, so that the storage unit is in the high resistance state; in the low resistance state, the data stored in the storage unit is 0, and the corresponding current flows from the third transistor to the second transistor, so that the storage unit is in the low resistance state.

[0081] When the data stored in the storage unit is 1, it is assumed that the first output signal obtained is greater than the second output signal in the PUF mode. When the data stored in the storage unit becomes 0, the storage unit changes from the high resistance state to the low state, and the first output signal and the second output signal obtained change relative to the data stored in the storage unit being 1 in the PUF mode. Since the first transistor, the storage unit and the second transistor are needed for generation of the first output signal, and the first transistor, the storage unit and the third transistor are needed for generation of the second output signal, the three transistors do not change, the storage unit changes from the high resistance state to the low state, and the first output signal and the second output signal are both needed to pass through the storage unit, the change of the state of the storage unit has the same effect on the first output signal and the second output signal, which is equivalent to that the first output signal and the second output signal obtained in the PUF mode when the data stored is 1 are respectively subtracted by a same signal value, the first output signal and the second output signal obtained in the PUF mode when the data stored is 0 are obtained, and the size relationship of the first output signal and the second output signal is not changed. Therefore, the change of the data stored in the storage unit does not change the response signal of the PUF, and the data storage function and the PUF function are multiplexed.

[0082] The data processing method of the three-terminal memory provided in the embodiment of the application comprises the following steps: in a storage mode, a row decoder and a column decoder receive a first external excitation, so that a three-terminal storage module writes data; in a reading mode, the row decoder and the column decoder receive a second external excitation, so that the three-terminal storage module generates a reading signal and transmits the reading signal to a comparator; the comparator compares the reading signal with a threshold signal to obtain storage data; in a PUF mode, the row decoder and the column decoder receive a third external excitation, so that the three-terminal storage module generates a first output signal and a second output signal and transmits the first output signal and the second output signal to the comparator; the comparator compares the first output signal with the second output signal to obtain a response signal in the PUF mode, and the data storage function and the PUF function are multiplexed.

[0083] On the basis of the above-mentioned embodiments, further, the row decoder and the column decoder receive the second external excitation, so that the three-terminal storage module generates a reading signal and transmits the reading signal to a comparator, which comprises the following steps:

[0084] After the row decoder and the column decoder receive the second external excitation, the row decoder supplies power to a RWL line and a write word line corresponding to the three-terminal storage module, and the column decoder supplies power to a BLb line corresponding to the three-terminal storage module, so that the three-terminal storage module outputs a reading signal to the comparator through a data output line; if the write word line is a WWL line, the data output line is a BL line; if the write word line is a WWL' line, the data output line is a SL line.

[0085] Specifically, after the row decoder and the column decoder receive the third external excitation, the row decoder supplies power to the RWL line, the WWL line and the WWL' line corresponding to the three-terminal storage module, so that the first transistor, the second transistor and the third transistor of the three-terminal storage module are turned on. The column decoder supplies power to the BLb line corresponding to the three-terminal storage module, so that the current flows into the first transistor of the three-terminal storage module, and then flows out from the second transistor and the third transistor of the three-terminal storage module through the storage unit of the three-terminal storage module. The current flowing out from the second transistor is transmitted to the comparator through the BL line, and the comparator obtains the first output signal. The current flowing out from the third transistor is transmitted to the comparator through the SL line, and the comparator obtains the second output signal.

[0086] On the basis of the above-mentioned embodiments, further, the row decoder and the column decoder receive the third external excitation, so that the three-terminal storage module generates the first output signal and the second output signal transmitted to the comparator, including:

[0087] After the row decoder and the column decoder receive the third external excitation, the row decoder supplies power to the RWL line, the WWL line and the WWL' line corresponding to the three-terminal storage module, and the column decoder supplies power to the BLb line corresponding to the three-terminal storage module, so that the three-terminal storage module outputs the first output signal through the BL line and outputs the second output signal through the SL line to the comparator.

[0088] Specifically, after the row decoder and the column decoder receive the third external excitation, the row decoder supplies power to the RWL line, the WWL line and the WWL' line corresponding to the three-terminal storage module, so that the first transistor, the second transistor and the third transistor of the three-terminal storage module are turned on. The column decoder supplies power to the BLb line corresponding to the three-terminal storage module, so that the current flows into the first transistor of the three-terminal storage module, and then flows out from the second transistor and the third transistor of the three-terminal storage module through the storage unit of the three-terminal storage module. The current flowing out from the second transistor is transmitted to the comparator through the BL line, and the comparator obtains the first output signal. The current flowing out from the third transistor is transmitted to the comparator through the SL line, and the comparator obtains the second output signal.

[0089] On the basis of the above-mentioned embodiments, further, the three-terminal memory data processing method provided by the embodiments of the present application further includes:

[0090] In the PUF mode, the row decoder and the column decoder receive a fourth external excitation, so that the first three-terminal storage module and the second three-terminal storage module store the same data, and the first three-terminal storage module generates a third output signal and the second three-terminal storage module generates a fourth output signal transmitted to the comparator; the comparator compares the third output signal and the fourth output signal to obtain a response signal of the PUF mode.

[0091] Specifically, the three-terminal memory provided by the embodiment of the present application can also realize the PUF function through two different three-terminal storage modules. After the row decoder and the column decoder receive a fourth external excitation, the row decoder supplies power to the WWL line and the WWL' line corresponding to the first three-terminal storage module, so that the second transistor and the third transistor of the first three-terminal storage module are turned on; the column decoder supplies power to the BL line corresponding to the first three-terminal storage module, and the SL line is grounded, so that the current flows from the second transistor, flows through the strong spin orbit coupling layer, and then flows out of the third transistor. After a preset time, the current flowing through the strong spin orbit coupling layer causes the magnetic moments in the adjacent free layers of the strong spin orbit coupling layer to be written in a specific direction, so as to write the first three-terminal storage module into a high resistance state (or a low resistance state), realizing the data writing of the first three-terminal storage module. At the same time, the row decoder supplies power to the WWL line and the WWL' line corresponding to the second three-terminal storage module, so that the second transistor and the third transistor of the second three-terminal storage module are turned on; the column decoder supplies power to the BL line corresponding to the second three-terminal storage module, and the SL line is grounded, so that the current flows from the second transistor, flows through the strong spin orbit coupling layer, and then flows out of the third transistor. After a preset time, the current flowing through the strong spin orbit coupling layer causes the magnetic moments in the adjacent free layers of the strong spin orbit coupling layer to be written in a specific direction, so as to write the second three-terminal storage module into a high resistance state (or a low resistance state), realizing the data writing of the second three-terminal storage module. The first three-terminal storage module and the second three-terminal storage module will write the same data, so as to store the same data. Then, the row decoder supplies power to the RWL line corresponding to the first three-terminal storage module and the RWL line corresponding to the second three-terminal storage module respectively, so that the first transistor of the first three-terminal storage module is turned on and the first transistor of the second three-terminal storage module is turned on. And the RWL line corresponding to the first three-terminal storage module and the RWL line corresponding to the second three-terminal storage module are supplied with power respectively, so that the second transistor of the first three-terminal storage module is turned on and the second transistor of the second three-terminal storage module is turned on; or, the WWL' line corresponding to the first three-terminal storage module and the WWL' line corresponding to the second three-terminal storage module are supplied with power respectively, so that the third transistor of the second three-terminal storage module is turned on and the third transistor of the second three-terminal storage module is turned on.

[0092] The column decoder supplies power to the BLb line corresponding to the first three-terminal memory module, so that the current flows into the first transistor of the first three-terminal memory module and passes through the memory cell of the first three-terminal memory module. When power is supplied to the RWL line corresponding to the first three-terminal memory module, the current passing through the memory cell of the first three-terminal memory module flows into the second transistor of the first three-terminal memory module, and then flows into the BL line corresponding to the first three-terminal memory module and is output to the comparator. The comparator obtains a third output signal. When power is supplied to the WWL' line corresponding to the first three-terminal memory module, the current passing through the memory cell of the first three-terminal memory module flows into the third transistor of the first three-terminal memory module, and then flows into the SL line corresponding to the first three-terminal memory module and is output to the comparator. The comparator obtains a third output signal.

[0093] Similarly, the column decoder supplies power to the BLb line corresponding to the second three-terminal memory module, so that the current flows into the first transistor of the second three-terminal memory module and passes through the memory cell of the second three-terminal memory module. When power is supplied to the RWL line corresponding to the second three-terminal memory module, the current passing through the memory cell of the second three-terminal memory module flows into the second transistor of the second three-terminal memory module, and then flows into the BL line corresponding to the second three-terminal memory module and is output to the comparator. The comparator obtains a fourth output signal. When power is supplied to the WWL' line corresponding to the second three-terminal memory module, the current passing through the memory cell of the second three-terminal memory module flows into the third transistor of the second three-terminal memory module, and then flows into the SL line corresponding to the second three-terminal memory module and is output to the comparator. The comparator obtains a fourth output signal.

[0094] The comparator can obtain a response signal of the PUF mode by comparing the third output signal and the fourth output signal.

[0095] The following describes the specific implementation process of the data processing method of the three-terminal memory provided by the embodiment of the application, taking a spin-orbit torque magnetic random memory as an example.

[0096] The spin-orbit torque magnetic random memory adopts the structure shown in FIG. 1, and each three-terminal memory module adopts the magnetic tunnel junction structure shown in FIG. 2. Figure 4 The spin-orbit torque magnetic random memory adopts the structure shown in FIG. 1, and each three-terminal memory module adopts the magnetic tunnel junction structure shown in FIG. 2. Figure 2 The spin-orbit torque magnetic random memory adopts the structure shown in FIG. 1, and each three-terminal memory module adopts the magnetic tunnel junction structure shown in FIG. 2.

[0097] In the write mode: after the row decoder and the column decoder receive the first external excitation, the row decoder supplies power to the WWL line and the WWL' line corresponding to the three-terminal storage module, so that the second transistor and the third transistor of the three-terminal storage module are turned on. The column decoder supplies power to the BL line corresponding to the three-terminal storage module, and the SL line is grounded, so that the current flows from the second transistor, through the strong spin orbit coupling layer, and then flows out of the third transistor. After a preset time, the current flowing through the strong spin orbit coupling layer causes the magnetic moment in the adjacent free layer of the strong spin orbit coupling layer to be written in a specific direction, thereby writing the memory as a high resistance state (or a low resistance state), realizing the writing of data. When it is necessary to write data of the opposite resistance state, the column decoder supplies power to the SL line corresponding to the three-terminal storage module, and the BL line is grounded, so that the current flows from the third transistor, through the strong spin orbit coupling layer, and then flows out of the second transistor. After a preset time, the current flowing through the strong spin orbit coupling layer causes the magnetic moment in the adjacent free layer of the strong spin orbit coupling layer to be rewritten in a direction opposite to the specific direction, thereby writing the memory as a low resistance state (or a high resistance state) to realize the writing of data.

[0098] In the read mode: after the row decoder and the column decoder receive the second external excitation, the row decoder supplies power to the RWL line corresponding to the three-terminal storage module, so that the first transistor of the three-terminal storage module is turned on, and the row decoder supplies power to the WWL line, so that the second transistor of the three-terminal storage module is turned on. The column decoder supplies power to the BLb line corresponding to the three-terminal storage module, so that the current flows from the first transistor, passes through the fixed layer, the barrier layer, the free layer and the strong spin orbit coupling layer, flows out of the second transistor, and is transmitted to the comparator through the BL line corresponding to the three-terminal storage module. The comparator compares the size of the current flowing out of the second transistor with the size of a preset current to obtain the read data.

[0099] Alternatively, after the row decoder and the column decoder receive the second external excitation, the row decoder supplies power to the WWL' line, so that the third transistor of the three-terminal storage module is turned on. The column decoder supplies power to the BLb line corresponding to the three-terminal storage module, so that the current flows from the first transistor, passes through the fixed layer, the barrier layer, the free layer and the strong spin orbit coupling layer, flows out of the third transistor, and is transmitted to the comparator through the SL line corresponding to the three-terminal storage module. The comparator compares the size of the current flowing out of the third transistor with the size of a preset current to obtain the read data.

[0100] In the PUF mode: after receiving the third external excitation, the row decoder and the column decoder supply power to the RWL line, the WWL line and the WWL' line corresponding to the three-terminal storage module, so that the first transistor, the second transistor and the third transistor of the three-terminal storage module are turned on. The column decoder supplies power to the BLb line corresponding to the three-terminal storage module, so that the current flows into the first transistor, passes through the fixed layer, the barrier layer, the free layer and the strong spin-orbit coupling layer, and flows out of the second transistor and the third transistor. The current flowing out of the second transistor is transmitted to the comparator through the BL line, and the comparator obtains the first output signal; the current flowing out of the third transistor is transmitted to the comparator through the SL line, and the comparator obtains the second output signal. The comparator compares the first output signal and the second output signal to obtain the response signal of the PUF mode.

[0101] In the PUF mode: after receiving the fourth external excitation, the row decoder and the column decoder supply power to the WWL line and the WWL' line corresponding to the three-terminal storage module X in the spin-orbit torque magnetic random memory, so that the second transistor and the third transistor of the three-terminal storage module X are turned on; the column decoder supplies power to the BL line corresponding to the three-terminal storage module X, and the SL line is grounded, so that the current flows into the second transistor, flows through the strong spin-orbit coupling layer, and then flows out of the third transistor. After a preset time, the current flowing through the strong spin-orbit coupling layer causes the magnetic moments in the adjacent free layer of the strong spin-orbit coupling layer to be written in a specific direction, thereby writing the three-terminal storage module X into a high resistance state, realizing the data writing of the three-terminal storage module X. At the same time, the row decoder supplies power to the WWL line and the WWL' line corresponding to the three-terminal storage module Y in the spin-orbit torque magnetic random memory, so that the second transistor and the third transistor of the three-terminal storage module Y are turned on; the column decoder supplies power to the BL line corresponding to the three-terminal storage module Y, and the SL line is grounded, so that the current flows into the second transistor, flows through the strong spin-orbit coupling layer, and then flows out of the third transistor. After a preset time, the current flowing through the strong spin-orbit coupling layer causes the magnetic moments in the adjacent free layer of the strong spin-orbit coupling layer to be written in a specific direction, thereby writing the three-terminal storage module Y into a high resistance state, realizing the data writing of the three-terminal storage module Y. The three-terminal storage module X and the three-terminal storage module Y will write the same data, thereby storing the same data.

[0102] Then, the row decoder supplies power to the RWL line corresponding to the three-terminal storage module X and the RWL line corresponding to the three-terminal storage module Y in the spin-orbit torque magnetic random memory, respectively, so that the first transistor of the three-terminal storage module X is turned on and the first transistor of the three-terminal storage module Y is turned on. And supply power to the RWL line corresponding to the three-terminal storage module X and the RWL line corresponding to the three-terminal storage module Y, respectively, so that the second transistor of the three-terminal storage module X is turned on and the second transistor of the three-terminal storage module Y is turned on.

[0103] The column decoder supplies power to the BLb line corresponding to the three-terminal storage module X, so that the current flows into the first transistor of the three-terminal storage module X, passes through the fixed layer, the barrier layer, the free layer and the strong spin-orbit coupling layer, and flows out of the second transistor of the three-terminal storage module X. The current flowing out of the second transistor is transmitted to the comparator through the BL line corresponding to the three-terminal storage module X, and the comparator obtains a third output signal. The column decoder supplies power to the BLb line corresponding to the three-terminal storage module Y, so that the current flows into the first transistor of the three-terminal storage module Y, passes through the fixed layer, the barrier layer, the free layer and the strong spin-orbit coupling layer, and flows out of the second transistor of the three-terminal storage module Y. The current flowing out of the second transistor is transmitted to the comparator through the BL line corresponding to the three-terminal storage module Y, and the comparator obtains a fourth output signal. The comparator compares the third output signal and the fourth output signal to obtain a response signal of the PUF mode.

[0104] The three-terminal storage module, the three-terminal memory and the data processing method thereof provided by the embodiments of the present application increase the difference inside a single three-terminal memory as an entropy source of the PUF mode, greatly increase the number of stimulus-response pairs in an array of the same scale, realize multiplexing of the data storage function and the PUF function of the three-terminal storage module, reduce the area overhead of the storage circuit and the security circuit, realize the PUF function through two different entropy sources, are suitable for various strong PUF and weak PUF structures, improve the randomness of the PUF output, and increase the number of stimulus-response pairs.

[0105] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer usable storage media containing computer usable program code (including but not limited to disk storage, CD-ROM, optical storage, etc.).

[0106] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system) and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The device that implements the functions specified in one flow or multiple flows and / or blocks. Figure 1 The device that implements the functions specified in one flow or multiple flows and / or blocks.

[0107] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flow Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0108] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flow Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0109] In this description, references to "one embodiment", "an embodiment", "some embodiments", "example", "exemplary", "specific example", or "some examples", etc., mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the present application. These phrases are not necessarily referring to the same embodiment or example. Furthermore, the description can use the term "comprising" to mean "including", "containing", or "consisting of", and the like, and that the description can refer to "method", "flow", or "block" to mean that comprising, including, or consisting of a process, flow, or block, respectively. This terminology can include the phrases not only themselves, but also derivations thereof.

[0110] The specific embodiments described above are examples of the present application and it is understood that the scope of the application is not limited to the scope of the specific embodiments described. Rather, the scope of the present application encompasses any modifications, equivalents, improvements, and alternatives falling within the spirit and scope of the present application.

Claims

1. A three-terminal memory module, characterized by, The three-terminal memory module comprises a first transistor, a second transistor, a third transistor and a storage unit, wherein: a first end of the storage unit is connected to a first end of the first transistor, a second end of the storage unit is connected to a first end of the second transistor, and a third end of the storage unit is connected to a first end of the third transistor.

2. The three-terminal memory module of claim 1, wherein, The storage unit adopts a magnetic tunnel junction.

3. A ternary memory, characterized by The memory device comprises a plurality of three-terminal memory modules as claimed in claim 1 or 2, a row decoder, a column decoder and a comparator, wherein: each three-terminal memory module is connected to the row decoder and the column decoder respectively, and the comparator is connected to each three-terminal memory module; the comparator obtains a read signal from the three-terminal memory module in a read mode and obtains storage data based on the read signal, and the comparator obtains a first output signal and a second output signal from the three-terminal memory module in a PUF mode and obtains a response signal of the PUF mode based on the first output signal and the second output signal, and the data storage function and the physically unclonable function of the three-terminal memory module are multiplexed.

4. The ternary memory of claim 3, wherein, a second end of the first transistor of each three-terminal memory module is connected to the column decoder through a complementary bit line, a second end of the second transistor of each three-terminal memory module is connected to the column decoder through a bit line, and a second end of the third transistor of each three-terminal memory module is connected to the column decoder through a source line; a third end of the first transistor of each three-terminal memory module is connected to the row decoder through a read word line, a third end of the second transistor of each three-terminal memory module is connected to the row decoder through a first write word line, and a third end of the third transistor of each three-terminal memory module is connected to the row decoder through a second write word line.

5. The ternary memory of claim 3, wherein, the comparator is connected to the second end of the second transistor of each three-terminal memory module through the complementary bit line and is connected to the second end of the third transistor of each three-terminal memory module through the source line.

6. The ternary memory of any one of claims 3 to 5, wherein, The plurality of three-terminal memory modules are arranged in an array.

7. A hardware encryption chip, characterized by The memory device comprises the three-terminal memory as claimed in any one of claims 3-6.

8. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor comprises the hardware encryption chip as claimed in claim 7.

9. A data processing method using the ternary memory of any one of claims 3 to 6, characterized in that, The memory device comprises: in a storage mode, the row decoder and the column decoder receive a first external excitation to cause the three-terminal memory module to write data; in a read mode, the row decoder and the column decoder receive a second external excitation to cause the three-terminal memory module to generate a read signal and transmit the read signal to the comparator; the comparator obtains storage data by comparing the read signal with a threshold signal; in a PUF mode, the row decoder and the column decoder receive a third external excitation to cause the three-terminal memory module to generate a first output signal and a second output signal and transmit the first output signal and the second output signal to the comparator; the comparator obtains a response signal of the PUF mode by comparing the first output signal with the second output signal.

10. The method of claim 9, wherein, the row decoder and the column decoder receive the second external excitation to cause the three-terminal memory module to generate the read signal and transmit the read signal to the comparator, and the comparator obtains the storage data by comparing the read signal with the threshold signal. After the row decoder and the column decoder receive the second external excitation, the row decoder supplies power to the read word line and the write word line corresponding to the three-terminal storage module, and the column decoder supplies power to the complementary bit line corresponding to the three-terminal storage module, so that the three-terminal storage module outputs a read signal to the comparator through the data output line; wherein, if the write word line is a first write word line, the data output line is a bit line; if the write word line is a second write word line, the data output line is a source line.

11. The method of claim 9, wherein, After the row decoder and the column decoder receive the third external excitation, the three-terminal storage module generates a first output signal and a second output signal and transmits them to the comparator, which comprises: After the row decoder and the column decoder receive the third external excitation, the row decoder supplies power to the read word line, the first write word line and the second write word line corresponding to the three-terminal storage module, and the column decoder supplies power to the complementary bit line corresponding to the three-terminal storage module, so that the three-terminal storage module outputs the first output signal through the bit line and outputs the second output signal through the source line to the comparator.

12. The method according to any one of claims 9 to 11, characterized in that, Further comprising: In the PUF mode, after the row decoder and the column decoder receive the fourth external excitation, the data stored in the first three-terminal storage module and the second three-terminal storage module are the same, and the first three-terminal storage module generates a third output signal and the second three-terminal storage module generates a fourth output signal and transmits them to the comparator; the comparator compares the third output signal and the fourth output signal to obtain a response signal of the PUF mode.

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